Ignore:
Timestamp:
Feb 26, 2013, 4:32:04 PM (12 years ago)
Author:
joannou
Message:

Bug fixing in vci_cc_vcache_wrapper component :

  • In TGT_RSP_DCACHE, using r_dcache_tgt_need_rsp instead of r_icache_tgt_need_rsp to check the need for a VCI response
  • In ICACHE_CC_CLACK, reinitializing r_cleanup_icache_req to false
  • In ICACHE_CC_CHECK, now testing if we come from ICACHE_MISS_DIR_UPDT for matching pending miss test
  • In DCACHE_IDLE,
    • using r_dcache_wbuf_req instead of r_dcache_updt_req for P1 wbuf update handling
    • moving initialization of r_dcache_save_* registers up right after the test for a valid processor request (so they are available when handling

all types of requests)

  • adding test for "not wbuf_write_miss" (waiting for the pipeline to be empty) to enter the itlb miss request handling
  • In DCACHE_TLB_PTE1_GET, initializing r_dcache_save_paddr before calling the MISS handling sub fsm
  • In DCACHE_TLB_PTE2_GET, initializing r_dcache_save_paddr before calling the MISS handling sub fsm
  • In DCACHE_MISS_SELECT, initializing r_dcache_miss_clack to true (reset to false in DCAHCE_CC_CLACK)
  • DCACHE_MISS_DIR_UPDT,
    • using r_dcache_cleanup_req instead of r_icache_cleanup_req
    • using r_dcache_save_paddr instead of r_dcache_vci_paddr
    • correcting the state written in the cache directory from ZOMBI to VALID when switching a slot to valid state
  • In DCACHE_CC_CLACK, reinitializing r_cleanup_dcache_req to false
  • In DCACHE_CC_CHECK, now testing if we come from DCACHE_MISS_DIR_UPDT for matching pending miss test
  • In CMD_IDLE,
    • adding a dcache_unc_req variable
    • updating the icache_miss_req variable : now taking unc requests into account
    • correcting the icache_miss_req variable : getting rid of the "not" before the r_vci_cmd_imiss_prio
    • updating data read unc test : now testing for a write buffer hit or miss
    • moved data linked load request in 3rd priority position
  • In CLEANUP_CMD_DATA_IDLE, adding parenthesis for the left shift on r_icache_cleanup_way
  • In CLEANUP_CMD_INS_IDLE, adding parenthesis for the left shift on r_icache_cleanup_way
  • Corrected some debug info (bad state names were displayed)
File:
1 edited

Legend:

Unmodified
Added
Removed
  • branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r299 r304  
    2323 *
    2424 * SOCLIB_LGPL_HEADER_END
     25 *
     26 * Maintainers: cesar.fuguet-tortolero@lip6.fr
     27 *              alexandre.joannou@lip6.fr
    2528 */
    2629
     
    11831186        if ( not r_tgt_dcache_req.read() )
    11841187        {
    1185             if ( not r_icache_tgt_need_rsp.read() or
     1188            if ( not r_dcache_tgt_need_rsp.read() or
    11861189                 p_vci_tgt_c.rspack.read() ) r_tgt_fsm = TGT_IDLE;
    11871190        }
     
    17241727            break;
    17251728        }
    1726        
     1729
    17271730        if ( not r_icache_cleanup_req.read() )
    17281731        {
     
    17641767{
    17651768    std::cout << "  <PROC " << name()
    1766               << " DCACHE_MISS_SELECT> Select a slot:" << std::dec
     1769              << " ICACHE_MISS_SELECT> Select a slot:" << std::dec
    17671770              << " / WAY = " << way
    17681771              << " / SET = " << set;
     
    17991802{
    18001803    std::cout << "  <PROC " << name()
    1801               << " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
     1804              << " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
    18021805              << " / WAY = " << r_icache_miss_way.read()
    18031806              << " / SET = " << r_icache_miss_set.read() << std::endl;
     
    20352038 
    20362039        r_icache_fsm = r_icache_fsm_save.read() ;
     2040        r_cleanup_icache_req = false;
    20372041
    20382042#if DEBUG_ICACHE
     
    20582062        paddr_t  mask  = ~((m_icache_words<<2)-1);
    20592063
    2060         if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
    2061                 ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
     2064        if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
     2065             (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
     2066            ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
    20622067        {
    20632068            // signaling the matching
     
    24542459        // Miss if the write request is non cacheable, and there is a pending
    24552460        // non cacheable write, or if the write buffer is full.
    2456         if ( r_dcache_updt_req.read() )
     2461        if ( r_dcache_wbuf_req.read() )
    24572462        {
    24582463            // miss if write not cacheable, and previous non cacheable write registered
     
    25112516        else if ( m_dreq.valid and not wbuf_write_miss )
    25122517        {
     2518            // register processor request and DCACHE response
     2519            r_dcache_save_vaddr      = m_dreq.addr;
     2520            r_dcache_save_be         = m_dreq.be;
     2521            r_dcache_save_wdata      = m_dreq.wdata;
     2522            r_dcache_save_paddr      = paddr;
     2523            r_dcache_save_cache_way  = cache_way;
     2524            r_dcache_save_cache_set  = cache_set;
     2525            r_dcache_save_cache_word = cache_word;
     2526
    25132527            // READ XTN requests from processor
    25142528            // They are executed in this DCACHE_IDLE state.
     
    28182832                if ( valid_req )        // processor request is valid after TLB check
    28192833                {
    2820                     // register processor request and DCACHE response
    2821                     r_dcache_save_vaddr      = m_dreq.addr;
    2822                     r_dcache_save_be         = m_dreq.be;
    2823                     r_dcache_save_wdata      = m_dreq.wdata;
    2824                     r_dcache_save_paddr      = paddr;
    2825                     r_dcache_save_cache_way  = cache_way;
    2826                     r_dcache_save_cache_set  = cache_set;
    2827                     r_dcache_save_cache_word = cache_word;
    28282834                    r_dcache_save_cacheable  = cacheable;
    28292835
     
    30163022       
    30173023        // itlb miss request
    3018         else if ( r_icache_tlb_miss_req.read() )
     3024        else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
    30193025        {
    30203026            r_dcache_tlb_ins    = true;
     
    30263032        r_dcache_updt_req = updt_request;
    30273033        r_dcache_wbuf_req = wbuf_request or
    3028                             (r_dcache_wbuf_req.read() and wbuf_write_miss); 
     3034                            (r_dcache_wbuf_req.read() and wbuf_write_miss);
    30293035        break;
    30303036    }
     
    32013207            r_dcache_vci_miss_req  = true;             
    32023208            r_dcache_vci_paddr     = r_dcache_tlb_paddr.read();
     3209            r_dcache_save_paddr    = r_dcache_tlb_paddr.read();
    32033210            r_dcache_miss_type     = PTE1_MISS;
    32043211            r_dcache_fsm           = DCACHE_MISS_SELECT;         
     
    34373444            r_dcache_vci_miss_req = true;
    34383445            r_dcache_vci_paddr    = r_dcache_tlb_paddr.read();
     3446            r_dcache_save_paddr   = r_dcache_tlb_paddr.read();
    34393447            r_dcache_miss_type    = PTE2_MISS;
    34403448
     
    39263934        {
    39273935            r_dcache_fsm      = DCACHE_IDLE;
    3928             m_drsp.valid        = true;
     3936            m_drsp.valid      = true;
    39293937        }
    39303938
     
    40504058                {
    40514059                    r_dcache_cleanup_req  = true;
     4060                    r_dcache_miss_clack   = true;
    40524061                    r_dcache_cleanup_line = victim;
    40534062                    r_dcache_cleanup_way  = way;
     
    40654074              << " DCACHE_MISS_SELECT> Select a slot:" << std::dec
    40664075              << " / WAY = "   << way
    4067               << " / SET = "   << set;
     4076              << " / SET = "   << set
     4077              << " / PADDR = " << std::hex << r_dcache_save_paddr.read();
    40684078    if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
    40694079    else        std::cout << std::endl;
     
    41034113{
    41044114    std::cout << "  <PROC " << name()
    4105               << " DCACHE_MISS_INVAL> Switch to ZOMBI state" << std::dec
     4115              << " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
    41064116              << " / way = "   << way
    41074117              << " / set = "   << set << std::endl;
     
    42894299            if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
    42904300            {
    4291                 if ( not r_icache_cleanup_req.read() )
     4301                if ( not r_dcache_cleanup_req.read() )
    42924302                {
    42934303                    r_dcache_cleanup_req    = true;
    4294                     r_dcache_cleanup_line   = r_dcache_vci_paddr.read()/(m_dcache_words<<2);
     4304                    r_dcache_cleanup_line   = r_dcache_save_paddr.read()/(m_dcache_words<<2);
    42954305                    r_dcache_cleanup_way    = r_dcache_miss_way.read();
    42964306                    r_dcache_miss_inval     = false;
     
    42994309m_cpt_dcache_dir_write++;
    43004310#endif
    4301                     r_dcache.write_dir( r_dcache_vci_paddr.read(),
     4311                    r_dcache.write_dir( r_dcache_save_paddr.read(),
    43024312                                        r_dcache_miss_way.read(),
    43034313                                        r_dcache_miss_set.read(),
     
    43084318    std::cout << "  <PROC " << name()
    43094319              << " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
    4310               << " PADDR = " << std::hex << r_dcache_vci_paddr.read()
     4320              << " PADDR = " << std::hex << r_dcache_save_paddr.read()
    43114321              << " / WAY = "   << std::dec << r_dcache_miss_way.read()
    43124322              << " / SET = "   << r_dcache_miss_set.read() << std::endl;
     
    43214331m_cpt_dcache_dir_write++;
    43224332#endif
    4323                 r_dcache.write_dir( r_dcache_vci_paddr.read(),
     4333                r_dcache.write_dir( r_dcache_save_paddr.read(),
    43244334                                    r_dcache_miss_way.read(),
    43254335                                    r_dcache_miss_set.read(),
    4326                                     CACHE_SLOT_STATE_ZOMBI );
     4336                                    CACHE_SLOT_STATE_VALID );
     4337
    43274338#if DEBUG_DCACHE
    43284339if ( m_debug_dcache_fsm )
     
    43304341    std::cout << "  <PROC " << name()
    43314342              << " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
    4332               << " PADDR = " << std::hex << r_dcache_vci_paddr.read()
     4343              << " PADDR = " << std::hex << r_dcache_save_paddr.read()
    43334344              << " / WAY = "   << std::dec << r_dcache_miss_way.read()
    43344345              << " / SET = "   << r_dcache_miss_set.read() << std::endl;
     4346
     4347    r_dcache.printTrace();
     4348
     4349
    43354350}
    43364351#endif
     
    46094624
    46104625        r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
    4611 
     4626        r_cleanup_dcache_req = false;
    46124627#if DEBUG_DCACHE
    46134628if ( m_debug_dcache_fsm )
     
    46354650
    46364651
    4637         if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and
     4652        if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
     4653             (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
    46384654            ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
    46394655        {
     
    50475063            size_t      wbuf_max;
    50485064
     5065            bool dcache_unc_req = r_dcache_vci_unc_req.read() and
     5066                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
     5067
    50495068            bool dcache_miss_req = r_dcache_vci_miss_req.read() and
    50505069                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
    50515070
    5052            bool dcache_ll_req   = r_dcache_vci_ll_req.read() and
     5071            bool dcache_ll_req   = r_dcache_vci_ll_req.read() and
    50535072                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
    50545073
    50555074            bool icache_miss_req = r_icache_miss_req.read() and
    5056                  ( not (r_dcache_vci_miss_req.read() or r_dcache_vci_ll_req.read())
    5057                        or not r_vci_cmd_imiss_prio.read() );
     5075                 ( not (r_dcache_vci_miss_req.read() or
     5076                        r_dcache_vci_ll_req.read() or
     5077                        r_dcache_vci_unc_req.read())
     5078                     or r_vci_cmd_imiss_prio.read() ) ;
    50585079
    50595080            // 1 - Data Read Miss
     
    50665087            }
    50675088            // 2 - Data Read Uncachable
    5068             else if ( r_dcache_vci_unc_req.read() )
     5089            else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
    50695090            {
    50705091                r_vci_cmd_fsm        = CMD_DATA_UNC;
     
    50725093//                m_cpt_dunc_transaction++;
    50735094            }
    5074             // 3 - Instruction Miss
     5095            // 3 - Data Linked Load
     5096            else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
     5097            {
     5098                r_dcache_vci_ll_req = false;
     5099                r_vci_cmd_fsm       = CMD_DATA_LL;
     5100//              m_cpt_ll_transaction++;
     5101            }
     5102            // 4 - Instruction Miss
    50755103            else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
    50765104            {
     
    50805108//                m_cpt_imiss_transaction++;
    50815109            }
    5082             // 4 - Instruction Uncachable
     5110            // 5 - Instruction Uncachable
    50835111            else if ( r_icache_unc_req.read() )
    50845112            {
     
    50875115//                m_cpt_iunc_transaction++;
    50885116            }
    5089             // 5 - Data Write
     5117            // 6 - Data Write
    50905118            else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
    50915119            {
     
    50965124//                m_cpt_write_transaction++;
    50975125//                m_length_write_transaction += (wbuf_max-wbuf_min+1);
    5098             }
    5099             // 6 - Data Linked Load
    5100             else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
    5101             {
    5102                 r_dcache_vci_ll_req = false;
    5103                 r_vci_cmd_fsm       = CMD_DATA_LL;
    5104 //              m_cpt_ll_transaction++;
    51055126            }
    51065127            // 7 - Data Store Conditionnal
     
    54375458            {
    54385459                r_cleanup_cmd_fsm   = CLEANUP_CMD_INS_GO;
    5439                 r_cleanup_cmd_trdid = r_icache_cleanup_way.read()<<1 + 1;
     5460                r_cleanup_cmd_trdid = (r_icache_cleanup_way.read()<<1) + 1;
    54405461            }
    54415462            break;
     
    54475468            {
    54485469                r_cleanup_cmd_fsm   = CLEANUP_CMD_INS_GO;
    5449                 r_cleanup_cmd_trdid = r_icache_cleanup_way.read()<<1 + 1;
     5470                r_cleanup_cmd_trdid = (r_icache_cleanup_way.read()<<1) + 1;
    54505471            }
    54515472            else if ( r_dcache_cleanup_req.read() ) // dcache request
     
    54685489{
    54695490    std::cout << "  <PROC " << name()
    5470               << " CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
     5491              << " CLEANUP_CMD_DATA_GO> Cleanup request for icache:" << std::hex
    54715492              << " PADDR = " << (r_dcache_cleanup_line.read()*m_dcache_words*4)
    54725493              << " / TRDID = " << std::dec << r_cleanup_cmd_trdid.read() << std::endl;
     
    54885509{
    54895510    std::cout << "  <PROC " << name()
    5490               << " CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
     5511              << " CLEANUP_CMD_INS_GO> Cleanup request for dcache:" << std::hex
    54915512              << " PADDR = " << (r_icache_cleanup_line.read()*m_icache_words*4)
    54925513              << " / TRDID = " << std::dec << r_cleanup_cmd_trdid.read() << std::endl;
     
    57185739        p_vci_ini_d.wdata   = 0;
    57195740        p_vci_ini_d.be      = 0xF;
    5720         p_vci_ini_d.trdid   = 0;    //TODO local table index
     5741        p_vci_ini_d.trdid   = 0;
    57215742        p_vci_ini_d.pktid   = TYPE_LL;
    57225743        p_vci_ini_d.plen    = 8;
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