Index: /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 303) +++ /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 304) @@ -23,4 +23,7 @@ * * SOCLIB_LGPL_HEADER_END + * + * Maintainers: cesar.fuguet-tortolero@lip6.fr + * alexandre.joannou@lip6.fr */ @@ -1183,5 +1186,5 @@ if ( not r_tgt_dcache_req.read() ) { - if ( not r_icache_tgt_need_rsp.read() or + if ( not r_dcache_tgt_need_rsp.read() or p_vci_tgt_c.rspack.read() ) r_tgt_fsm = TGT_IDLE; } @@ -1724,5 +1727,5 @@ break; } - + if ( not r_icache_cleanup_req.read() ) { @@ -1764,5 +1767,5 @@ { std::cout << " Select a slot:" << std::dec + << " ICACHE_MISS_SELECT> Select a slot:" << std::dec << " / WAY = " << way << " / SET = " << set; @@ -1799,5 +1802,5 @@ { std::cout << " Switch to ZOMBI state" << std::dec + << " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec << " / WAY = " << r_icache_miss_way.read() << " / SET = " << r_icache_miss_set.read() << std::endl; @@ -2035,4 +2038,5 @@ r_icache_fsm = r_icache_fsm_save.read() ; + r_cleanup_icache_req = false; #if DEBUG_ICACHE @@ -2058,6 +2062,7 @@ paddr_t mask = ~((m_icache_words<<2)-1); - if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and - ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching + if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or + (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and + ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching { // signaling the matching @@ -2454,5 +2459,5 @@ // Miss if the write request is non cacheable, and there is a pending // non cacheable write, or if the write buffer is full. - if ( r_dcache_updt_req.read() ) + if ( r_dcache_wbuf_req.read() ) { // miss if write not cacheable, and previous non cacheable write registered @@ -2511,4 +2516,13 @@ else if ( m_dreq.valid and not wbuf_write_miss ) { + // register processor request and DCACHE response + r_dcache_save_vaddr = m_dreq.addr; + r_dcache_save_be = m_dreq.be; + r_dcache_save_wdata = m_dreq.wdata; + r_dcache_save_paddr = paddr; + r_dcache_save_cache_way = cache_way; + r_dcache_save_cache_set = cache_set; + r_dcache_save_cache_word = cache_word; + // READ XTN requests from processor // They are executed in this DCACHE_IDLE state. @@ -2818,12 +2832,4 @@ if ( valid_req ) // processor request is valid after TLB check { - // register processor request and DCACHE response - r_dcache_save_vaddr = m_dreq.addr; - r_dcache_save_be = m_dreq.be; - r_dcache_save_wdata = m_dreq.wdata; - r_dcache_save_paddr = paddr; - r_dcache_save_cache_way = cache_way; - r_dcache_save_cache_set = cache_set; - r_dcache_save_cache_word = cache_word; r_dcache_save_cacheable = cacheable; @@ -3016,5 +3022,5 @@ // itlb miss request - else if ( r_icache_tlb_miss_req.read() ) + else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss ) { r_dcache_tlb_ins = true; @@ -3026,5 +3032,5 @@ r_dcache_updt_req = updt_request; r_dcache_wbuf_req = wbuf_request or - (r_dcache_wbuf_req.read() and wbuf_write_miss); + (r_dcache_wbuf_req.read() and wbuf_write_miss); break; } @@ -3201,4 +3207,5 @@ r_dcache_vci_miss_req = true; r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + r_dcache_save_paddr = r_dcache_tlb_paddr.read(); r_dcache_miss_type = PTE1_MISS; r_dcache_fsm = DCACHE_MISS_SELECT; @@ -3437,4 +3444,5 @@ r_dcache_vci_miss_req = true; r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + r_dcache_save_paddr = r_dcache_tlb_paddr.read(); r_dcache_miss_type = PTE2_MISS; @@ -3926,5 +3934,5 @@ { r_dcache_fsm = DCACHE_IDLE; - m_drsp.valid = true; + m_drsp.valid = true; } @@ -4050,4 +4058,5 @@ { r_dcache_cleanup_req = true; + r_dcache_miss_clack = true; r_dcache_cleanup_line = victim; r_dcache_cleanup_way = way; @@ -4065,5 +4074,6 @@ << " DCACHE_MISS_SELECT> Select a slot:" << std::dec << " / WAY = " << way - << " / SET = " << set; + << " / SET = " << set + << " / PADDR = " << std::hex << r_dcache_save_paddr.read(); if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl; else std::cout << std::endl; @@ -4103,5 +4113,5 @@ { std::cout << " Switch to ZOMBI state" << std::dec + << " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec << " / way = " << way << " / set = " << set << std::endl; @@ -4289,8 +4299,8 @@ if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup { - if ( not r_icache_cleanup_req.read() ) + if ( not r_dcache_cleanup_req.read() ) { r_dcache_cleanup_req = true; - r_dcache_cleanup_line = r_dcache_vci_paddr.read()/(m_dcache_words<<2); + r_dcache_cleanup_line = r_dcache_save_paddr.read()/(m_dcache_words<<2); r_dcache_cleanup_way = r_dcache_miss_way.read(); r_dcache_miss_inval = false; @@ -4299,5 +4309,5 @@ m_cpt_dcache_dir_write++; #endif - r_dcache.write_dir( r_dcache_vci_paddr.read(), + r_dcache.write_dir( r_dcache_save_paddr.read(), r_dcache_miss_way.read(), r_dcache_miss_set.read(), @@ -4308,5 +4318,5 @@ std::cout << " Switch slot to ZOMBI state" - << " PADDR = " << std::hex << r_dcache_vci_paddr.read() + << " PADDR = " << std::hex << r_dcache_save_paddr.read() << " / WAY = " << std::dec << r_dcache_miss_way.read() << " / SET = " << r_dcache_miss_set.read() << std::endl; @@ -4321,8 +4331,9 @@ m_cpt_dcache_dir_write++; #endif - r_dcache.write_dir( r_dcache_vci_paddr.read(), + r_dcache.write_dir( r_dcache_save_paddr.read(), r_dcache_miss_way.read(), r_dcache_miss_set.read(), - CACHE_SLOT_STATE_ZOMBI ); + CACHE_SLOT_STATE_VALID ); + #if DEBUG_DCACHE if ( m_debug_dcache_fsm ) @@ -4330,7 +4341,11 @@ std::cout << " Switch slot to VALID state" - << " PADDR = " << std::hex << r_dcache_vci_paddr.read() + << " PADDR = " << std::hex << r_dcache_save_paddr.read() << " / WAY = " << std::dec << r_dcache_miss_way.read() << " / SET = " << r_dcache_miss_set.read() << std::endl; + + r_dcache.printTrace(); + + } #endif @@ -4609,5 +4624,5 @@ r_dcache_fsm = r_dcache_fsm_cc_save.read() ; - + r_cleanup_dcache_req = false; #if DEBUG_DCACHE if ( m_debug_dcache_fsm ) @@ -4635,5 +4650,6 @@ - if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and + if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or + (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching { @@ -5047,13 +5063,18 @@ size_t wbuf_max; + bool dcache_unc_req = r_dcache_vci_unc_req.read() and + ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); + bool dcache_miss_req = r_dcache_vci_miss_req.read() and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); - bool dcache_ll_req = r_dcache_vci_ll_req.read() and + bool dcache_ll_req = r_dcache_vci_ll_req.read() and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); bool icache_miss_req = r_icache_miss_req.read() and - ( not (r_dcache_vci_miss_req.read() or r_dcache_vci_ll_req.read()) - or not r_vci_cmd_imiss_prio.read() ); + ( not (r_dcache_vci_miss_req.read() or + r_dcache_vci_ll_req.read() or + r_dcache_vci_unc_req.read()) + or r_vci_cmd_imiss_prio.read() ) ; // 1 - Data Read Miss @@ -5066,5 +5087,5 @@ } // 2 - Data Read Uncachable - else if ( r_dcache_vci_unc_req.read() ) + else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read())) { r_vci_cmd_fsm = CMD_DATA_UNC; @@ -5072,5 +5093,12 @@ // m_cpt_dunc_transaction++; } - // 3 - Instruction Miss + // 3 - Data Linked Load + else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read())) + { + r_dcache_vci_ll_req = false; + r_vci_cmd_fsm = CMD_DATA_LL; +// m_cpt_ll_transaction++; + } + // 4 - Instruction Miss else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) ) { @@ -5080,5 +5108,5 @@ // m_cpt_imiss_transaction++; } - // 4 - Instruction Uncachable + // 5 - Instruction Uncachable else if ( r_icache_unc_req.read() ) { @@ -5087,5 +5115,5 @@ // m_cpt_iunc_transaction++; } - // 5 - Data Write + // 6 - Data Write else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) ) { @@ -5096,11 +5124,4 @@ // m_cpt_write_transaction++; // m_length_write_transaction += (wbuf_max-wbuf_min+1); - } - // 6 - Data Linked Load - else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read())) - { - r_dcache_vci_ll_req = false; - r_vci_cmd_fsm = CMD_DATA_LL; -// m_cpt_ll_transaction++; } // 7 - Data Store Conditionnal @@ -5437,5 +5458,5 @@ { r_cleanup_cmd_fsm = CLEANUP_CMD_INS_GO; - r_cleanup_cmd_trdid = r_icache_cleanup_way.read()<<1 + 1; + r_cleanup_cmd_trdid = (r_icache_cleanup_way.read()<<1) + 1; } break; @@ -5447,5 +5468,5 @@ { r_cleanup_cmd_fsm = CLEANUP_CMD_INS_GO; - r_cleanup_cmd_trdid = r_icache_cleanup_way.read()<<1 + 1; + r_cleanup_cmd_trdid = (r_icache_cleanup_way.read()<<1) + 1; } else if ( r_dcache_cleanup_req.read() ) // dcache request @@ -5468,5 +5489,5 @@ { std::cout << " Cleanup request for icache:" << std::hex + << " CLEANUP_CMD_DATA_GO> Cleanup request for icache:" << std::hex << " PADDR = " << (r_dcache_cleanup_line.read()*m_dcache_words*4) << " / TRDID = " << std::dec << r_cleanup_cmd_trdid.read() << std::endl; @@ -5488,5 +5509,5 @@ { std::cout << " Cleanup request for dcache:" << std::hex + << " CLEANUP_CMD_INS_GO> Cleanup request for dcache:" << std::hex << " PADDR = " << (r_icache_cleanup_line.read()*m_icache_words*4) << " / TRDID = " << std::dec << r_cleanup_cmd_trdid.read() << std::endl; @@ -5718,5 +5739,5 @@ p_vci_ini_d.wdata = 0; p_vci_ini_d.be = 0xF; - p_vci_ini_d.trdid = 0; //TODO local table index + p_vci_ini_d.trdid = 0; p_vci_ini_d.pktid = TYPE_LL; p_vci_ini_d.plen = 8;