Index: /branches/v5/platforms/tsar_generic_mmu/Makefile
===================================================================
--- /branches/v5/platforms/tsar_generic_mmu/Makefile	(revision 306)
+++ /branches/v5/platforms/tsar_generic_mmu/Makefile	(revision 306)
@@ -0,0 +1,8 @@
+
+simulator.x: top.cpp top.desc
+	soclib-cc -P -p top.desc -I. -o simul.x
+
+clean:
+	soclib-cc -x -p top.desc -I.
+	rm -rf *.o *.x tty*
+
Index: /branches/v5/platforms/tsar_generic_mmu/soclib.conf
===================================================================
--- /branches/v5/platforms/tsar_generic_mmu/soclib.conf	(revision 306)
+++ /branches/v5/platforms/tsar_generic_mmu/soclib.conf	(revision 306)
@@ -0,0 +1,5 @@
+config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI'])
+
+#config.addDescPath("/path/to/tsar/trunk/lib/")
+#config.addDescPath("/path/to/tsar/trunk/modules/")
+#config.addDescPath("/path/to/tsar/branches/v5/modules/")
Index: /branches/v5/platforms/tsar_generic_mmu/top.cpp
===================================================================
--- /branches/v5/platforms/tsar_generic_mmu/top.cpp	(revision 306)
+++ /branches/v5/platforms/tsar_generic_mmu/top.cpp	(revision 306)
@@ -0,0 +1,801 @@
+/////////////////////////////////////////////////////////////////////////
+// File: top.cpp 
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : august 2012
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture with virtual memory.
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The number of processors per cluster cannot be larger than 8.
+// 
+// - It uses vci_local_crossbar as local interconnect 
+// - It uses virtual_dspin as global interconnect
+// - It uses the vci_cc_vcache_wrapper
+// - It uses the vci_mem_cache
+// - It contains one vci_xicu and one vci_multi_dma per cluster.
+//
+// All clusters are identical, but the cluster containing address
+// 0xBFC00000 (called io_cluster), that contains 5 extra components:
+// - the boot rom (BROM)
+// - the disk controller (BDEV)
+// - the multi-channel network controller (MNIC)
+// - the multi-channel tty controller (MTTY)
+// - the frame buffer controller (FBUF)
+//
+// It is build with one single component implementing a cluster:
+// The TsarClusterMmu component is defined in files
+// tsar_cluster_mmu.* (with * = cpp, h, sd)
+//
+// The IRQs are connected to XICUs as follow:
+// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
+// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
+// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
+// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
+// 
+// The main hardware parameters must be defined in the hard_config.h file :
+// - CLUSTER_X     : number of clusters in a row (power of 2)
+// - CLUSTER_Y     : number of clusters in a column (power of 2)
+// - CLUSTER_SIZE     : size of the segment allocated to a cluster
+// - NB_PROCS_MAX     : number of processors per cluster (power of 2)
+// - NB_DMAS_MAX      : number of DMA channels per cluster (< 9)
+// - NB_TTYS          : number of TTY channels in I/O cluster (< 16)
+// - NB_NICS          : number of NIC channels in I/O cluster (< 9)
+// 
+// Some secondary hardware parameters must be defined in this top.cpp file:
+// - XRAM_LATENCY     : external ram latency 
+// - MEMC_WAYS        : L2 cache number of ways
+// - MEMC_SETS        : L2 cache number of sets
+// - L1_IWAYS     
+// - L1_ISETS    
+// - L1_DWAYS   
+// - L1_DSETS  
+// - FBUF_X_SIZE      : width of frame buffer (pixels)
+// - FBUF_Y_SIZE      : heigth of frame buffer (lines)
+// - BDEV_SECTOR_SIZE : block size for block drvice
+// - BDEV_IMAGE_NAME  : file pathname for block device 
+// - NIC_RX_NAME      : file pathname for NIC received packets
+// - NIC_TX_NAME      : file pathname for NIC transmited packets
+// - NIC_TIMEOUT      : max number of cycles before closing a container
+//
+// General policy for 32 bits physical address decoding:
+// All segments base addresses are multiple of 64 Kbytes
+// Therefore the 16 address MSB bits completely define the target: 
+// The (x_width + y_width) MSB bits (left aligned) define
+// the cluster index, and the 8 LSB bits define the local index:
+//      | X_ID  | Y_ID  |---| LADR |     OFFSET          |
+//      |x_width|y_width|---|  8   |       16            |
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "tsar_cluster_mmu.h"
+#include "alloc_elems.h"
+
+///////////////////////////////////////////////////
+//      OS
+///////////////////////////////////////////////////
+#define USE_ALMOS 0
+
+#define almos_bootloader_pathname "bootloader.bin"
+#define almos_kernel_pathname     "kernel-soclib.bin@0xbfc10000:D"
+#define almos_archinfo_pathname   "arch-info.bin@0xBFC08000:D"
+
+///////////////////////////////////////////////////
+//               Parallelisation
+///////////////////////////////////////////////////
+#define USE_OPENMP               0
+
+#if USE_OPENMP
+#include <omp.h>
+#endif
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)   (y + CLUSTER_Y*x)
+
+// flit widths for the DSPIN network
+#define cmd_width            40
+#define rsp_width            33
+
+// VCI format
+#define cell_width            4
+#define address_width         32
+#define plen_width            8
+#define error_width           2
+#define clen_width            1
+#define rflag_width           1
+#define srcid_width           14
+#define pktid_width           4
+#define trdid_width           4
+#define wrplen_width          1
+
+////////////////////////////////////////////////////////////
+//    Main Hardware Parameters values         
+//////////////////////i/////////////////////////////////////
+
+// Create a symbolic link to your local giet_vm copy
+// This directory must contain:
+// - hard_config.h
+// - soft.elf
+// - display/images.raw
+// - nic/rx_data.txt
+// - nic/tx_data.txt
+
+#include "giet_vm/hard_config.h"
+
+////////////////////////////////////////////////////////////
+//    Secondary Hardware Parameters values         
+//////////////////////i/////////////////////////////////////
+
+#define XRAM_LATENCY          0
+
+#define MEMC_WAYS             16
+#define MEMC_SETS             256
+
+#define L1_IWAYS              4
+#define L1_ISETS              64
+
+#define L1_DWAYS              4
+#define L1_DSETS              64
+
+#define FBUF_X_SIZE           128
+#define FBUF_Y_SIZE           128
+
+#define BDEV_SECTOR_SIZE      512
+#define BDEV_IMAGE_NAME       "giet_vm/display/images.raw"
+
+#define NIC_RX_NAME           "giet_vm/nic/rx_data.txt"
+#define NIC_TX_NAME           "giet_vm/nic/tx_data.txt"
+#define NIC_TIMEOUT           10000
+
+////////////////////////////////////////////////////////////
+//    Software to be loaded in ROM & RAM         
+//////////////////////i/////////////////////////////////////
+
+#define BOOT_SOFT_NAME        "giet_vm/soft.elf"
+
+////////////////////////////////////////////////////////////
+//     DEBUG Parameters default values         
+//////////////////////i/////////////////////////////////////
+
+#define MAX_FROZEN_CYCLES     10000
+
+#define TRACE_MEMC_ID         0
+#define TRACE_PROC_ID         1000000
+
+/////////////////////////////////////////////////////////
+//    Physical segments definition
+/////////////////////////////////////////////////////////
+// There is 3 segments replicated in all clusters
+// and 5 specific segments in the "IO" cluster 
+// (containing address 0xBF000000)
+/////////////////////////////////////////////////////////
+
+// specific segments in "IO" cluster : absolute physical address
+
+#define BROM_BASE               0xBFC00000      
+#define BROM_SIZE               0x00100000   // 1 Mbytes
+
+#define FBUF_BASE               0xBFD00000      
+#define FBUF_SIZE               0x00200000   // 2 Mbytes
+
+#define BDEV_BASE               0xBFF10000      
+#define BDEV_SIZE               0x00001000   // 4 Kbytes
+
+#define MTTY_BASE               0xBFF20000      
+#define MTTY_SIZE               0x00001000   // 4 Kbytes
+
+#define MNIC_BASE               0xBFF80000      
+#define MNIC_SIZE               0x00002000 * (NB_NICS + 1)  // 8 Kbytes per channel + 8 Kbytes
+
+// replicated segments : address is incremented by a cluster offset 
+//     offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+#define MEMC_BASE               0x00000000      
+#define MEMC_SIZE               0x00C00000   // 12 Mbytes
+
+#define XICU_BASE               0x00F00000      
+#define XICU_SIZE               0x00001000   // 4 Kbytes
+
+#define CDMA_BASE               0x00F30000      
+#define CDMA_SIZE               0x00001000 * NB_DMAS_MAX  // 4 Kbytes per channel  
+
+////////////////////////////////////////////////////////////////////
+//     TGTID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+////////////////////////////////////////////////////////////////////
+
+#define MEMC_TGTID               0
+#define XICU_TGTID               1
+#define CDMA_TGTID               2
+#define MTTY_TGTID               3
+#define FBUF_TGTID               4
+#define BROM_TGTID               5
+#define BDEV_TGTID               6
+#define MNIC_TGTID               7
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+   using namespace sc_core;
+   using namespace soclib::caba;
+   using namespace soclib::common;
+
+
+   char     soft_name[256]   = BOOT_SOFT_NAME;     // pathname to binary code
+   size_t   ncycles          = 1000000000;         // simulated cycles
+   char     disk_name[256]   = BDEV_IMAGE_NAME;    // pathname to the disk image
+   char     nic_rx_name[256] = NIC_RX_NAME;        // pathname to the rx packets file
+   char     nic_tx_name[256] = NIC_TX_NAME;        // pathname to the tx packets file
+   ssize_t  threads_nr       = 1;                  // simulator's threads number
+   bool     debug_ok         = false;              // trace activated
+   size_t   debug_period     = 1;                  // trace period
+   size_t   debug_memc_id    = TRACE_MEMC_ID;      // index of memc to be traced (cluster_id)  
+   size_t   debug_proc_id    = TRACE_PROC_ID;      // index of proc to be traced
+   uint32_t debug_from       = 0;                  // trace start cycle
+   uint32_t frozen_cycles    = MAX_FROZEN_CYCLES;  // monitoring frozen processor
+
+   ////////////// command line arguments //////////////////////
+   if (argc > 1)
+   {
+      for (int n = 1; n < argc; n = n + 2)
+      {
+         if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
+         {
+            ncycles = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+         {
+            strcpy(soft_name, argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+         {
+            strcpy(disk_name, argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+         {
+            debug_ok = true;
+            debug_from = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
+         {
+            debug_memc_id = atoi(argv[n+1]);
+            assert( (debug_memc_id < (CLUSTER_X*CLUSTER_Y) ) && 
+                   "debug_memc_id larger than XMAX * YMAX" );
+         }
+         else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
+         {
+            debug_proc_id = atoi(argv[n+1]);
+            assert( (debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) && 
+                   "debug_proc_id larger than XMAX * YMAX * NB_PROCS" );
+         }
+         else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
+         {
+            threads_nr = atoi(argv[n+1]);
+            threads_nr = (threads_nr < 1) ? 1 : threads_nr;
+         }
+         else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
+         {
+            frozen_cycles = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
+         {
+            debug_period = atoi(argv[n+1]);
+         }
+         else
+         {
+            std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+            std::cout << "   The order is not important." << std::endl;
+            std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+            std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+            std::cout << "     -DISK pathname_for_disk_image" << std::endl;
+            std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+            std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+            std::cout << "     -THREADS simulator's threads number" << std::endl;
+            std::cout << "     -FROZEN max_number_of_lines" << std::endl;
+            std::cout << "     -PERIOD number_of_cycles between trace" << std::endl;
+            std::cout << "     -MEMCID index_memc_to_be_traced" << std::endl;
+            std::cout << "     -PROCID index_proc_to_be_traced" << std::endl;
+            exit(0);
+         }
+      }
+   }
+
+   // checking hardware parameters
+   assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or
+             (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and
+           "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" );
+
+   assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or
+             (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and
+           "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" );
+
+   assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
+             (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
+           "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
+
+   assert( (NB_DMAS_MAX < 9) and
+           "The NB_DMAS_MAX parameter must be smaller than 9" );
+
+   assert( (NB_TTYS < 15) and
+           "The NB_TTYS parameter must be smaller than 15" );
+
+   assert( (NB_NICS < 9) and
+           "The NB_NICS parameter must be smaller than 9" );
+
+   std::cout << std::endl;
+   std::cout << " - CLUSTER_X    = " << CLUSTER_X << std::endl;
+   std::cout << " - CLUSTER_Y    = " << CLUSTER_Y << std::endl;
+   std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX <<  std::endl;
+   std::cout << " - NB_DMAS_MAX  = " << NB_DMAS_MAX <<  std::endl;
+   std::cout << " - NB_TTYS      = " << NB_TTYS <<  std::endl;
+   std::cout << " - NB_NICS      = " << NB_NICS <<  std::endl;
+   std::cout << " - MEMC_WAYS    = " << MEMC_WAYS << std::endl;
+   std::cout << " - MEMC_SETS    = " << MEMC_SETS << std::endl;
+   std::cout << " - RAM_LATENCY  = " << XRAM_LATENCY << std::endl;
+   std::cout << " - MAX_FROZEN   = " << frozen_cycles << std::endl;
+
+   std::cout << std::endl;
+
+#if USE_OPENMP
+   omp_set_dynamic(false);
+   omp_set_num_threads(threads_nr);
+   std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+   // Define VCI parameters
+   typedef soclib::caba::VciParams<cell_width,
+           plen_width,
+           address_width,
+           error_width,                                   
+           clen_width,
+           rflag_width,
+           srcid_width,
+           pktid_width,
+           trdid_width,
+           wrplen_width> vci_param;
+
+   // Define parameters depending on mesh size
+   size_t   cluster_io_id;
+   size_t   x_width;
+   size_t   y_width;
+
+   if      (CLUSTER_X == 1) x_width = 0;
+   else if (CLUSTER_X == 2) x_width = 1;
+   else if (CLUSTER_X <= 4) x_width = 2;
+   else if (CLUSTER_X <= 8) x_width = 3;
+   else                        x_width = 4;
+
+   if      (CLUSTER_Y == 1) y_width = 0;
+   else if (CLUSTER_Y == 2) y_width = 1;
+   else if (CLUSTER_Y <= 4) y_width = 2;
+   else if (CLUSTER_Y <= 8) y_width = 3;
+   else                        y_width = 4;
+
+   cluster_io_id = 0xBF >> (8 - x_width - y_width);
+
+   /////////////////////
+   //  Mapping Tables
+   /////////////////////
+
+   // direct network
+   MappingTable maptabd(address_width, 
+         IntTab(x_width + y_width, 16 - x_width - y_width), 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         0x00FF0000);
+
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t y = 0; y < CLUSTER_Y; y++)
+      {
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+         std::ostringstream    sh;
+         sh << "d_seg_memc_" << x << "_" << y;
+         maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+
+         std::ostringstream    si;
+         si << "d_seg_xicu_" << x << "_" << y;
+         maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
+
+         std::ostringstream    sd;
+         sd << "d_seg_mdma_" << x << "_" << y;
+         maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
+
+         if ( cluster(x,y) == cluster_io_id )
+         {
+            maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
+            maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
+            maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
+            maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false));
+            maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
+         }
+      }
+   }
+   std::cout << maptabd << std::endl;
+
+   // coherence network
+   // - tgtid_c_proc = srcid_c_proc = local procid
+   // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX
+   MappingTable maptabc(address_width, 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         0x00FF0000);
+
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t y = 0; y < CLUSTER_Y; y++)
+      {
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+         // cleanup requests must be routed to the memory cache
+         std::ostringstream sh;
+         sh << "c_seg_memc_" << x << "_" << y;
+         maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset, 
+                     0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false));
+
+         // update & invalidate requests must be routed to the proper processor
+         for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++) 
+         {
+            std::ostringstream sp;
+            sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+            maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 
+                         0x10 , IntTab(cluster(x,y), p) , false)); 
+         }
+      }
+   }
+   std::cout << maptabc << std::endl;
+
+   // external network
+   MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
+
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t y = 0; y < CLUSTER_Y ; y++)
+      { 
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+         std::ostringstream sh;
+         sh << "x_seg_memc_" << x << "_" << y;
+         maptabx.add(Segment(sh.str(), MEMC_BASE+offset, 
+                     MEMC_SIZE, IntTab(cluster(x,y)), false));
+      }
+   }
+   std::cout << maptabx << std::endl;
+
+   ////////////////////
+   // Signals
+   ///////////////////
+
+   sc_clock      signal_clk("clk");
+   sc_signal<bool>    signal_resetn("resetn");
+
+   // Horizontal inter-clusters DSPIN signals
+   DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2);
+   DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2);
+   DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2);
+   DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2);
+
+   // Vertical inter-clusters DSPIN signals
+   DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2);
+   DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2);
+   DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2);
+   DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2);
+
+   // Mesh boundaries DSPIN signals
+   DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4);
+   DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4);
+   DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4);
+   DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4);
+
+
+   ////////////////////////////
+   //      Loader    
+   ////////////////////////////
+
+#if USE_ALMOS
+   soclib::common::Loader loader(almos_bootloader_pathname,
+                                 almos_archinfo_pathname,
+                                 almos_kernel_pathname);
+#else
+   soclib::common::Loader loader(soft_name);
+#endif
+
+   typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+   proc_iss::set_loader(loader);
+
+   ////////////////////////////
+   // Clusters construction
+   ////////////////////////////
+
+   TsarClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[CLUSTER_X][CLUSTER_Y];
+
+#if USE_OPENMP
+#pragma omp parallel
+    {
+#pragma omp for
+#endif
+        for(size_t i = 0; i  < (CLUSTER_X * CLUSTER_Y); i++)
+        {
+            size_t x = i / CLUSTER_Y;
+            size_t y = i % CLUSTER_Y;
+
+#if USE_OPENMP
+#pragma omp critical
+            {
+#endif
+            std::ostringstream sc;
+            sc << "cluster_" << x << "_" << y;
+            clusters[x][y] = new TsarClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>
+            (
+                sc.str().c_str(),
+                NB_PROCS_MAX,
+                NB_TTYS,  
+                NB_DMAS_MAX, 
+                x,
+                y,
+                cluster(x,y),
+                maptabd,
+                maptabc,
+                maptabx,
+                x_width,
+                y_width,
+                MEMC_TGTID,
+                XICU_TGTID,
+                CDMA_TGTID,
+                FBUF_TGTID,
+                MTTY_TGTID,
+                BROM_TGTID,
+                MNIC_TGTID,
+                BDEV_TGTID,
+                MEMC_WAYS,
+                MEMC_SETS,
+                L1_IWAYS,
+                L1_ISETS,
+                L1_DWAYS,
+                L1_DSETS,
+                XRAM_LATENCY,
+                (cluster(x,y) == cluster_io_id),
+                FBUF_X_SIZE,
+                FBUF_Y_SIZE,
+                disk_name,
+                BDEV_SECTOR_SIZE,
+                NB_NICS,
+                nic_rx_name,
+                nic_tx_name,
+                NIC_TIMEOUT,
+                loader,
+                frozen_cycles,
+                debug_from,
+                debug_ok and (cluster(x,y) == debug_memc_id),
+                debug_ok and (cluster(x,y) == debug_proc_id) 
+            );
+
+            std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
+#if USE_OPENMP
+            } // end critical
+#endif
+        } // end for
+#if USE_OPENMP
+    }
+#endif
+
+   ///////////////////////////////////////////////////////////////
+   //     Net-list 
+   ///////////////////////////////////////////////////////////////
+
+   // Clock & RESET
+   for (size_t x = 0; x < (CLUSTER_X); x++){
+      for (size_t y = 0; y < CLUSTER_Y; y++){
+         clusters[x][y]->p_clk     (signal_clk);
+         clusters[x][y]->p_resetn  (signal_resetn);
+      }
+   }
+
+   // Inter Clusters horizontal connections
+   if (CLUSTER_X > 1){
+      for (size_t x = 0; x < (CLUSTER_X-1); x++){
+         for (size_t y = 0; y < CLUSTER_Y; y++){
+            for (size_t k = 0; k < 2; k++){
+               clusters[x][y]->p_cmd_out[k][EAST]      (signal_dspin_h_cmd_inc[x][y][k]);
+               clusters[x+1][y]->p_cmd_in[k][WEST]     (signal_dspin_h_cmd_inc[x][y][k]);
+               clusters[x][y]->p_cmd_in[k][EAST]       (signal_dspin_h_cmd_dec[x][y][k]);
+               clusters[x+1][y]->p_cmd_out[k][WEST]    (signal_dspin_h_cmd_dec[x][y][k]);
+               clusters[x][y]->p_rsp_out[k][EAST]      (signal_dspin_h_rsp_inc[x][y][k]);
+               clusters[x+1][y]->p_rsp_in[k][WEST]     (signal_dspin_h_rsp_inc[x][y][k]);
+               clusters[x][y]->p_rsp_in[k][EAST]       (signal_dspin_h_rsp_dec[x][y][k]);
+               clusters[x+1][y]->p_rsp_out[k][WEST]    (signal_dspin_h_rsp_dec[x][y][k]);
+            }
+         }
+      }
+   }
+   std::cout << std::endl << "Horizontal connections established" << std::endl;   
+
+   // Inter Clusters vertical connections
+   if (CLUSTER_Y > 1) {
+      for (size_t y = 0; y < (CLUSTER_Y-1); y++){
+         for (size_t x = 0; x < CLUSTER_X; x++){
+            for (size_t k = 0; k < 2; k++){
+               clusters[x][y]->p_cmd_out[k][NORTH]     (signal_dspin_v_cmd_inc[x][y][k]);
+               clusters[x][y+1]->p_cmd_in[k][SOUTH]    (signal_dspin_v_cmd_inc[x][y][k]);
+               clusters[x][y]->p_cmd_in[k][NORTH]      (signal_dspin_v_cmd_dec[x][y][k]);
+               clusters[x][y+1]->p_cmd_out[k][SOUTH]   (signal_dspin_v_cmd_dec[x][y][k]);
+               clusters[x][y]->p_rsp_out[k][NORTH]     (signal_dspin_v_rsp_inc[x][y][k]);
+               clusters[x][y+1]->p_rsp_in[k][SOUTH]    (signal_dspin_v_rsp_inc[x][y][k]);
+               clusters[x][y]->p_rsp_in[k][NORTH]      (signal_dspin_v_rsp_dec[x][y][k]);
+               clusters[x][y+1]->p_rsp_out[k][SOUTH]   (signal_dspin_v_rsp_dec[x][y][k]);
+            }
+         }
+      }
+   }
+   std::cout << "Vertical connections established" << std::endl;
+
+   // East & West boundary cluster connections
+   for (size_t y = 0; y < CLUSTER_Y; y++)
+   {
+      for (size_t k = 0; k < 2; k++)
+      {
+         clusters[0][y]->p_cmd_in[k][WEST]          (signal_dspin_false_cmd_in[0][y][k][WEST]);
+         clusters[0][y]->p_cmd_out[k][WEST]         (signal_dspin_false_cmd_out[0][y][k][WEST]);
+         clusters[0][y]->p_rsp_in[k][WEST]          (signal_dspin_false_rsp_in[0][y][k][WEST]);
+         clusters[0][y]->p_rsp_out[k][WEST]         (signal_dspin_false_rsp_out[0][y][k][WEST]);
+
+         clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST]     (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]);
+         clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST]    (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]);
+         clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST]     (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]);
+         clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST]    (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]);
+      }
+   }
+
+   // North & South boundary clusters connections
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t k = 0; k < 2; k++)
+      {
+         clusters[x][0]->p_cmd_in[k][SOUTH]         (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
+         clusters[x][0]->p_cmd_out[k][SOUTH]        (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
+         clusters[x][0]->p_rsp_in[k][SOUTH]         (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
+         clusters[x][0]->p_rsp_out[k][SOUTH]        (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
+
+         clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH]    (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]);
+         clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH]   (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]);
+         clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH]    (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]);
+         clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH]   (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]);
+      }
+   }
+
+
+   ////////////////////////////////////////////////////////
+   //   Simulation
+   ///////////////////////////////////////////////////////
+
+   sc_start(sc_core::sc_time(0, SC_NS));
+   signal_resetn = false;
+
+   // network boundaries signals
+   for (size_t x = 0; x < CLUSTER_X ; x++){
+      for (size_t y = 0; y < CLUSTER_Y ; y++){
+         for (size_t k = 0; k < 2; k++){
+            for (size_t a = 0; a < 4; a++){
+               signal_dspin_false_cmd_in[x][y][k][a].write = false;
+               signal_dspin_false_cmd_in[x][y][k][a].read = true;
+               signal_dspin_false_cmd_out[x][y][k][a].write = false;
+               signal_dspin_false_cmd_out[x][y][k][a].read = true;
+
+               signal_dspin_false_rsp_in[x][y][k][a].write = false;
+               signal_dspin_false_rsp_in[x][y][k][a].read = true;
+               signal_dspin_false_rsp_out[x][y][k][a].write = false;
+               signal_dspin_false_rsp_out[x][y][k][a].read = true;
+            }
+         }
+      }
+   }
+
+   sc_start(sc_core::sc_time(1, SC_NS));
+   signal_resetn = true;
+
+   for (size_t n = 1; n < ncycles; n++)
+   {
+
+      if (debug_ok and (n > debug_from) and (n % debug_period == 0))
+      {
+         std::cout << "****************** cycle " << std::dec << n ;
+         std::cout << " ************************************************" << std::endl;
+
+             //clusters[0][0]->memc->print_trace();
+         // trace proc[debug_proc_id] 
+/*
+         if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) )
+         {
+             size_t proc_x = debug_proc_id / CLUSTER_Y;
+             size_t proc_y = debug_proc_id % CLUSTER_Y;
+
+             clusters[proc_x][proc_y]->proc[0]->print_trace();
+
+             clusters[proc_x][proc_y]->signal_vci_ini_d_proc[0].print_trace("proc_ini_d");
+             clusters[proc_x][proc_y]->signal_vci_ini_c_proc[0].print_trace("proc_ini_c");
+             clusters[proc_x][proc_y]->signal_vci_tgt_c_proc[0].print_trace("proc_tgt_c");
+         }
+
+         // trace memc[debug_memc_id] 
+         if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) )
+         {
+             size_t memc_x = debug_memc_id / CLUSTER_Y;
+             size_t memc_y = debug_memc_id % CLUSTER_Y;
+
+             clusters[memc_x][memc_y]->memc->print_trace();
+
+             clusters[memc_x][memc_y]->signal_vci_tgt_d_memc.print_trace("memc_tgt_d");
+             clusters[memc_x][memc_y]->signal_vci_ini_c_memc.print_trace("memc_ini_c");
+             clusters[memc_x][memc_y]->signal_vci_tgt_c_memc.print_trace("memc_tgt_c");
+         }
+
+// clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0");
+// clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1");
+// clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0");
+// clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1");
+
+// if ( clusters[1][1]->signal_irq_mdma[0].read() ) 
+//    std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl;
+// if ( clusters[1][1]->signal_proc_it[0].read() )
+//    std::cout <<  " IRQ_PROC_1_1 activated" << std::endl << std::endl;
+
+// trace ioc component 
+// size_t io_x   = cluster_io_id / CLUSTER_Y;
+// size_t io_y   = cluster_io_id % CLUSTER_Y;
+// clusters[io_x][io_y]->bdev->print_trace();
+// clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d  ");
+// clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d  ");
+
+// clusters[1][1]->mdma->print_trace();
+// clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("mdma_1_1_tgt_d  ");
+// clusters[1][1]->signal_vci_ini_d_mdma.print_trace("mdma_1_1_ini_d  ");
+*/
+      }
+
+      sc_start(sc_core::sc_time(1, SC_NS));
+   }
+   return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+   try {
+      return _main(argc, argv);
+   } catch (std::exception &e) {
+      std::cout << e.what() << std::endl;
+   } catch (...) {
+      std::cout << "Unknown exception occured" << std::endl;
+      throw;
+   }
+   return 1;
+}
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
Index: /branches/v5/platforms/tsar_generic_mmu/top.desc
===================================================================
--- /branches/v5/platforms/tsar_generic_mmu/top.desc	(revision 306)
+++ /branches/v5/platforms/tsar_generic_mmu/top.desc	(revision 306)
@@ -0,0 +1,23 @@
+# -*- python -*-
+
+todo = Platform('caba', 'top.cpp',
+	uses = [
+            Uses('caba:tsar_cluster_mmu', 
+                 iss_t = 'common:gdb_iss', 
+                 gdb_iss_t = 'common:mips32el', 
+                 cmd_width = 40, 
+                 rsp_width = 33),
+	        Uses('common:elf_file_loader'),
+            Uses('common:plain_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1,
+)
Index: /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/metadata/tsar_cluster_mmu.sd
===================================================================
--- /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/metadata/tsar_cluster_mmu.sd	(revision 306)
+++ /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/metadata/tsar_cluster_mmu.sd	(revision 306)
@@ -0,0 +1,49 @@
+# -*- python -*-
+
+Module('caba:tsar_cluster_mmu',
+	classname = 'soclib::caba::TsarClusterMmu',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		parameter.Int('cmd_width'),
+		parameter.Int('rsp_width'),
+		],
+	header_files = [ '../source/include/tsar_cluster_mmu.h', ],
+	implementation_files = [ '../source/src/tsar_cluster_mmu.cpp', ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+		Uses('caba:vci_cc_vcache_wrapper', 
+                     iss_t = 'common:gdb_iss', 
+                     gdb_iss_t = 'common:mips32el'),
+		Uses('caba:vci_mem_cache'),
+		Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_xicu'),
+        Uses('caba:vci_local_crossbar'),
+        Uses('caba:virtual_dspin_router', 
+                     flit_width = parameter.Reference('cmd_width')),
+        Uses('caba:virtual_dspin_router', 
+                     flit_width = parameter.Reference('rsp_width')),
+        Uses('caba:vci_vdspin_target_wrapper', 
+                     dspin_cmd_width = parameter.Reference('cmd_width'), 
+                     dspin_rsp_width = parameter.Reference('rsp_width')),
+        Uses('caba:vci_vdspin_initiator_wrapper', 
+                     dspin_cmd_width = parameter.Reference('cmd_width'), 
+                     dspin_rsp_width = parameter.Reference('rsp_width')),
+		Uses('caba:vci_multi_tty'),
+		Uses('caba:vci_framebuffer'),
+		Uses('caba:vci_multi_nic'),
+		Uses('caba:vci_block_device_tsar_v4'),
+		Uses('caba:vci_multi_dma'),
+		Uses('common:elf_file_loader'),
+		],
+	ports = [
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 
+		Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')),
+		],
+)
Index: /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/include/tsar_cluster_mmu.h
===================================================================
--- /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/include/tsar_cluster_mmu.h	(revision 306)
+++ /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/include/tsar_cluster_mmu.h	(revision 306)
@@ -0,0 +1,171 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsar_cluster_mmu.h
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef SOCLIB_CABA_TSAR_CLUSTER_MMU_H
+#define SOCLIB_CABA_TSAR_CLUSTER_MMU_H
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_xicu.h"
+#include "vci_local_crossbar.h"
+#include "virtual_dspin_router.h"
+#include "vci_vdspin_target_wrapper.h"
+#include "vci_vdspin_initiator_wrapper.h"
+#include "vci_multi_tty.h"
+#include "vci_multi_nic.h"
+#include "vci_block_device_tsar_v4.h"
+#include "vci_framebuffer.h"
+#include "vci_multi_dma.h"
+#include "vci_mem_cache.h"
+#include "vci_cc_vcache_wrapper.h"
+
+namespace soclib {
+namespace caba	{
+
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+class TsarClusterMmu 
+///////////////////////////////////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+
+  public:
+
+	// Ports
+    sc_in<bool>                             		p_clk;
+    sc_in<bool>                             		p_resetn;
+	soclib::caba::DspinOutput<cmd_width>   			**p_cmd_out;
+	soclib::caba::DspinInput<cmd_width>    			**p_cmd_in;
+    soclib::caba::DspinOutput<rsp_width>           	**p_rsp_out;
+    soclib::caba::DspinInput<rsp_width>            	**p_rsp_in;
+
+    // interrupt signals
+	sc_signal<bool>     	signal_false;
+	sc_signal<bool> 		signal_proc_it[8];
+	sc_signal<bool> 		signal_irq_mdma[8];
+	sc_signal<bool>			signal_irq_mtty[23];
+	sc_signal<bool> 		signal_irq_mnic_rx[8];	// unused
+	sc_signal<bool> 		signal_irq_mnic_tx[8];	// unused
+	sc_signal<bool> 		signal_irq_bdev;
+	
+	// DSPIN signals between DSPIN routers and VCI/DSPIN wrappers
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_c;
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_c; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_c;
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_c;
+
+	// VCI signals between VCI/DSPIN wrappers and local crossbars
+	VciSignals<vci_param>  		signal_vci_l2g_d; 
+	VciSignals<vci_param>  		signal_vci_g2l_d; 
+	VciSignals<vci_param>  		signal_vci_l2g_c; 
+	VciSignals<vci_param>  		signal_vci_g2l_c; 
+
+	// Direct VCI signals
+	VciSignals<vci_param> 		signal_vci_ini_d_proc[4]; 
+	VciSignals<vci_param>  		signal_vci_ini_d_bdev; 
+	VciSignals<vci_param>  		signal_vci_ini_d_mdma; 
+
+	VciSignals<vci_param>		signal_vci_tgt_d_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mtty;
+	VciSignals<vci_param> 		signal_vci_tgt_d_xicu;
+	VciSignals<vci_param> 		signal_vci_tgt_d_bdev;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mdma;
+	VciSignals<vci_param> 		signal_vci_tgt_d_brom;
+	VciSignals<vci_param> 		signal_vci_tgt_d_fbuf;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mnic;
+
+	// Coherence VCi signals
+	VciSignals<vci_param> 		signal_vci_ini_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_tgt_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_ini_c_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_c_memc;
+
+	// external RAM VCI signal
+	VciSignals<vci_param> 		signal_vci_xram;
+	
+    // Components
+
+    VciCcVCacheWrapper<vci_param, iss_t>*                 	proc[8];
+    VciMemCache<vci_param>*                               	memc;
+    VciXicu<vci_param>*                                     	xicu;
+    VciLocalCrossbar<vci_param>*                                xbard;
+    VciLocalCrossbar<vci_param>*                                xbarc;
+    VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*      tgtwrapperd;
+    VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*   iniwrapperd;
+    VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*      tgtwrapperc;
+    VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*   iniwrapperc;
+    VirtualDspinRouter<cmd_width>*                              cmdrouter;
+    VirtualDspinRouter<rsp_width>*	                        	rsprouter;
+    VciSimpleRam<vci_param>*                                    brom;
+    VciMultiTty<vci_param>*                                     mtty;
+    VciFrameBuffer<vci_param>*                                  fbuf;
+    VciMultiNic<vci_param>*                                     mnic;
+    VciBlockDeviceTsarV4<vci_param>*                            bdev;
+    VciMultiDma<vci_param>*                                     mdma;
+    VciSimpleRam<vci_param>*                                    xram;
+
+	TsarClusterMmu(sc_module_name                     insname,
+                     size_t                             nb_procs,      // number of processors 
+                     size_t                             nb_ttys,       // number of TTY terminals 
+                     size_t                             nb_dmas,       // number of DMA channels 
+                     size_t                             x,             // x coordinate
+                     size_t                             y,             // y coordinate
+                     size_t                             cluster,       // y + ymax*x
+                     const soclib::common::MappingTable &mtd,          // direct mapping table
+                     const soclib::common::MappingTable &mtc,          // coherence mapping table
+                     const soclib::common::MappingTable &mtx,          // xram mapping table
+                     size_t	                            x_width,       // x field number of bits
+                     size_t	                            y_width,       // y field number of bits
+                     size_t	                            tgtid_memc,
+                     size_t	                            tgtid_xicu,
+                     size_t                             tgtid_mdma,
+                     size_t	                            tgtid_fbuf,
+                     size_t                             tgtid_mtty,
+                     size_t                             tgtid_brom,
+                     size_t                             tgtid_mnic,
+                     size_t                             tgtid_bdev,
+                     size_t                             memc_ways,
+                     size_t                             memc_sets,
+                     size_t                             l1_i_ways,
+                     size_t                             l1_i_sets, 
+                     size_t                             l1_d_ways,
+                     size_t                             l1_d_sets,	
+                     size_t                             xram_latency,  // external ram latency
+                     bool                               io,	           // I/O cluster if true
+                     size_t                             xfb,           // frame buffer pixels
+                     size_t                             yfb,           // frame buffer lines
+                     char*                              disk_name,     // virtual disk name for BDEV
+                     size_t                             block_size,    // block size for BDEV
+                     size_t                             nic_channels,  // number of channels
+                     char*                              nic_rx_name,   // file name rx packets
+                     char*                              nic_tx_name,   // file name tx packets
+                     uint32_t							nic_timeout,   // number of cycles
+			         const Loader                       &loader,       // loader for BROM
+                     uint32_t                           frozen_cycles, // max frozen cycles
+                     uint32_t                           start_debug_cycle,
+                     bool                               memc_debug_ok, 
+                     bool                               proc_debug_ok); 
+
+	~TsarClusterMmu();
+};
+}}
+
+#endif
Index: /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/src/tsar_cluster_mmu.cpp
===================================================================
--- /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/src/tsar_cluster_mmu.cpp	(revision 306)
+++ /branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/src/tsar_cluster_mmu.cpp	(revision 306)
@@ -0,0 +1,575 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsar_cluster_mmu.c
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+// This file define a TSAR cluster architecture with virtual memory:
+// - It uses the virtual_dspin_router as distributed global interconnect 
+// - It uses the vci_local_crossbar as local interconnect 
+// - It uses the vci_cc_vcache_wrapper
+// - It uses the vci_mem_cache
+// - It contains a private RAM with a variable latency to emulate the L3 cache
+// - It can contains 1, 2 or 4 processors
+// - Each processor has a private dma channel (vci_multi_dma)
+// - It uses the vci_xicu interrupt controller
+// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster 
+//   containing address 0xBFC00000.
+// - The Multi-TTY component controls up to 15 terminals. 
+// - Each Multi-DMA component controls up to 8 DMA channels.
+// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
+// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
+// - The BDEV IRQ is connected to IRQ_IN[31]
+////////////////////////////////////////////////////////////////////////////////// 
+
+#include "../include/tsar_cluster_mmu.h"
+
+namespace soclib {
+namespace caba  {
+
+//////////////////////////////////////////////////////////////////////////
+//                 Constructor
+//////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarClusterMmu(
+         sc_module_name                     insname,
+         size_t                             nb_procs,
+         size_t                             nb_ttys,
+         size_t                             nb_dmas,
+         size_t                             x_id,
+         size_t                             y_id,
+         size_t                             cluster_id,
+         const soclib::common::MappingTable &mtd,
+         const soclib::common::MappingTable &mtc, 
+         const soclib::common::MappingTable &mtx, 
+         size_t                             x_width,
+         size_t                             y_width,
+         size_t                             tgtid_memc,
+         size_t                             tgtid_xicu,
+         size_t                             tgtid_mdma,
+         size_t                             tgtid_fbuf,
+         size_t                             tgtid_mtty,
+         size_t                             tgtid_brom,
+         size_t                             tgtid_mnic,
+         size_t                             tgtid_bdev,
+         size_t                             memc_ways,
+         size_t                             memc_sets,
+         size_t                             l1_i_ways,
+         size_t                             l1_i_sets,
+         size_t                             l1_d_ways,
+         size_t                             l1_d_sets,
+         size_t                             xram_latency,
+         bool                               io,
+         size_t                             xfb,
+         size_t                             yfb,
+         char*                              disk_name,
+         size_t                             block_size,
+         size_t                             nic_channels,
+         char*                              nic_rx_name,
+         char*                              nic_tx_name,
+         uint32_t                           nic_timeout,
+         const Loader                      &loader,
+         uint32_t                           frozen_cycles,
+         uint32_t                           debug_start_cycle,
+         bool                               memc_debug_ok,
+         bool                               proc_debug_ok)
+            : soclib::caba::BaseModule(insname),
+            p_clk("clk"),
+            p_resetn("resetn")
+
+{
+    // Vectors of ports definition
+
+    p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
+    p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
+    p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
+    p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
+
+    // Components definition 
+
+    // on direct network : local srcid[proc] in [0..nb_procs-1]
+    // on direct network : local srcid[mdma] = nb_procs
+    // on direct network : local srcid[bdev] = nb_procs + 1
+
+    // on coherence network : local srcid[proc] in [0...nb_procs-1]
+    // on coherence network : local srcid[memc] = nb_procs
+
+    std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
+
+    for (size_t p = 0; p < nb_procs; p++)
+    { 
+        std::ostringstream sproc;
+        sproc << "proc_" << x_id << "_" << y_id << "_" << p;
+        proc[p] = new VciCcVCacheWrapper<vci_param, iss_t>(
+                      sproc.str().c_str(),
+                      cluster_id*nb_procs + p,
+                      mtd,                            // Mapping Table Direct
+                      mtc,                            // Mapping Table Coherence
+                      IntTab(cluster_id,p),           // SRCID_D
+                      IntTab(cluster_id,p),           // SRCID_C
+                      IntTab(cluster_id,p),           // TGTID_C
+                      8,                              // ITLB ways
+                      8,                              // ITLB sets
+                      8,                              // DTLB ways
+                      8,                              // DTLB sets
+                      l1_i_ways,l1_i_sets,16,         // ICACHE size
+                      l1_d_ways,l1_d_sets,16,         // DCACHE size
+                      4,                              // WBUF nlines
+                      4,                              // WBUF nwords
+                      x_width,
+                      y_width,
+                      nb_procs,                       // MEMC local index
+                      frozen_cycles,                  // max frozen cycles
+                      debug_start_cycle,
+                      proc_debug_ok);
+    }
+
+    std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream smemc;
+    smemc << "memc_" << x_id << "_" << y_id;
+    memc = new VciMemCache<vci_param>(
+                     smemc.str().c_str(),
+                     mtd, mtc, mtx,
+                     IntTab(cluster_id),              // SRCID_X
+                     IntTab(cluster_id, nb_procs),    // SRCID_C
+                     IntTab(cluster_id, tgtid_memc),  // TGTID_D
+                     IntTab(cluster_id, nb_procs),    // TGTID_C
+                     memc_ways, memc_sets, 16,        // CACHE SIZE
+                     //4096,                            // HEAP SIZE
+                     256,                            // HEAP SIZE
+                     8,                               // TRANSACTION TABLE DEPTH
+                     8,                               // UPDATE TABLE DEPTH
+                     debug_start_cycle,
+                     memc_debug_ok);
+
+    std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sxram;
+    sxram << "xram_" << x_id << "_" << y_id;
+    xram = new VciSimpleRam<vci_param>(
+                     sxram.str().c_str(),
+                     IntTab(cluster_id),
+                     mtx,
+                     loader,
+                     xram_latency);
+
+    std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sicu;
+    sicu << "xicu_" << x_id << "_" << y_id;
+    xicu = new VciXicu<vci_param>(
+                     sicu.str().c_str(),
+                     mtd,                               // mapping table
+                     IntTab(cluster_id, tgtid_xicu),    // TGTID_D
+                     nb_procs,                          // number of timer IRQs
+                     32,                                // number of hard IRQs
+                     0,                                 // number of soft IRQs
+                     nb_procs);                         // number of output IRQs
+
+    std::cout << "  - building dma_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sdma;
+    sdma << "dma_" << x_id << "_" << y_id;
+    mdma = new VciMultiDma<vci_param>(
+                     sdma.str().c_str(),
+                     mtd,
+                     IntTab(cluster_id, nb_procs),        // SRCID
+                     IntTab(cluster_id, tgtid_mdma),      // TGTID
+                     64,                                  // burst size
+                     nb_dmas);                           // number of IRQs
+
+    std::cout << "  - building xbard_" << x_id << "_" << y_id << std::endl;
+
+    size_t nb_direct_initiators      = nb_procs + 1;
+    size_t nb_direct_targets         = 3;
+    if ( io )
+    {
+        nb_direct_initiators         = nb_procs + 2;
+        nb_direct_targets            = 8;
+    }
+    std::ostringstream sd;
+    sd << "xbard_" << x_id << "_" << y_id;
+    xbard = new VciLocalCrossbar<vci_param>(
+                     sd.str().c_str(),
+                     mtd,
+                     IntTab(cluster_id),           // cluster initiator index
+                     IntTab(cluster_id),           // cluster target index
+                     nb_direct_initiators,         // number of initiators
+                     nb_direct_targets);           // number of targets      
+
+    std::cout << "  - building xbarc_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sc;
+    sc << "xbarc_" << x_id << "_" << y_id;
+    xbarc = new VciLocalCrossbar<vci_param>(
+                     sc.str().c_str(),
+                     mtc,
+                     IntTab(cluster_id),           // cluster initiator index
+                     IntTab(cluster_id),           // cluster target index
+                     nb_procs + 1,                 // number of initiators
+                     nb_procs + 1);                // number of targets
+
+    std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream wid;
+    wid << "iniwrapperd_" << x_id << "_" << y_id;
+    iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                     wid.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+    std::ostringstream wtd;
+    wtd << "tgtwrapperd_" << x_id << "_" << y_id;
+    tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+                     wtd.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+    std::ostringstream wic;
+    wic << "iniwrapperc_" << x_id << "_" << y_id;
+    iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                     wic.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+    std::ostringstream wtc;
+    wtc << "tgtwrapperc_" << x_id << "_" << y_id;
+    tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+    wtc.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+    std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream scmd;
+    scmd << "cmdrouter_" << x_id << "_" << y_id;
+    cmdrouter = new VirtualDspinRouter<cmd_width>(
+                     scmd.str().c_str(),
+                     x_id,y_id,                    // coordinate in the mesh
+                     x_width, y_width,             // x & y fields width
+                     4,4);                         // input & output fifo depths
+
+    std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream srsp;
+    srsp << "rsprouter_" << x_id << "_" << y_id;
+    rsprouter = new VirtualDspinRouter<rsp_width>(
+                     srsp.str().c_str(),
+                     x_id,y_id,                    // coordinates in mesh
+                     x_width, y_width,             // x & y fields width
+                     4,4);                         // input & output fifo depths
+
+    // IO cluster components
+    if ( io )
+    {
+        std::cout << "  - building brom" << std::endl;
+
+        brom = new VciSimpleRam<vci_param>(
+                        "brom",
+                        IntTab(cluster_id, tgtid_brom),
+                        mtd,
+                        loader);
+
+        std::cout << "  - building fbuf" << std::endl;
+
+        fbuf = new VciFrameBuffer<vci_param>(
+                        "fbuf",
+                        IntTab(cluster_id, tgtid_fbuf),
+                        mtd,
+                        xfb, yfb); 
+
+        std::cout << "  - building fbuf" << std::endl;
+
+        bdev = new VciBlockDeviceTsarV4<vci_param>(
+                        "bdev",
+                        mtd,
+                        IntTab(cluster_id, nb_procs+1),
+                        IntTab(cluster_id, tgtid_bdev),
+                        disk_name,
+                        block_size,
+                        64);            // burst size
+
+        std::cout << "  - building mnic" << std::endl;
+
+        mnic = new VciMultiNic<vci_param>(
+                        "mnic",
+                        IntTab(cluster_id, tgtid_mnic),
+                        mtd,
+                        nic_channels,
+                        nic_rx_name,
+                        nic_tx_name,
+                        0,   // default mac address MAC4
+                        0 ); // default mac address MAC2
+
+        std::cout << "  - building mtty" << std::endl;
+
+        std::vector<std::string> vect_names;
+        for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
+        {
+            std::ostringstream term_name;
+            term_name <<  "term" << tid;
+            vect_names.push_back(term_name.str().c_str());
+        }
+        mtty = new VciMultiTty<vci_param>(
+                        "mtty",
+                        IntTab(cluster_id, tgtid_mtty),
+                        mtd, 
+                        vect_names);
+    }
+
+    std::cout << std::endl;
+
+    ////////////////////////////////////
+    // Connections are defined here
+    ////////////////////////////////////
+
+    // CMDROUTER and RSPROUTER
+    cmdrouter->p_clk                        (this->p_clk);
+    cmdrouter->p_resetn                     (this->p_resetn);
+    rsprouter->p_clk                        (this->p_clk);
+    rsprouter->p_resetn                     (this->p_resetn);
+    for (int x = 0; x < 2; x++)
+    {
+        for(int y = 0; y < 4; y++)
+        {
+            cmdrouter->p_out[x][y]          (this->p_cmd_out[x][y]);
+            cmdrouter->p_in[x][y]           (this->p_cmd_in[x][y]);
+            rsprouter->p_out[x][y]          (this->p_rsp_out[x][y]);
+            rsprouter->p_in[x][y]           (this->p_rsp_in[x][y]);
+        }
+    }
+
+    cmdrouter->p_out[0][4]                  (signal_dspin_cmd_g2l_d);
+    cmdrouter->p_out[1][4]                  (signal_dspin_cmd_g2l_c);
+    cmdrouter->p_in[0][4]                   (signal_dspin_cmd_l2g_d);
+    cmdrouter->p_in[1][4]                   (signal_dspin_cmd_l2g_c);
+
+    rsprouter->p_out[0][4]                  (signal_dspin_rsp_g2l_d);
+    rsprouter->p_out[1][4]                  (signal_dspin_rsp_g2l_c);
+    rsprouter->p_in[0][4]                   (signal_dspin_rsp_l2g_d);
+    rsprouter->p_in[1][4]                   (signal_dspin_rsp_l2g_c);
+
+    std::cout << "  - CMD & RSP routers connected" << std::endl;
+
+    // VCI/DSPIN WRAPPERS
+    iniwrapperd->p_clk                      (this->p_clk);
+    iniwrapperd->p_resetn                   (this->p_resetn);
+    iniwrapperd->p_vci                      (signal_vci_l2g_d);
+    iniwrapperd->p_dspin_out                (signal_dspin_cmd_l2g_d);
+    iniwrapperd->p_dspin_in                 (signal_dspin_rsp_g2l_d);
+
+    tgtwrapperd->p_clk                      (this->p_clk);
+    tgtwrapperd->p_resetn                   (this->p_resetn);
+    tgtwrapperd->p_vci                      (signal_vci_g2l_d);
+    tgtwrapperd->p_dspin_out                (signal_dspin_rsp_l2g_d);
+    tgtwrapperd->p_dspin_in                 (signal_dspin_cmd_g2l_d);
+
+    iniwrapperc->p_clk                      (this->p_clk);
+    iniwrapperc->p_resetn                   (this->p_resetn);
+    iniwrapperc->p_vci                      (signal_vci_l2g_c);
+    iniwrapperc->p_dspin_out                (signal_dspin_cmd_l2g_c);
+    iniwrapperc->p_dspin_in                 (signal_dspin_rsp_g2l_c);
+
+    tgtwrapperc->p_clk                      (this->p_clk);
+    tgtwrapperc->p_resetn                   (this->p_resetn);
+    tgtwrapperc->p_vci                      (signal_vci_g2l_c);
+    tgtwrapperc->p_dspin_out                (signal_dspin_rsp_l2g_c);
+    tgtwrapperc->p_dspin_in                 (signal_dspin_cmd_g2l_c);
+
+    std::cout << "  - VCI/DSPIN wrappers connected" << std::endl;
+
+    // CROSSBAR direct
+    xbard->p_clk                            (this->p_clk);
+    xbard->p_resetn                         (this->p_resetn);
+    xbard->p_initiator_to_up                (signal_vci_l2g_d);
+    xbard->p_target_to_up                   (signal_vci_g2l_d);
+
+    xbard->p_to_target[tgtid_memc]          (signal_vci_tgt_d_memc);
+    xbard->p_to_target[tgtid_xicu]          (signal_vci_tgt_d_xicu);
+    xbard->p_to_target[tgtid_mdma]          (signal_vci_tgt_d_mdma);
+
+    xbard->p_to_initiator[nb_procs]         (signal_vci_ini_d_mdma);
+
+    for (size_t p = 0; p < nb_procs; p++)
+    {
+        xbard->p_to_initiator[p]            (signal_vci_ini_d_proc[p]);
+    }
+
+    if ( io )
+    {
+        xbard->p_to_target[tgtid_mtty]      (signal_vci_tgt_d_mtty);
+        xbard->p_to_target[tgtid_brom]      (signal_vci_tgt_d_brom);
+        xbard->p_to_target[tgtid_bdev]      (signal_vci_tgt_d_bdev);
+        xbard->p_to_target[tgtid_fbuf]      (signal_vci_tgt_d_fbuf);
+        xbard->p_to_target[tgtid_mnic]      (signal_vci_tgt_d_mnic);
+
+        xbard->p_to_initiator[nb_procs+1]   (signal_vci_ini_d_bdev);
+    }
+
+    std::cout << "  - Direct crossbar connected" << std::endl;
+
+    // CROSSBAR coherence
+    xbarc->p_clk                            (this->p_clk);
+    xbarc->p_resetn                         (this->p_resetn);
+    xbarc->p_initiator_to_up                (signal_vci_l2g_c);
+    xbarc->p_target_to_up                   (signal_vci_g2l_c);
+    xbarc->p_to_initiator[nb_procs]         (signal_vci_ini_c_memc);
+    xbarc->p_to_target[nb_procs]            (signal_vci_tgt_c_memc);
+    for (size_t p = 0; p < nb_procs; p++) 
+    {
+        xbarc->p_to_target[p]               (signal_vci_tgt_c_proc[p]);
+        xbarc->p_to_initiator[p]            (signal_vci_ini_c_proc[p]);
+    }
+
+    std::cout << "  - Coherence crossbar connected" << std::endl;
+
+    // Processors
+    for (size_t p = 0; p < nb_procs; p++)
+    {
+        proc[p]->p_clk                      (this->p_clk);
+        proc[p]->p_resetn                   (this->p_resetn);
+        proc[p]->p_vci_ini_d                (signal_vci_ini_d_proc[p]);
+        proc[p]->p_vci_ini_c                (signal_vci_ini_c_proc[p]);
+        proc[p]->p_vci_tgt_c                (signal_vci_tgt_c_proc[p]);
+        proc[p]->p_irq[0]                   (signal_proc_it[p]);
+        for ( size_t j = 1 ; j < 6 ; j++)
+        {
+            proc[p]->p_irq[j]               (signal_false);
+        }
+    }
+
+    std::cout << "  - Processors connected" << std::endl;
+
+    // XICU
+    xicu->p_clk                     	(this->p_clk);
+    xicu->p_resetn                  	(this->p_resetn);
+    xicu->p_vci                     	(signal_vci_tgt_d_xicu);
+    for ( size_t p=0 ; p<nb_procs ; p++)
+    {
+        xicu->p_irq[p]              	(signal_proc_it[p]);
+    }
+    for ( size_t i=0 ; i<32 ; i++)
+    {
+        if ( io ) // I/O cluster
+        {
+            if      (i < 8)                  xicu->p_hwi[i] (signal_false);
+            else if (i < (8 + nb_dmas))      xicu->p_hwi[i]	(signal_irq_mdma[i-8]);
+            else if (i < 16)                 xicu->p_hwi[i] (signal_false);
+            else if (i < (16 + nb_ttys))     xicu->p_hwi[i] (signal_irq_mtty[i-16]);
+            else if (i < 31)                 xicu->p_hwi[i]	(signal_false);
+            else                             xicu->p_hwi[i] (signal_irq_bdev);
+        }
+        else      // other clusters
+        {
+            if      (i < 8)                  xicu->p_hwi[i] (signal_false);
+            else if (i < (8 + nb_dmas))      xicu->p_hwi[i]	(signal_irq_mdma[i-8]);
+            else                             xicu->p_hwi[i]	(signal_false);
+        }
+    }
+
+    std::cout << "  - XICU connected" << std::endl;
+
+    // MEMC
+    memc->p_clk                     	(this->p_clk);
+    memc->p_resetn                  	(this->p_resetn);
+    memc->p_vci_ixr                 	(signal_vci_xram);
+    memc->p_vci_tgt                 	(signal_vci_tgt_d_memc);
+    memc->p_vci_ini                 	(signal_vci_ini_c_memc);
+    memc->p_vci_tgt_cleanup         	(signal_vci_tgt_c_memc);
+
+    std::cout << "  - MEMC connected" << std::endl;
+
+    // XRAM
+    xram->p_clk                     	(this->p_clk);
+    xram->p_resetn                  	(this->p_resetn);
+    xram->p_vci                 	      (signal_vci_xram);
+
+    std::cout << "  - XRAM connected" << std::endl;
+
+    // CDMA
+    mdma->p_clk                       	(this->p_clk);
+    mdma->p_resetn                    	(this->p_resetn);
+    mdma->p_vci_target                	(signal_vci_tgt_d_mdma);
+    mdma->p_vci_initiator             	(signal_vci_ini_d_mdma);
+    for (size_t i=0 ; i<nb_dmas ; i++)
+    {
+        mdma->p_irq[i]                  (signal_irq_mdma[i]);
+    }
+
+    std::cout << "  - MDMA connected" << std::endl;
+
+	 // Components in I/O cluster
+
+	 if ( io )
+	 {
+        // BDEV            
+	     bdev->p_clk                    (this->p_clk);
+        bdev->p_resetn                 (this->p_resetn);
+        bdev->p_irq                    (signal_irq_bdev);
+        bdev->p_vci_target             (signal_vci_tgt_d_bdev);
+        bdev->p_vci_initiator          (signal_vci_ini_d_bdev);
+
+        std::cout << "  - BDEV connected" << std::endl;
+
+        // FBUF
+        fbuf->p_clk                    (this->p_clk);
+        fbuf->p_resetn                 (this->p_resetn);
+        fbuf->p_vci                    (signal_vci_tgt_d_fbuf);
+
+        std::cout << "  - FBUF connected" << std::endl;
+
+        // MNIC
+        mnic->p_clk                    (this->p_clk);
+        mnic->p_resetn                 (this->p_resetn);
+        mnic->p_vci                    (signal_vci_tgt_d_mnic);
+        for ( size_t i=0 ; i<nic_channels ; i++ )
+        {
+            mnic->p_rx_irq[i]          (signal_irq_mnic_rx[i]);
+            mnic->p_tx_irq[i]          (signal_irq_mnic_tx[i]);
+        }
+
+        std::cout << "  - MNIC connected" << std::endl;
+
+        // BROM
+        brom->p_clk                    (this->p_clk);
+        brom->p_resetn                 (this->p_resetn);
+        brom->p_vci                    (signal_vci_tgt_d_brom);
+
+        std::cout << "  - BROM connected" << std::endl;
+
+        // MTTY
+        mtty->p_clk                    (this->p_clk);
+        mtty->p_resetn                 (this->p_resetn);
+        mtty->p_vci                    (signal_vci_tgt_d_mtty);
+        for ( size_t i=0 ; i<nb_ttys ; i++ )
+        {
+            mtty->p_irq[i]           	(signal_irq_mtty[i]);
+        }
+
+        std::cout << "  - MTTY connected" << std::endl;
+   }
+} // end constructor
+
+///////////////////////////////////////////////////////////////////////////
+//    destructor
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarClusterMmu() {}
+
+}
+}
+
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+
+
+
Index: /branches/v5/platforms/tsar_mono_mmu/Makefile
===================================================================
--- /branches/v5/platforms/tsar_mono_mmu/Makefile	(revision 306)
+++ /branches/v5/platforms/tsar_mono_mmu/Makefile	(revision 306)
@@ -0,0 +1,8 @@
+.PHONY : simul.x
+
+simul.x: top.cpp top.desc
+	soclib-cc -j8 -P -p top.desc -I. -o simul.x
+
+clean:
+	soclib-cc -x -p top.desc -I.
+	rm -rf *.o *.x tty*
Index: /branches/v5/platforms/tsar_mono_mmu/soclib.conf
===================================================================
--- /branches/v5/platforms/tsar_mono_mmu/soclib.conf	(revision 306)
+++ /branches/v5/platforms/tsar_mono_mmu/soclib.conf	(revision 306)
@@ -0,0 +1,5 @@
+config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI'])
+
+#config.addDescPath("/path/to/tsar/trunk/lib/")
+#config.addDescPath("/path/to/tsar/trunk/modules/")
+#config.addDescPath("/path/to/tsar/branches/v5/modules/")
Index: /branches/v5/platforms/tsar_mono_mmu/top.cpp
===================================================================
--- /branches/v5/platforms/tsar_mono_mmu/top.cpp	(revision 306)
+++ /branches/v5/platforms/tsar_mono_mmu/top.cpp	(revision 306)
@@ -0,0 +1,392 @@
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#ifdef _OPENMP
+#include <omp.h>
+#endif
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache.h"
+#include "vci_cc_vcache_wrapper.h"
+#include "vci_xicu.h"
+#include "vci_simhelper.h"
+#include "vci_multi_dma.h"
+
+// VCI format
+
+#define    cell_width	         4
+#define    address_width	    32
+#define    plen_width	         8
+#define    error_width	         2
+#define    clen_width	         1
+#define    rflag_width	         1
+#define    srcid_width          14
+#define    pktid_width           4
+#define    trdid_width	         4
+#define    wrplen_width	         1
+
+//   segments definition in direct space
+
+#define    XICU_BASE	0xd8200000
+#define    XICU_SIZE	0x00001000
+
+#define	   MDMA_BASE	0xe8000000
+#define	   MDMA_SIZE	0x00000014
+
+#define    MTTY_BASE	0xd0200000
+#define    MTTY_SIZE	0x00000010
+
+#define    EXIT_BASE	0xe0000000
+#define    EXIT_SIZE	0x00000010
+
+#define    BOOT_BASE	0xbfc00000
+#define    BOOT_SIZE	0x00040000
+
+#define    MEMC_BASE    0x00000000
+#define    MEMC_SIZE    0x02000000
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+
+using namespace sc_core;
+using namespace soclib::common;
+using namespace soclib::caba;
+
+#ifdef _OPENMP
+        omp_set_dynamic(false);
+	omp_set_num_threads(1);
+	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+    char	soft_name[256] 	= "test.elf";	// pathname to binary code
+    size_t	ncycles		= 1000000000;	// max number of simulation cycles
+    bool	trace_ok	= false;
+    size_t	from_cycle	= 0;		// debug start cycle 
+    size_t	max_frozen	= 10000;		// max number of frozen cycles
+    size_t      nprocs          = 1;    
+
+    /////////////// command line arguments ////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
+            {
+                trace_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-MAXFROZEN") == 0) && (n+1<argc) )
+            {
+                max_frozen = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -TRACE debug_start_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    // Define VCI parameters
+    typedef VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    // Define processor type
+    typedef soclib::common::Mips32ElIss proc_iss;
+
+    // Mapping table for direct network
+    soclib::common::MappingTable maptabd(32, IntTab(6), IntTab(6), 0xF0000000);
+    maptabd.add(Segment("memc_d" , MEMC_BASE , MEMC_SIZE , IntTab(0), true));
+    maptabd.add(Segment("boot_d" , BOOT_BASE , BOOT_SIZE , IntTab(1), true));
+    maptabd.add(Segment("exit_d" , EXIT_BASE , EXIT_SIZE , IntTab(2), false));
+    maptabd.add(Segment("mtty_d" , MTTY_BASE , MTTY_SIZE , IntTab(3), false));
+    maptabd.add(Segment("xicu_d" , XICU_BASE , XICU_SIZE , IntTab(4), false));
+    maptabd.add(Segment("mdma_d" , MDMA_BASE , MDMA_SIZE , IntTab(5), false));
+    std::cout << maptabd << std::endl;
+
+    // Mapping table for coherence network
+    soclib::common::MappingTable maptabc(32, IntTab(srcid_width), IntTab(srcid_width), 0xF0000000);
+    maptabc.add(
+        Segment( "proc_c"
+                , 0x0000000
+                , 0x10
+                , IntTab(0)
+                , false
+        )
+    );
+
+    maptabc.add(
+        Segment( "memc_c"
+                , nprocs << (address_width - srcid_width)
+                , 0x10
+                , IntTab(nprocs)
+                , false
+        )
+    );
+    std::cout << maptabc << std::endl;
+	
+    // Signals
+
+    sc_clock        signal_clk			("signal_clk");
+    sc_signal<bool> signal_resetn		("isgnal_resetn");
+   
+    sc_signal<bool> signal_mdma_irq		("signal_mdma_irq");
+    sc_signal<bool> signal_mtty_irq		("signal_mtty_irq");
+    sc_signal<bool> signal_proc_irq		("signal_proc_irq"); 
+    sc_signal<bool> signal_false		("signal_false");
+
+    VciSignals<vci_param> signal_vci_ini_d_proc	("vci_ini_d_proc");
+    VciSignals<vci_param> signal_vci_ini_c_proc	("vci_ini_c_proc");
+    VciSignals<vci_param> signal_vci_tgt_c_proc	("vci_tgt_c_proc");
+
+    VciSignals<vci_param> signal_vci_tgt_d_mtty	("signal_vci_tgt_d_mtty");
+
+    VciSignals<vci_param> signal_vci_tgt_d_exit	("signal_vci_tgt_d_exit");
+
+    VciSignals<vci_param> signal_vci_tgt_d_xicu	("signal_vci_tgt_d_xicu");
+
+    VciSignals<vci_param> signal_vci_ini_d_mdma	("signal_vci_ini_d_mdma");
+    VciSignals<vci_param> signal_vci_tgt_d_mdma	("signal_vci_tgt_d_mdma");
+
+    VciSignals<vci_param> signal_vci_tgt_d_brom ("signal_vci_tgt_d_brom");
+
+
+    VciSignals<vci_param> signal_vci_ini_c_memc ("signal_vci_ini_c_memc");
+    VciSignals<vci_param> signal_vci_tgt_d_memc ("signal_vci_tgt_d_memc");
+    VciSignals<vci_param> signal_vci_tgt_c_memc ("signal_vci_tgt_c_memc");
+
+    VciSignals<vci_param> signal_vci_xram	("signal_vci_xram");
+
+    // Components
+
+    soclib::common::Loader loader(soft_name);
+
+    VciCcVCacheWrapper<vci_param, proc_iss > 
+    proc("proc", 
+         0,			// proc_id 
+         maptabd, 		// direct space
+         maptabc, 		// coherence space
+         IntTab(0),		// srcid_d
+         IntTab(0),		// srcid_c
+         IntTab(0),		// tgtid_c
+         8,8,			// itlb size
+         8,8,			// dtlb size
+         4,64,16,		// icache size
+         4,64,16,		// dcache size
+         4, 4, 			// wbuf size
+         0, 0,                  // x, y Width
+         nprocs,                // memory cache local id
+         max_frozen,		// max frozen cycles
+         from_cycle, trace_ok);
+
+    VciSimpleRam<vci_param> 
+    rom("rom", 
+         IntTab(1), 		// tgtid_d
+         maptabd, 
+         loader);
+
+    VciSimpleRam<vci_param> 
+    xram("xram", 
+         IntTab(0),		// tgtid_d(RAM) = tgtid_d(MEMC) 
+         maptabd, 
+         loader);
+
+    VciMemCache<vci_param> 
+    memc("memc",
+         maptabd,
+         maptabc,
+         maptabd,
+         IntTab(0),		// srcid_x
+         IntTab(1),		// srcid_c
+         IntTab(0), 		// tgtid_d
+         IntTab(1),		// tgtid_c
+         16,256,16, 		// cache size
+         1024,			// HEAP size
+         4,			// TRT size
+         4,			// UPT size
+         from_cycle, trace_ok);
+       
+    VciSimhelper<vci_param> 
+    vciexit("vciexit",
+         IntTab(2), 		// tgtid_d
+         maptabd);
+
+    VciXicu<vci_param> 
+    xicu("xicu", 
+         maptabd,
+         IntTab(4),		// tgtid_d
+         1,			// number of timers
+         2,			// number of hard interrupts 
+         0,			// number of soft interrupts
+         1);			// number of output IRQs
+
+    VciMultiTty<vci_param> 
+    mtty("mtty", 
+         IntTab(3),		// tgtid_d 
+         maptabd, 
+         "mtty0", NULL);
+
+    VciMultiDma<vci_param>
+    mdma("mdma", 
+         maptabd, 
+         IntTab(1),		// srcid_d 
+         IntTab(5), 		// tgtid_d
+         64,			// burst size
+         1);			// number of channels 
+	
+    VciVgmn<vci_param> 
+    ringd("ringd",
+         maptabd, 
+         2, 			// number of initiators
+         6, 			// number of targets
+         2, 
+         8);
+
+    VciVgmn<vci_param> 
+    ringc("ringc",
+         maptabc, 
+         2, 			// number of initiators
+         2, 			// number of targets
+         2, 
+         8);
+
+    // net-list
+    proc.p_clk(signal_clk);  
+    proc.p_resetn		(signal_resetn);  
+    proc.p_irq[0]		(signal_proc_irq); 
+    proc.p_irq[1]		(signal_false); 
+    proc.p_irq[2]		(signal_false); 
+    proc.p_irq[3]		(signal_false); 
+    proc.p_irq[4]		(signal_false); 
+    proc.p_irq[5]		(signal_false); 
+    proc.p_vci_ini_d		(signal_vci_ini_d_proc);
+    proc.p_vci_ini_c		(signal_vci_ini_c_proc);
+    proc.p_vci_tgt_c		(signal_vci_tgt_c_proc);
+
+    rom.p_clk			(signal_clk);
+    rom.p_resetn		(signal_resetn);
+    rom.p_vci			(signal_vci_tgt_d_brom);
+
+    xicu.p_resetn		(signal_resetn);
+    xicu.p_clk			(signal_clk);
+    xicu.p_vci			(signal_vci_tgt_d_xicu);
+    xicu.p_hwi[0]		(signal_mtty_irq);
+    xicu.p_hwi[1]		(signal_mdma_irq);
+    xicu.p_irq[0]		(signal_proc_irq);
+
+    mdma.p_clk			(signal_clk);
+    mdma.p_resetn		(signal_resetn);
+    mdma.p_vci_target		(signal_vci_tgt_d_mdma);
+    mdma.p_vci_initiator	(signal_vci_ini_d_mdma);
+    mdma.p_irq[0]		(signal_mdma_irq); 
+
+    mtty.p_clk			(signal_clk);
+    mtty.p_resetn		(signal_resetn);
+    mtty.p_vci			(signal_vci_tgt_d_mtty);
+    mtty.p_irq[0]		(signal_mtty_irq); 
+
+    vciexit.p_clk		(signal_clk);
+    vciexit.p_resetn		(signal_resetn);
+    vciexit.p_vci		(signal_vci_tgt_d_exit);
+
+    memc.p_clk			(signal_clk);
+    memc.p_resetn		(signal_resetn);
+    memc.p_vci_tgt		(signal_vci_tgt_d_memc);
+    memc.p_vci_tgt_cleanup	(signal_vci_tgt_c_memc);
+    memc.p_vci_ini		(signal_vci_ini_c_memc);
+    memc.p_vci_ixr		(signal_vci_xram);
+
+    xram.p_clk			(signal_clk);
+    xram.p_resetn		(signal_resetn);
+    xram.p_vci			(signal_vci_xram);
+	
+    ringc.p_clk			(signal_clk);
+    ringc.p_resetn		(signal_resetn);
+    ringc.p_to_initiator[0]	(signal_vci_ini_c_proc);
+    ringc.p_to_initiator[1]	(signal_vci_ini_c_memc);
+    ringc.p_to_target[0]	(signal_vci_tgt_c_proc);
+    ringc.p_to_target[1]	(signal_vci_tgt_c_memc);
+
+    ringd.p_clk			(signal_clk);
+    ringd.p_resetn		(signal_resetn);
+    ringd.p_to_initiator[0]	(signal_vci_ini_d_proc);
+    ringd.p_to_initiator[1]	(signal_vci_ini_d_mdma);
+    ringd.p_to_target[0]	(signal_vci_tgt_d_memc);
+    ringd.p_to_target[1]	(signal_vci_tgt_d_brom);
+    ringd.p_to_target[2]	(signal_vci_tgt_d_exit);
+    ringd.p_to_target[3]	(signal_vci_tgt_d_mtty);
+    ringd.p_to_target[4]	(signal_vci_tgt_d_xicu);
+    ringd.p_to_target[5]	(signal_vci_tgt_d_mdma);
+	
+    // simulation loop
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+        
+    signal_false = false;
+
+    for ( size_t n=1 ; n<ncycles ; n++ )
+    {
+        if ( trace_ok and (n > from_cycle) )
+        {
+            std::cout << "****************** cycle " << std::dec << n
+                      << " ************************************************" << std::endl;
+            proc.print_trace();
+            memc.print_trace();
+            signal_vci_ini_d_proc.print_trace("proc_ini_d");
+            signal_vci_tgt_c_proc.print_trace("proc_tgt_c");
+            signal_vci_ini_c_proc.print_trace("proc_ini_c");
+            signal_vci_tgt_d_memc.print_trace("memc_tgt_d");
+            signal_vci_tgt_c_memc.print_trace("memc_tgt_c");
+            signal_vci_ini_c_memc.print_trace("memc_ini_c");
+            if ( signal_proc_irq.read() ) std::cout << "---- IRQ ----" << std::endl;
+        }
+        sc_start(sc_core::sc_time(1, SC_NS));
+    }
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: /branches/v5/platforms/tsar_mono_mmu/top.desc
===================================================================
--- /branches/v5/platforms/tsar_mono_mmu/top.desc	(revision 306)
+++ /branches/v5/platforms/tsar_mono_mmu/top.desc	(revision 306)
@@ -0,0 +1,27 @@
+# -*- python -*-
+
+todo = Platform('caba', 'top.cpp',
+    uses = [
+                Uses('common:mapping_table'),
+                Uses('caba:vci_cc_vcache_wrapper', iss_t = 'common:mips32el'),
+                Uses('caba:vci_simple_ram'),
+                Uses('caba:vci_logger'),
+                Uses('caba:vci_multi_tty'),
+                Uses('caba:vci_xicu'),
+                Uses('caba:vci_multi_dma'),
+                Uses('caba:vci_vgmn'),
+                Uses('caba:vci_simhelper'),
+                Uses('caba:vci_mem_cache'),
+                Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)