Index: branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 305)
+++ branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 313)
@@ -175,4 +175,5 @@
     "CAS_DIR_LOCK",
     "CAS_DIR_HIT_READ",
+    "CAS_DIR_HIT_COMPARE",
     "CAS_DIR_HIT_WRITE",
     "CAS_UPT_LOCK",
@@ -434,7 +435,7 @@
 
       // Allocation for CAS FSM
-      r_cas_to_ixr_cmd_data        = new sc_signal<data_t>[nwords];
-      r_cas_rdata                  = new sc_signal<data_t>[2];
-
+      r_cas_to_ixr_cmd_data       = new sc_signal<data_t>[nwords];
+      r_cas_data                  = new sc_signal<data_t>[nwords];
+      r_cas_rdata                 = new sc_signal<data_t>[2];
 
       // Simulation
@@ -4328,5 +4329,5 @@
             if( r_alloc_dir_fsm.read() == ALLOC_DIR_CAS )
             {
-              r_cas_fsm = CAS_DIR_LOCK;
+                r_cas_fsm = CAS_DIR_LOCK;
             }
 
@@ -4334,7 +4335,7 @@
             if( m_debug_cas_fsm )
             {
-              std::cout 
-                << "  <MEMC " << name() << ".CAS_DIR_REQ> Requesting DIR lock "
-                << std::endl;
+                std::cout 
+                    << "  <MEMC " << name() << ".CAS_DIR_REQ> Requesting DIR lock "
+                    << std::endl;
             }
 #endif
@@ -4363,5 +4364,5 @@
 
                 if ( entry.valid )  r_cas_fsm = CAS_DIR_HIT_READ;
-                else          r_cas_fsm = CAS_MISS_TRT_LOCK;
+                else                r_cas_fsm = CAS_MISS_TRT_LOCK;
 
 #if DEBUG_MEMC_CAS
@@ -4378,21 +4379,21 @@
             else
             {
-              std::cout
-                << "VCI_MEM_CACHE ERROR " << name()
-                << " CAS_DIR_LOCK state" << std::endl
-                << "Bad DIR allocation"   << std::endl;
-
-              exit(0);
+                std::cout
+                    << "VCI_MEM_CACHE ERROR " << name()
+                    << " CAS_DIR_LOCK state" << std::endl
+                    << "Bad DIR allocation"   << std::endl;
+
+                exit(0);
             }
 
             break;
         }
+
         /////////////////////
         case CAS_DIR_HIT_READ:  // update directory for lock and dirty bit
-                               // and check data change in cache
+                                // and check data change in cache
         {
             size_t way  = r_cas_way.read();
             size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-            size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
 
             // update directory (lock & dirty bits)
@@ -4402,5 +4403,5 @@
             entry.dirty          = true;
             entry.lock           = true;
-            entry.tag          = r_cas_tag.read();
+            entry.tag            = r_cas_tag.read();
             entry.owner.srcid    = r_cas_copy.read();
 #if L1_MULTI_CACHE
@@ -4413,18 +4414,41 @@
             m_cache_directory.write(set, way, entry);
 
-            // read data in cache & check data change
-            bool ok = ( r_cas_rdata[0].read() == m_cache_data.read(way, set, word) );
-            if ( r_cas_cpt.read()==4 )  // 64 bits CAS
-                ok &= ( r_cas_rdata[1] == m_cache_data.read(way, set, word+1));
+            // Stored data from cache in buffer to do the comparison in next state
+            m_cache_data.read_line(way, set, r_cas_data);
+
+            r_cas_fsm = CAS_DIR_HIT_COMPARE;
+
+#if DEBUG_MEMC_CAS
+            if(m_debug_cas_fsm)
+            {
+                std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_READ> Read data from "
+                    << " cache and store it in buffer"
+                    << std::endl;
+            }
+#endif
+            break;
+        }
+
+        case CAS_DIR_HIT_COMPARE:
+        {
+            size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+
+            // Read data in buffer & check data change
+            bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read());
+
+            if(r_cas_cpt.read() == 4)     // 64 bits CAS
+                ok &= (r_cas_rdata[1] == r_cas_data[word+1]);
 
             // to avoid livelock, force the atomic access to fail pseudo-randomly
-            bool forced_fail = ( (r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS );
-            r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((-(r_cas_lfsr & 1)) & 0xd0000001);
-
-            if( ok and not forced_fail )  // no data change
+            bool forced_fail = ((r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS);
+            r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001);
+
+            // cas success
+            if(ok and not forced_fail)
             {
                 r_cas_fsm = CAS_DIR_HIT_WRITE;
             }
-            else                            // return failure
+            // cas failure
+            else
             {
                 r_cas_fsm = CAS_RSP_FAIL;
@@ -4432,14 +4456,16 @@
 
 #if DEBUG_MEMC_CAS
-if( m_debug_cas_fsm )
-{
-    std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_READ> Test if CAS success:"
-              << " / expected value = " << r_cas_rdata[0].read()
-              << " / actual value = " << m_cache_data.read(way, set, word)
-              << " / forced_fail = " << forced_fail << std::endl;
-}
+            if(m_debug_cas_fsm)
+            {
+                std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_COMPARE> Compare the old"
+                    << " and the new data"
+                    << " / expected value = " << r_cas_rdata[0].read()
+                    << " / actual value = "   << r_cas_data[word].read()
+                    << " / forced_fail = "    << forced_fail << std::endl;
+            }
 #endif
             break;
         }
+
         //////////////////////
         case CAS_DIR_HIT_WRITE:    // test if a CC transaction is required
@@ -4477,15 +4503,19 @@
                     m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
 
+                r_cas_fsm = CAS_RSP_SUCCESS;
+
                 // monitor
                 if ( m_monitor_ok )
                 {
                     vci_addr_t address = m_cmd_cas_addr_fifo.read();
-                char buf[80];
-                snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
+
+                    char buf[80];
+                    snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
+                             m_cmd_cas_srcid_fifo.read());
+
                     check_monitor( buf, address, r_cas_wdata.read() );
                     if ( r_cas_cpt.read()==4 )
                     check_monitor( buf, address+4, m_cmd_cas_wdata_fifo.read() );
                 }
-                r_cas_fsm = CAS_RSP_SUCCESS;
 
 #if DEBUG_MEMC_CAS
@@ -4704,7 +4734,5 @@
                 {
                     // fill the data buffer
-                    size_t way  = r_cas_way.read();
-                    size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-                        size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                    size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
                     for(size_t i = 0; i<m_words; i++)
                     {
@@ -4719,5 +4747,5 @@
                         else
                         {
-                            r_cas_to_ixr_cmd_data[i] = m_cache_data.read(way, set, i);
+                            r_cas_to_ixr_cmd_data[i] = r_cas_data[i].read();
                         }
                     }
@@ -5822,19 +5850,20 @@
         ////////////////////
         case ALLOC_DIR_CAS:
-        if ((( r_cas_fsm.read()        != CAS_DIR_REQ       )  &&
-             ( r_cas_fsm.read()        != CAS_DIR_LOCK      )  &&
-             ( r_cas_fsm.read()        != CAS_DIR_HIT_READ  )  &&
-             ( r_cas_fsm.read()        != CAS_DIR_HIT_WRITE )  &&
-             ( r_cas_fsm.read()        != CAS_BC_TRT_LOCK   )  &&
-             ( r_cas_fsm.read()        != CAS_BC_UPT_LOCK   )  &&
-             ( r_cas_fsm.read()        != CAS_MISS_TRT_LOCK )  &&
-             ( r_cas_fsm.read()        != CAS_UPT_LOCK      )  &&
-             ( r_cas_fsm.read()        != CAS_UPT_HEAP_LOCK ))
+        if ((( r_cas_fsm.read()        != CAS_DIR_REQ         )  &&
+             ( r_cas_fsm.read()        != CAS_DIR_LOCK        )  &&
+             ( r_cas_fsm.read()        != CAS_DIR_HIT_READ    )  &&
+             ( r_cas_fsm.read()        != CAS_DIR_HIT_COMPARE )  &&
+             ( r_cas_fsm.read()        != CAS_DIR_HIT_WRITE   )  &&
+             ( r_cas_fsm.read()        != CAS_BC_TRT_LOCK     )  &&
+             ( r_cas_fsm.read()        != CAS_BC_UPT_LOCK     )  &&
+             ( r_cas_fsm.read()        != CAS_MISS_TRT_LOCK   )  &&
+             ( r_cas_fsm.read()        != CAS_UPT_LOCK        )  &&
+             ( r_cas_fsm.read()        != CAS_UPT_HEAP_LOCK   ))
             ||
-            (( r_cas_fsm.read()        == CAS_UPT_HEAP_LOCK )  &&
-             ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS    ))
+            (( r_cas_fsm.read()        == CAS_UPT_HEAP_LOCK   )  &&
+             ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS      ))
             ||
-            (( r_cas_fsm.read()        == CAS_MISS_TRT_LOCK )  &&
-             ( r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS     )))
+            (( r_cas_fsm.read()        == CAS_MISS_TRT_LOCK   )  &&
+             ( r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS       )))
         {
           if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ )
