Changeset 313 for branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include

Timestamp:

Mar 12, 2013, 3:20:33 PM (12 years ago)

Author:

cfuguet

Message:

Erasing useless template parameters for the communication/dspin_dhccp_param class.

Modifying consequently the vci_mem_cache_dspin_coherence class to use the
dspin_dhccp_param class without templates.

Introducing in the vci_mem_cache and the vci_mem_cache_dspin_coherence modules
the state CAS_DIR_HIT_COMPARE.

Before this modification, the comparison between the expected data and the actual
data was done directly in the CAS_DIR_HIT_READ state using the data obtained in the
same cycle from the cache.

Now, the data obtained from the cache is stored in a buffer and the next cycle,
in the CAS_DIR_HIT_COMPARE state, the comparison is made using the data from the
buffer.

This modifications allows to eliminate a critical path obtained in the ASIC
synthesis of the memory cache.

File:

• branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache.h (modified) (5 diffs)

branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache.h

@@ -58 +58 @@
   using namespace sc_core;
 
-  template<typename vci_param, int from_mc_flit_width, int from_l1_flit_width>
+  template<typename vci_param>
     class VciMemCache
     : public soclib::caba::BaseModule
@@ -69 +69 @@
       typedef uint32_t be_t;
       typedef uint32_t copy_t;
-
-      typedef soclib::caba::DspinDhccpParam
-        <from_mc_flit_width
-        ,from_l1_flit_width> dspin_param;
 
       /* States of the TGT_CMD fsm */
@@ -225 +221 @@
         CAS_DIR_LOCK,
         CAS_DIR_HIT_READ,
+        CAS_DIR_HIT_COMPARE,
         CAS_DIR_HIT_WRITE,
         CAS_UPT_LOCK,
@@ -383 +380 @@
       soclib::caba::VciInitiator<vci_param> p_vci_ixr;
 
-      soclib::caba::DspinInput <from_l1_flit_width> p_dspin_in;
-      soclib::caba::DspinOutput<from_mc_flit_width> p_dspin_out;
+      soclib::caba::DspinInput<33>          p_dspin_in;
+      soclib::caba::DspinOutput<40>         p_dspin_out;
 
       VciMemCache(
@@ -690 +687 @@
       sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
       sc_signal<size_t>   r_cas_upt_index;  // Update Table index
+      sc_signal<data_t> * r_cas_data;       // cache line data
 
       // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)