Changeset 319 for branches/v5/modules


Ignore:
Timestamp:
Mar 13, 2013, 3:38:46 PM (12 years ago)
Author:
cfuguet
Message:

Fix bug in vci_mem_cache_dspin_coherence. The write signal
in the dspin port must depend on the rok of clients fifos when
in state HEADER of multicast update or invalidate

File:
1 edited

Legend:

Unmodified
Added
Removed

  • branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache.cpp

    r317 r319  
    552552            << " | " << cleanup_fsm_str[r_cleanup_fsm] << std::endl;
    553553  std::cout << "  "  << cc_send_fsm_str[r_cc_send_fsm]
     554            << " | " << cc_receive_fsm_str[r_cc_receive_fsm]
    554555            << " | " << multi_ack_fsm_str[r_multi_ack_fsm]
    555556            << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm]
    … …  
    802803#endif
    803804
    804   m_debug_global        = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    805   m_debug_tgt_cmd_fsm   = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    806   m_debug_tgt_rsp_fsm   = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    807   m_debug_cc_send_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     805  m_debug_global         = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     806  m_debug_tgt_cmd_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     807  m_debug_tgt_rsp_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     808  m_debug_cc_send_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    808809  m_debug_cc_receive_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    809   m_debug_multi_ack_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    810   m_debug_read_fsm      = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    811   m_debug_write_fsm     = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    812   m_debug_cas_fsm       = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    813   m_debug_cleanup_fsm   = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    814   m_debug_ixr_cmd_fsm   = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    815   m_debug_ixr_rsp_fsm   = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    816   m_debug_xram_rsp_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     810  m_debug_multi_ack_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     811  m_debug_read_fsm       = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     812  m_debug_write_fsm      = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     813  m_debug_cas_fsm        = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     814  m_debug_cleanup_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     815  m_debug_ixr_cmd_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     816  m_debug_ixr_rsp_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
     817  m_debug_xram_rsp_fsm   = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
    817818
    818819#if DEBUG_MEMC_GLOBAL
    … …  
    821822    std::cout
    822823        << "---------------------------------------------"           << std::dec << std::endl
    823         << "MEM_CACHE "           << m_srcid_ini
    824         << " ; Time = "           << m_cpt_cycles                                << std::endl
    825         << " - TGT_CMD FSM    = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()]       << std::endl
    826         << " - TGT_RSP FSM    = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()]       << std::endl
    827         << " - CC_SEND FSM  = " << cc_send_fsm_str[r_cc_send_fsm.read()]   << std::endl
    828         << " - CC_RECEIVE FSM  = " << cc_receive_fsm_str[r_cc_receive_fsm.read()]   << std::endl
    829         << " - MULTI_ACK FSM  = " << multi_ack_fsm_str[r_multi_ack_fsm.read()]   << std::endl
    830         << " - READ FSM       = " << read_fsm_str[r_read_fsm.read()]             << std::endl
    831         << " - WRITE FSM      = " << write_fsm_str[r_write_fsm.read()]           << std::endl
    832         << " - CAS FSM        = " << cas_fsm_str[r_cas_fsm.read()]               << std::endl
    833         << " - CLEANUP FSM    = " << cleanup_fsm_str[r_cleanup_fsm.read()]       << std::endl
    834         << " - IXR_CMD FSM    = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()]       << std::endl
    835         << " - IXR_RSP FSM    = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()]       << std::endl
    836         << " - XRAM_RSP FSM   = " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()]     << std::endl
    837         << " - ALLOC_DIR FSM  = " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()]   << std::endl
    838         << " - ALLOC_TRT FSM  = " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()]   << std::endl
    839         << " - ALLOC_UPT FSM  = " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()]   << std::endl
    840         << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl;
     824        << "MEM_CACHE "            << m_srcid_ini
     825        << " ; Time = "            << m_cpt_cycles                                << std::endl
     826        << " - TGT_CMD FSM    = "  << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()]       << std::endl
     827        << " - TGT_RSP FSM    = "  << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()]       << std::endl
     828        << " - CC_SEND FSM  = "    << cc_send_fsm_str[r_cc_send_fsm.read()]       << std::endl
     829        << " - CC_RECEIVE FSM  = " << cc_receive_fsm_str[r_cc_receive_fsm.read()] << std::endl
     830        << " - MULTI_ACK FSM  = "  << multi_ack_fsm_str[r_multi_ack_fsm.read()]   << std::endl
     831        << " - READ FSM       = "  << read_fsm_str[r_read_fsm.read()]             << std::endl
     832        << " - WRITE FSM      = "  << write_fsm_str[r_write_fsm.read()]           << std::endl
     833        << " - CAS FSM        = "  << cas_fsm_str[r_cas_fsm.read()]               << std::endl
     834        << " - CLEANUP FSM    = "  << cleanup_fsm_str[r_cleanup_fsm.read()]       << std::endl
     835        << " - IXR_CMD FSM    = "  << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()]       << std::endl
     836        << " - IXR_RSP FSM    = "  << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()]       << std::endl
     837        << " - XRAM_RSP FSM   = "  << xram_rsp_fsm_str[r_xram_rsp_fsm.read()]     << std::endl
     838        << " - ALLOC_DIR FSM  = "  << alloc_dir_fsm_str[r_alloc_dir_fsm.read()]   << std::endl
     839        << " - ALLOC_TRT FSM  = "  << alloc_trt_fsm_str[r_alloc_trt_fsm.read()]   << std::endl
     840        << " - ALLOC_UPT FSM  = "  << alloc_upt_fsm_str[r_alloc_upt_fsm.read()]   << std::endl
     841        << " - ALLOC_HEAP FSM = "  << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl;
    841842  }
    842843#endif
    … …  
    73947395            DspinDhccpParam::FROM_MC_TYPE);
    73957396
    7396         p_dspin_out.write = true;
     7397        p_dspin_out.write = m_xram_rsp_to_cc_send_inst_fifo.rok();
    73977398        p_dspin_out.data  = flit;
    73987399
    … …  
    75427543            DspinDhccpParam::FROM_MC_TYPE);
    75437544
    7544         p_dspin_out.write = true;
     7545        p_dspin_out.write = m_write_to_cc_send_inst_fifo.rok();
    75457546        p_dspin_out.data  = flit;
    75467547
    … …  
    76447645            DspinDhccpParam::FROM_MC_TYPE);
    76457646
    7646         p_dspin_out.write = true;
     7647        p_dspin_out.write = m_cas_to_cc_send_inst_fifo.rok();
    76477648        p_dspin_out.data  = flit;
    76487649
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