Changeset 328 for branches/v5


Ignore:
Timestamp:
Mar 18, 2013, 3:45:25 PM (12 years ago)
Author:
cfuguet
Message:

Including TYPE_CLEANUP_ACK_INST and TYPE_CLEANUP_ACK_DATA in the
dspin_dhccp_param class. These types will be decoded by the L1 cache to do the
request to the concerned FSM (DATA/INST).

Including a communication register between the CLEANUP FSM and the CC_SEND FSM
to signal if the CLEANUP_ACK to send concerns the DATA or the INSTRUCTION cache
of the L1.

Location:
branches/v5
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • branches/v5/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h

    r313 r328  
    239239      TYPE_MULTI_INVAL_DATA = TYPE_MULTI_INVAL,
    240240      TYPE_MULTI_INVAL_INST = 3,
    241       TYPE_CLEANUP_ACK      = 4
     241      TYPE_CLEANUP_ACK      = 4,
     242      TYPE_CLEANUP_ACK_DATA = TYPE_CLEANUP_ACK,
     243      TYPE_CLEANUP_ACK_INST = 5
    242244    };
    243245
  • branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache.h

    r313 r328  
    664664      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
    665665      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
     666      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
    666667
    667668      ///////////////////////////////////////////////////////
  • branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache.cpp

    r320 r328  
    45364536      r_cleanup_to_cc_send_way_index = r_cleanup_way_index.read();
    45374537      r_cleanup_to_cc_send_srcid     = r_cleanup_srcid.read();
     4538      r_cleanup_to_cc_send_inst      = r_cleanup_inst.read();
    45384539
    45394540      r_cleanup_fsm = CLEANUP_IDLE;
     
    73317332        uint64_t flit = 0;
    73327333 
     7334        uint8_t cleanup_ack_type;
     7335        if(r_cleanup_to_cc_send_inst.read())
     7336        {
     7337          cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_INST;
     7338        }
     7339        else
     7340        {
     7341          cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_DATA;
     7342        }
     7343
    73337344        DspinDhccpParam::dspin_set(
    73347345            flit,
     
    73537364        DspinDhccpParam::dspin_set(
    73547365            flit,
    7355             DspinDhccpParam::TYPE_CLEANUP_ACK,
     7366            cleanup_ack_type,
    73567367            DspinDhccpParam::FROM_MC_TYPE);
    73577368
     
    73647375    case CC_SEND_XRAM_RSP_INVAL_HEADER:
    73657376      {
     7377        if(not m_xram_rsp_to_cc_send_inst_fifo.rok()) break;
     7378
    73667379        uint8_t multi_inval_type;
    73677380        if(m_xram_rsp_to_cc_send_inst_fifo.read())
     
    73967409            DspinDhccpParam::FROM_MC_TYPE);
    73977410
    7398         p_dspin_out.write = m_xram_rsp_to_cc_send_inst_fifo.rok();
     7411        p_dspin_out.write = true;
    73997412        p_dspin_out.data  = flit;
    74007413
     
    75127525    case CC_SEND_WRITE_UPDT_HEADER:
    75137526      {
     7527        if(not m_write_to_cc_send_inst_fifo.rok()) break;
     7528
    75147529        uint8_t multi_updt_type;
    75157530        if(m_write_to_cc_send_inst_fifo.read())
     
    75447559            DspinDhccpParam::FROM_MC_TYPE);
    75457560
    7546         p_dspin_out.write = m_write_to_cc_send_inst_fifo.rok();
     7561        p_dspin_out.write = true;
    75477562        p_dspin_out.data  = flit;
    75487563
     
    76147629    case CC_SEND_CAS_UPDT_HEADER:
    76157630      {
     7631        if (not m_cas_to_cc_send_inst_fifo.rok()) break;
     7632
    76167633        uint8_t multi_updt_type;
    76177634        if(m_cas_to_cc_send_inst_fifo.read())
     
    76467663            DspinDhccpParam::FROM_MC_TYPE);
    76477664
    7648         p_dspin_out.write = m_cas_to_cc_send_inst_fifo.rok();
     7665        p_dspin_out.write = true;
    76497666        p_dspin_out.data  = flit;
    76507667
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