Index: /branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp
===================================================================
--- /branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp	(revision 332)
+++ /branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp	(revision 333)
@@ -5273,14 +5273,14 @@
             // a request of the other, then update the client    //
             ///////////////////////////////////////////////////////
-            // r_cc_send_last_client : 0 dcache 1 icache
-            bool update_last_client;
+            // r_cc_send_last_client : 0 dcache / 1 icache
+            bool update_last_client = r_cc_send_last_client.read();
             if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
             {
-                if(r_icache_cc_send_req.read()) // request from icache
+                if (r_icache_cc_send_req.read()) // request from icache
                     update_last_client = 1; // update last client to icache
             }
             else // last client was icache
             {
-                if(r_dcache_cc_send_req.read()) // request from dcache
+                if (r_dcache_cc_send_req.read()) // request from dcache
                     update_last_client = 0; // update last client to dcache
             }
@@ -5308,6 +5308,14 @@
         case CC_SEND_CLEANUP_1:
         {
+/**/
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+        std::cout << "  <PROC " << name()
+              << " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
+}
+#endif
             // wait for the first flit to be consumed
-            if(p_dspin_out.read.read())
+            if (p_dspin_out.read.read())
                 r_cc_send_fsm = CC_SEND_CLEANUP_2;
 
@@ -5316,4 +5324,12 @@
         ///////////////////////////
         case CC_SEND_CLEANUP_2:
+/**/
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+        std::cout << "  <PROC " << name()
+              << " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
+}
+#endif
         {
             assert( p_dspin_out.read.read() and
@@ -5321,7 +5337,7 @@
 
             // wait for the second flit to be consumed
-            if(p_dspin_out.read.read())
-            {
-                if(r_cc_send_last_client.read() == 0) // dcache active request
+            if (p_dspin_out.read.read())
+            {
+                if (r_cc_send_last_client.read() == 0) // dcache active request
                     r_dcache_cc_send_req = false; // reset dcache request
                 else // icache active request
Index: /branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache_dspin_coherence.cpp
===================================================================
--- /branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache_dspin_coherence.cpp	(revision 332)
+++ /branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache_dspin_coherence.cpp	(revision 333)
@@ -518,5 +518,5 @@
   {
     std::cout << " MEMC Write Monitor : " << buf << " Address = " << std::hex << addr
-              << " / Data = " << data << std::endl;
+              << " / Data = " << data << " at cycle " << std::dec << m_cpt_cycles << std::endl;
   }
 }
@@ -4151,5 +4151,5 @@
       // It must be freed and the copy registered in directory
       // must point to the next copy in heap
-      if(match_heap)
+      else if(match_heap)
       {
         dir_entry.ptr            = heap_entry.next;
@@ -4164,4 +4164,5 @@
         r_cleanup_fsm            = CLEANUP_HEAP_FREE;
       }
+
       // The matching copy is in the heap, but is not the first copy
       // The directory entry must be modified to decrement count