Changeset 336 for branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include

Timestamp:

Mar 27, 2013, 2:25:37 PM (11 years ago)

Author:

cfuguet

Message:

Bug fix in the vci_cc_vcache_wrapper and vci_mem_cache components
(and the corresponding dspin coherence versions)

vci_cc_vcache_wrapper:

In the VCI_CMD FSM of the cc_vcache, for the SC command as for the
CAS command, we must set the CONS bit in the VCI packet. In the
same manner we must unset the CONTIG bit in the VCI packet for these
two commands.
These two kind of commands have two flits with the same VCI address.

vci_mem_cache

In the state WRITE_DIR_REQ, we don't have to rewrite the registers
address or word index because they will be assigned with the correct
values in the WRITE_IDLE or WRITE_RSP states.

File:

• branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h (modified) (1 diff)

branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h

@@ -565 +565 @@
       sc_signal<size_t>   r_write_upt_index;  // index in Update Table
       sc_signal<bool>     r_write_sc_fail;    // sc command failed
-      sc_signal<bool>     r_write_pending_sc; // sc command pending in WRITE fsm
+      sc_signal<bool>     r_write_pending_sc; // sc command pending
 
       // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)