Changeset 341 for branches/v5/modules

Timestamp:

Mar 28, 2013, 7:08:48 PM (12 years ago)

Author:

joannou

Message:

In vci_cc_vcache_wrapper_dspin_coherence, DCACHE_TLB_PTE1_MISS and DCACHE_TLB_PTE2_MIS are now interruptible by a coherence request.
\o/ v5 works \o/ ... or does it :)

File:

• branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp (modified) (2 diffs)

branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp

@@ -2857 +2857 @@
     case DCACHE_TLB_PTE1_GET:   // try to read a PT1 entry in dcache
     {
+        // coherence request (from CC_RECEIVE FSM)
+        if ( r_cc_receive_dcache_req.read() )
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            break;
+        }
+
         uint32_t        entry;
         size_t          way;
@@ -3137 +3145 @@
     case DCACHE_TLB_PTE2_GET:   // Try to get a PTE2 (64 bits) in the dcache
     {
+        // coherence request (from CC_RECEIVE FSM)
+        if ( r_cc_receive_dcache_req.read() )
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            break;
+        }
+
         uint32_t        pte_flags;
         uint32_t        pte_ppn;