- Timestamp:
- Mar 29, 2013, 6:56:36 PM (12 years ago)
- Location:
- branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_vcache_wrapper_dspin_coherence.h (modified) (4 diffs)
-
src/vci_cc_vcache_wrapper_dspin_coherence.cpp (modified) (26 diffs)
Legend:
- Unmodified
- Added
- Removed
-
branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/include/vci_cc_vcache_wrapper_dspin_coherence.h
r331 r346 1 1 /* -*- c++ -*- 2 * 2 3 * File : vci_cc_vcache_wrapper.h 3 4 * Copyright (c) UPMC, Lip6, SoC … … 285 286 sc_in<bool> p_resetn; 286 287 sc_in<bool> p_irq[iss_t::n_irq]; 287 soclib::caba::VciInitiator<vci_param> p_vci _ini_d;288 soclib::caba::DspinInput <40> p_dspin_in;289 soclib::caba::DspinOutput<33> p_dspin_out;288 soclib::caba::VciInitiator<vci_param> p_vci; 289 soclib::caba::DspinInput <40> p_dspin_in; 290 soclib::caba::DspinOutput<33> p_dspin_out; 290 291 291 292 private: 292 293 293 294 // STRUCTURAL PARAMETERS 294 soclib::common::AddressDecodingTable<uint32_t, bool> 295 const soclib::common::Segment m_segment; 296 const vci_srcid_t m_srcid_d;297 const vci_srcid_t m_srcid_c;298 295 soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table; 296 297 const vci_srcid_t m_srcid; 298 const size_t m_cc_global_id; 299 const size_t m_nline_width; 299 300 const size_t m_itlb_ways; 300 301 const size_t m_itlb_sets; 301 302 302 const size_t m_dtlb_ways; 303 303 const size_t m_dtlb_sets; 304 305 304 const size_t m_icache_ways; 306 305 const size_t m_icache_sets; 307 306 const paddr_t m_icache_yzmask; 308 307 const size_t m_icache_words; 309 310 308 const size_t m_dcache_ways; 311 309 const size_t m_dcache_sets; 312 310 const paddr_t m_dcache_yzmask; 313 311 const size_t m_dcache_words; 314 315 312 const size_t m_x_width; 316 313 const size_t m_y_width; 317 318 const size_t m_memory_cache_local_id;319 314 const size_t m_proc_id; 320 315 const uint32_t m_max_frozen_cycles; 321 316 const size_t m_paddr_nbits; 317 uint32_t m_debug_start_cycle; 318 bool m_debug_ok; 322 319 323 320 //////////////////////////////////////// … … 332 329 // debug variables (for each FSM) 333 330 ///////////////////////////////////////////// 334 uint32_t m_debug_start_cycle;335 bool m_debug_ok;336 331 bool m_debug_previous_hit; 337 332 bool m_idebug_previous_hit; … … 686 681 public: 687 682 VciCcVCacheWrapper( 688 sc_module_name insname, 689 int proc_id, 690 const soclib::common::MappingTable &mtp, 691 const soclib::common::MappingTable &mtc, 692 const soclib::common::IntTab &initiator_index_d, 693 const soclib::common::IntTab &initiator_index_c, 694 const soclib::common::IntTab &target_index_d, 695 size_t itlb_ways, 696 size_t itlb_sets, 697 size_t dtlb_ways, 698 size_t dtlb_sets, 699 size_t icache_ways, 700 size_t icache_sets, 701 size_t icache_words, 702 size_t dcache_ways, 703 size_t dcache_sets, 704 size_t dcache_words, 705 size_t wbuf_nlines, 706 size_t wbuf_nwords, 707 size_t x_width, 708 size_t y_width, 709 uint32_t memory_cache_local_id, 710 uint32_t max_frozen_cycles, 711 uint32_t debug_start_cycle, 712 bool debug_ok); 683 sc_module_name name, 684 const int proc_id, 685 const soclib::common::MappingTable &mtd, 686 const soclib::common::IntTab &srcid, 687 const size_t cc_global_id, 688 const size_t itlb_ways, 689 const size_t itlb_sets, 690 const size_t dtlb_ways, 691 const size_t dtlb_sets, 692 const size_t icache_ways, 693 const size_t icache_sets, 694 const size_t icache_words, 695 const size_t dcache_ways, 696 const size_t dcache_sets, 697 const size_t dcache_words, 698 const size_t wbuf_nlines, 699 const size_t wbuf_nwords, 700 const size_t x_width, 701 const size_t y_width, 702 const uint32_t max_frozen_cycles, 703 const uint32_t debug_start_cycle, 704 const bool debug_ok ); 713 705 714 706 ~VciCcVCacheWrapper(); -
branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp
r341 r346 162 162 #define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t> 163 163 164 using soclib::common::uint32_log2;164 using namespace soclib::common; 165 165 166 166 ///////////////////////////////// 167 167 tmpl(/**/)::VciCcVCacheWrapper( 168 168 sc_module_name name, 169 int proc_id, 170 const soclib::common::MappingTable &mtd, 171 const soclib::common::MappingTable &mtc, 172 const soclib::common::IntTab &initiator_index_d, 173 const soclib::common::IntTab &initiator_index_c, 174 const soclib::common::IntTab &target_index_c, 175 size_t itlb_ways, 176 size_t itlb_sets, 177 size_t dtlb_ways, 178 size_t dtlb_sets, 179 size_t icache_ways, 180 size_t icache_sets, 181 size_t icache_words, 182 size_t dcache_ways, 183 size_t dcache_sets, 184 size_t dcache_words, 185 size_t wbuf_nlines, 186 size_t wbuf_nwords, 187 size_t x_width, 188 size_t y_width, 189 uint32_t memory_cache_local_id, 190 uint32_t max_frozen_cycles, 191 uint32_t debug_start_cycle, 192 bool debug_ok) 169 const int proc_id, 170 const MappingTable &mtd, 171 const IntTab &srcid, 172 const size_t cc_global_id, 173 const size_t itlb_ways, 174 const size_t itlb_sets, 175 const size_t dtlb_ways, 176 const size_t dtlb_sets, 177 const size_t icache_ways, 178 const size_t icache_sets, 179 const size_t icache_words, 180 const size_t dcache_ways, 181 const size_t dcache_sets, 182 const size_t dcache_words, 183 const size_t wbuf_nlines, 184 const size_t wbuf_nwords, 185 const size_t x_width, 186 const size_t y_width, 187 const uint32_t max_frozen_cycles, 188 const uint32_t debug_start_cycle, 189 const bool debug_ok ) 193 190 : soclib::caba::BaseModule(name), 194 191 195 p_clk("clk"), 196 p_resetn("resetn"), 197 p_vci_ini_d("vci_ini_d"), 198 p_dspin_in("dspin_in"), 199 p_dspin_out("dspin_out"), 200 201 m_cacheability_table(mtd.getCacheabilityTable()), 202 m_segment(mtc.getSegment(target_index_c)), 203 m_srcid_d(mtd.indexForId(initiator_index_d)), 204 m_srcid_c(mtc.indexForId(initiator_index_c)), 205 206 m_itlb_ways(itlb_ways), 207 m_itlb_sets(itlb_sets), 208 209 m_dtlb_ways(dtlb_ways), 210 m_dtlb_sets(dtlb_sets), 211 212 m_icache_ways(icache_ways), 213 m_icache_sets(icache_sets), 214 m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)), 215 m_icache_words(icache_words), 216 217 m_dcache_ways(dcache_ways), 218 m_dcache_sets(dcache_sets), 219 m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)), 220 m_dcache_words(dcache_words), 221 222 m_x_width(x_width), 223 m_y_width(y_width), 224 225 m_memory_cache_local_id(memory_cache_local_id), 226 m_proc_id(proc_id), 227 m_max_frozen_cycles(max_frozen_cycles), 228 m_paddr_nbits(vci_param::N), 229 230 m_debug_start_cycle(debug_start_cycle), 231 m_debug_ok(debug_ok), 192 p_clk("p_clk"), 193 p_resetn("p_resetn"), 194 p_vci("p_vci"), 195 p_dspin_in("p_dspin_in"), 196 p_dspin_out("p_dspin_out"), 197 198 m_cacheability_table( mtd.getCacheabilityTable() ), 199 m_srcid( mtd.indexForId(srcid) ), 200 m_cc_global_id( cc_global_id ), 201 m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ), 202 m_itlb_ways( itlb_ways ), 203 m_itlb_sets( itlb_sets ), 204 m_dtlb_ways( dtlb_ways ), 205 m_dtlb_sets( dtlb_sets ), 206 m_icache_ways( icache_ways ), 207 m_icache_sets( icache_sets ), 208 m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ), 209 m_icache_words( icache_words ), 210 m_dcache_ways( dcache_ways ), 211 m_dcache_sets( dcache_sets ), 212 m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ), 213 m_dcache_words( dcache_words ), 214 m_x_width( x_width ), 215 m_y_width( y_width ), 216 m_proc_id( proc_id ), 217 m_max_frozen_cycles( max_frozen_cycles ), 218 m_paddr_nbits( vci_param::N ), 219 m_debug_start_cycle( debug_start_cycle ), 220 m_debug_ok( debug_ok ), 232 221 233 222 r_mmu_ptpr("r_mmu_ptpr"), … … 3050 3039 // We should compute the access locality: 3051 3040 // The PPN MSB bits define the destination cluster index. 3052 // The m_srcid _dMSB bits define the source cluster index.3041 // The m_srcid MSB bits define the source cluster index. 3053 3042 // The number of bits to compare depends on the number of clusters, 3054 3043 // and can be obtained in the mapping table. … … 3305 3294 // We should compute the access locality: 3306 3295 // The PPN MSB bits define the destination cluster index. 3307 // The m_srcid _dMSB bits define the source cluster index.3296 // The m_srcid MSB bits define the source cluster index. 3308 3297 // The number of bits to compare depends on the number of clusters, 3309 3298 // and can be obtained in the mapping table. … … 5004 4993 case CMD_DATA_WRITE: 5005 4994 { 5006 if ( p_vci _ini_d.cmdack.read() )4995 if ( p_vci.cmdack.read() ) 5007 4996 { 5008 4997 r_vci_cmd_cpt = r_vci_cmd_cpt + 1; … … 5020 5009 { 5021 5010 // The CAS and SC VCI commands contain two flits 5022 if ( p_vci _ini_d.cmdack.read() )5011 if ( p_vci.cmdack.read() ) 5023 5012 { 5024 5013 r_vci_cmd_cpt = r_vci_cmd_cpt + 1; … … 5035 5024 { 5036 5025 // all read VCI commands contain one single flit 5037 if ( p_vci _ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE;5026 if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE; 5038 5027 break; 5039 5028 } … … 5073 5062 case RSP_IDLE: 5074 5063 { 5075 if ( p_vci _ini_d.rspval.read() )5064 if ( p_vci.rspval.read() ) 5076 5065 { 5077 5066 r_vci_rsp_cpt = 0; 5078 5067 5079 if ( (p_vci _ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC )5068 if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC ) 5080 5069 { 5081 5070 r_vci_rsp_fsm = RSP_DATA_UNC; 5082 5071 } 5083 else if ( (p_vci _ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS )5072 else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS ) 5084 5073 { 5085 5074 r_vci_rsp_fsm = RSP_DATA_MISS; 5086 5075 } 5087 else if ( (p_vci _ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_UNC )5076 else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC ) 5088 5077 { 5089 5078 r_vci_rsp_fsm = RSP_INS_UNC; 5090 5079 } 5091 else if ( (p_vci _ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_MISS )5080 else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS ) 5092 5081 { 5093 5082 r_vci_rsp_fsm = RSP_INS_MISS; 5094 5083 } 5095 else if ( (p_vci _ini_d.rpktid.read() & 0x7) == TYPE_WRITE )5084 else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE ) 5096 5085 { 5097 5086 r_vci_rsp_fsm = RSP_DATA_WRITE; 5098 5087 } 5099 else if ( (p_vci _ini_d.rpktid.read() & 0x7) == TYPE_CAS )5088 else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS ) 5100 5089 { 5101 5090 r_vci_rsp_fsm = RSP_DATA_UNC; 5102 5091 } 5103 else if ( (p_vci _ini_d.rpktid.read() & 0x7) == TYPE_LL )5092 else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL ) 5104 5093 { 5105 5094 r_vci_rsp_fsm = RSP_DATA_LL; 5106 5095 } 5107 else if ( (p_vci _ini_d.rpktid.read() & 0x7) == TYPE_SC )5096 else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC ) 5108 5097 { 5109 5098 r_vci_rsp_fsm = RSP_DATA_UNC; … … 5119 5108 case RSP_INS_MISS: 5120 5109 { 5121 if ( p_vci _ini_d.rspval.read() )5122 { 5123 if ( (p_vci _ini_d.rerror.read()&0x1) != 0 ) // error reported5110 if ( p_vci.rspval.read() ) 5111 { 5112 if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported 5124 5113 { 5125 5114 r_vci_rsp_ins_error = true; 5126 if ( p_vci _ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;5115 if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; 5127 5116 } 5128 5117 else // no error reported … … 5135 5124 r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; 5136 5125 vci_rsp_fifo_icache_put = true, 5137 vci_rsp_fifo_icache_data = p_vci _ini_d.rdata.read();5138 if ( p_vci _ini_d.reop.read() )5126 vci_rsp_fifo_icache_data = p_vci.rdata.read(); 5127 if ( p_vci.reop.read() ) 5139 5128 { 5140 5129 assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and … … 5151 5140 case RSP_INS_UNC: 5152 5141 { 5153 if (p_vci _ini_d.rspval.read() )5154 { 5155 assert( p_vci _ini_d.reop.read() and5142 if (p_vci.rspval.read() ) 5143 { 5144 assert( p_vci.reop.read() and 5156 5145 "illegal VCI response packet for uncachable instruction"); 5157 5146 5158 if ( (p_vci _ini_d.rerror.read()&0x1) != 0 ) // error reported5147 if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported 5159 5148 { 5160 5149 r_vci_rsp_ins_error = true; … … 5166 5155 { 5167 5156 vci_rsp_fifo_icache_put = true; 5168 vci_rsp_fifo_icache_data = p_vci _ini_d.rdata.read();5157 vci_rsp_fifo_icache_data = p_vci.rdata.read(); 5169 5158 r_vci_rsp_fsm = RSP_IDLE; 5170 5159 } … … 5176 5165 case RSP_DATA_MISS: 5177 5166 { 5178 if ( p_vci _ini_d.rspval.read() )5179 { 5180 if ( (p_vci _ini_d.rerror.read()&0x1) != 0 ) // error reported5167 if ( p_vci.rspval.read() ) 5168 { 5169 if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported 5181 5170 { 5182 5171 r_vci_rsp_data_error = true; 5183 if ( p_vci _ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;5172 if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; 5184 5173 } 5185 5174 else // no error reported … … 5192 5181 r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; 5193 5182 vci_rsp_fifo_dcache_put = true, 5194 vci_rsp_fifo_dcache_data = p_vci _ini_d.rdata.read();5195 if ( p_vci _ini_d.reop.read() )5183 vci_rsp_fifo_dcache_data = p_vci.rdata.read(); 5184 if ( p_vci.reop.read() ) 5196 5185 { 5197 5186 assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and … … 5208 5197 case RSP_DATA_UNC: 5209 5198 { 5210 if (p_vci _ini_d.rspval.read() )5211 { 5212 assert( p_vci _ini_d.reop.read() and5199 if (p_vci.rspval.read() ) 5200 { 5201 assert( p_vci.reop.read() and 5213 5202 "illegal VCI response packet for uncachable read data"); 5214 5203 5215 if ( (p_vci _ini_d.rerror.read()&0x1) != 0 ) // error reported5204 if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported 5216 5205 { 5217 5206 r_vci_rsp_data_error = true; … … 5223 5212 { 5224 5213 vci_rsp_fifo_dcache_put = true; 5225 vci_rsp_fifo_dcache_data = p_vci _ini_d.rdata.read();5214 vci_rsp_fifo_dcache_data = p_vci.rdata.read(); 5226 5215 r_vci_rsp_fsm = RSP_IDLE; 5227 5216 } … … 5233 5222 case RSP_DATA_LL: 5234 5223 { 5235 if ( p_vci _ini_d.rspval.read() )5236 { 5237 if ( (p_vci _ini_d.rerror.read()&0x1) != 0 ) // error reported5224 if ( p_vci.rspval.read() ) 5225 { 5226 if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported 5238 5227 { 5239 5228 r_vci_rsp_data_error = true; … … 5244 5233 if(r_vci_rsp_fifo_dcache.wok()) 5245 5234 { 5246 assert(!p_vci _ini_d.reop.read() &&5235 assert(!p_vci.reop.read() && 5247 5236 "illegal VCI response packet for LL"); 5248 5237 vci_rsp_fifo_dcache_put = true; 5249 vci_rsp_fifo_dcache_data = p_vci _ini_d.rdata.read();5238 vci_rsp_fifo_dcache_data = p_vci.rdata.read(); 5250 5239 r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; 5251 5240 } … … 5256 5245 if(r_vci_rsp_fifo_dcache.wok()) 5257 5246 { 5258 assert(p_vci _ini_d.reop.read() &&5247 assert(p_vci.reop.read() && 5259 5248 "illegal VCI response packet for LL"); 5260 5249 vci_rsp_fifo_dcache_put = true; 5261 vci_rsp_fifo_dcache_data = p_vci _ini_d.rdata.read();5250 vci_rsp_fifo_dcache_data = p_vci.rdata.read(); 5262 5251 r_vci_rsp_fsm = RSP_IDLE; 5263 5252 } … … 5270 5259 case RSP_DATA_WRITE: 5271 5260 { 5272 if (p_vci _ini_d.rspval.read())5273 { 5274 assert( p_vci _ini_d.reop.read() and5261 if (p_vci.rspval.read()) 5262 { 5263 assert( p_vci.reop.read() and 5275 5264 "a VCI response packet must contain one flit for a write transaction"); 5276 5265 5277 5266 r_vci_rsp_fsm = RSP_IDLE; 5278 uint32_t wbuf_index = p_vci _ini_d.rtrdid.read();5267 uint32_t wbuf_index = p_vci.rtrdid.read(); 5279 5268 bool cacheable = r_wbuf.completed(wbuf_index); 5280 5269 if ( not cacheable ) r_dcache_pending_unc_write = false; 5281 if ( (p_vci _ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();5270 if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); 5282 5271 } 5283 5272 break; … … 5545 5534 case CC_RECEIVE_INVAL_HEADER: 5546 5535 { 5547 // sample updt tab index in the HEADER, th an skip to second flit5536 // sample updt tab index in the HEADER, then skip to second flit 5548 5537 uint64_t receive_data = p_dspin_in.data.read(); 5549 5538 // for data INVAL, wait for dcache to take the request … … 5683 5672 vci_rsp_fifo_dcache_put, 5684 5673 vci_rsp_fifo_dcache_data); 5674 5685 5675 ///////////////// updt FIFO update ////////////////////// 5686 5676 //TODO check this … … 5708 5698 (r_vci_cmd_fsm.read() == CMD_DATA_SC ); 5709 5699 5710 p_vci _ini_d.pktid = 0;5711 p_vci _ini_d.srcid = m_srcid_d;5712 p_vci _ini_d.cons = is_sc_or_cas;5713 p_vci _ini_d.contig = not is_sc_or_cas;5714 p_vci _ini_d.wrap = false;5715 p_vci _ini_d.clen = 0;5716 p_vci _ini_d.cfixed = false;5700 p_vci.pktid = 0; 5701 p_vci.srcid = m_srcid; 5702 p_vci.cons = is_sc_or_cas; 5703 p_vci.contig = not is_sc_or_cas; 5704 p_vci.wrap = false; 5705 p_vci.clen = 0; 5706 p_vci.cfixed = false; 5717 5707 5718 5708 switch ( r_vci_cmd_fsm.read() ) { 5719 5709 5720 5710 case CMD_IDLE: 5721 p_vci _ini_d.cmdval = false;5722 p_vci _ini_d.address = 0;5723 p_vci _ini_d.wdata = 0;5724 p_vci _ini_d.be = 0;5725 p_vci _ini_d.trdid = 0;5726 p_vci _ini_d.pktid = 0;5727 p_vci _ini_d.plen = 0;5728 p_vci _ini_d.cmd = vci_param::CMD_NOP;5729 p_vci _ini_d.eop = false;5711 p_vci.cmdval = false; 5712 p_vci.address = 0; 5713 p_vci.wdata = 0; 5714 p_vci.be = 0; 5715 p_vci.trdid = 0; 5716 p_vci.pktid = 0; 5717 p_vci.plen = 0; 5718 p_vci.cmd = vci_param::CMD_NOP; 5719 p_vci.eop = false; 5730 5720 break; 5731 5721 5732 5722 case CMD_INS_MISS: 5733 p_vci _ini_d.cmdval = true;5734 p_vci _ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;5735 p_vci _ini_d.wdata = 0;5736 p_vci _ini_d.be = 0xF;5737 p_vci _ini_d.trdid = 0;5738 p_vci _ini_d.pktid = TYPE_READ_INS_MISS;5739 p_vci _ini_d.plen = m_icache_words<<2;5740 p_vci _ini_d.cmd = vci_param::CMD_READ;5741 p_vci _ini_d.eop = true;5723 p_vci.cmdval = true; 5724 p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask; 5725 p_vci.wdata = 0; 5726 p_vci.be = 0xF; 5727 p_vci.trdid = 0; 5728 p_vci.pktid = TYPE_READ_INS_MISS; 5729 p_vci.plen = m_icache_words<<2; 5730 p_vci.cmd = vci_param::CMD_READ; 5731 p_vci.eop = true; 5742 5732 break; 5743 5733 5744 5734 case CMD_INS_UNC: 5745 p_vci _ini_d.cmdval = true;5746 p_vci _ini_d.address = r_icache_vci_paddr.read() & ~0x3;5747 p_vci _ini_d.wdata = 0;5748 p_vci _ini_d.be = 0xF;5749 p_vci _ini_d.trdid = 0;5750 p_vci _ini_d.pktid = TYPE_READ_INS_UNC;5751 p_vci _ini_d.plen = 4;5752 p_vci _ini_d.cmd = vci_param::CMD_READ;5753 p_vci _ini_d.eop = true;5735 p_vci.cmdval = true; 5736 p_vci.address = r_icache_vci_paddr.read() & ~0x3; 5737 p_vci.wdata = 0; 5738 p_vci.be = 0xF; 5739 p_vci.trdid = 0; 5740 p_vci.pktid = TYPE_READ_INS_UNC; 5741 p_vci.plen = 4; 5742 p_vci.cmd = vci_param::CMD_READ; 5743 p_vci.eop = true; 5754 5744 break; 5755 5745 5756 5746 case CMD_DATA_MISS: 5757 p_vci _ini_d.cmdval = true;5758 p_vci _ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;5759 p_vci _ini_d.wdata = 0;5760 p_vci _ini_d.be = 0xF;5761 p_vci _ini_d.trdid = 0;5762 p_vci _ini_d.pktid = TYPE_READ_DATA_MISS;5763 p_vci _ini_d.plen = m_dcache_words << 2;5764 p_vci _ini_d.cmd = vci_param::CMD_READ;5765 p_vci _ini_d.eop = true;5747 p_vci.cmdval = true; 5748 p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; 5749 p_vci.wdata = 0; 5750 p_vci.be = 0xF; 5751 p_vci.trdid = 0; 5752 p_vci.pktid = TYPE_READ_DATA_MISS; 5753 p_vci.plen = m_dcache_words << 2; 5754 p_vci.cmd = vci_param::CMD_READ; 5755 p_vci.eop = true; 5766 5756 break; 5767 5757 5768 5758 case CMD_DATA_UNC: 5769 p_vci _ini_d.cmdval = true;5770 p_vci _ini_d.address = r_dcache_vci_paddr.read() & ~0x3;5771 p_vci _ini_d.wdata = 0;5772 p_vci _ini_d.be = r_dcache_vci_unc_be.read();5773 p_vci _ini_d.trdid = 0;5774 p_vci _ini_d.pktid = TYPE_READ_DATA_UNC;5775 p_vci _ini_d.plen = 4;5776 p_vci _ini_d.cmd = vci_param::CMD_READ;5777 p_vci _ini_d.eop = true;5759 p_vci.cmdval = true; 5760 p_vci.address = r_dcache_vci_paddr.read() & ~0x3; 5761 p_vci.wdata = 0; 5762 p_vci.be = r_dcache_vci_unc_be.read(); 5763 p_vci.trdid = 0; 5764 p_vci.pktid = TYPE_READ_DATA_UNC; 5765 p_vci.plen = 4; 5766 p_vci.cmd = vci_param::CMD_READ; 5767 p_vci.eop = true; 5778 5768 break; 5779 5769 5780 5770 case CMD_DATA_WRITE: 5781 p_vci _ini_d.cmdval = true;5782 p_vci _ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;5783 p_vci _ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());5784 p_vci _ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read());5785 p_vci _ini_d.trdid = r_wbuf.getIndex();5786 p_vci _ini_d.pktid = TYPE_WRITE;5787 p_vci _ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;5788 p_vci _ini_d.cmd = vci_param::CMD_WRITE;5789 p_vci _ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());5771 p_vci.cmdval = true; 5772 p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; 5773 p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); 5774 p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); 5775 p_vci.trdid = r_wbuf.getIndex(); 5776 p_vci.pktid = TYPE_WRITE; 5777 p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; 5778 p_vci.cmd = vci_param::CMD_WRITE; 5779 p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); 5790 5780 break; 5791 5781 5792 5782 case CMD_DATA_LL: 5793 p_vci _ini_d.cmdval = true;5794 p_vci _ini_d.address = r_dcache_vci_paddr.read() & ~0x3;5795 p_vci _ini_d.wdata = 0;5796 p_vci _ini_d.be = 0xF;5797 p_vci _ini_d.trdid = 0;5798 p_vci _ini_d.pktid = TYPE_LL;5799 p_vci _ini_d.plen = 8;5800 p_vci _ini_d.cmd = vci_param::CMD_LOCKED_READ;5801 p_vci _ini_d.eop = true;5783 p_vci.cmdval = true; 5784 p_vci.address = r_dcache_vci_paddr.read() & ~0x3; 5785 p_vci.wdata = 0; 5786 p_vci.be = 0xF; 5787 p_vci.trdid = 0; 5788 p_vci.pktid = TYPE_LL; 5789 p_vci.plen = 8; 5790 p_vci.cmd = vci_param::CMD_LOCKED_READ; 5791 p_vci.eop = true; 5802 5792 break; 5803 5793 5804 5794 case CMD_DATA_SC: 5805 p_vci _ini_d.cmdval = true;5806 p_vci _ini_d.address = r_dcache_vci_paddr.read() & ~0x3;5807 if ( r_vci_cmd_cpt.read() == 0 ) p_vci _ini_d.wdata = r_dcache_llsc_key.read();5808 else p_vci _ini_d.wdata = r_dcache_vci_sc_data.read();5809 p_vci _ini_d.be = 0xF;5810 p_vci _ini_d.trdid = 0;5811 p_vci _ini_d.pktid = TYPE_SC;5812 p_vci _ini_d.plen = 8;5813 p_vci _ini_d.cmd = vci_param::CMD_NOP;5814 p_vci _ini_d.eop = (r_vci_cmd_cpt.read() == 1);5795 p_vci.cmdval = true; 5796 p_vci.address = r_dcache_vci_paddr.read() & ~0x3; 5797 if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read(); 5798 else p_vci.wdata = r_dcache_vci_sc_data.read(); 5799 p_vci.be = 0xF; 5800 p_vci.trdid = 0; 5801 p_vci.pktid = TYPE_SC; 5802 p_vci.plen = 8; 5803 p_vci.cmd = vci_param::CMD_NOP; 5804 p_vci.eop = (r_vci_cmd_cpt.read() == 1); 5815 5805 break; 5816 5806 5817 5807 case CMD_DATA_CAS: 5818 p_vci _ini_d.cmdval = true;5819 p_vci _ini_d.address = r_dcache_vci_paddr.read() & ~0x3;5820 if ( r_vci_cmd_cpt.read() == 0 ) p_vci _ini_d.wdata = r_dcache_vci_cas_old.read();5821 else p_vci _ini_d.wdata = r_dcache_vci_cas_new.read();5822 p_vci _ini_d.be = 0xF;5823 p_vci _ini_d.trdid = 0;5824 p_vci _ini_d.pktid = TYPE_CAS;5825 p_vci _ini_d.plen = 8;5826 p_vci _ini_d.cmd = vci_param::CMD_NOP;5827 p_vci _ini_d.eop = (r_vci_cmd_cpt.read() == 1);5808 p_vci.cmdval = true; 5809 p_vci.address = r_dcache_vci_paddr.read() & ~0x3; 5810 if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read(); 5811 else p_vci.wdata = r_dcache_vci_cas_new.read(); 5812 p_vci.be = 0xF; 5813 p_vci.trdid = 0; 5814 p_vci.pktid = TYPE_CAS; 5815 p_vci.plen = 8; 5816 p_vci.cmd = vci_param::CMD_NOP; 5817 p_vci.eop = (r_vci_cmd_cpt.read() == 1); 5828 5818 break; 5829 5819 } // end switch r_vci_cmd_fsm 5830 5820 5831 5821 // VCI initiator response on the direct network 5832 // it depends on the VCI RSP state5822 // it depends on the VCI_RSP FSM 5833 5823 5834 5824 switch (r_vci_rsp_fsm.read() ) 5835 5825 { 5836 case RSP_DATA_WRITE : p_vci _ini_d.rspack = true; break;5837 case RSP_INS_MISS : p_vci _ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;5838 case RSP_INS_UNC : p_vci _ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;5839 case RSP_DATA_MISS : p_vci _ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;5840 case RSP_DATA_UNC : p_vci _ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;5841 case RSP_DATA_LL : p_vci _ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;5842 case RSP_IDLE : p_vci _ini_d.rspack = false; break;5826 case RSP_DATA_WRITE : p_vci.rspack = true; break; 5827 case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; 5828 case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; 5829 case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; 5830 case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; 5831 case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; 5832 case RSP_IDLE : p_vci.rspack = false; break; 5843 5833 } // end switch r_vci_rsp_fsm 5844 5834 5845 ///////////////// 5846 // CC_SEND FSM // 5847 ///////////////// 5835 5836 // Send coherence packets on DSPIN L2M 5837 // it depends on the CC_SEND FSM 5838 5848 5839 uint64_t dspin_send_data = 0; 5849 5840 switch ( r_cc_send_fsm.read() ) 5850 5841 { 5851 ////////////////// /////////5842 ////////////////// 5852 5843 case CC_SEND_IDLE: 5853 5844 { … … 5855 5846 break; 5856 5847 } 5857 /////////////////////// ////5848 /////////////////////// 5858 5849 case CC_SEND_CLEANUP_1: 5859 5850 { 5860 5851 // initialize dspin send data 5861 DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_EOP); 5862 DspinDhccpParam::dspin_set(dspin_send_data,m_srcid_c,DspinDhccpParam::CLEANUP_SRCID); 5863 DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC); 5864 // dcache active request 5865 if(r_cc_send_last_client.read() == 0) 5866 { 5867 // compute global id 5868 uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B)); 5869 uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read(); 5870 global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 5871 5852 DspinDhccpParam::dspin_set(dspin_send_data, 5853 0, 5854 DspinDhccpParam::FROM_L1_EOP); 5855 DspinDhccpParam::dspin_set(dspin_send_data, 5856 m_cc_global_id, 5857 DspinDhccpParam::CLEANUP_SRCID); 5858 DspinDhccpParam::dspin_set(dspin_send_data, 5859 0, 5860 DspinDhccpParam::FROM_L1_BC); 5861 5862 if(r_cc_send_last_client.read() == 0) // dcache active request 5863 { 5864 uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read() 5865 >> (m_nline_width - m_x_width - m_y_width) 5866 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 5867 5872 5868 DspinDhccpParam::dspin_set(dspin_send_data, 5873 global_id,5874 DspinDhccpParam::CLEANUP_DEST);5869 dest, 5870 DspinDhccpParam::CLEANUP_DEST); 5875 5871 5876 5872 DspinDhccpParam::dspin_set(dspin_send_data, 5877 r_dcache_cc_send_nline.read() & 0x300000000ULL,5878 DspinDhccpParam::CLEANUP_NLINE_MSB);5873 r_dcache_cc_send_nline.read() & 0x300000000ULL, 5874 DspinDhccpParam::CLEANUP_NLINE_MSB); 5879 5875 5880 5876 DspinDhccpParam::dspin_set(dspin_send_data, 5881 r_dcache_cc_send_way.read(),5882 DspinDhccpParam::CLEANUP_WAY_INDEX);5877 r_dcache_cc_send_way.read(), 5878 DspinDhccpParam::CLEANUP_WAY_INDEX); 5883 5879 5884 5880 DspinDhccpParam::dspin_set(dspin_send_data, 5885 DspinDhccpParam::TYPE_CLEANUP_DATA, 5886 DspinDhccpParam::FROM_L1_TYPE); 5887 } 5888 // icache active request 5889 else 5890 { 5891 // compute global id 5892 uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B)); 5893 uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read(); 5894 global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 5881 DspinDhccpParam::TYPE_CLEANUP_DATA, 5882 DspinDhccpParam::FROM_L1_TYPE); 5883 } 5884 else // icache active request 5885 { 5886 uint64_t dest = (uint64_t)r_icache_cc_send_nline.read() 5887 >> (m_nline_width - m_x_width - m_y_width) 5888 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 5895 5889 5896 5890 DspinDhccpParam::dspin_set(dspin_send_data, 5897 global_id,5898 DspinDhccpParam::CLEANUP_DEST);5891 dest, 5892 DspinDhccpParam::CLEANUP_DEST); 5899 5893 5900 5894 DspinDhccpParam::dspin_set(dspin_send_data, 5901 r_icache_cc_send_nline.read() & 0x300000000ULL,5902 DspinDhccpParam::CLEANUP_NLINE_MSB);5895 r_icache_cc_send_nline.read() & 0x300000000ULL, 5896 DspinDhccpParam::CLEANUP_NLINE_MSB); 5903 5897 5904 5898 DspinDhccpParam::dspin_set(dspin_send_data, 5905 r_icache_cc_send_way.read(),5906 DspinDhccpParam::CLEANUP_WAY_INDEX);5899 r_icache_cc_send_way.read(), 5900 DspinDhccpParam::CLEANUP_WAY_INDEX); 5907 5901 5908 5902 DspinDhccpParam::dspin_set(dspin_send_data, 5909 DspinDhccpParam::TYPE_CLEANUP_INST,5910 DspinDhccpParam::FROM_L1_TYPE);5903 DspinDhccpParam::TYPE_CLEANUP_INST, 5904 DspinDhccpParam::FROM_L1_TYPE); 5911 5905 } 5912 5906 // send flit … … 5915 5909 break; 5916 5910 } 5917 /////////////////////// ////5911 /////////////////////// 5918 5912 case CC_SEND_CLEANUP_2: 5919 5913 { 5920 5914 // initialize dspin send data 5921 DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP); 5922 // dcache active request 5923 if(r_cc_send_last_client.read() == 0) 5915 DspinDhccpParam::dspin_set(dspin_send_data, 5916 1, 5917 DspinDhccpParam::FROM_L1_EOP); 5918 5919 if(r_cc_send_last_client.read() == 0) // dcache active request 5924 5920 { 5925 5921 DspinDhccpParam::dspin_set(dspin_send_data, 5926 r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, 5927 DspinDhccpParam::CLEANUP_NLINE_LSB); 5928 } 5929 // icache active request 5930 else 5922 r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, 5923 DspinDhccpParam::CLEANUP_NLINE_LSB); 5924 } 5925 else // icache active request 5931 5926 { 5932 5927 DspinDhccpParam::dspin_set(dspin_send_data, 5933 r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,5934 DspinDhccpParam::CLEANUP_NLINE_LSB);5928 r_icache_cc_send_nline.read() & 0xFFFFFFFFULL, 5929 DspinDhccpParam::CLEANUP_NLINE_LSB); 5935 5930 } 5936 5931 // send flit … … 5939 5934 break; 5940 5935 } 5941 /////////////////////// ////5936 /////////////////////// 5942 5937 case CC_SEND_MULTI_ACK: 5943 5938 { 5944 5939 // initialize dspin send data 5945 DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP);5946 DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC);5947 5940 DspinDhccpParam::dspin_set(dspin_send_data, 5948 DspinDhccpParam::TYPE_MULTI_ACK, 5949 DspinDhccpParam::FROM_L1_TYPE); 5950 // dcache active request 5951 if(r_cc_send_last_client.read() == 0) 5952 { 5953 // compute global id 5954 uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B)); 5955 uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read(); 5956 global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 5957 5941 1, 5942 DspinDhccpParam::FROM_L1_EOP); 5943 DspinDhccpParam::dspin_set(dspin_send_data, 5944 0, 5945 DspinDhccpParam::FROM_L1_BC); 5946 DspinDhccpParam::dspin_set(dspin_send_data, 5947 DspinDhccpParam::TYPE_MULTI_ACK, 5948 DspinDhccpParam::FROM_L1_TYPE); 5949 5950 if(r_cc_send_last_client.read() == 0) // dcache active request 5951 { 5952 uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read() 5953 >> (m_nline_width - m_x_width - m_y_width) 5954 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 5955 5958 5956 DspinDhccpParam::dspin_set(dspin_send_data, 5959 global_id,5960 DspinDhccpParam::MULTI_ACK_DEST);5957 dest, 5958 DspinDhccpParam::MULTI_ACK_DEST); 5961 5959 5962 5960 DspinDhccpParam::dspin_set(dspin_send_data, 5963 r_dcache_cc_send_updt_tab_idx.read(), 5964 DspinDhccpParam::MULTI_ACK_UPDT_INDEX); 5965 } 5966 // icache active request 5967 else 5968 { 5969 // compute global id 5970 uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B)); 5971 uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read(); 5972 global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 5961 r_dcache_cc_send_updt_tab_idx.read(), 5962 DspinDhccpParam::MULTI_ACK_UPDT_INDEX); 5963 } 5964 else // icache active request 5965 { 5966 uint64_t dest = (uint64_t)r_icache_cc_send_nline.read() 5967 >> (m_nline_width - m_x_width - m_y_width) 5968 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 5969 5973 5970 5974 5971 DspinDhccpParam::dspin_set(dspin_send_data, 5975 global_id,5976 DspinDhccpParam::MULTI_ACK_DEST);5972 dest, 5973 DspinDhccpParam::MULTI_ACK_DEST); 5977 5974 5978 5975 DspinDhccpParam::dspin_set(dspin_send_data, 5979 r_icache_cc_send_updt_tab_idx.read(),5980 DspinDhccpParam::MULTI_ACK_UPDT_INDEX);5976 r_icache_cc_send_updt_tab_idx.read(), 5977 DspinDhccpParam::MULTI_ACK_UPDT_INDEX); 5981 5978 } 5982 5979 // send flit … … 5987 5984 } // end switch CC_SEND FSM 5988 5985 5989 // //////////////////5990 // CC_RECEIVE FSM //5991 //////////////////// 5986 // Receive coherence packets 5987 // It depends on the CC_RECEIVE FSM 5988 5992 5989 switch( r_cc_receive_fsm.read() ) 5993 5990 {
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