Index: branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h
===================================================================
--- branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h	(revision 336)
+++ branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h	(revision 346)
@@ -326,6 +326,4 @@
 
       // debug variables (for each FSM)
-      size_t       m_debug_start_cycle;
-      bool         m_debug_ok;
       bool         m_debug_global;
       bool         m_debug_tgt_cmd_fsm;
@@ -379,5 +377,4 @@
       soclib::caba::VciTarget<vci_param>    p_vci_tgt;
       soclib::caba::VciInitiator<vci_param> p_vci_ixr;
-
       soclib::caba::DspinInput<33>          p_dspin_in;
       soclib::caba::DspinOutput<40>         p_dspin_out;
@@ -385,19 +382,18 @@
       VciMemCache(
           sc_module_name name,                                // Instance Name
-          const soclib::common::MappingTable &mtp,            // Mapping table for primary requets
-          const soclib::common::MappingTable &mtc,            // Mapping table for coherence requets
-          const soclib::common::MappingTable &mtx,            // Mapping table for XRAM
-          const soclib::common::IntTab &vci_ixr_index,        // VCI port to XRAM (initiator)
-          const soclib::common::IntTab &vci_ini_index,        // VCI port to PROC (initiator)
-          const soclib::common::IntTab &vci_tgt_index,        // VCI port to PROC (target)
-          const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
-          size_t nways,                                       // Number of ways per set
-          size_t nsets,                                       // Number of sets
-          size_t nwords,                                      // Number of words per line
-          size_t heap_size=1024,                              // Size of the heap
-          size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
-          size_t update_tab_lines=UPDATE_TAB_LINES,           // Size of the UPT
-          size_t debug_start_cycle=0,
-          bool   debug_ok=false);
+          const soclib::common::MappingTable &mtp,            // Mapping table for direct network
+          const soclib::common::MappingTable &mtx,            // Mapping table for external network
+          const soclib::common::IntTab       &srcid_x,        // global index on external network
+          const soclib::common::IntTab       &tgtid_d,        // global index on direct network
+          const size_t                       cc_global_id,    // global index on cc network
+          const size_t                       nways,           // Number of ways per set
+          const size_t                       nsets,           // Number of sets
+          const size_t                       nwords,          // Number of words per line
+          const size_t                       max_copies,      // max number of copies in heap
+          const size_t                       heap_size=1024,  // number of heap entries
+          const size_t                       trt_lines=TRANSACTION_TAB_LINES, 
+          const size_t                       upt_lines=UPDATE_TAB_LINES,       
+          const size_t                       debug_start_cycle=0,
+          const bool                         debug_ok=false );
 
       ~VciMemCache();
@@ -417,45 +413,39 @@
 
       // Component attributes
-      std::list<soclib::common::Segment> m_seglist;  // memory cached into the cache
-      std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
-
-      const size_t    m_initiators; // Number of initiators
-      const size_t    m_heap_size;  // Size of the heap
-      const size_t    m_ways;       // Number of ways in a set
-      const size_t    m_sets;       // Number of cache sets
-      const size_t    m_words;      // Number of words in a line
-      const size_t    m_srcid_ixr;  // Srcid for requests to XRAM
-      const size_t    m_srcid_ini;  // Srcid for requests to processors
-
-      uint32_t        m_transaction_tab_lines;
-      TransactionTab  m_transaction_tab;  // xram transaction table
-      uint32_t        m_update_tab_lines;
-      UpdateTab       m_update_tab;       // pending update & invalidate
-      CacheDirectory  m_cache_directory;  // data cache directory
-      CacheData       m_cache_data;       // data array[set][way][word]
-      HeapDirectory   m_heap;             // heap for copies
+      std::list<soclib::common::Segment> m_seglist;          // segments allocated to memcache
+      size_t                             m_nseg;             // number of segments
+      soclib::common::Segment            **m_seg;            // array of segments pointers
+      const size_t                       m_srcid_x;          // global index on external network
+      const size_t                       m_initiators;       // Number of initiators
+      const size_t                       m_heap_size;        // Size of the heap
+      const size_t                       m_ways;             // Number of ways in a set
+      const size_t                       m_sets;             // Number of cache sets
+      const size_t                       m_words;            // Number of words in a line
+      const size_t                       m_cc_global_id;     // global_index on cc network
+      size_t                             m_debug_start_cycle;
+      bool                               m_debug_ok;
+      uint32_t                           m_trt_lines;
+      TransactionTab                     m_trt;              // xram transaction table
+      uint32_t                           m_upt_lines;
+      UpdateTab                          m_upt;              // pending update & invalidate
+      CacheDirectory                     m_cache_directory;  // data cache directory
+      CacheData                          m_cache_data;       // data array[set][way][word]
+      HeapDirectory                      m_heap;             // heap for copies
+      size_t                             m_max_copies;       // max number of copies in heap
       GenericLLSCGlobalTable
-      <
-        32  ,   // desired number of slots
-        4096,   // number of processors in the system
-        8000,   // registratioÃ§n life span (in # of LL operations)
-        typename vci_param::fast_addr_t // address type
-      >
-      m_llsc_table;       // ll/sc global registration table
+      < 32  ,                              // number of slots
+        4096,                              // number of processors in the system
+        8000,                              // registratioÃ§n life span (in # of LL operations)
+        typename vci_param::fast_addr_t >  // address type
+                                         m_llsc_table;       // ll/sc global registration table
 
       // adress masks
-      const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
-      const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
-      const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
-      const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline;
 
       // broadcast address
-      uint32_t m_broadcast_address;
-
-      //////////////////////////////////////////////////
-      // Others registers
-      //////////////////////////////////////////////////
-      sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
-      sc_signal<size_t> xxx_count;
+      uint32_t                                                m_broadcast_address;
 
       //////////////////////////////////////////////////
@@ -495,8 +485,4 @@
       sc_signal<int>         r_tgt_cmd_fsm;
 
-      size_t                   m_nseg;
-      size_t                   m_ncseg;
-      soclib::common::Segment  **m_seg;
-      soclib::common::Segment  **m_cseg;
       ///////////////////////////////////////////////////////
       // Registers controlled by the READ fsm
