Index: branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/include/vci_cc_vcache_wrapper_dspin_coherence.h =================================================================== --- branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/include/vci_cc_vcache_wrapper_dspin_coherence.h (revision 341) +++ branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/include/vci_cc_vcache_wrapper_dspin_coherence.h (revision 346) @@ -1,3 +1,4 @@ /* -*- c++ -*- + * * File : vci_cc_vcache_wrapper.h * Copyright (c) UPMC, Lip6, SoC @@ -285,39 +286,35 @@ sc_in p_resetn; sc_in p_irq[iss_t::n_irq]; - soclib::caba::VciInitiator p_vci_ini_d; - soclib::caba::DspinInput <40> p_dspin_in; - soclib::caba::DspinOutput<33> p_dspin_out; + soclib::caba::VciInitiator p_vci; + soclib::caba::DspinInput <40> p_dspin_in; + soclib::caba::DspinOutput<33> p_dspin_out; private: // STRUCTURAL PARAMETERS - soclib::common::AddressDecodingTable m_cacheability_table; - const soclib::common::Segment m_segment; - const vci_srcid_t m_srcid_d; - const vci_srcid_t m_srcid_c; - + soclib::common::AddressDecodingTable m_cacheability_table; + + const vci_srcid_t m_srcid; + const size_t m_cc_global_id; + const size_t m_nline_width; const size_t m_itlb_ways; const size_t m_itlb_sets; - const size_t m_dtlb_ways; const size_t m_dtlb_sets; - const size_t m_icache_ways; const size_t m_icache_sets; const paddr_t m_icache_yzmask; const size_t m_icache_words; - const size_t m_dcache_ways; const size_t m_dcache_sets; const paddr_t m_dcache_yzmask; const size_t m_dcache_words; - const size_t m_x_width; const size_t m_y_width; - - const size_t m_memory_cache_local_id; const size_t m_proc_id; const uint32_t m_max_frozen_cycles; const size_t m_paddr_nbits; + uint32_t m_debug_start_cycle; + bool m_debug_ok; //////////////////////////////////////// @@ -332,6 +329,4 @@ // debug variables (for each FSM) ///////////////////////////////////////////// - uint32_t m_debug_start_cycle; - bool m_debug_ok; bool m_debug_previous_hit; bool m_idebug_previous_hit; @@ -686,29 +681,26 @@ public: VciCcVCacheWrapper( - sc_module_name insname, - int proc_id, - const soclib::common::MappingTable &mtp, - const soclib::common::MappingTable &mtc, - const soclib::common::IntTab &initiator_index_d, - const soclib::common::IntTab &initiator_index_c, - const soclib::common::IntTab &target_index_d, - size_t itlb_ways, - size_t itlb_sets, - size_t dtlb_ways, - size_t dtlb_sets, - size_t icache_ways, - size_t icache_sets, - size_t icache_words, - size_t dcache_ways, - size_t dcache_sets, - size_t dcache_words, - size_t wbuf_nlines, - size_t wbuf_nwords, - size_t x_width, - size_t y_width, - uint32_t memory_cache_local_id, - uint32_t max_frozen_cycles, - uint32_t debug_start_cycle, - bool debug_ok); + sc_module_name name, + const int proc_id, + const soclib::common::MappingTable &mtd, + const soclib::common::IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok ); ~VciCcVCacheWrapper(); Index: branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp =================================================================== --- branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp (revision 341) +++ branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp (revision 346) @@ -162,72 +162,61 @@ #define tmpl(...) template __VA_ARGS__ VciCcVCacheWrapper -using soclib::common::uint32_log2; +using namespace soclib::common; ///////////////////////////////// tmpl(/**/)::VciCcVCacheWrapper( sc_module_name name, - int proc_id, - const soclib::common::MappingTable &mtd, - const soclib::common::MappingTable &mtc, - const soclib::common::IntTab &initiator_index_d, - const soclib::common::IntTab &initiator_index_c, - const soclib::common::IntTab &target_index_c, - size_t itlb_ways, - size_t itlb_sets, - size_t dtlb_ways, - size_t dtlb_sets, - size_t icache_ways, - size_t icache_sets, - size_t icache_words, - size_t dcache_ways, - size_t dcache_sets, - size_t dcache_words, - size_t wbuf_nlines, - size_t wbuf_nwords, - size_t x_width, - size_t y_width, - uint32_t memory_cache_local_id, - uint32_t max_frozen_cycles, - uint32_t debug_start_cycle, - bool debug_ok) + const int proc_id, + const MappingTable &mtd, + const IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok ) : soclib::caba::BaseModule(name), - p_clk("clk"), - p_resetn("resetn"), - p_vci_ini_d("vci_ini_d"), - p_dspin_in("dspin_in"), - p_dspin_out("dspin_out"), - - m_cacheability_table(mtd.getCacheabilityTable()), - m_segment(mtc.getSegment(target_index_c)), - m_srcid_d(mtd.indexForId(initiator_index_d)), - m_srcid_c(mtc.indexForId(initiator_index_c)), - - m_itlb_ways(itlb_ways), - m_itlb_sets(itlb_sets), - - m_dtlb_ways(dtlb_ways), - m_dtlb_sets(dtlb_sets), - - m_icache_ways(icache_ways), - m_icache_sets(icache_sets), - m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)), - m_icache_words(icache_words), - - m_dcache_ways(dcache_ways), - m_dcache_sets(dcache_sets), - m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)), - m_dcache_words(dcache_words), - - m_x_width(x_width), - m_y_width(y_width), - - m_memory_cache_local_id(memory_cache_local_id), - m_proc_id(proc_id), - m_max_frozen_cycles(max_frozen_cycles), - m_paddr_nbits(vci_param::N), - - m_debug_start_cycle(debug_start_cycle), - m_debug_ok(debug_ok), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_vci("p_vci"), + p_dspin_in("p_dspin_in"), + p_dspin_out("p_dspin_out"), + + m_cacheability_table( mtd.getCacheabilityTable() ), + m_srcid( mtd.indexForId(srcid) ), + m_cc_global_id( cc_global_id ), + m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ), + m_itlb_ways( itlb_ways ), + m_itlb_sets( itlb_sets ), + m_dtlb_ways( dtlb_ways ), + m_dtlb_sets( dtlb_sets ), + m_icache_ways( icache_ways ), + m_icache_sets( icache_sets ), + m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ), + m_icache_words( icache_words ), + m_dcache_ways( dcache_ways ), + m_dcache_sets( dcache_sets ), + m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ), + m_dcache_words( dcache_words ), + m_x_width( x_width ), + m_y_width( y_width ), + m_proc_id( proc_id ), + m_max_frozen_cycles( max_frozen_cycles ), + m_paddr_nbits( vci_param::N ), + m_debug_start_cycle( debug_start_cycle ), + m_debug_ok( debug_ok ), r_mmu_ptpr("r_mmu_ptpr"), @@ -3050,5 +3039,5 @@ // We should compute the access locality: // The PPN MSB bits define the destination cluster index. - // The m_srcid_d MSB bits define the source cluster index. + // The m_srcid MSB bits define the source cluster index. // The number of bits to compare depends on the number of clusters, // and can be obtained in the mapping table. @@ -3305,5 +3294,5 @@ // We should compute the access locality: // The PPN MSB bits define the destination cluster index. - // The m_srcid_d MSB bits define the source cluster index. + // The m_srcid MSB bits define the source cluster index. // The number of bits to compare depends on the number of clusters, // and can be obtained in the mapping table. @@ -5004,5 +4993,5 @@ case CMD_DATA_WRITE: { - if ( p_vci_ini_d.cmdack.read() ) + if ( p_vci.cmdack.read() ) { r_vci_cmd_cpt = r_vci_cmd_cpt + 1; @@ -5020,5 +5009,5 @@ { // The CAS and SC VCI commands contain two flits - if ( p_vci_ini_d.cmdack.read() ) + if ( p_vci.cmdack.read() ) { r_vci_cmd_cpt = r_vci_cmd_cpt + 1; @@ -5035,5 +5024,5 @@ { // all read VCI commands contain one single flit - if ( p_vci_ini_d.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE; + if ( p_vci.cmdack.read() ) r_vci_cmd_fsm = CMD_IDLE; break; } @@ -5073,37 +5062,37 @@ case RSP_IDLE: { - if ( p_vci_ini_d.rspval.read() ) + if ( p_vci.rspval.read() ) { r_vci_rsp_cpt = 0; - if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC ) + if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC ) { r_vci_rsp_fsm = RSP_DATA_UNC; } - else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS ) + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS ) { r_vci_rsp_fsm = RSP_DATA_MISS; } - else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_UNC ) + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC ) { r_vci_rsp_fsm = RSP_INS_UNC; } - else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_READ_INS_MISS ) + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS ) { r_vci_rsp_fsm = RSP_INS_MISS; } - else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_WRITE ) + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE ) { r_vci_rsp_fsm = RSP_DATA_WRITE; } - else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_CAS ) + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS ) { r_vci_rsp_fsm = RSP_DATA_UNC; } - else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_LL ) + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL ) { r_vci_rsp_fsm = RSP_DATA_LL; } - else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_SC ) + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC ) { r_vci_rsp_fsm = RSP_DATA_UNC; @@ -5119,10 +5108,10 @@ case RSP_INS_MISS: { - if ( p_vci_ini_d.rspval.read() ) - { - if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported { r_vci_rsp_ins_error = true; - if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; } else // no error reported @@ -5135,6 +5124,6 @@ r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; vci_rsp_fifo_icache_put = true, - vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read(); - if ( p_vci_ini_d.reop.read() ) + vci_rsp_fifo_icache_data = p_vci.rdata.read(); + if ( p_vci.reop.read() ) { assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and @@ -5151,10 +5140,10 @@ case RSP_INS_UNC: { - if (p_vci_ini_d.rspval.read() ) - { - assert( p_vci_ini_d.reop.read() and + if (p_vci.rspval.read() ) + { + assert( p_vci.reop.read() and "illegal VCI response packet for uncachable instruction"); - if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported { r_vci_rsp_ins_error = true; @@ -5166,5 +5155,5 @@ { vci_rsp_fifo_icache_put = true; - vci_rsp_fifo_icache_data = p_vci_ini_d.rdata.read(); + vci_rsp_fifo_icache_data = p_vci.rdata.read(); r_vci_rsp_fsm = RSP_IDLE; } @@ -5176,10 +5165,10 @@ case RSP_DATA_MISS: { - if ( p_vci_ini_d.rspval.read() ) - { - if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported { r_vci_rsp_data_error = true; - if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; } else // no error reported @@ -5192,6 +5181,6 @@ r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; vci_rsp_fifo_dcache_put = true, - vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); - if ( p_vci_ini_d.reop.read() ) + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + if ( p_vci.reop.read() ) { assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and @@ -5208,10 +5197,10 @@ case RSP_DATA_UNC: { - if (p_vci_ini_d.rspval.read() ) - { - assert( p_vci_ini_d.reop.read() and + if (p_vci.rspval.read() ) + { + assert( p_vci.reop.read() and "illegal VCI response packet for uncachable read data"); - if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported { r_vci_rsp_data_error = true; @@ -5223,5 +5212,5 @@ { vci_rsp_fifo_dcache_put = true; - vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); r_vci_rsp_fsm = RSP_IDLE; } @@ -5233,7 +5222,7 @@ case RSP_DATA_LL: { - if ( p_vci_ini_d.rspval.read() ) - { - if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) // error reported + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported { r_vci_rsp_data_error = true; @@ -5244,8 +5233,8 @@ if(r_vci_rsp_fifo_dcache.wok()) { - assert(!p_vci_ini_d.reop.read() && + assert(!p_vci.reop.read() && "illegal VCI response packet for LL"); vci_rsp_fifo_dcache_put = true; - vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; } @@ -5256,8 +5245,8 @@ if(r_vci_rsp_fifo_dcache.wok()) { - assert(p_vci_ini_d.reop.read() && + assert(p_vci.reop.read() && "illegal VCI response packet for LL"); vci_rsp_fifo_dcache_put = true; - vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read(); + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); r_vci_rsp_fsm = RSP_IDLE; } @@ -5270,14 +5259,14 @@ case RSP_DATA_WRITE: { - if (p_vci_ini_d.rspval.read()) - { - assert( p_vci_ini_d.reop.read() and + if (p_vci.rspval.read()) + { + assert( p_vci.reop.read() and "a VCI response packet must contain one flit for a write transaction"); r_vci_rsp_fsm = RSP_IDLE; - uint32_t wbuf_index = p_vci_ini_d.rtrdid.read(); + uint32_t wbuf_index = p_vci.rtrdid.read(); bool cacheable = r_wbuf.completed(wbuf_index); if ( not cacheable ) r_dcache_pending_unc_write = false; - if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); + if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); } break; @@ -5545,5 +5534,5 @@ case CC_RECEIVE_INVAL_HEADER: { - // sample updt tab index in the HEADER, than skip to second flit + // sample updt tab index in the HEADER, then skip to second flit uint64_t receive_data = p_dspin_in.data.read(); // for data INVAL, wait for dcache to take the request @@ -5683,4 +5672,5 @@ vci_rsp_fifo_dcache_put, vci_rsp_fifo_dcache_data); + ///////////////// updt FIFO update ////////////////////// //TODO check this @@ -5708,146 +5698,147 @@ (r_vci_cmd_fsm.read() == CMD_DATA_SC ); - p_vci_ini_d.pktid = 0; - p_vci_ini_d.srcid = m_srcid_d; - p_vci_ini_d.cons = is_sc_or_cas; - p_vci_ini_d.contig = not is_sc_or_cas; - p_vci_ini_d.wrap = false; - p_vci_ini_d.clen = 0; - p_vci_ini_d.cfixed = false; + p_vci.pktid = 0; + p_vci.srcid = m_srcid; + p_vci.cons = is_sc_or_cas; + p_vci.contig = not is_sc_or_cas; + p_vci.wrap = false; + p_vci.clen = 0; + p_vci.cfixed = false; switch ( r_vci_cmd_fsm.read() ) { case CMD_IDLE: - p_vci_ini_d.cmdval = false; - p_vci_ini_d.address = 0; - p_vci_ini_d.wdata = 0; - p_vci_ini_d.be = 0; - p_vci_ini_d.trdid = 0; - p_vci_ini_d.pktid = 0; - p_vci_ini_d.plen = 0; - p_vci_ini_d.cmd = vci_param::CMD_NOP; - p_vci_ini_d.eop = false; + p_vci.cmdval = false; + p_vci.address = 0; + p_vci.wdata = 0; + p_vci.be = 0; + p_vci.trdid = 0; + p_vci.pktid = 0; + p_vci.plen = 0; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = false; break; case CMD_INS_MISS: - p_vci_ini_d.cmdval = true; - p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask; - p_vci_ini_d.wdata = 0; - p_vci_ini_d.be = 0xF; - p_vci_ini_d.trdid = 0; - p_vci_ini_d.pktid = TYPE_READ_INS_MISS; - p_vci_ini_d.plen = m_icache_words<<2; - p_vci_ini_d.cmd = vci_param::CMD_READ; - p_vci_ini_d.eop = true; + p_vci.cmdval = true; + p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_INS_MISS; + p_vci.plen = m_icache_words<<2; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; break; case CMD_INS_UNC: - p_vci_ini_d.cmdval = true; - p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3; - p_vci_ini_d.wdata = 0; - p_vci_ini_d.be = 0xF; - p_vci_ini_d.trdid = 0; - p_vci_ini_d.pktid = TYPE_READ_INS_UNC; - p_vci_ini_d.plen = 4; - p_vci_ini_d.cmd = vci_param::CMD_READ; - p_vci_ini_d.eop = true; + p_vci.cmdval = true; + p_vci.address = r_icache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_INS_UNC; + p_vci.plen = 4; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; break; case CMD_DATA_MISS: - p_vci_ini_d.cmdval = true; - p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; - p_vci_ini_d.wdata = 0; - p_vci_ini_d.be = 0xF; - p_vci_ini_d.trdid = 0; - p_vci_ini_d.pktid = TYPE_READ_DATA_MISS; - p_vci_ini_d.plen = m_dcache_words << 2; - p_vci_ini_d.cmd = vci_param::CMD_READ; - p_vci_ini_d.eop = true; + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_DATA_MISS; + p_vci.plen = m_dcache_words << 2; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; break; case CMD_DATA_UNC: - p_vci_ini_d.cmdval = true; - p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; - p_vci_ini_d.wdata = 0; - p_vci_ini_d.be = r_dcache_vci_unc_be.read(); - p_vci_ini_d.trdid = 0; - p_vci_ini_d.pktid = TYPE_READ_DATA_UNC; - p_vci_ini_d.plen = 4; - p_vci_ini_d.cmd = vci_param::CMD_READ; - p_vci_ini_d.eop = true; + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = r_dcache_vci_unc_be.read(); + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_DATA_UNC; + p_vci.plen = 4; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; break; case CMD_DATA_WRITE: - p_vci_ini_d.cmdval = true; - p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; - p_vci_ini_d.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); - p_vci_ini_d.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); - p_vci_ini_d.trdid = r_wbuf.getIndex(); - p_vci_ini_d.pktid = TYPE_WRITE; - p_vci_ini_d.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; - p_vci_ini_d.cmd = vci_param::CMD_WRITE; - p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); + p_vci.cmdval = true; + p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; + p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); + p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); + p_vci.trdid = r_wbuf.getIndex(); + p_vci.pktid = TYPE_WRITE; + p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; + p_vci.cmd = vci_param::CMD_WRITE; + p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); break; case CMD_DATA_LL: - p_vci_ini_d.cmdval = true; - p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; - p_vci_ini_d.wdata = 0; - p_vci_ini_d.be = 0xF; - p_vci_ini_d.trdid = 0; - p_vci_ini_d.pktid = TYPE_LL; - p_vci_ini_d.plen = 8; - p_vci_ini_d.cmd = vci_param::CMD_LOCKED_READ; - p_vci_ini_d.eop = true; + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_LL; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_LOCKED_READ; + p_vci.eop = true; break; case CMD_DATA_SC: - p_vci_ini_d.cmdval = true; - p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; - if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_llsc_key.read(); - else p_vci_ini_d.wdata = r_dcache_vci_sc_data.read(); - p_vci_ini_d.be = 0xF; - p_vci_ini_d.trdid = 0; - p_vci_ini_d.pktid = TYPE_SC; - p_vci_ini_d.plen = 8; - p_vci_ini_d.cmd = vci_param::CMD_NOP; - p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1); + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read(); + else p_vci.wdata = r_dcache_vci_sc_data.read(); + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_SC; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = (r_vci_cmd_cpt.read() == 1); break; case CMD_DATA_CAS: - p_vci_ini_d.cmdval = true; - p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3; - if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_cas_old.read(); - else p_vci_ini_d.wdata = r_dcache_vci_cas_new.read(); - p_vci_ini_d.be = 0xF; - p_vci_ini_d.trdid = 0; - p_vci_ini_d.pktid = TYPE_CAS; - p_vci_ini_d.plen = 8; - p_vci_ini_d.cmd = vci_param::CMD_NOP; - p_vci_ini_d.eop = (r_vci_cmd_cpt.read() == 1); + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read(); + else p_vci.wdata = r_dcache_vci_cas_new.read(); + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_CAS; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = (r_vci_cmd_cpt.read() == 1); break; } // end switch r_vci_cmd_fsm // VCI initiator response on the direct network - // it depends on the VCI RSP state + // it depends on the VCI_RSP FSM switch (r_vci_rsp_fsm.read() ) { - case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break; - case RSP_INS_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break; - case RSP_INS_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break; - case RSP_DATA_MISS : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; - case RSP_DATA_UNC : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; - case RSP_DATA_LL : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break; - case RSP_IDLE : p_vci_ini_d.rspack = false; break; + case RSP_DATA_WRITE : p_vci.rspack = true; break; + case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; + case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; + case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_IDLE : p_vci.rspack = false; break; } // end switch r_vci_rsp_fsm - ///////////////// - // CC_SEND FSM // - ///////////////// + + // Send coherence packets on DSPIN L2M + // it depends on the CC_SEND FSM + uint64_t dspin_send_data = 0; switch ( r_cc_send_fsm.read() ) { - /////////////////////////// + ////////////////// case CC_SEND_IDLE: { @@ -5855,58 +5846,61 @@ break; } - /////////////////////////// + /////////////////////// case CC_SEND_CLEANUP_1: { // initialize dspin send data - DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_EOP); - DspinDhccpParam::dspin_set(dspin_send_data,m_srcid_c,DspinDhccpParam::CLEANUP_SRCID); - DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC); - // dcache active request - if(r_cc_send_last_client.read() == 0) - { - // compute global id - uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B)); - uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read(); - global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); - + DspinDhccpParam::dspin_set(dspin_send_data, + 0, + DspinDhccpParam::FROM_L1_EOP); + DspinDhccpParam::dspin_set(dspin_send_data, + m_cc_global_id, + DspinDhccpParam::CLEANUP_SRCID); + DspinDhccpParam::dspin_set(dspin_send_data, + 0, + DspinDhccpParam::FROM_L1_BC); + + if(r_cc_send_last_client.read() == 0) // dcache active request + { + uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + DspinDhccpParam::dspin_set(dspin_send_data, - global_id, - DspinDhccpParam::CLEANUP_DEST); + dest, + DspinDhccpParam::CLEANUP_DEST); DspinDhccpParam::dspin_set(dspin_send_data, - r_dcache_cc_send_nline.read() & 0x300000000ULL, - DspinDhccpParam::CLEANUP_NLINE_MSB); + r_dcache_cc_send_nline.read() & 0x300000000ULL, + DspinDhccpParam::CLEANUP_NLINE_MSB); DspinDhccpParam::dspin_set(dspin_send_data, - r_dcache_cc_send_way.read(), - DspinDhccpParam::CLEANUP_WAY_INDEX); + r_dcache_cc_send_way.read(), + DspinDhccpParam::CLEANUP_WAY_INDEX); DspinDhccpParam::dspin_set(dspin_send_data, - DspinDhccpParam::TYPE_CLEANUP_DATA, - DspinDhccpParam::FROM_L1_TYPE); - } - // icache active request - else - { - // compute global id - uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B)); - uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read(); - global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + DspinDhccpParam::TYPE_CLEANUP_DATA, + DspinDhccpParam::FROM_L1_TYPE); + } + else // icache active request + { + uint64_t dest = (uint64_t)r_icache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); DspinDhccpParam::dspin_set(dspin_send_data, - global_id, - DspinDhccpParam::CLEANUP_DEST); + dest, + DspinDhccpParam::CLEANUP_DEST); DspinDhccpParam::dspin_set(dspin_send_data, - r_icache_cc_send_nline.read() & 0x300000000ULL, - DspinDhccpParam::CLEANUP_NLINE_MSB); + r_icache_cc_send_nline.read() & 0x300000000ULL, + DspinDhccpParam::CLEANUP_NLINE_MSB); DspinDhccpParam::dspin_set(dspin_send_data, - r_icache_cc_send_way.read(), - DspinDhccpParam::CLEANUP_WAY_INDEX); + r_icache_cc_send_way.read(), + DspinDhccpParam::CLEANUP_WAY_INDEX); DspinDhccpParam::dspin_set(dspin_send_data, - DspinDhccpParam::TYPE_CLEANUP_INST, - DspinDhccpParam::FROM_L1_TYPE); + DspinDhccpParam::TYPE_CLEANUP_INST, + DspinDhccpParam::FROM_L1_TYPE); } // send flit @@ -5915,22 +5909,23 @@ break; } - /////////////////////////// + /////////////////////// case CC_SEND_CLEANUP_2: { // initialize dspin send data - DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP); - // dcache active request - if(r_cc_send_last_client.read() == 0) + DspinDhccpParam::dspin_set(dspin_send_data, + 1, + DspinDhccpParam::FROM_L1_EOP); + + if(r_cc_send_last_client.read() == 0) // dcache active request { DspinDhccpParam::dspin_set(dspin_send_data, - r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, - DspinDhccpParam::CLEANUP_NLINE_LSB); - } - // icache active request - else + r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, + DspinDhccpParam::CLEANUP_NLINE_LSB); + } + else // icache active request { DspinDhccpParam::dspin_set(dspin_send_data, - r_icache_cc_send_nline.read() & 0xFFFFFFFFULL, - DspinDhccpParam::CLEANUP_NLINE_LSB); + r_icache_cc_send_nline.read() & 0xFFFFFFFFULL, + DspinDhccpParam::CLEANUP_NLINE_LSB); } // send flit @@ -5939,44 +5934,46 @@ break; } - /////////////////////////// + /////////////////////// case CC_SEND_MULTI_ACK: { // initialize dspin send data - DspinDhccpParam::dspin_set(dspin_send_data,1,DspinDhccpParam::FROM_L1_EOP); - DspinDhccpParam::dspin_set(dspin_send_data,0,DspinDhccpParam::FROM_L1_BC); DspinDhccpParam::dspin_set(dspin_send_data, - DspinDhccpParam::TYPE_MULTI_ACK, - DspinDhccpParam::FROM_L1_TYPE); - // dcache active request - if(r_cc_send_last_client.read() == 0) - { - // compute global id - uint32_t nline_size = vci_param::N - (uint32_log2(m_dcache_words)) - (uint32_log2(vci_param::B)); - uint64_t global_id = (uint64_t) r_dcache_cc_send_nline.read(); - global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); - + 1, + DspinDhccpParam::FROM_L1_EOP); + DspinDhccpParam::dspin_set(dspin_send_data, + 0, + DspinDhccpParam::FROM_L1_BC); + DspinDhccpParam::dspin_set(dspin_send_data, + DspinDhccpParam::TYPE_MULTI_ACK, + DspinDhccpParam::FROM_L1_TYPE); + + if(r_cc_send_last_client.read() == 0) // dcache active request + { + uint64_t dest = (uint64_t)r_dcache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + DspinDhccpParam::dspin_set(dspin_send_data, - global_id, - DspinDhccpParam::MULTI_ACK_DEST); + dest, + DspinDhccpParam::MULTI_ACK_DEST); DspinDhccpParam::dspin_set(dspin_send_data, - r_dcache_cc_send_updt_tab_idx.read(), - DspinDhccpParam::MULTI_ACK_UPDT_INDEX); - } - // icache active request - else - { - // compute global id - uint32_t nline_size = vci_param::N - (uint32_log2(m_icache_words)) - (uint32_log2(vci_param::B)); - uint64_t global_id = (uint64_t) r_icache_cc_send_nline.read(); - global_id >>= (nline_size - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + r_dcache_cc_send_updt_tab_idx.read(), + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + } + else // icache active request + { + uint64_t dest = (uint64_t)r_icache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + DspinDhccpParam::dspin_set(dspin_send_data, - global_id, - DspinDhccpParam::MULTI_ACK_DEST); + dest, + DspinDhccpParam::MULTI_ACK_DEST); DspinDhccpParam::dspin_set(dspin_send_data, - r_icache_cc_send_updt_tab_idx.read(), - DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + r_icache_cc_send_updt_tab_idx.read(), + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); } // send flit @@ -5987,7 +5984,7 @@ } // end switch CC_SEND FSM - //////////////////// - // CC_RECEIVE FSM // - //////////////////// + // Receive coherence packets + // It depends on the CC_RECEIVE FSM + switch( r_cc_receive_fsm.read() ) { Index: branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h =================================================================== --- branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h (revision 341) +++ branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h (revision 346) @@ -326,6 +326,4 @@ // debug variables (for each FSM) - size_t m_debug_start_cycle; - bool m_debug_ok; bool m_debug_global; bool m_debug_tgt_cmd_fsm; @@ -379,5 +377,4 @@ soclib::caba::VciTarget p_vci_tgt; soclib::caba::VciInitiator p_vci_ixr; - soclib::caba::DspinInput<33> p_dspin_in; soclib::caba::DspinOutput<40> p_dspin_out; @@ -385,19 +382,18 @@ VciMemCache( sc_module_name name, // Instance Name - const soclib::common::MappingTable &mtp, // Mapping table for primary requets - const soclib::common::MappingTable &mtc, // Mapping table for coherence requets - const soclib::common::MappingTable &mtx, // Mapping table for XRAM - const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) - const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) - const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) - const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup - size_t nways, // Number of ways per set - size_t nsets, // Number of sets - size_t nwords, // Number of words per line - size_t heap_size=1024, // Size of the heap - size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT - size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT - size_t debug_start_cycle=0, - bool debug_ok=false); + const soclib::common::MappingTable &mtp, // Mapping table for direct network + const soclib::common::MappingTable &mtx, // Mapping table for external network + const soclib::common::IntTab &srcid_x, // global index on external network + const soclib::common::IntTab &tgtid_d, // global index on direct network + const size_t cc_global_id, // global index on cc network + const size_t nways, // Number of ways per set + const size_t nsets, // Number of sets + const size_t nwords, // Number of words per line + const size_t max_copies, // max number of copies in heap + const size_t heap_size=1024, // number of heap entries + const size_t trt_lines=TRANSACTION_TAB_LINES, + const size_t upt_lines=UPDATE_TAB_LINES, + const size_t debug_start_cycle=0, + const bool debug_ok=false ); ~VciMemCache(); @@ -417,45 +413,39 @@ // Component attributes - std::list m_seglist; // memory cached into the cache - std::list m_cseglist; // coherence segment for the cache - - const size_t m_initiators; // Number of initiators - const size_t m_heap_size; // Size of the heap - const size_t m_ways; // Number of ways in a set - const size_t m_sets; // Number of cache sets - const size_t m_words; // Number of words in a line - const size_t m_srcid_ixr; // Srcid for requests to XRAM - const size_t m_srcid_ini; // Srcid for requests to processors - - uint32_t m_transaction_tab_lines; - TransactionTab m_transaction_tab; // xram transaction table - uint32_t m_update_tab_lines; - UpdateTab m_update_tab; // pending update & invalidate - CacheDirectory m_cache_directory; // data cache directory - CacheData m_cache_data; // data array[set][way][word] - HeapDirectory m_heap; // heap for copies + std::list m_seglist; // segments allocated to memcache + size_t m_nseg; // number of segments + soclib::common::Segment **m_seg; // array of segments pointers + const size_t m_srcid_x; // global index on external network + const size_t m_initiators; // Number of initiators + const size_t m_heap_size; // Size of the heap + const size_t m_ways; // Number of ways in a set + const size_t m_sets; // Number of cache sets + const size_t m_words; // Number of words in a line + const size_t m_cc_global_id; // global_index on cc network + size_t m_debug_start_cycle; + bool m_debug_ok; + uint32_t m_trt_lines; + TransactionTab m_trt; // xram transaction table + uint32_t m_upt_lines; + UpdateTab m_upt; // pending update & invalidate + CacheDirectory m_cache_directory; // data cache directory + CacheData m_cache_data; // data array[set][way][word] + HeapDirectory m_heap; // heap for copies + size_t m_max_copies; // max number of copies in heap GenericLLSCGlobalTable - < - 32 , // desired number of slots - 4096, // number of processors in the system - 8000, // registratioçn life span (in # of LL operations) - typename vci_param::fast_addr_t // address type - > - m_llsc_table; // ll/sc global registration table + < 32 , // number of slots + 4096, // number of processors in the system + 8000, // registratioçn life span (in # of LL operations) + typename vci_param::fast_addr_t > // address type + m_llsc_table; // ll/sc global registration table // adress masks - const soclib::common::AddressMaskingTable m_x; - const soclib::common::AddressMaskingTable m_y; - const soclib::common::AddressMaskingTable m_z; - const soclib::common::AddressMaskingTable m_nline; + const soclib::common::AddressMaskingTable m_x; + const soclib::common::AddressMaskingTable m_y; + const soclib::common::AddressMaskingTable m_z; + const soclib::common::AddressMaskingTable m_nline; // broadcast address - uint32_t m_broadcast_address; - - ////////////////////////////////////////////////// - // Others registers - ////////////////////////////////////////////////// - sc_signal r_copies_limit; // Limit of the number of copies for one line - sc_signal xxx_count; + uint32_t m_broadcast_address; ////////////////////////////////////////////////// @@ -495,8 +485,4 @@ sc_signal r_tgt_cmd_fsm; - size_t m_nseg; - size_t m_ncseg; - soclib::common::Segment **m_seg; - soclib::common::Segment **m_cseg; /////////////////////////////////////////////////////// // Registers controlled by the READ fsm Index: branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache_dspin_coherence.cpp =================================================================== --- branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache_dspin_coherence.cpp (revision 341) +++ branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache_dspin_coherence.cpp (revision 346) @@ -1,3 +1,4 @@ /* -*- c++ -*- +* * File : vci_mem_cache.cpp * Date : 30/10/2008 @@ -275,5 +276,5 @@ VciMemCache -using soclib::common::uint32_log2; +using namespace soclib::common; //////////////////////////////// @@ -282,50 +283,48 @@ tmpl(/**/) ::VciMemCache( - sc_module_name name, - const soclib::common::MappingTable &mtp, - const soclib::common::MappingTable &mtc, - const soclib::common::MappingTable &mtx, - const soclib::common::IntTab &vci_ixr_index, - const soclib::common::IntTab &vci_ini_index, - const soclib::common::IntTab &vci_tgt_index, - const soclib::common::IntTab &vci_tgt_index_cleanup, - size_t nways, // number of ways per set - size_t nsets, // number of cache sets - size_t nwords, // number of words in cache line - size_t heap_size, // number of heap entries - size_t transaction_tab_lines, // number of TRT entries - size_t update_tab_lines, // number of UPT entries - size_t debug_start_cycle, - bool debug_ok) + sc_module_name name, + const MappingTable &mtp, // mapping table for direct network + const MappingTable &mtx, // mapping table for external network + const IntTab &srcid_x, // global index on external network + const IntTab &tgtid_d, // global index on direct network + const size_t cc_global_id, // global index on cc network + const size_t nways, // number of ways per set + const size_t nsets, // number of associative sets + const size_t nwords, // number of words in cache line + const size_t max_copies, // max number of copies in heap + const size_t heap_size, // number of heap entries + const size_t trt_lines, // number of TRT entries + const size_t upt_lines, // number of UPT entries + const size_t debug_start_cycle, + const bool debug_ok) : soclib::caba::BaseModule(name), - m_debug_start_cycle(debug_start_cycle), - m_debug_ok(debug_ok), - - p_clk("clk"), - p_resetn("resetn"), - p_vci_tgt("vci_tgt"), - p_vci_ixr("vci_ixr"), - p_dspin_in("dspin_tgt"), - p_dspin_out("cc_send"), - - m_seglist(mtp.getSegmentList(vci_tgt_index)), - m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)), - - m_initiators(1 << vci_param::S), - m_heap_size(heap_size), - m_ways(nways), - m_sets(nsets), - m_words(nwords), - m_srcid_ixr(mtx.indexForId(vci_ixr_index)), - m_srcid_ini(mtc.indexForId(vci_ini_index)), - m_transaction_tab_lines(transaction_tab_lines), - m_transaction_tab(transaction_tab_lines, nwords), - m_update_tab_lines(update_tab_lines), - m_update_tab(update_tab_lines), + p_clk( "p_clk" ), + p_resetn( "p_resetn" ), + p_vci_tgt( "p_vci_tgt" ), + p_vci_ixr( "p_vci_ixr" ), + p_dspin_in( "p_dspin_in" ), + p_dspin_out( "p_dspin_out" ), + + m_seglist( mtp.getSegmentList(tgtid_d) ), + m_nseg( 0 ), + m_srcid_x( mtx.indexForId(srcid_x) ), + m_initiators( 1 << vci_param::S ), + m_heap_size( heap_size ), + m_ways( nways ), + m_sets( nsets ), + m_words( nwords ), + m_cc_global_id( cc_global_id ), + m_debug_start_cycle( debug_start_cycle ), + m_debug_ok( debug_ok ), + m_trt_lines(trt_lines), + m_trt(trt_lines, nwords), + m_upt_lines(upt_lines), + m_upt(upt_lines), m_cache_directory(nways, nsets, nwords, vci_param::N), m_cache_data(nways, nsets, nwords), m_heap(m_heap_size), + m_max_copies( max_copies ), m_llsc_table(), @@ -368,7 +367,4 @@ r_tgt_cmd_fsm("r_tgt_cmd_fsm"), - m_nseg(0), - m_ncseg(0), - r_read_fsm("r_read_fsm"), @@ -416,80 +412,64 @@ r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") { - assert(IS_POW_OF_2(nsets)); - assert(IS_POW_OF_2(nwords)); - assert(IS_POW_OF_2(nways)); - assert(nsets); - assert(nwords); - assert(nways); - - // check Transaction table size - assert((uint32_log2(transaction_tab_lines) <= vci_param::T) and + assert(IS_POW_OF_2(nsets)); + assert(IS_POW_OF_2(nwords)); + assert(IS_POW_OF_2(nways)); + assert(nsets); + assert(nwords); + assert(nways); + + // check Transaction table size + assert((uint32_log2(trt_lines) <= vci_param::T) and "Need more bits for VCI TRDID field"); - // Get the segments associated to the MemCache - std::list::iterator seg; - size_t i; - - for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) - { - m_nseg++; - } - for(seg = m_cseglist.begin(); seg != m_cseglist.end() ; seg++) - { - m_ncseg++; - } - - m_seg = new soclib::common::Segment*[m_nseg]; - - i = 0; - for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++) - { - m_seg[i] = & (*seg); - i++; - } - - m_cseg = new soclib::common::Segment*[m_ncseg]; - - i = 0; - for(seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++) - { - m_cseg[i] = & (*seg); - i++; - } - - // Allocation for IXR_RSP FSM - r_ixr_rsp_to_xram_rsp_rok = new sc_signal[m_transaction_tab_lines]; - - // Allocation for XRAM_RSP FSM - r_xram_rsp_victim_data = new sc_signal[nwords]; - r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; - r_xram_rsp_to_ixr_cmd_data = new sc_signal[nwords]; - - // Allocation for READ FSM - r_read_data = new sc_signal[nwords]; - r_read_to_tgt_rsp_data = new sc_signal[nwords]; - - // Allocation for WRITE FSM - r_write_data = new sc_signal[nwords]; - r_write_be = new sc_signal[nwords]; - r_write_to_cc_send_data = new sc_signal[nwords]; - r_write_to_cc_send_be = new sc_signal[nwords]; - r_write_to_ixr_cmd_data = new sc_signal[nwords]; - - // Allocation for CAS FSM - r_cas_to_ixr_cmd_data = new sc_signal[nwords]; - r_cas_data = new sc_signal[nwords]; - r_cas_rdata = new sc_signal[2]; - - - // Simulation - - SC_METHOD(transition); - dont_initialize(); - sensitive << p_clk.pos(); - - SC_METHOD(genMoore); - dont_initialize(); - sensitive << p_clk.neg(); + // Get the segments associated to the MemCache + std::list::iterator seg; + size_t i = 0; + + for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) + { + m_nseg++; + } + + m_seg = new soclib::common::Segment*[m_nseg]; + + for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++) + { + m_seg[i] = & (*seg); + i++; + } + + // Allocation for IXR_RSP FSM + r_ixr_rsp_to_xram_rsp_rok = new sc_signal[m_trt_lines]; + + // Allocation for XRAM_RSP FSM + r_xram_rsp_victim_data = new sc_signal[nwords]; + r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; + r_xram_rsp_to_ixr_cmd_data = new sc_signal[nwords]; + + // Allocation for READ FSM + r_read_data = new sc_signal[nwords]; + r_read_to_tgt_rsp_data = new sc_signal[nwords]; + + // Allocation for WRITE FSM + r_write_data = new sc_signal[nwords]; + r_write_be = new sc_signal[nwords]; + r_write_to_cc_send_data = new sc_signal[nwords]; + r_write_to_cc_send_be = new sc_signal[nwords]; + r_write_to_ixr_cmd_data = new sc_signal[nwords]; + + // Allocation for CAS FSM + r_cas_to_ixr_cmd_data = new sc_signal[nwords]; + r_cas_data = new sc_signal[nwords]; + r_cas_rdata = new sc_signal[2]; + + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); } // end constructor @@ -580,5 +560,5 @@ std::cout << "----------------------------------" << std::dec << std::endl; std::cout - << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl + << "MEM_CACHE " << name() << " / Time = " << m_cpt_cycles << std::endl << "- READ RATE = " << (double) m_cpt_read/m_cpt_cycles << std::endl << "- READ TOTAL = " << m_cpt_read << std::endl @@ -666,6 +646,6 @@ // Initializing Tables - m_transaction_tab.init(); - m_update_tab.init(); + m_trt.init(); + m_upt.init(); m_llsc_table.init(); @@ -728,5 +708,5 @@ #endif - for(size_t i=0; i Modify an existing entry in TRT" << std::endl; - m_transaction_tab.print(r_write_trt_index.read()); + m_trt.print(r_write_trt_index.read()); } #endif @@ -2752,5 +2730,5 @@ { size_t wok_index = 0; - bool wok = !m_transaction_tab.full(wok_index); + bool wok = !m_trt.full(wok_index); if(wok) // set a new entry in TRT { @@ -2787,5 +2765,5 @@ size_t nb_copies = r_write_count.read(); - wok =m_update_tab.set(false, // it's an inval transaction + wok =m_upt.set(false, // it's an inval transaction true, // it's a broadcast true, // it needs a response @@ -2830,5 +2808,5 @@ // register a write request to XRAM in TRT - m_transaction_tab.set(r_write_trt_index.read(), + m_trt.set(r_write_trt_index.read(), false, // write request to XRAM m_nline[(vci_addr_t)(r_write_address.read())], @@ -3160,5 +3138,5 @@ if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) { - m_transaction_tab.erase(r_ixr_rsp_trt_index.read()); + m_trt.erase(r_ixr_rsp_trt_index.read()); r_ixr_rsp_fsm = IXR_RSP_IDLE; @@ -3184,5 +3162,5 @@ assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || p_vci_ixr.rerror.read()) and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); - m_transaction_tab.write_rsp(index, + m_trt.write_rsp(index, r_ixr_rsp_cpt.read(), data, @@ -3238,5 +3216,5 @@ { size_t ptr = r_xram_rsp_trt_index.read(); - size_t lines = m_transaction_tab_lines; + size_t lines = m_trt_lines; for(size_t i=0 ; i Get acces to UPT," << " but an invalidation is already registered at this address" << std::endl; - m_update_tab.print(); + m_upt.print(); } #endif } - else if(m_update_tab.is_full() && r_xram_rsp_victim_inval.read()) + else if(m_upt.is_full() && r_xram_rsp_victim_inval.read()) { r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; @@ -3375,5 +3353,5 @@ std::cout << " Get acces to UPT," << " but the table is full" << std::endl; - m_update_tab.print(); + m_upt.print(); } #endif @@ -3463,5 +3441,5 @@ size_t count_copies = r_xram_rsp_victim_count.read(); - bool wok = m_update_tab.set(false, // it's an inval transaction + bool wok = m_upt.set(false, // it's an inval transaction brdcast, // set brdcast bit false, // it does not need a response @@ -3501,5 +3479,5 @@ // If the victim is not dirty, we don't need another XRAM put transaction, // and we canwe erase the TRT entry - if(!r_xram_rsp_victim_dirty.read()) m_transaction_tab.erase(r_xram_rsp_trt_index.read()); + if(!r_xram_rsp_victim_dirty.read()) m_trt.erase(r_xram_rsp_trt_index.read()); // Next state @@ -3515,5 +3493,5 @@ if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) { - m_transaction_tab.set(r_xram_rsp_trt_index.read(), + m_trt.set(r_xram_rsp_trt_index.read(), false, // write to XRAM r_xram_rsp_victim_nline.read(), // line index @@ -3740,5 +3718,5 @@ case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error { - m_transaction_tab.erase(r_xram_rsp_trt_index.read()); + m_trt.erase(r_xram_rsp_trt_index.read()); // Next state @@ -4435,5 +4413,5 @@ bool match_inval; - match_inval = m_update_tab.search_inval(r_cleanup_nline.read(), index); + match_inval = m_upt.search_inval(r_cleanup_nline.read(), index); // no pending inval @@ -4458,8 +4436,8 @@ // pending inval - r_cleanup_write_srcid = m_update_tab.srcid(index); - r_cleanup_write_trdid = m_update_tab.trdid(index); - r_cleanup_write_pktid = m_update_tab.pktid(index); - r_cleanup_write_need_rsp = m_update_tab.need_rsp(index); + r_cleanup_write_srcid = m_upt.srcid(index); + r_cleanup_write_trdid = m_upt.trdid(index); + r_cleanup_write_pktid = m_upt.pktid(index); + r_cleanup_write_need_rsp = m_upt.need_rsp(index); r_cleanup_index = index; @@ -4497,5 +4475,5 @@ size_t count = 0; - m_update_tab.decrement(r_cleanup_index.read(), count); + m_upt.decrement(r_cleanup_index.read(), count); // invalidation transaction finished @@ -4539,5 +4517,5 @@ } - m_update_tab.clear(r_cleanup_index.read()); + m_upt.clear(r_cleanup_index.read()); if(r_cleanup_write_need_rsp.read()) @@ -4919,5 +4897,5 @@ size_t nb_copies = r_cas_count.read(); - wok = m_update_tab.set(true, // it's an update transaction + wok = m_upt.set(true, // it's an update transaction false, // it's not a broadcast true, // it needs a response @@ -5125,5 +5103,5 @@ } size_t wok_index = 0; - bool wok = !m_transaction_tab.full(wok_index); + bool wok = !m_trt.full(wok_index); if(wok) { @@ -5158,5 +5136,5 @@ // register a broadcast inval transaction in UPT - wok = m_update_tab.set(false, // it's an inval transaction + wok = m_upt.set(false, // it's an inval transaction true, // it's a broadcast true, // it needs a response @@ -5216,5 +5194,5 @@ { // set TRT - m_transaction_tab.set(r_cas_trt_index.read(), + m_trt.set(r_cas_trt_index.read(), false, // PUT request to XRAM m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())], @@ -5361,9 +5339,9 @@ { size_t index = 0; - bool hit_read = m_transaction_tab.hit_read( + bool hit_read = m_trt.hit_read( m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()],index); - bool hit_write = m_transaction_tab.hit_write( + bool hit_write = m_trt.hit_write( m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]); - bool wok = !m_transaction_tab.full(index); + bool wok = !m_trt.full(index); #if DEBUG_MEMC_CAS @@ -5405,5 +5383,5 @@ } - m_transaction_tab.set(r_cas_trt_index.read(), + m_trt.set(r_cas_trt_index.read(), true, // read request m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()], @@ -7162,5 +7140,5 @@ p_vci_ixr.be = 0xF; p_vci_ixr.pktid = 0; - p_vci_ixr.srcid = m_srcid_ixr; + p_vci_ixr.srcid = m_srcid_x; p_vci_ixr.cons = false; p_vci_ixr.wrap = false; @@ -7288,4 +7266,5 @@ // Response signals on the p_vci_tgt port //////////////////////////////////////////////////// + switch(r_tgt_rsp_fsm.read()) { @@ -7384,4 +7363,5 @@ // Initiator command signals on the p_dspin_out port (CC_SEND FSM) //////////////////////////////////////////////////////////////////// + p_dspin_out.write = false; p_dspin_out.data = 0; @@ -7389,4 +7369,5 @@ switch(r_cc_send_fsm.read()) { + case CC_SEND_XRAM_RSP_IDLE: case CC_SEND_WRITE_IDLE: @@ -7463,5 +7444,5 @@ DspinDhccpParam::dspin_set( flit, - m_srcid_ini, + m_cc_global_id, DspinDhccpParam::MULTI_INVAL_SRCID); @@ -7516,5 +7497,5 @@ DspinDhccpParam::dspin_set( flit, - m_srcid_ini, + m_cc_global_id, DspinDhccpParam::BROADCAST_SRCID); @@ -7613,5 +7594,5 @@ DspinDhccpParam::dspin_set( flit, - m_srcid_ini, + m_cc_global_id, DspinDhccpParam::MULTI_UPDT_SRCID); @@ -7717,5 +7698,5 @@ DspinDhccpParam::dspin_set( flit, - m_srcid_ini, + m_cc_global_id, DspinDhccpParam::MULTI_UPDT_SRCID);