Changeset 347 for trunk/softs/tsar_boot/conf

Timestamp:

Apr 1, 2013, 8:57:02 PM (12 years ago)

Author:

cfuguet

Message:

Introducing dcache line invalidation mechanism in the boot_ioc_read
function, when using platform without cache coherency.

Introducing two parameters in the defs_platform.h file:

CACHE_COHERENCE

Equals to 0 when no cache coherency

CACHE_LINE_SIZE

Number of bytes in a cache line

• TODO: Use the config register of the cache models to get

this size

Adding new platform configuration file for the

caba_vgsb_xicu_mmu SOCLIB platform.

Location:

trunk/softs/tsar_boot/conf

Files:

• platform_fpga_de2-115/defs_platform.h (modified) (1 diff)
• platform_vgsb_xicu_mmu (added)
• platform_vgsb_xicu_mmu/defs_platform.h (added)
• platform_vgsb_xicu_mmu/platform_fpga.dts (added)
• platform_vgsb_xicu_mmu/platform_soclib.dts (added)

trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h

@@ -1 @@
-#define NB_PROCS     4
-#define NB_CLUSTERS  1
+#define NB_PROCS        4
+#define NB_CLUSTERS     1
 
-#define IRQ_PER_PROC 1
+#define IRQ_PER_PROC    1
 
-#define IOC_BASE     0xFB000000
-#define VCIBD_BASE   0xFB000000
-#define TTY_BASE     0xFC000000
-#define ICU_BASE     0xFD000000
+#define CACHE_COHERENCE 1
+#define CACHE_LINE_SIZE 64//bytes
+
+#define IOC_BASE        0xFB000000
+#define VCIBD_BASE      0xFB000000
+#define TTY_BASE        0xFC000000
+#define ICU_BASE        0xFD000000