Ignore:
Timestamp:
Apr 1, 2013, 8:57:02 PM (12 years ago)
Author:
cfuguet
Message:

Introducing dcache line invalidation mechanism in the boot_ioc_read
function, when using platform without cache coherency.

Introducing two parameters in the defs_platform.h file:

CACHE_COHERENCE

Equals to 0 when no cache coherency

CACHE_LINE_SIZE

Number of bytes in a cache line

  • TODO: Use the config register of the cache models to get

this size

Adding new platform configuration file for the

caba_vgsb_xicu_mmu SOCLIB platform.


File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h

    r302 r347  
    1 #define NB_PROCS     4
    2 #define NB_CLUSTERS  1
     1#define NB_PROCS        4
     2#define NB_CLUSTERS     1
    33
    4 #define IRQ_PER_PROC 1
     4#define IRQ_PER_PROC    1
    55
    6 #define IOC_BASE     0xFB000000
    7 #define VCIBD_BASE   0xFB000000
    8 #define TTY_BASE     0xFC000000
    9 #define ICU_BASE     0xFD000000
     6#define CACHE_COHERENCE 1
     7#define CACHE_LINE_SIZE 64//bytes
     8
     9#define IOC_BASE        0xFB000000
     10#define VCIBD_BASE      0xFB000000
     11#define TTY_BASE        0xFC000000
     12#define ICU_BASE        0xFD000000
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