Index: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 354)
+++ branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 355)
@@ -34,5 +34,5 @@
 #define DEBUG_DCACHE		1
 #define DEBUG_ICACHE		1
-#define DEBUG_CLEANUP		0
+#define DEBUG_CLEANUP		1
 
 namespace soclib {
@@ -1488,12 +1488,4 @@
         if (m_ireq.valid) m_cost_ins_miss_frz++;
 
-        // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
-        {
-            r_icache_fsm = ICACHE_CC_CHECK;
-            r_icache_fsm_save = r_icache_fsm.read();
-            break;
-        }
-
 #ifdef INSTRUMENTATION
 m_cpt_icache_dir_write++;
@@ -1736,5 +1728,6 @@
 #endif
         }
-        else if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
+        else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
+                 (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
                  (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
                  ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
@@ -3304,6 +3297,6 @@
             {
                 pt_updt                = true;
-                r_dcache_vci_cas_old    = pte_flags;
-                r_dcache_vci_cas_new    = pte_flags | PTE_L_MASK;
+                r_dcache_vci_cas_old   = pte_flags;
+                r_dcache_vci_cas_new   = pte_flags | PTE_L_MASK;
                 pte_flags              = pte_flags | PTE_L_MASK;
 		        r_dcache_tlb_pte_flags = pte_flags;
@@ -3315,6 +3308,6 @@
             {
                 pt_updt                = true;
-                r_dcache_vci_cas_old    = pte_flags;
-                r_dcache_vci_cas_new    = pte_flags | PTE_R_MASK;
+                r_dcache_vci_cas_old   = pte_flags;
+                r_dcache_vci_cas_new   = pte_flags | PTE_R_MASK;
                 pte_flags              = pte_flags | PTE_R_MASK;
 		        r_dcache_tlb_pte_flags = pte_flags;
@@ -3828,4 +3821,5 @@
                                   &found,
                                   &cleanup );
+
             if ( found )
             {
@@ -3870,12 +3864,4 @@
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
-        // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
-        {
-            r_dcache_fsm = DCACHE_CC_CHECK;
-            r_dcache_fsm_cc_save = r_dcache_fsm.read();
-            break;
-        }
-
         size_t  way   = r_dcache_miss_way.read();
         size_t  set   = r_dcache_miss_set.read();
@@ -3927,15 +3913,4 @@
     {
         if ( m_dreq.valid) m_cost_data_miss_frz++;
-
-/**/
-#if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-        std::cout << "  <PROC " << name()
-              << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
-        std::cout << "  <PROC " << name()
-              << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
-}
-#endif
 
         // coherence request (from CC_RECEIVE FSM)
@@ -4013,15 +3988,4 @@
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
-/**/
-#if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-        std::cout << "  <PROC " << name()
-              << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
-        std::cout << "  <PROC " << name()
-              << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
-}
-#endif
-
         if ( r_vci_rsp_fifo_dcache.rok() )	// one word available
         {
@@ -4065,15 +4029,4 @@
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
-/**/
-#if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-        std::cout << "  <PROC " << name()
-              << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
-        std::cout << "  <PROC " << name()
-              << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
-}
-#endif
-
         // coherence request (from CC_RECEIVE FSM)
         if ( r_cc_receive_dcache_req.read() )
@@ -4420,5 +4373,6 @@
 #endif
         }
-        else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
+        else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
+                  (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
                   (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
                   ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
@@ -5326,12 +5280,4 @@
         case CC_SEND_CLEANUP_1:
         {
-/**/
-#if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-        std::cout << "  <PROC " << name()
-              << " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
-}
-#endif
             // wait for the first flit to be consumed
             if (p_dspin_out.read.read())
@@ -5342,16 +5288,5 @@
         ///////////////////////////
         case CC_SEND_CLEANUP_2:
-/**/
-#if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-        std::cout << "  <PROC " << name()
-              << " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
-}
-#endif
-        {
-            assert( p_dspin_out.read.read() and
-                    "The interconnect should accept the second cleanup flit instantly" );
-
+        {
             // wait for the second flit to be consumed
             if (p_dspin_out.read.read())
@@ -5401,14 +5336,4 @@
         case CC_RECEIVE_IDLE:
         {
-/**/
-#if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-        std::cout << "  <PROC " << name()
-              << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
-        std::cout << "  <PROC " << name()
-              << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
-}
-#endif
             // a coherence request has arrived
             if (p_dspin_in.write.read())
@@ -5481,14 +5406,4 @@
         case CC_RECEIVE_BRDCAST_HEADER:
         {
-/**/
-#if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-        std::cout << "  <PROC " << name()
-              << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
-        std::cout << "  <PROC " << name()
-              << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
-}
-#endif
             // no actual data in the HEADER, just skip to second flit
             r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
@@ -5498,14 +5413,4 @@
         case CC_RECEIVE_BRDCAST_NLINE:
         {
-/**/
-#if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-        std::cout << "  <PROC " << name()
-              << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
-        std::cout << "  <PROC " << name()
-              << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
-}
-#endif
             // initialize dspin received data
             uint64_t receive_data = p_dspin_in.data.read();
@@ -5514,5 +5419,5 @@
             // not to actually post a request to an available cache => need a
             // flip_flop to check that ?
-            if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
+            if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
             {
                 // request dcache to handle the BROADCAST
@@ -5559,5 +5464,5 @@
             uint64_t receive_data = p_dspin_in.data.read();
             // for data INVAL, wait for dcache to take the request
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
+            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
             {
                 // request dcache to handle the INVAL
@@ -5570,5 +5475,5 @@
             }
             // for ins INVAL, wait for icache to take the request
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
+            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
             {
                 // request icache to handle the INVAL
@@ -5614,5 +5519,5 @@
             // for data INVAL, wait for dcache to take the request and fifo to
             // be empty
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty())
+            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
             {
                 r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
@@ -5625,5 +5530,5 @@
             // for ins INVAL, wait for icache to take the request and fifo to be
             // empty
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())
+            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
             {
                 r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
@@ -5641,7 +5546,7 @@
         case CC_RECEIVE_UPDT_DATA:
         {
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
+            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
                 r_cc_receive_dcache_req = true;
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
+            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
                 r_cc_receive_icache_req = true;
 
@@ -5649,5 +5554,5 @@
             uint64_t receive_data = p_dspin_in.data.read();
             // wait for the fifo
-            if (r_cc_receive_updt_fifo_be.wok())
+            if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
             {
                 cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
@@ -5980,4 +5885,5 @@
             p_dspin_out.data  = dspin_send_data;
             p_dspin_out.write = true;
+
             break;
         }