Changeset 361 for trunk/modules/vci_mem_cache_v4
- Timestamp:
- Apr 10, 2013, 12:54:31 PM (12 years ago)
- Location:
- trunk/modules/vci_mem_cache_v4/caba/source
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
r291 r361 29 29 * alexandre.joannou@lip6.fr 30 30 * 31 * Modifications done by Christophe Choichillon on the 7/04/2009:32 * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE33 * - Adding a new VCI target port for the CLEANUP network34 * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP35 *36 * Modifications to do :37 * - Adding new variables used by the CLEANUP FSM38 *39 31 */ 40 32 … … 106 98 INIT_CMD_INVAL_NLINE, 107 99 INIT_CMD_XRAM_BRDCAST, 100 INIT_CMD_WRITE_BRDCAST, 101 INIT_CMD_CAS_BRDCAST, 108 102 INIT_CMD_UPDT_IDLE, 109 INIT_CMD_WRITE_BRDCAST,110 103 INIT_CMD_UPDT_NLINE, 111 104 INIT_CMD_UPDT_INDEX, 112 105 INIT_CMD_UPDT_DATA, 113 106 INIT_CMD_CAS_UPDT_IDLE, 114 INIT_CMD_CAS_BRDCAST,115 107 INIT_CMD_CAS_UPDT_NLINE, 116 108 INIT_CMD_CAS_UPDT_INDEX, … … 215 207 CAS_DIR_LOCK, 216 208 CAS_DIR_HIT_READ, 209 CAS_DIR_HIT_COMPARE, 217 210 CAS_DIR_HIT_WRITE, 218 211 CAS_UPT_LOCK, … … 372 365 soclib::caba::VciInitiator<vci_param> p_vci_ixr; 373 366 367 #if MONITOR_MEMCACHE_FSM 368 sc_out<int> p_read_fsm; 369 sc_out<int> p_write_fsm; 370 sc_out<int> p_xram_rsp_fsm; 371 sc_out<int> p_cas_fsm; 372 sc_out<int> p_cleanup_fsm; 373 sc_out<int> p_alloc_heap_fsm; 374 sc_out<int> p_alloc_dir_fsm; 375 sc_out<int> p_alloc_trt_fsm; 376 sc_out<int> p_alloc_upt_fsm; 377 sc_out<int> p_tgt_cmd_fsm; 378 sc_out<int> p_tgt_rsp_fsm; 379 sc_out<int> p_ixr_cmd_fsm; 380 sc_out<int> p_ixr_rsp_fsm; 381 sc_out<int> p_init_cmd_fsm; 382 sc_out<int> p_init_rsp_fsm; 383 #endif 384 374 385 VciMemCacheV4( 375 386 sc_module_name name, // Instance Name … … 660 671 sc_signal<size_t> r_cas_trt_index; // Transaction Table index 661 672 sc_signal<size_t> r_cas_upt_index; // Update Table index 673 sc_signal<data_t> * r_cas_data; // cache line data 662 674 663 675 // Buffer between CAS fsm and INIT_CMD fsm (XRAM read) … … 770 782 sc_signal<int> r_tgt_rsp_fsm; 771 783 sc_signal<size_t> r_tgt_rsp_cpt; 784 sc_signal<bool> r_tgt_rsp_key_sent; 772 785 773 786 //////////////////////////////////////////////////// -
trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h
r291 r361 78 78 wdata.assign(source.wdata.begin(),source.wdata.end()); 79 79 rerror = source.rerror; 80 ll_key = source.ll_key; 80 81 } 81 82 -
trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r340 r361 80 80 "INIT_CMD_INVAL_NLINE", 81 81 "INIT_CMD_XRAM_BRDCAST", 82 "INIT_CMD_WRITE_BRDCAST", 83 "INIT_CMD_CAS_BRDCAST", 82 84 "INIT_CMD_UPDT_IDLE", 83 "INIT_CMD_WRITE_BRDCAST",84 85 "INIT_CMD_UPDT_NLINE", 85 86 "INIT_CMD_UPDT_INDEX", 86 87 "INIT_CMD_UPDT_DATA", 87 88 "INIT_CMD_CAS_UPDT_IDLE", 88 "INIT_CMD_CAS_BRDCAST",89 89 "INIT_CMD_CAS_UPDT_NLINE", 90 90 "INIT_CMD_CAS_UPDT_INDEX", … … 175 175 "CAS_DIR_LOCK", 176 176 "CAS_DIR_HIT_READ", 177 "CAS_DIR_HIT_COMPARE", 177 178 "CAS_DIR_HIT_WRITE", 178 179 "CAS_UPT_LOCK", … … 372 373 r_alloc_heap_fsm("r_alloc_heap_fsm"), 373 374 r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") 375 376 #if MONITOR_MEMCACHE_FSM 377 , 378 p_read_fsm ("p_read_fsm"), 379 p_write_fsm ("p_write_fsm"), 380 p_xram_rsp_fsm ("p_xram_rsp_fsm"), 381 p_cas_fsm ("p_cas_fsm"), 382 p_cleanup_fsm ("p_cleanup_fsm"), 383 p_alloc_heap_fsm ("p_alloc_heap_fsm"), 384 p_alloc_dir_fsm ("p_alloc_dir_fsm"), 385 p_alloc_trt_fsm ("p_alloc_trt_fsm"), 386 p_alloc_upt_fsm ("p_alloc_upt_fsm"), 387 p_tgt_cmd_fsm ("p_tgt_cmd_fsm"), 388 p_tgt_rsp_fsm ("p_tgt_rsp_fsm"), 389 p_ixr_cmd_fsm ("p_ixr_cmd_fsm"), 390 p_ixr_rsp_fsm ("p_ixr_rsp_fsm"), 391 p_init_cmd_fsm ("p_init_cmd_fsm"), 392 p_init_rsp_fsm ("p_init_rsp_fsm") 393 #endif 374 394 { 375 395 assert(IS_POW_OF_2(nsets)); … … 434 454 435 455 // Allocation for CAS FSM 436 r_cas_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 437 r_cas_rdata = new sc_signal<data_t>[2]; 456 r_cas_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 457 r_cas_data = new sc_signal<data_t>[nwords]; 458 r_cas_rdata = new sc_signal<data_t>[2]; 438 459 439 460 … … 684 705 685 706 r_copies_limit = 3; 707 708 r_tgt_rsp_key_sent = false; 686 709 687 710 // Activity counters … … 4359 4382 r_cas_count = entry.count; 4360 4383 4361 if ( entry.valid ) 4362 else r_cas_fsm = CAS_MISS_TRT_LOCK;4384 if ( entry.valid ) r_cas_fsm = CAS_DIR_HIT_READ; 4385 else r_cas_fsm = CAS_MISS_TRT_LOCK; 4363 4386 4364 4387 #if DEBUG_MEMC_CAS … … 4387 4410 ///////////////////// 4388 4411 case CAS_DIR_HIT_READ: // update directory for lock and dirty bit 4389 // and check data change in cache4412 // and check data change in cache 4390 4413 { 4391 4414 size_t way = r_cas_way.read(); 4392 4415 size_t set = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; 4393 size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];4394 4416 4395 4417 // update directory (lock & dirty bits) … … 4399 4421 entry.dirty = true; 4400 4422 entry.lock = true; 4401 entry.tag = r_cas_tag.read();4423 entry.tag = r_cas_tag.read(); 4402 4424 entry.owner.srcid = r_cas_copy.read(); 4403 4425 #if L1_MULTI_CACHE … … 4410 4432 m_cache_directory.write(set, way, entry); 4411 4433 4412 // read data in cache & check data change 4413 bool ok = ( r_cas_rdata[0].read() == m_cache_data.read(way, set, word) ); 4414 if ( r_cas_cpt.read()==4 ) // 64 bits CAS 4415 ok &= ( r_cas_rdata[1] == m_cache_data.read(way, set, word+1)); 4434 // Stored data from cache in buffer to do the comparison in next state 4435 m_cache_data.read_line(way, set, r_cas_data); 4436 4437 r_cas_fsm = CAS_DIR_HIT_COMPARE; 4438 4439 #if DEBUG_MEMC_CAS 4440 if(m_debug_cas_fsm) 4441 { 4442 std::cout 4443 << " <MEMC " << name() << ".CAS_DIR_HIT_READ> Read data from " 4444 << " cache and store it in buffer" 4445 << std::endl; 4446 } 4447 #endif 4448 break; 4449 } 4450 4451 case CAS_DIR_HIT_COMPARE: 4452 { 4453 size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]; 4454 4455 // Read data in buffer & check data change 4456 bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read()); 4457 4458 if(r_cas_cpt.read() == 4) // 64 bits CAS 4459 ok &= (r_cas_rdata[1] == r_cas_data[word+1]); 4416 4460 4417 4461 // to avoid livelock, force the atomic access to fail pseudo-randomly 4418 bool forced_fail = ( (r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS ); 4419 r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((-(r_cas_lfsr & 1)) & 0xd0000001); 4420 4421 if( ok and not forced_fail ) // no data change 4462 bool forced_fail = ((r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS); 4463 r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001); 4464 4465 // cas success 4466 if(ok and not forced_fail) 4422 4467 { 4423 4468 r_cas_fsm = CAS_DIR_HIT_WRITE; 4424 4469 } 4425 else // return failure 4470 // cas failure 4471 else 4426 4472 { 4427 4473 r_cas_fsm = CAS_RSP_FAIL; … … 4429 4475 4430 4476 #if DEBUG_MEMC_CAS 4431 if( m_debug_cas_fsm ) 4432 { 4433 std::cout << " <MEMC " << name() << ".CAS_DIR_HIT_READ> Test if CAS success:" 4434 << " / expected value = " << r_cas_rdata[0].read() 4435 << " / actual value = " << m_cache_data.read(way, set, word) 4436 << " / forced_fail = " << forced_fail << std::endl; 4437 } 4477 if(m_debug_cas_fsm) 4478 { 4479 std::cout 4480 << " <MEMC " << name() << ".CAS_DIR_HIT_COMPARE> Compare the old" 4481 << " and the new data" 4482 << " / expected value = " << r_cas_rdata[0].read() 4483 << " / actual value = " << r_cas_data[word].read() 4484 << " / forced_fail = " << forced_fail << std::endl; 4485 } 4438 4486 #endif 4439 4487 break; … … 5493 5541 } 5494 5542 #endif 5495 if ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ) 5543 5544 uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length.read() - 1; 5545 bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); 5546 bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); 5547 5548 if ( (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll)) 5496 5549 { 5497 r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; 5550 // Last word in case of READ or second flit in case if LL 5551 r_tgt_rsp_key_sent = false; 5498 5552 r_read_to_tgt_rsp_req = false; 5553 r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; 5499 5554 } 5500 5555 else 5501 5556 { 5502 r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; 5557 if (is_ll) { 5558 r_tgt_rsp_key_sent = true; // Send second flit of ll 5559 } 5560 else { 5561 r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read 5562 } 5503 5563 } 5504 5564 } … … 5583 5643 } 5584 5644 #endif 5585 if ( (r_tgt_rsp_cpt.read() == 5586 (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) 5587 || r_xram_rsp_to_tgt_rsp_rerror.read() ) 5645 uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1; 5646 bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); 5647 bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); 5648 bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); 5649 5650 if (((is_last_word or is_error) and not is_ll) or 5651 (r_tgt_rsp_key_sent.read() and is_ll)) 5588 5652 { 5589 r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; 5653 // Last word sent in case of READ or second flit sent in case if LL 5654 r_tgt_rsp_key_sent = false; 5590 5655 r_xram_rsp_to_tgt_rsp_req = false; 5656 r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; 5591 5657 } 5592 5658 else 5593 5659 { 5594 r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; 5660 if (is_ll) 5661 { 5662 r_tgt_rsp_key_sent = true; // Send second flit of ll 5663 } 5664 else 5665 { 5666 r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read 5667 } 5595 5668 } 5596 5669 } … … 5819 5892 //////////////////// 5820 5893 case ALLOC_DIR_CAS: 5821 if ((( r_cas_fsm.read() != CAS_DIR_REQ ) && 5822 ( r_cas_fsm.read() != CAS_DIR_LOCK ) && 5823 ( r_cas_fsm.read() != CAS_DIR_HIT_READ ) && 5824 ( r_cas_fsm.read() != CAS_DIR_HIT_WRITE ) && 5825 ( r_cas_fsm.read() != CAS_BC_TRT_LOCK ) && 5826 ( r_cas_fsm.read() != CAS_BC_UPT_LOCK ) && 5827 ( r_cas_fsm.read() != CAS_MISS_TRT_LOCK ) && 5828 ( r_cas_fsm.read() != CAS_UPT_LOCK ) && 5829 ( r_cas_fsm.read() != CAS_UPT_HEAP_LOCK )) 5894 if ((( r_cas_fsm.read() != CAS_DIR_REQ ) && 5895 ( r_cas_fsm.read() != CAS_DIR_LOCK ) && 5896 ( r_cas_fsm.read() != CAS_DIR_HIT_READ ) && 5897 ( r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) && 5898 ( r_cas_fsm.read() != CAS_DIR_HIT_WRITE ) && 5899 ( r_cas_fsm.read() != CAS_BC_TRT_LOCK ) && 5900 ( r_cas_fsm.read() != CAS_BC_UPT_LOCK ) && 5901 ( r_cas_fsm.read() != CAS_MISS_TRT_LOCK ) && 5902 ( r_cas_fsm.read() != CAS_UPT_LOCK ) && 5903 ( r_cas_fsm.read() != CAS_UPT_HEAP_LOCK )) 5830 5904 || 5831 (( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK ) &&5832 ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS ))5905 (( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK ) && 5906 ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS )) 5833 5907 || 5834 (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) &&5835 ( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS )))5908 (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) && 5909 ( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS ))) 5836 5910 { 5837 5911 if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ ) … … 6328 6402 ///////////////////////////// 6329 6403 { 6404 #if MONITOR_MEMCACHE_FSM 6405 p_read_fsm.write (r_read_fsm.read()); 6406 p_write_fsm.write (r_write_fsm.read()); 6407 p_xram_rsp_fsm.write (r_xram_rsp_fsm.read()); 6408 p_cas_fsm.write (r_cas_fsm.read()); 6409 p_cleanup_fsm.write (r_cleanup_fsm.read()); 6410 p_alloc_heap_fsm.write(r_alloc_heap_fsm.read()); 6411 p_alloc_dir_fsm.write (r_alloc_dir_fsm.read()); 6412 p_alloc_trt_fsm.write (r_alloc_trt_fsm.read()); 6413 p_alloc_upt_fsm.write (r_alloc_upt_fsm.read()); 6414 p_tgt_cmd_fsm.write (r_tgt_cmd_fsm.read()); 6415 p_tgt_rsp_fsm.write (r_tgt_rsp_fsm.read()); 6416 p_ixr_cmd_fsm.write (r_ixr_cmd_fsm.read()); 6417 p_ixr_rsp_fsm.write (r_ixr_rsp_fsm.read()); 6418 p_init_cmd_fsm.write (r_init_cmd_fsm.read()); 6419 p_init_rsp_fsm.write (r_init_rsp_fsm.read()); 6420 #endif 6330 6421 //////////////////////////////////////////////////////////// 6331 6422 // Command signals on the p_vci_ixr port … … 6455 6546 p_vci_tgt.reop = false; 6456 6547 break; 6548 6457 6549 case TGT_RSP_READ: 6458 p_vci_tgt.rspval = true; 6459 if( ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL) 6460 && (r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1)) ) 6461 p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()-1].read(); 6462 else if ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL) 6463 p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read(); 6550 { 6551 uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length - 1; 6552 bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); 6553 bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); 6554 6555 p_vci_tgt.rspval = true; 6556 6557 if ( is_ll and not r_tgt_rsp_key_sent.read() ) 6558 { 6559 // LL response first flit 6560 p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read(); 6561 } 6464 6562 else 6465 p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); 6466 p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); 6467 p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); 6468 p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read(); 6469 p_vci_tgt.rerror = 0; 6470 p_vci_tgt.reop = ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ); 6563 { 6564 // LL response second flit or READ response 6565 p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); 6566 } 6567 6568 p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); 6569 p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); 6570 p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read(); 6571 p_vci_tgt.rerror = 0; 6572 p_vci_tgt.reop = (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll); 6471 6573 break; 6574 } 6575 6472 6576 case TGT_RSP_WRITE: 6473 6577 /*if( ((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) ) … … 6487 6591 p_vci_tgt.reop = true; 6488 6592 break; 6593 6489 6594 case TGT_RSP_CLEANUP: 6490 6595 p_vci_tgt.rspval = true; … … 6496 6601 p_vci_tgt.reop = true; 6497 6602 break; 6603 6498 6604 case TGT_RSP_CAS: 6499 6605 p_vci_tgt.rspval = true; … … 6505 6611 p_vci_tgt.reop = true; 6506 6612 break; 6613 6507 6614 case TGT_RSP_XRAM: 6508 p_vci_tgt.rspval = true; 6509 if( ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL) 6510 && (r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length-1)) ) 6511 p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read(); 6512 else 6513 p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); 6514 p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); 6515 p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); 6516 p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); 6517 p_vci_tgt.rerror = r_xram_rsp_to_tgt_rsp_rerror.read(); 6518 p_vci_tgt.reop = (( r_tgt_rsp_cpt.read() 6519 == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) 6520 || r_xram_rsp_to_tgt_rsp_rerror.read()); 6615 { 6616 uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1; 6617 bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); 6618 bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); 6619 bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); 6620 6621 p_vci_tgt.rspval = true; 6622 6623 if( is_ll and not r_tgt_rsp_key_sent.read() ) { 6624 // LL response first flit 6625 p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read(); 6626 } 6627 else { 6628 // LL response second flit or READ response 6629 p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); 6630 } 6631 6632 p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); 6633 p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); 6634 p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); 6635 p_vci_tgt.rerror = is_error; 6636 p_vci_tgt.reop = (((is_last_word or is_error) and not is_ll) or 6637 (r_tgt_rsp_key_sent.read() and is_ll)); 6521 6638 break; 6639 } 6640 6522 6641 case TGT_RSP_INIT: 6523 6642 p_vci_tgt.rspval = true;
Note: See TracChangeset
for help on using the changeset viewer.