Changeset 361 for trunk/modules/vci_mem_cache_v4/caba/source/include

Timestamp:

Apr 10, 2013, 12:54:31 PM (12 years ago)

Author:

cfuguet

Message:

Bugfix in vci_mem_cache_v4:

In function "copy()" of the xram_transaction table the LL key was not
copied into register. Hence, the key coming from the XRAM_RSP to the
TGT_RSP FSM was never correct.

In TGT_RSP FSM, in case of LL response, the two response flits were
inverted. We must send first the key and then the data.

Add:

Add the COMPARE_HIT_COMPARE state in the CAS FSM to optimize timing.
(This modification has been already done in the vci_mem_cache v5).

Add output ports for debug. This ports are used only if the
MONITOR_MEMCACHE_FSM compilation directive is gave.

Location:

trunk/modules/vci_mem_cache_v4/caba/source/include

Files:

• vci_mem_cache_v4.h (modified) (6 diffs)
• xram_transaction_v4.h (modified) (1 diff)

trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

@@ -29 +29 @@
  *              alexandre.joannou@lip6.fr
  *
- * Modifications done by Christophe Choichillon on the 7/04/2009:
- * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
- * - Adding a new VCI target port for the CLEANUP network
- * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
- *
- * Modifications to do :
- * - Adding new variables used by the CLEANUP FSM
- *
  */
 
@@ -106 +98 @@
         INIT_CMD_INVAL_NLINE,
         INIT_CMD_XRAM_BRDCAST,
+        INIT_CMD_WRITE_BRDCAST,
+        INIT_CMD_CAS_BRDCAST,
         INIT_CMD_UPDT_IDLE,
-        INIT_CMD_WRITE_BRDCAST,
         INIT_CMD_UPDT_NLINE,
         INIT_CMD_UPDT_INDEX,
         INIT_CMD_UPDT_DATA,
         INIT_CMD_CAS_UPDT_IDLE,
-        INIT_CMD_CAS_BRDCAST,
         INIT_CMD_CAS_UPDT_NLINE,
         INIT_CMD_CAS_UPDT_INDEX,
@@ -215 +207 @@
         CAS_DIR_LOCK,
         CAS_DIR_HIT_READ,
+        CAS_DIR_HIT_COMPARE,
         CAS_DIR_HIT_WRITE,
         CAS_UPT_LOCK,
@@ -372 +365 @@
       soclib::caba::VciInitiator<vci_param> p_vci_ixr;
 
+#if MONITOR_MEMCACHE_FSM
+      sc_out<int>                           p_read_fsm; 
+      sc_out<int>                           p_write_fsm; 
+      sc_out<int>                           p_xram_rsp_fsm; 
+      sc_out<int>                           p_cas_fsm; 
+      sc_out<int>                           p_cleanup_fsm; 
+      sc_out<int>                           p_alloc_heap_fsm; 
+      sc_out<int>                           p_alloc_dir_fsm; 
+      sc_out<int>                           p_alloc_trt_fsm; 
+      sc_out<int>                           p_alloc_upt_fsm; 
+      sc_out<int>                           p_tgt_cmd_fsm; 
+      sc_out<int>                           p_tgt_rsp_fsm; 
+      sc_out<int>                           p_ixr_cmd_fsm; 
+      sc_out<int>                           p_ixr_rsp_fsm; 
+      sc_out<int>                           p_init_cmd_fsm; 
+      sc_out<int>                           p_init_rsp_fsm; 
+#endif
+                                                        
       VciMemCacheV4(
           sc_module_name name,                                // Instance Name
@@ -660 +671 @@
       sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
       sc_signal<size_t>   r_cas_upt_index;  // Update Table index
+      sc_signal<data_t> * r_cas_data;       // cache line data
 
       // Buffer between CAS fsm and INIT_CMD fsm (XRAM read)
@@ -770 +782 @@
       sc_signal<int>      r_tgt_rsp_fsm;
       sc_signal<size_t>   r_tgt_rsp_cpt;
+      sc_signal<bool>     r_tgt_rsp_key_sent;
 
       ////////////////////////////////////////////////////

trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h

@@ -78 +78 @@
         wdata.assign(source.wdata.begin(),source.wdata.end());
         rerror      = source.rerror;
+        ll_key      = source.ll_key;
     }