Index: /trunk/softs/tests_cc_vcache/Makefile.inc =================================================================== --- /trunk/softs/tests_cc_vcache/Makefile.inc (revision 373) +++ /trunk/softs/tests_cc_vcache/Makefile.inc (revision 373) @@ -0,0 +1,27 @@ +all: test.elf + +COMMON= ../common +LDSCRIPT?= ../common/ldscript + +CC= mipsel-unknown-elf-gcc +LD= mipsel-unknown-elf-ld +DU= mipsel-unknown-elf-objdump + +CFLAGS= -mips32 -nostdinc -I. -I${COMMON} -mno-abicalls +### LDFLAGS=-mips32 -nostdlib -Wl,-T${LDSCRIPT} -Ttext=0xbfc00000 + +#### object files generation +test.o: test.S + ${CC} ${CFLAGS} -c -o $@ $< + ${DU} -D $@ > $@.txt + +subr.o: ${COMMON}/subr.S + ${CC} ${CFLAGS} -c -o $@ $< + ${DU} -D $@ > $@.txt + +### linking : test.o has to be the first object +test.elf: test.o subr.o ${EXTRA_OBJ} + ${LD} -o $@ -T ${LDSCRIPT} -Ttext 0xbfc00000 $^ + ${DU} -D $@ > $@.txt +clean: + rm -f *.o test.elf *.txt run.out temp Index: /trunk/softs/tests_cc_vcache/README =================================================================== --- /trunk/softs/tests_cc_vcache/README (revision 373) +++ /trunk/softs/tests_cc_vcache/README (revision 373) @@ -0,0 +1,46 @@ +This is a very basic framework for running regression tests against +a mips32+ccvcache TSAR platform. Here's the layout of this directory: + +../../../platforms/tsarv4_mono_mmu + contains the soclib platform description and simulation executable. + It should be compiled before starting tests. + it uses the vci_simhelper component, used to stop the simulation + with an exit value. The framework uses this exit status + (with other things, see below) to determine if a test + is successfull. The simulator will exit with a non-0 exit status + after 100000 cycles (and a message to stderr), so the tests are + expected to be simple. + The platform has a tty, which is redirected to a file along with + the simlulator's output. The test framework may search for specific + strings in this file to determine if a test was successfull. +common/ + Some common functions, ldscripts, etc ... used by the tests. + It has a subr.S which holds usefull subroutines, such as + print() and printx(). +Makefile.inc + included from the test's Makefiles. Basic stuff to compile a + mips32 ELF executable for a test. It expects a test.S, + add the subr.S from common and eventually additionnal object + files. +test_*/ + these directories holds the test themselves. They have a run + script which does what is needed to compile and run a test, + print "test failed" or "test passed" on stdout, and clean the + directory if it's successfull. A sample script will call + make, then run the simulator with srdout/stderr redirected + to a file. If the simulator exists with a 0 status, this + script search for some strings in the output (that the + test program would have printed). This is an additionnal way + to check that all worked properly. + Tests are written in assembly; as we're testing for very specific + conditions (such as an instruction in a branch's delay slot on + a page boundary), we don't want the compiler to optimise things + or otherwise reorder instructions. + If the test was successfull, the 'run' script cleanups the + directory. Otherwise the 'run.out' file is available to + start looking at what's wrong. +run_tests + runs all the test_*/run scripts - the goal being that + all of them print "test passsed" :). Directories are explicitely + listed in the run_tests script (order does matter to have a readable + output) Index: /trunk/softs/tests_cc_vcache/bilan =================================================================== --- /trunk/softs/tests_cc_vcache/bilan (revision 373) +++ /trunk/softs/tests_cc_vcache/bilan (revision 373) @@ -0,0 +1,106 @@ +-n test_sanity: +test passsed +-n test_exceptions: +test passsed +-n test_mmu_basic: +test passsed +-n test_excep_ls: +test passsed +-n test_excep_ls_delayslot: +test passsed +-n test_excep_ls_llsc: +test passsed +-n test_excep_if: +test passsed +-n test_excep_if_delayslot: +test passsed +-n test_excep_if_llsc: +test passsed +-n test_exception_epc_modify: +test passsed +-n test_dtlb_inval: +test passsed +-n test_dtlb_inval2: +test passsed +-n test_dtlb_inval3: +test passsed +-n test_itlb_inval: +test passsed +-n test_itlb_inval2: +test passsed +-n test_idtlb_inval: +test passsed +-n test_idtlb_inval2: +test passsed +-n test_idtlb_inval3: +test passsed +-n test_idtlb_inval4: +test passsed +-n test_dtlb_ptprinval: +test passsed +-n test_itlb_ptprinval: +test passsed +-n test_idtlb_ptprinval: +test passsed +-n test_sync: +test passsed +-n test_sc_update_cache: +test passsed +-n test_pte_llsc: +test passsed +-n test_interrupt: +test passsed +-n test_interrupt_epc_modify: +test passsed +-n test_xicu_timer: +test passsed +-n test_interrupt_delayslot: +test FAILED +-n test_interrupt_mask: +test passsed +-n test_interrupt_external_mask: +test passsed +-n test_excep_cop: +test passsed +-n test_excep_cop_delayslot: +test passsed +-n test_excep_cop1: +test passsed +-n test_syscall: +test passsed +-n test_syscall_delayslot: +test passsed +-n test_breakpoint: +test passsed +-n test_breakpoint_delayslot: +test passsed +-n test_ri: +test passsed +-n test_ri_delayslot: +test passsed +-n test_ao: +test passsed +-n test_ao_delayslot: +test passsed +-n test_trap: +test passsed +-n test_trap_delayslot: +test passsed +-n test_fpediv: +test FAILED +-n test_fpe_delayslot: +test FAILED +-n test_dcache_inval_pa: +test passsed +-n test_icache_inval_pa: +test passsed +-n test_pte2i_ref: +test passsed +-n test_pte2lw_ref: +test passsed +-n test_pte2ll_ref: +test passsed +-n test_pte2sw_dirty: +test passsed +-n test_pte2sc_dirty: +test passsed Index: /trunk/softs/tests_cc_vcache/common/common.sh =================================================================== --- /trunk/softs/tests_cc_vcache/common/common.sh (revision 373) +++ /trunk/softs/tests_cc_vcache/common/common.sh (revision 373) @@ -0,0 +1,3 @@ +SIMUL=../../../platforms/tsarv4_mono_mmu/simul.x + +#SIMUL=../../../../soclib-svn-june-2009/soclib/soclib/platform/topcells/caba_vgsb_almo_mmu/simul.x Index: /trunk/softs/tests_cc_vcache/common/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/common/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/common/ldscript (revision 373) @@ -0,0 +1,65 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ + +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/common/misc.h =================================================================== --- /trunk/softs/tests_cc_vcache/common/misc.h (revision 373) +++ /trunk/softs/tests_cc_vcache/common/misc.h (revision 373) @@ -0,0 +1,56 @@ +/* multi-tty definitions */ +#define TTY_BASE 0xd0200000 +#define TTY_WRITE 0 +#define TTY_STATUS 1 +#define TTY_READ 2 + +/* vci_exit definitions */ +#define EXIT_BASE 0xe0000000 + +#define BOOT_ADDRESS 0xbfc00000 +#define EXCEP_ADDRESS 0xbfc00380 + +/* vci dma */ +#define DMA_BASE 0xe8000000 +#define DMA_SRC 0 +#define DMA_DST 4 +#define DMA_LEN 8 +#define DMA_RESET 12 + +/* cop0 definitions */ +#define COP_0_BADVADDR $8 +#define COP0_STATUS $12 +#define COP0_CAUSE $13 +#define COP0_EXPC $14 + +/* easy print macros */ +#define PRINT(str) \ + la a0, str;\ + jal print; \ + nop + +#define PRINT_SYNC(str) \ + la a0, str;\ + jal print_sync; \ + nop + + + +#define PRINTX \ + jal printx;\ + nop + +#define PUTCHAR(c) li a0, c; sb a0, 0(k0) + +#define EXIT(a) \ + li a0, a; \ + sw a0, 4(k1); \ + 1: j 1b; \ + nop + +/* some magic numers to test */ +#define MAGIC1 0xdead +#define MAGIC2 0xbeef +#define MAGIC3 0x900d +#define MAGIC4 0xf00d + Index: /trunk/softs/tests_cc_vcache/common/registers.h =================================================================== --- /trunk/softs/tests_cc_vcache/common/registers.h (revision 373) +++ /trunk/softs/tests_cc_vcache/common/registers.h (revision 373) @@ -0,0 +1,32 @@ +#define zero $0 +#define at $at +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 Index: /trunk/softs/tests_cc_vcache/common/subr.S =================================================================== --- /trunk/softs/tests_cc_vcache/common/subr.S (revision 373) +++ /trunk/softs/tests_cc_vcache/common/subr.S (revision 373) @@ -0,0 +1,78 @@ +#include +/* test common subroutines + + .text +/* + * void print(char *): print a string to the multitty. + * assumes k0 points to the tty base. + */ + .globl print +print: + .set noreorder + move t0, a0 +1: + lb t1, 0(t0); + beq t1, zero, end + nop + sb t1, 0(k0) + addiu t0, t0, 1 + j 1b + nop +end: + jr ra + nop + +/* + * void print_sync(char *): print a string to the multitty with a sync instruction for each character. + * assumes k0 points to the tty base. + */ + .globl print_sync +print_sync: + .set noreorder + move t0, a0 +1: + lb t1, 0(t0); + beq t1, zero, end_print_sync + nop + sb t1, 0(k0) + sync + addiu t0, t0, 1 + j 1b + nop +end_print_sync: + jr ra + nop + + +/* + * void printx(uint32_t): print a number in hex to the multitty + * assumes points to the tty base. + */ + .globl printx +printx: + .set noreorder + move t0, a0 + li t1, '0' + sb t1, 0(k0) + li t1, 'x' + sb t1, 0(k0) + li t1, 8 +1: + lui t2, 0xf000; + and t2, t0, t2 + srl t2, t2, 28 + slti t3, t2, 0xa + beq t3, zero, 2f /* in range A-F */ + nop + addi t2, t2, '0' + j 3f + nop +2: + addi t2, t2, 'A' - 0xa +3: + sb t2, 0(k0) + addi t1, t1, -1 + bgtz t1, 1b + sll t0, t0, 4 + jr ra + nop Index: /trunk/softs/tests_cc_vcache/common/vcache.h =================================================================== --- /trunk/softs/tests_cc_vcache/common/vcache.h (revision 373) +++ /trunk/softs/tests_cc_vcache/common/vcache.h (revision 373) @@ -0,0 +1,66 @@ +/* cop2/vcache definitions */ +#define VC_PTPR $0 /* set Page Table Pointer Register */ +#define VC_TLB_EN $1 /* set Data & Inst TLBs Mode Register */ +#define VC_TLB_EN_ITLB 0x8 /* enable instruction TLB */ +#define VC_TLB_EN_DTLB 0x4 /* enable data TLB */ +#define VC_TLB_EN_ICACHE 0x2 /* enable instruction cache */ +#define VC_TLB_EN_DCACHE 0x1 /* enable data cache */ +#define VC_ICACHE_FLUSH $2 /* Instruction Cache flush */ +#define VC_DCACHE_FLUSH $3 /* Data Cache flush */ +#define VC_ITLB_INVAL $4 /* Instruction TLB line invalidate */ +#define VC_DTLB_INVAL $5 /* Data TLB line invalidate */ +#define VC_ICACHE_INVAL $6 /* Instruction Cache line invalidate */ +#define VC_DCACHE_INVAL $7 /* Data Cache line invalidate */ +#define VC_ICACHE_PREFETCH $8 /* Instruction Cache line prefetch */ +#define VC_DCACHE_PREFETCH $9 /* Data Cache line prefetch */ +#define VC_SYNC $10 /* Complete pending writes */ +#define VC_IERR_TYPE $11 /* Instruction Exception type Register */ +#define VC_DERR_TYPE $12 /* Data Exception type Register */ +#define VC_DATA_LO $17 /* misc register low */ +#define VC_DATA_HI $18 /* misc register hight */ +#define VC_ICACHE_INVAL_PA $19 /* misc register hight */ +#define VC_DCACHE_INVAL_PA $20 /* misc register hight */ +#define VC_ERR_PT1_UNMAPPED 0x001 /* Page fault on Table1 (invalid PTE) */ +#define VC_ERR_PT2_UNMAPPED 0x002 /* Page fault on Table 2 (invalid PTE) */ +#define VC_ERR_PRIVILEGE_VIOLATION 0x004 /* Protected access in user mode */ +#define VC_ERR_WRITE_VIOLATION 0x008 /* Write access to a non write page */ +#define VC_ERR_EXEC_VIOLATION 0x010 /* Exec access to a non exec page */ +#define VC_ERR_UNDEFINED_XTN 0x020 /* Undefined external access address */ +#define VC_ERR_PT1_ILLEGAL_ACCESS 0x040 /* Bus Error in Table1 access */ +#define VC_ERR_PT2_ILLEGAL_ACCESS 0x080 /* Bus Error in Table2 access */ +#define VC_ERR_CACHE_ILLEGAL_ACCESS 0x100 /* Bus Error during the cache access */ +#define VC_I_BAD_VADDR $13 /* Instruction Bad Virtual Address Register */ +#define VC_D_BAD_VADDR $14 /* Data Bad Virtual Address Register */ +#define VC_DATA_L $17 /* cache parameters */ +#define VC_DATA_H $18 /* cache parameters */ +#define VC_ICACHE_INVAL_PA $19 /* icache inval per physical address */ +#define VC_DCACHE_INVAL_PA $20 /* dcache inval per physical address */ + +/* vcache page level 1 format */ +#define PTE1_V (1 << 31) /* entry valid */ +#define PTE1_T (1 << 30) /* 0 == entry is a PTE1 (maps a 2M page) */ +#define PTE1_L (1 << 29) /* accessed by local CPU */ +#define PTE1_R (1 << 28) /* accessed by remote CPU */ +#define PTE1_C (1 << 27) /* cachable */ +#define PTE1_W (1 << 26) /* writable */ +#define PTE1_X (1 << 25) /* executable */ +#define PTE1_U (1 << 24) /* user-accessible */ +#define PTE1_G (1 << 23) /* global */ +#define PTE1_D (1 << 22) /* dirty */ + +/* vcache page level 2 format: same as level 1, PTE1_T */ +#define PTE2_V (1 << 31) /* entry valid */ + /* reserved, 0 */ +#define PTE2_L (1 << 29) /* accessed by local CPU */ +#define PTE2_R (1 << 28) /* accessed by remote CPU */ +#define PTE2_C (1 << 27) /* cachable */ +#define PTE2_W (1 << 26) /* writable */ +#define PTE2_X (1 << 25) /* executable */ +#define PTE2_U (1 << 24) /* user-accessible */ +#define PTE2_G (1 << 23) /* global */ +#define PTE2_D (1 << 22) /* dirty */ +#define PTE2_os 0xff /* OS-reserved bits */ + +#define PTE2_SHIFT 12 +#define PTE2_MASK 0x0001ff000 +#define VADDR_TO_PTE2I(va) (((va) & PTE2_MASK) >> PTE2_SHIFT) Index: /trunk/softs/tests_cc_vcache/common/xicu.h =================================================================== --- /trunk/softs/tests_cc_vcache/common/xicu.h (revision 373) +++ /trunk/softs/tests_cc_vcache/common/xicu.h (revision 373) @@ -0,0 +1,96 @@ +#define XICU_BASE 0xd8200000 +#define __XICU_FUNC_SHIFT 7 +#define __XICU_IDX_SHIFT 2 +#define __XICU_RIDX(func, idx) \ + ((((func) & 0x1f) << __XICU_FUNC_SHIFT) + \ + (((idx) & 0x1f) << __XICU_IDX_SHIFT)) + +/* triggers the wtiidx interrupt. R/W */ +#define XICU_WTI_REG_FUNC 0x00 +#define XICU_WTI_REG(wtiidx) __XICU_RIDX(XICU_WTI_REG_FUNC, wtiidx) + +/* Timer period R/W */ +#define XICU_PTI_PER_FUNC 0x01 +#define XICU_PTI_PER(ptiidx) __XICU_RIDX(XICU_PTI_PER_FUNC, ptiidx) + +/* timer value R/W */ +#define XICU_PTI_VAL_FUNC 0x02 +#define XICU_PTI_VAL(ptiidx) __XICU_RIDX(XICU_PTI_VAL_FUNC, ptiidx) + +/* Timer interrupt acknowledge. R */ +#define XICU_PTI_ACK_FUNC 0x03 +#define XICU_PTI_ACK(ptiidx) __XICU_RIDX(XICU_PTI_ACK_FUNC, ptiidx) + +/* + * remaining registers define the way interrupt sources are mutiplexed to + * the output lines. Indexed by output line number. + */ +/* + * Multiplex timers to output lines: + * XICU_MSK_PTI mask register for outidx line (bit to 1 enable interrupt) + * XICU_MSK_PTI_E atomically add a set of bits to XICU_MSK_PTI + * XICU_MSK_PTI_D atomically clear a set of bits from XICU_MSK_PTI + * XICU_PTI_ACT get active PTI lines for this output line + */ +#define XICU_MSK_PTI_FUNC 0x04 /* R/W */ +#define XICU_MSK_PTI(outidx) __XICU_RIDX(XICU_MSK_PTI_FUNC, outidx) + +#define XICU_MSK_PTI_E_FUNC 0x05 /* W */ +#define XICU_MSK_PTI_E(outidx) __XICU_RIDX(XICU_MSK_PTI_E_FUNC, outidx) + +#define XICU_MSK_PTI_D_FUNC 0x06 /* W */ +#define XICU_MSK_PTI_D(outidx) __XICU_RIDX(XICU_MSK_PTI_D_FUNC, outidx) + +#define XICU_PTI_ACT_FUNC 0x06 /* R */ +#define XICU_PTI_ACT(outidx) __XICU_RIDX(XICU_PTI_ACT_FUNC, outidx) + +/* + * Multiplex hardware input lines to output lines: + * XICU_MSK_HWI mask register for outidx line (bit to 1 enable interrupt) + * XICU_MSK_HWI_E atomically add a set of bits to XICU_MSK_HWI + * XICU_MSK_HWI_D atomically clear a set of bits from XICU_MSK_HWI + * XICU_HWI_ACT get active HWI lines for this output line + */ +#define XICU_MSK_HWI_FUNC 0x08 /* R/W */ +#define XICU_MSK_HWI(outidx) __XICU_RIDX(XICU_MSK_HWI_FUNC, outidx) + +#define XICU_MSK_HWI_E_FUNC 0x09 /* W */ +#define XICU_MSK_HWI_E(outidx) __XICU_RIDX(XICU_MSK_HWI_E_FUNC, outidx) + +#define XICU_MSK_HWI_D_FUNC 0x0a /* W */ +#define XICU_MSK_HWI_D(outidx) __XICU_RIDX(XICU_MSK_HWI_D_FUNC, outidx) + +#define XICU_HWI_ACT_FUNC 0x0a /* R */ +#define XICU_HWI_ACT(outidx) __XICU_RIDX(XICU_HWI_ACT_FUNC, outidx) + +/* + * Multiplex hardware input lines to output lines: + * XICU_MSK_WTI mask register for outidx line (bit to 1 enable interrupt) + * XICU_MSK_WTI_E atomically add a set of bits to XICU_MSK_WTI + * XICU_MSK_WTI_D atomically clear a set of bits from XICU_MSK_WTI + * XICU_WTI_ACT get active WTI lines for this output line + */ +#define XICU_MSK_WTI_FUNC 0x0c /* R/W */ +#define XICU_MSK_WTI(outidx) __XICU_RIDX(XICU_MSK_WTI_FUNC, outidx) + +#define XICU_MSK_WTI_E_FUNC 0x0d /* W */ +#define XICU_MSK_WTI_E(outidx) __XICU_RIDX(XICU_MSK_WTI_E_FUNC, outidx) + +#define XICU_MSK_WTI_D_FUNC 0x0e /* W */ +#define XICU_MSK_WTI_D(outidx) __XICU_RIDX(XICU_MSK_WTI_D_FUNC, outidx) + +#define XICU_WTI_ACT_FUNC 0x0e /* R */ +#define XICU_WTI_ACT(outidx) __XICU_RIDX(XICU_WTI_ACT_FUNC, outidx) + +/* source priority encoder for outpout lines */ +#define XICU_PRIO_FUNC 0x0f +#define XICU_PRIO(outidx) __XICU_RIDX(XICU_PRIO_FUNC, outidx) + +#define XICU_PRIO_PTI 0x00000001 /* Timer interrrupt pending */ +#define XICU_PRIO_PTII(val) ((val) >> 8 & 0x1f) /* first PTI pending */ +#define XICU_PRIO_HWI 0x00000002 /* Hardware interrrupt pending */ +#define XICU_PRIO_HWII(val) ((val) >> 16 & 0x1f) /* first HWI pending */ +#define XICU_PRIO_WTI 0x00000004 /* write-triggered interrrupt pending */ +#define XICU_PRIO_WTII(val) ((val) >> 24 & 0x1f) /* first WTI pending */ + +#define XICU_PRIO_PENDING (XICU_PRIO_PTI|XICU_PRIO_HWI|XICU_PRIO_WTI) Index: /trunk/softs/tests_cc_vcache/run_tests =================================================================== --- /trunk/softs/tests_cc_vcache/run_tests (revision 373) +++ /trunk/softs/tests_cc_vcache/run_tests (revision 373) @@ -0,0 +1,36 @@ +#!/bin/sh + +PATH=${PATH}:/dsk/l1/misc/bouyer/tmp/tsarmips/obj/netbsd-5/tooldir/bin +export PATH +SOCLIB_TTY=TERM +export SOCLIB_TTY + +for dir in test_sanity test_exceptions test_mmu_basic \ + test_excep_ls test_excep_ls_delayslot test_excep_ls_llsc \ + test_excep_if test_excep_if_delayslot test_excep_if_llsc \ + test_exception_epc_modify \ + test_dtlb_inval test_dtlb_inval2 test_dtlb_inval3 \ + test_itlb_inval test_itlb_inval2 \ + test_idtlb_inval test_idtlb_inval2 test_idtlb_inval3 test_idtlb_inval4 \ + test_dtlb_ptprinval test_itlb_ptprinval test_idtlb_ptprinval \ + test_sync \ + test_llsc test_sc_no_ll test_sc_update_cache test_pte_llsc \ + test_interrupt \ + test_interrupt_epc_modify \ + test_xicu_timer \ + test_interrupt_delayslot \ + test_interrupt_mask \ + test_interrupt_external_mask \ + test_excep_cop test_excep_cop_delayslot test_excep_cop1 \ + test_syscall test_syscall_delayslot \ + test_breakpoint test_breakpoint_delayslot \ + test_ri test_ri_delayslot \ + test_ao test_ao_delayslot \ + test_trap test_trap_delayslot \ + test_dcache_inval_pa test_icache_inval_pa \ + test_pte2i_ref test_pte2lw_ref test_pte2ll_ref test_pte2sw_dirty test_pte2sc_dirty \ + test_dma_basic test_dma_unaligned \ + ; do + echo -n ${dir}": " + (cd $dir && ./run) +done Index: /trunk/softs/tests_cc_vcache/test_ao/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_ao/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ao/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_ao/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_ao/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ao/mtty0 (revision 373) @@ -0,0 +1,2 @@ +start +status 0x00400002 cause 0x00000030 pc 0xBFC00034 badva 0x00000000 Index: /trunk/softs/tests_cc_vcache/test_ao/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_ao/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ao/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000030 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_ao/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_ao/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ao/test.S (revision 373) @@ -0,0 +1,63 @@ +/* + * arithmetic overflow test: check that a add can generates an exception + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + la a0, 0x7fffffff + li a1, 0x02 + add a0, a0, a1 + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_ao_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_ao_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ao_delayslot/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_ao_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_ao_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ao_delayslot/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000030 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_ao_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_ao_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ao_delayslot/test.S (revision 373) @@ -0,0 +1,84 @@ +/* + * arithmetic overflow test: check that a overflow in a delay slot is + * properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + la a0, 0x7fffffff + li a1, 0x02 + j exit + add a0, a0, a1 + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_breakpoint/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_breakpoint/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_breakpoint/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_breakpoint/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_breakpoint/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_breakpoint/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000024 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_breakpoint/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_breakpoint/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_breakpoint/test.S (revision 373) @@ -0,0 +1,86 @@ +/* + * breakpoint test: check that a breakpoint generates an exception, and we can + * return + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + break + bne a3, zero, exit + nop + /* we should not get there, a3 is not 0 */ + EXIT(2) +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + mfc0 a0, COP0_EXPC + addiu a0, a0, 4 + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000024 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_breakpoint_delayslot/test.S (revision 373) @@ -0,0 +1,85 @@ +/* + * breakpoint test: check that a breakpoint in a delay slot is properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + j exit + break + nop + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/mtty0 (revision 373) @@ -0,0 +1,4 @@ +start +mmu started before DMA 0x0000BEEF +mmu started after DMA 0x0000F00D +mmu started after FLUSH 0x0000F00D Index: /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/run (revision 373) @@ -0,0 +1,38 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started before DMA 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started after DMA 0x0000F00D$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started after FLUSH 0x0000F00D$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 3 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dcache_inval_pa/test.S (revision 373) @@ -0,0 +1,136 @@ +/* + * cache inval test: check that VC_DCACHE_INVAL_PA does the job + * on a cc_vcache, the cache invalidation/update should be done by hardware + * and VC_DCACHE_INVAL_PA should not be needed. + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_a) + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + la a1, DMA_BASE + la a0, testval2 + sw a0, DMA_SRC(a1) + la a0, testval + sw a0, DMA_DST(a1) + li a0, 4 + sw a0, DMA_LEN(a1) /* start DMA */ +loop: + lw a0, DMA_LEN(a1) + bne a0, zero, loop; + nop + + PRINT(mmustr_b) + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + + la a0, testval + mtc2 a0, VC_DATA_LO + mtc2 zero, VC_DATA_HI + mtc2 zero, VC_DCACHE_INVAL_PA + nop + + PRINT(mmustr_c) + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started before DMA \0" +mmustr_b: .ascii "mmu started after DMA \0" +mmustr_c: .ascii "mmu started after FLUSH \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +data_a: + .word MAGIC1 +testval: + .word MAGIC2 +data_b: + .word MAGIC3 +testval2: + .word MAGIC4 + .globl pte2_a + +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + (DMA_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */ Index: /trunk/softs/tests_cc_vcache/test_dma_basic/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_dma_basic/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dma_basic/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_dma_basic/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_dma_basic/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dma_basic/mtty0 (revision 373) @@ -0,0 +1,2 @@ +before DMA 0x0000BEEF 0x0000F00D +after DMA 0x0000F00D 0x0000F00D 0x0000BEEF 0x0000DEAD 0x0000DEAD Index: /trunk/softs/tests_cc_vcache/test_dma_basic/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_dma_basic/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dma_basic/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^after DMA 0x0000F00D 0x0000F00D 0x0000BEEF 0x0000DEAD 0x0000DEAD$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_dma_basic/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_dma_basic/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dma_basic/test.S (revision 373) @@ -0,0 +1,135 @@ +/* + * basic DMA check: check that the DMA engine works and and doens't + * clobbers memory + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(mmustr_a) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, testval2 + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + la t0, testval + la t1, testval3 + lw a0, 0(t0); + sw a0, 0(t1) + + la a1, DMA_BASE + la a0, tstsrc + sw a0, DMA_SRC(a1) + la a0, tstdst + sw a0, DMA_DST(a1) + la a0, 0x18 + sw a0, DMA_LEN(a1) /* start DMA */ +loop: + lw a0, DMA_LEN(a1) + bne a0, zero, loop; + nop + sw a0, DMA_RESET(a1) /* reset DMA */ + + la a0, testval2 + sw a0, DMA_SRC(a1) + la a0, testval + sw a0, DMA_DST(a1) + la a0, 0x4 + sw a0, DMA_LEN(a1) /* start DMA */ +loop2: + lw a0, DMA_LEN(a1) + bne a0, zero, loop2; + nop + sw a0, DMA_RESET(a1) /* reset DMA */ + + PRINT(mmustr_b) + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, testval2 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, testval3 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, tstsrc + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, tstdst + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "before DMA \0" +mmustr_b: .ascii "after DMA \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +testval: + .word MAGIC2 +testval2: + .word MAGIC4 +testval3: + .word MAGIC4 +tstdst: + .word 0 + .org 0x1000 + .word 0 +tstsrc: + .word MAGIC1 + Index: /trunk/softs/tests_cc_vcache/test_dma_unaligned/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_dma_unaligned/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dma_unaligned/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_dma_unaligned/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_dma_unaligned/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dma_unaligned/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^after DMA this is the test string unaligned and more than 64 chars long abcdefghijklmnopqrstuvwxyz ABCDEFGHIJKLMNOPQRSTUVWXYZ 123456789 abcdefghijklmnopqrstuvwxyz$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_dma_unaligned/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_dma_unaligned/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dma_unaligned/test.S (revision 373) @@ -0,0 +1,96 @@ +/* + * basic DMA check: check that the DMA engine works and and doens't + * clobbers memory + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(mmustr_a) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la t0, tstdst + sw zero, 0(t0); + PRINT(tstdst) + PUTCHAR('E') + PUTCHAR('\n') + + la a1, DMA_BASE + la a0, tstsrc + sw a0, DMA_SRC(a1) + la a0, tstdst + sw a0, DMA_DST(a1) + la a0, 160 #strlen(tstsrc) + sw a0, DMA_LEN(a1) /* start DMA */ +loop: + lw a0, DMA_LEN(a1) + bne a0, zero, loop; + nop + + PRINT(mmustr_b) + PRINT(tstdst) + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "before DMA \0" +mmustr_b: .ascii "after DMA \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +testval: + .word MAGIC2 +testval2: + .word MAGIC4 +testval3: + .word MAGIC4 +tstdst: + .word 0 + .org 0x1000 +testval4: + .word MAGIC1 +tstsrc: + .ascii "this is the test string unaligned and more than 64 chars long abcdefghijklmnopqrstuvwxyz ABCDEFGHIJKLMNOPQRSTUVWXYZ 123456789 abcdefghijklmnopqrstuvwxyz\n\0" Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval/mtty0 (revision 373) @@ -0,0 +1,2 @@ +start +mmu started 0x0000BEEF status 0x00400002 cause 0x0000001C pc 0xBFC00080 badva 0x00200004 Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF status 0x00400002 cause 0x0000001C pc 0xBFC00080 badva 0x00200004$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval/test.S (revision 373) @@ -0,0 +1,117 @@ +/* + * dtlb inval: a write to VC_DTLB_INVAL should invalidate the corresponding + * dtlb entry. On a ccvcache, VC_DTLB_INVAL should not be needed, and + * the first access after clearing pte2_a should fail + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la a0, pte2_a + sw zero, 0(a0) /* invalidate PTE2 entry */ + sync + la t0, testval + 0x00200000 + lw a0, 0(t0); /* TLB entry not invalidated yet, we can do this */ + PRINTX + PUTCHAR('\n') + la t0, testval + 0x00200000 + mtc2 t0, VC_DTLB_INVAL /* invalidate VA */ + lw a0, 0(t0); /* now this should fail */ + PRINTX + PUTCHAR('\n') + + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval2/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval2/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval2/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval2/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval2/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval2/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval2/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval2/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval2/test.S (revision 373) @@ -0,0 +1,121 @@ +/* + * dtlb inval: a write to a PTE2 should invalidate the corresponding + * dtlb entry. + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, pte2_a + la a0, 0x1000 >> 12 + sw a0, 4(t0) /* swap PTE2 entry */ +1: + ll a0, 0(t0) + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 0(t0) + beqz a0, 1b + nop + + la t0, testval + 0x00200000 + lw a0, 0(t0); /* should get MAGIC1 */ + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .align 12 + .word MAGIC2 + .word MAGIC1 + .globl pte2_a +/* + * one PD with a level 2 PTP: we switch an entry in the PTP and + * check that the dtlb is invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval3/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval3/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval3/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval3/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval3/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval3/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "mmu started 0x0000BEEF 0xAC400000 0x0000900D status 0x00400002 cause 0x0000001C pc 0xBFC000D4 badva 0x00200004" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_dtlb_inval3/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_inval3/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_inval3/test.S (revision 373) @@ -0,0 +1,128 @@ +/* + * dtlb inval: a write to a PTE2 should invalidate the corresponding + * dtlb entry. Check that this is true is we change only the write flag + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, testval + 0x00200000 + la a0, MAGIC3 + sw a0, 0(t0) + la t0, pte2_a +1: + ll a0, 0(t0) + la a1, ~PTE2_W + and a1, a0, a1 + sc a1, 0(t0) + beqz a1, 1b + nop + PRINTX + PUTCHAR(' ') + + la t0, testval + 0x00200000 + lw a0, 0(t0); /* should get MAGIC3 */ + PRINTX + PUTCHAR(' ') + la t0, testval + 0x00200000 + la a0, MAGIC1 + sw a0, 0(t0) + + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .align 12 + .word MAGIC2 + .word MAGIC1 + .globl pte2_a +/* + * one PD with a level 2 PTP: we switch an entry in the PTP and + * check that the dtlb is invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_W + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started ptpr_b 0x0000F00D$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started ptpr_a 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_dtlb_ptprinval/test.S (revision 373) @@ -0,0 +1,145 @@ +/* + * dtlb inval on PTPR write: check that no stale entry exists in the dtlb + * after MMU context swicth + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_b + srl a0, a0, 13 + mtc2 a0, VC_PTPR # PTPR <= pte1_b + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_b) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX # print MAGIC3 + PUTCHAR('\n') + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR # PTPR <= pte1_a + nop + PRINT(mmustr_a) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX # print MAGIC1 + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started ptpr_a \0" +mmustr_b: .ascii "mmu started ptpr_b \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .org data_a + 0x1000 +data_b: + .word MAGIC3 + .word MAGIC4 + +/* + * two PD with two different PTE2 for code: check that dtlb points to + * the right one by loading 2 different data at the same virtual address + */ + .globl pte2_a +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + + .org pte2_a + 4092 + .word 0 + .globl pte2_b +pte2_b: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x1000 >> 12 /* check real value of data_b */ + + .org pte2_b + 4092 + .word 0 + + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 + .globl pte1_b +pte1_b: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x3000 >> 12) /* map PA 0x1000 at VA 0x00200000 via pte2_b */ + .org pte1_b + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_b + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_b + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_b + 8188 + .word 0 Index: /trunk/softs/tests_cc_vcache/test_excep_cop/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_cop/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x1000002C pc 0xBFC0002C badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_cop/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop/test.S (revision 373) @@ -0,0 +1,71 @@ +/* + * coproc unusable exception test: we take an exception on COP1 use + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + li t3, MAGIC1 + mtc1 t3,$f2 + mfc1 a0,$f2 + PRINTX + PUTCHAR('\n') + nop + nop + nop + nop + +1: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_excep_cop1/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop1/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop1/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_cop1/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop1/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop1/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x1000002C pc 0xBFC00030 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_cop1/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop1/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop1/test.S (revision 373) @@ -0,0 +1,71 @@ +/* + * trap test: check that we get a trap on FPU access though [ls][dw]c1 + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV), enable cop1 */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, div1; + lwc1 $f0, 0(a0) + PRINTX + PUTCHAR('\n') + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl div1 +div1: + .float 10.0 + .globl div2 +div2: + .float 0.0 Index: /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x9000002C pc 0xBFC00028 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_cop_delayslot/test.S (revision 373) @@ -0,0 +1,65 @@ +/* + * coproc unusable exception test: 0x80000000 bit is set in cause register + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + j 1f + mtc1 t3,$f2 + nop + +1: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_excep_if/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_if/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_excep_if/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if/mtty0 (revision 373) @@ -0,0 +1,4 @@ +start +mmu started +status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000 +0x00000004: 0x0000BEEF Index: /trunk/softs/tests_cc_vcache/test_excep_if/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_if/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if/test.S (revision 373) @@ -0,0 +1,135 @@ +/* + * ifetch bus fault exception test: we can restart the faulting instruction + * We use the MMU to cause fault. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00200000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + move a1, zero + la s0, testval + jal doload + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0xbfc01000 at PA 0xbfc01000 */ + la t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8 + la a0, (0xbfc01000 >> PTE2_SHIFT) + sw a0, 4(t0) + la a0, (PTE2_V | PTE2_C | PTE2_X) + sw a0, 0(t0) + /* la a0, 0xbfc01000 + mtc2 a0, VC_ITLB_INVAL */ + + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + /* + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + + /* we should not get there */ + nop + nop + EXIT(1) + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2 +pte2: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .org pte2 + 4092 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 Index: /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000) - 4; + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x80000018 pc 0xBFC00FFC badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if_delayslot/test.S (revision 373) @@ -0,0 +1,135 @@ +/* + * ifetch bus fault exception test: we can restart the faulting instruction + * when the fault occurs in the branch delay slot. + * We use the MMU to cause fault. + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00200000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + move a1, zero + la s0, testval + jal doload + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0xbfc01000 at PA 0xbfc01000 */ + la t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8 + la a0, (0xbfc01000 >> PTE2_SHIFT) + sw a0, 4(t0) + la a0, (PTE2_V | PTE2_C | PTE2_X) + sw a0, 0(t0) + /* la a0, 0xbfc01000 + mtc2 a0, VC_ITLB_INVAL */ + + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + /* + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + + /* we should not get there */ + nop + nop + EXIT(1) + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2 +pte2: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .org pte2 + 4092 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 Index: /trunk/softs/tests_cc_vcache/test_excep_if_llsc/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if_llsc/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if_llsc/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_if_llsc/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if_llsc/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if_llsc/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_excep_if_llsc/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if_llsc/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if_llsc/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_if_llsc/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_if_llsc/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_if_llsc/test.S (revision 373) @@ -0,0 +1,136 @@ +/* + * ifetch bus fault exception test: we can restart the faulting instruction + * We use the MMU to cause fault. + * Match what NetBSD does for page table update: sw for ppn, ll/sc for flags + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00200000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + move a1, zero + la s0, testval + jal doload + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0xbfc01000 at PA 0xbfc01000 */ + la t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8 + la a0, (0xbfc01000 >> PTE2_SHIFT) + sw a0, 4(t0) +1: + ll a0, 0(t0) + la a0, (PTE2_V | PTE2_C | PTE2_X) + sc a0, 0(t0) + beqz a0, 1b + + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + /* + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + /* we should not get there */ + nop + nop + EXIT(1) + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2 +pte2: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .org pte2 + 4092 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 Index: /trunk/softs/tests_cc_vcache/test_excep_intr/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_intr/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_intr/Makefile (revision 373) @@ -0,0 +1,3 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc +CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY} Index: /trunk/softs/tests_cc_vcache/test_excep_intr/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_intr/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_intr/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_excep_intr/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_intr/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_intr/mtty0 (revision 373) @@ -0,0 +1,4 @@ +start +status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000001 +status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001 +end 0x0000BEEF 0x00000001 Index: /trunk/softs/tests_cc_vcache/test_excep_intr/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_intr/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_intr/run (revision 373) @@ -0,0 +1,44 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^end 0x0000BEEF 0x00000001$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 3 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} +echo +i=1180 +while true; do + echo -n " DELAY=$i: " + make INTERRUPT_DELAY=$i --quiet || exit 1 + ${SIMUL} > run.out 2>&1 + if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + else + echo "test FAILED" + exit 1 + fi + else + echo "test FAILED" + exit 1 + fi + i=$((i+1)) +done + Index: /trunk/softs/tests_cc_vcache/test_excep_intr/run.out =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_intr/run.out (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_intr/run.out (revision 373) @@ -0,0 +1,25 @@ + + SystemC 2.2.0 --- Apr 14 2011 18:52:40 + Copyright (c) 1996-2006 by all Contributors + ALL RIGHTS RESERVED +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + + + + +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + +Loading at 0xbfc00000 size 262144: .text .reginfo +Loading at 0 size 33554432: .data +start +status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000001 +status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001 +end 0x0000BEEF 0x00000001 +vci_exit terminate simulation, status 0d0 +couldn't find string 2 in output - mtty not working ? Index: /trunk/softs/tests_cc_vcache/test_excep_intr/subr.o.txt =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_intr/subr.o.txt (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_intr/subr.o.txt (revision 373) @@ -0,0 +1,49 @@ + +subr.o: file format elf32-littlemips + + +Disassembly of section .text: + +00000000 : + 0: 00804021 move t0,a0 + 4: 81090000 lb t1,0(t0) + 8: 11200005 beqz t1,20 + c: 00000000 nop + 10: a3490000 sb t1,0(k0) + 14: 25080001 addiu t0,t0,1 + 18: 08000001 j 4 + 1c: 00000000 nop + +00000020 : + 20: 03e00008 jr ra + 24: 00000000 nop + +00000028 : + 28: 00804021 move t0,a0 + 2c: 24090030 li t1,48 + 30: a3490000 sb t1,0(k0) + 34: 24090078 li t1,120 + 38: a3490000 sb t1,0(k0) + 3c: 24090008 li t1,8 + 40: 3c0af000 lui t2,0xf000 + 44: 010a5024 and t2,t0,t2 + 48: 000a5702 srl t2,t2,0x1c + 4c: 294b000a slti t3,t2,10 + 50: 11600004 beqz t3,64 + 54: 00000000 nop + 58: 214a0030 addi t2,t2,48 + 5c: 0800001a j 68 + 60: 00000000 nop + 64: 214a0037 addi t2,t2,55 + 68: a34a0000 sb t2,0(k0) + 6c: 2129ffff addi t1,t1,-1 + 70: 1d20fff3 bgtz t1,40 + 74: 00084100 sll t0,t0,0x4 + 78: 03e00008 jr ra + 7c: 00000000 nop + +Disassembly of section .reginfo: + +00000000 <.reginfo>: + 0: 84000f10 lh zero,3856(zero) + ... Index: /trunk/softs/tests_cc_vcache/test_excep_intr/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_intr/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_intr/test.S (revision 373) @@ -0,0 +1,201 @@ +/* + * Check interrupt while in trap handler. + * Cache is enabled so we have one instruction/cycle + */ +#include +#include +#include +#include + +#define DOLOAD_ADDR 0x80000000 + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00200000 - 16 + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + /* + * interrupt in INTERRUPT_DELAY cycles. + */ + li a0, INTERRUPT_DELAY + sw a0, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + nop + nop + nop + nop + nop + + nop + move a1, zero + la s0, DOLOAD_ADDR + jalr s0 + nop + j end + nop + /* we should not end there */ + EXIT(1) + +end: + PRINT(endstr) + move a0, a1 + PRINTX + PUTCHAR(' ') + la a0, myvar + lw a0, 0(a0) + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + move s0, a0 + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + PUTCHAR('\n') + /* map VA DOLOAD_ADDR at PA 0xbfc01000 */ + la t0, pte22 + VADDR_TO_PTE2I(DOLOAD_ADDR) * 8 + la a0, (0xbfc01000 >> PTE2_SHIFT) + sw a0, 4(t0) + la a0, (PTE2_V | PTE2_C | PTE2_X) + sw a0, 0(t0) + mtc2 zero, VC_DCACHE_FLUSH /* flush the whole data cache */ + + andi a0, s0, 0xff00 + beq a0, zero, notintr + nop + + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) +notintr: + la a1, myvar + la a0, 0(a1) + beq a0, zero, noex + nop + EXIT(2) +noex: + li a0, 1 + sw a0, 0(a1) + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + /* + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + la s0, testval + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + /* we should not get there */ + EXIT(1) + nop + .data +myvar: .word 0 +testval: + .word MAGIC2 + .globl pte2 +pte2: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .org pte2 + 4092 + .globl pte22 +pte22: + .align 12 + .word 0 + .word 0 + .org pte22 + 4092 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (DOLOAD_ADDR >> 21) * 4 + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map VA DOLOAD_ADDR with 4k page: check real address of PTE22 !!! */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (XICU_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_excep_intr/test.elf.txt =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_intr/test.elf.txt (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_intr/test.elf.txt (revision 373) @@ -0,0 +1,273 @@ + +test.elf: file format elf32-littlemips + + +Disassembly of section .text: + +bfc00000 <_start>: +bfc00000: 3c1ad020 lui k0,0xd020 +bfc00004: 3c1be000 lui k1,0xe000 +bfc00008: 3c1d001f lui sp,0x1f +bfc0000c: 37bdfff0 ori sp,sp,0xfff0 +bfc00010: 40806800 mtc0 zero,c0_cause +bfc00014: 3c040000 lui a0,0x0 +bfc00018: 24844000 addiu a0,a0,16384 +bfc0001c: 00042342 srl a0,a0,0xd +bfc00020: 48840000 mtc2 a0,$0 + ... +bfc0002c: 2404000f li a0,15 +bfc00030: 48840800 mtc2 a0,$1 +bfc00034: 3c04bfc0 lui a0,0xbfc0 +bfc00038: 2484024c addiu a0,a0,588 +bfc0003c: 0ff000e4 jal bfc00390 +bfc00040: 00000000 nop +bfc00044: 3c08d820 lui t0,0xd820 +bfc00048: 8d040180 lw a0,384(t0) +bfc0004c: 24040001 li a0,1 +bfc00050: ad040280 sw a0,640(t0) +bfc00054: 3410beef li s0,0xbeef +bfc00058: 2404049c li a0,1180 +bfc0005c: ad040080 sw a0,128(t0) +bfc00060: 8d040180 lw a0,384(t0) +bfc00064: 3c040040 lui a0,0x40 +bfc00068: 24840401 addiu a0,a0,1025 +bfc0006c: 40846000 mtc0 a0,c0_status + ... +bfc00088: 00002821 move a1,zero +bfc0008c: 3c108000 lui s0,0x8000 +bfc00090: 0200f809 jalr s0 +bfc00094: 00000000 nop +bfc00098: 0bf0002c j bfc000b0 +bfc0009c: 00000000 nop +bfc000a0: 24040001 li a0,1 +bfc000a4: af640000 sw a0,0(k1) +bfc000a8: 0bf0002a j bfc000a8 <_start+0xa8> +bfc000ac: 00000000 nop + +bfc000b0 : +bfc000b0: 3c04bfc0 lui a0,0xbfc0 +bfc000b4: 24840253 addiu a0,a0,595 +bfc000b8: 0ff000e4 jal bfc00390 +bfc000bc: 00000000 nop +bfc000c0: 00a02021 move a0,a1 +bfc000c4: 0ff000ee jal bfc003b8 +bfc000c8: 00000000 nop +bfc000cc: 24040020 li a0,32 +bfc000d0: a3440000 sb a0,0(k0) +bfc000d4: 3c040000 lui a0,0x0 +bfc000d8: 24840000 addiu a0,a0,0 +bfc000dc: 8c840000 lw a0,0(a0) +bfc000e0: 0ff000ee jal bfc003b8 +bfc000e4: 00000000 nop +bfc000e8: 2404000a li a0,10 +bfc000ec: a3440000 sb a0,0(k0) +bfc000f0: 24040000 li a0,0 +bfc000f4: af640000 sw a0,0(k1) +bfc000f8: 0bf0003e j bfc000f8 +bfc000fc: 00000000 nop + +bfc00100 : +bfc00100: 27bdfff8 addiu sp,sp,-8 +bfc00104: afa40004 sw a0,4(sp) +bfc00108: afbf0008 sw ra,8(sp) +bfc0010c: 3c04bfc0 lui a0,0xbfc0 +bfc00110: 24840228 addiu a0,a0,552 +bfc00114: 0ff000e4 jal bfc00390 +bfc00118: 00000000 nop +bfc0011c: 40046000 mfc0 a0,c0_status +bfc00120: 0ff000ee jal bfc003b8 +bfc00124: 00000000 nop +bfc00128: 3c04bfc0 lui a0,0xbfc0 +bfc0012c: 24840230 addiu a0,a0,560 +bfc00130: 0ff000e4 jal bfc00390 +bfc00134: 00000000 nop +bfc00138: 40046800 mfc0 a0,c0_cause +bfc0013c: 00808021 move s0,a0 +bfc00140: 0ff000ee jal bfc003b8 +bfc00144: 00000000 nop +bfc00148: 3c04bfc0 lui a0,0xbfc0 +bfc0014c: 24840238 addiu a0,a0,568 +bfc00150: 0ff000e4 jal bfc00390 +bfc00154: 00000000 nop +bfc00158: 40047000 mfc0 a0,c0_epc +bfc0015c: 0ff000ee jal bfc003b8 +bfc00160: 00000000 nop +bfc00164: 3c04bfc0 lui a0,0xbfc0 +bfc00168: 2484023d addiu a0,a0,573 +bfc0016c: 0ff000e4 jal bfc00390 +bfc00170: 00000000 nop +bfc00174: 40044000 mfc0 a0,c0_badvaddr +bfc00178: 0ff000ee jal bfc003b8 +bfc0017c: 00000000 nop +bfc00180: 3c04bfc0 lui a0,0xbfc0 +bfc00184: 24840245 addiu a0,a0,581 +bfc00188: 0ff000e4 jal bfc00390 +bfc0018c: 00000000 nop +bfc00190: 3c08d820 lui t0,0xd820 +bfc00194: 8d040780 lw a0,1920(t0) +bfc00198: 0ff000ee jal bfc003b8 +bfc0019c: 00000000 nop +bfc001a0: 2404000a li a0,10 +bfc001a4: a3440000 sb a0,0(k0) +bfc001a8: 3c080000 lui t0,0x0 +bfc001ac: 25082000 addiu t0,t0,8192 +bfc001b0: 3c04000b lui a0,0xb +bfc001b4: 3484fc01 ori a0,a0,0xfc01 +bfc001b8: ad040004 sw a0,4(t0) +bfc001bc: 3c048a00 lui a0,0x8a00 +bfc001c0: ad040000 sw a0,0(t0) +bfc001c4: 48801800 mtc2 zero,$3 +bfc001c8: 3204ff00 andi a0,s0,0xff00 +bfc001cc: 10800003 beqz a0,bfc001dc +bfc001d0: 00000000 nop +bfc001d4: 3c08d820 lui t0,0xd820 +bfc001d8: ad000080 sw zero,128(t0) + +bfc001dc : +bfc001dc: 3c050000 lui a1,0x0 +bfc001e0: 24a50000 addiu a1,a1,0 +bfc001e4: 24a40000 addiu a0,a1,0 +bfc001e8: 10800005 beqz a0,bfc00200 +bfc001ec: 00000000 nop +bfc001f0: 24040002 li a0,2 +bfc001f4: af640000 sw a0,0(k1) +bfc001f8: 0bf0007e j bfc001f8 +bfc001fc: 00000000 nop + +bfc00200 : +bfc00200: 24040001 li a0,1 +bfc00204: aca40000 sw a0,0(a1) +bfc00208: 8fa40004 lw a0,4(sp) +bfc0020c: 8fbf0008 lw ra,8(sp) +bfc00210: 27bd0008 addiu sp,sp,8 +bfc00214: 42000018 eret +bfc00218: 24040001 li a0,1 +bfc0021c: af640000 sw a0,0(k1) +bfc00220: 0bf00088 j bfc00220 +bfc00224: 00000000 nop + +bfc00228 : +bfc00228: 74617473 jalx b185d1cc <_stack+0xb145d1dc> +bfc0022c: 00207375 0x207375 + +bfc00230 : +bfc00230: 75616320 jalx b5858c80 <_stack+0xb5458c90> +bfc00234: 00206573 tltu at,zero,0x195 + +bfc00238 : +bfc00238: 20637020 addi v1,v1,28704 + ... + +bfc0023d : +bfc0023d: 6220 sw ra,128(sp) +bfc0023f: 6461 restore 8,ra,s0 +bfc00241: 6176 btnez bfc0032f +bfc00243: 0020 addiu s0,sp,128 + +bfc00245 : +bfc00245: 7820 sd s1,0(s0) +bfc00247: 6369 addiu sp,840 +bfc00249: 2075 beqz s0,bfc00335 + ... + +bfc0024c : +bfc0024c: 72617473 0x72617473 +bfc00250: 65000a74 0x65000a74 + +bfc00253 : +bfc00253: 6e65 li a2,101 +bfc00255: 2064 beqz s0,bfc0031f + ... + +bfc00380 : +bfc00380: 0bf00040 j bfc00100 +bfc00384: 00000000 nop + ... + +bfc00390 : +bfc00390: 00804021 move t0,a0 +bfc00394: 81090000 lb t1,0(t0) +bfc00398: 11200005 beqz t1,bfc003b0 +bfc0039c: 00000000 nop +bfc003a0: a3490000 sb t1,0(k0) +bfc003a4: 25080001 addiu t0,t0,1 +bfc003a8: 0bf000e5 j bfc00394 +bfc003ac: 00000000 nop + +bfc003b0 : +bfc003b0: 03e00008 jr ra +bfc003b4: 00000000 nop + +bfc003b8 : +bfc003b8: 00804021 move t0,a0 +bfc003bc: 24090030 li t1,48 +bfc003c0: a3490000 sb t1,0(k0) +bfc003c4: 24090078 li t1,120 +bfc003c8: a3490000 sb t1,0(k0) +bfc003cc: 24090008 li t1,8 +bfc003d0: 3c0af000 lui t2,0xf000 +bfc003d4: 010a5024 and t2,t0,t2 +bfc003d8: 000a5702 srl t2,t2,0x1c +bfc003dc: 294b000a slti t3,t2,10 +bfc003e0: 11600004 beqz t3,bfc003f4 +bfc003e4: 00000000 nop +bfc003e8: 214a0030 addi t2,t2,48 +bfc003ec: 0bf000fe j bfc003f8 +bfc003f0: 00000000 nop +bfc003f4: 214a0037 addi t2,t2,55 +bfc003f8: a34a0000 sb t2,0(k0) +bfc003fc: 2129ffff addi t1,t1,-1 +bfc00400: 1d20fff3 bgtz t1,bfc003d0 +bfc00404: 00084100 sll t0,t0,0x4 +bfc00408: 03e00008 jr ra +bfc0040c: 00000000 nop + ... + +bfc01000 : +bfc01000: 3c100000 lui s0,0x0 +bfc01004: 26100004 addiu s0,s0,4 +bfc01008: 03e00008 jr ra +bfc0100c: 8e050000 lw a1,0(s0) +bfc01010: 24040001 li a0,1 +bfc01014: af640000 sw a0,0(k1) +bfc01018: 0bf00406 j bfc01018 +bfc0101c: 00000000 nop +bfc01020: 00000000 nop + +Disassembly of section .reginfo: + +bfc01024 <.reginfo>: +bfc01024: bc010130 cache 0x1,304(zero) + ... +bfc01038: 00008000 sll s0,zero,0x0 + +Disassembly of section .data: + +00000000 : + 0: 00000000 nop + +00000004 : + 4: 0000beef 0xbeef + ... + +00001000 : + 1000: 8a000000 lwl zero,0(s0) + 1004: 000bfc00 sll ra,t3,0x10 + ... + +00002000 : + ... + +00004000 : + 4000: 8c000000 lw zero,0(zero) + ... + 5000: c0000002 ll zero,2(zero) + ... + 57f8: c0000001 ll zero,1(zero) + ... + 5a04: 84000681 lh zero,1665(zero) + ... + 5b04: 840006c1 lh zero,1729(zero) + ... + 5c00: 84000700 lh zero,1792(zero) + ... Index: /trunk/softs/tests_cc_vcache/test_excep_ls/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_ls/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls/mtty0 (revision 373) @@ -0,0 +1,4 @@ +start +mmu started +status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004 +0x00000004: 0x0000BEEF Index: /trunk/softs/tests_cc_vcache/test_excep_ls/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_ls/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls/test.S (revision 373) @@ -0,0 +1,103 @@ +/* + * load/store bus fault exception test: we can restart the faulting instruction + * We use the MMU to cause fault + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + /* 0x00000000 not mapped yet: we fault, load the MMU and retry */ + move a1, zero + la s0, testval + lw a1, 0(s0) /* this should trigger the exception */ + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0 at PA 0: just copy entry for 0x00200000 */ + la t0, pte1 + 0x00200000 + lw a0, 4(t0) + sw a0, 0(t0) + /* mtc2 zero, VC_DTLB_INVAL */ + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte1 +pte1: + .align 13 + .word 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x8000001C pc 0xBFC000AC badva 0x00000004$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls_delayslot/test.S (revision 373) @@ -0,0 +1,123 @@ +/* + * load/store bus fault exception test: we can restart the jump when the + * instruction in the delay slot takes a fault. + * We use the MMU to cause fault + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + /* 0x00000000 not mapped yet: we fault, load the MMU and retry */ + move a1, zero + la s0, testval + jal doload + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl doload +doload: + nop + nop + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0 at PA 0: just copy entry for 0x00200000 */ + la t0, pte1 + 0x00200000 + lw a0, 4(t0) + sw a0, 0(t0) + /* mtc2 zero, VC_DTLB_INVAL */ + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte1 +pte1: + .align 13 + .word 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_excep_ls_llsc/test.S (revision 373) @@ -0,0 +1,107 @@ +/* + * load/store bus fault exception test: we can restart the faulting instruction + * We use the MMU to cause fault + * Match what NetBSD does for page table update: sw for ppn, ll/sc for flags + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + /* 0x00000000 not mapped yet: we fault, load the MMU and retry */ + move a1, zero + la s0, testval + lw a1, 0(s0) /* this should trigger the exception */ + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0 at PA 0: just copy entry for 0x00200000 */ + la t0, pte1 + 0x00200000 +1: + ll a0, 0(t0) + lw a0, 4(t0) + sc a0, 0(t0) + beqz a0, 1b + /* mtc2 zero, VC_DTLB_INVAL */ + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte1 +pte1: + .align 13 + .word 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_exception_epc_modify/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_exception_epc_modify/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_exception_epc_modify/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_exception_epc_modify/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_exception_epc_modify/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_exception_epc_modify/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^eret$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_exception_epc_modify/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_exception_epc_modify/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_exception_epc_modify/test.S (revision 373) @@ -0,0 +1,71 @@ +/* + * Check that on return from exception the modified EPC is handled. + * We use a load to an unaligned address to trigger the exception. + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + li a0, 1 + lw a0, 0(a0) /* fault */ + + /* we shouldn't get there */ + EXIT(1) + + .globl exret + +exret: + PRINT(eretstr) + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + la a0, exret + mtc0 a0, COP0_EXPC + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_exceptions/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_exceptions/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_exceptions/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_exceptions/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_exceptions/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_exceptions/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400006 cause 0x00000010 pc 0xBFC0001C badva 0x00000001$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_exceptions/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_exceptions/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_exceptions/test.S (revision 373) @@ -0,0 +1,60 @@ +/* + * Check that the exeption vector is called on exception. + * We use a load to an unaligned address to trigger the exception. + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + li a0, 1 + lw a0, 0(a0) /* fault */ + + /* we shouldn't get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + li a0, '\n' + sb a0, 0(k0) + + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_fpe_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpe_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpe_delayslot/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_fpe_delayslot/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpe_delayslot/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpe_delayslot/mtty0 (revision 373) @@ -0,0 +1,2 @@ +start +0x00000000 0x00000000 Index: /trunk/softs/tests_cc_vcache/test_fpe_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpe_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpe_delayslot/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_fpe_delayslot/run.out =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpe_delayslot/run.out (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpe_delayslot/run.out (revision 373) @@ -0,0 +1,23 @@ + + SystemC 2.2.0 --- Apr 14 2011 18:52:40 + Copyright (c) 1996-2006 by all Contributors + ALL RIGHTS RESERVED +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + + + + +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + +Loading at 0xbfc00000 size 262144: .text .reginfo +Loading at 0 size 33554432: .data +start +0x00000000 0x00000000 +vci_exit terminate simulation, status 0d0 +couldn't find string 1 in output - mtty not working ? Index: /trunk/softs/tests_cc_vcache/test_fpe_delayslot/subr.o.txt =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpe_delayslot/subr.o.txt (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpe_delayslot/subr.o.txt (revision 373) @@ -0,0 +1,49 @@ + +subr.o: file format elf32-littlemips + + +Disassembly of section .text: + +00000000 : + 0: 00804021 move t0,a0 + 4: 81090000 lb t1,0(t0) + 8: 11200005 beqz t1,20 + c: 00000000 nop + 10: a3490000 sb t1,0(k0) + 14: 25080001 addiu t0,t0,1 + 18: 08000001 j 4 + 1c: 00000000 nop + +00000020 : + 20: 03e00008 jr ra + 24: 00000000 nop + +00000028 : + 28: 00804021 move t0,a0 + 2c: 24090030 li t1,48 + 30: a3490000 sb t1,0(k0) + 34: 24090078 li t1,120 + 38: a3490000 sb t1,0(k0) + 3c: 24090008 li t1,8 + 40: 3c0af000 lui t2,0xf000 + 44: 010a5024 and t2,t0,t2 + 48: 000a5702 srl t2,t2,0x1c + 4c: 294b000a slti t3,t2,10 + 50: 11600004 beqz t3,64 + 54: 00000000 nop + 58: 214a0030 addi t2,t2,48 + 5c: 0800001a j 68 + 60: 00000000 nop + 64: 214a0037 addi t2,t2,55 + 68: a34a0000 sb t2,0(k0) + 6c: 2129ffff addi t1,t1,-1 + 70: 1d20fff3 bgtz t1,40 + 74: 00084100 sll t0,t0,0x4 + 78: 03e00008 jr ra + 7c: 00000000 nop + +Disassembly of section .reginfo: + +00000000 <.reginfo>: + 0: 84000f10 lh zero,3856(zero) + ... Index: /trunk/softs/tests_cc_vcache/test_fpe_delayslot/temp =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpe_delayslot/temp (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpe_delayslot/temp (revision 373) @@ -0,0 +1,8775 @@ +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + + + + +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + +Loading at 0xbfc00000 size 262144: .text .reginfo +Loading at 0 size 33554432: .data +****************** cycle 1 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 2 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 3 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 4 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 5 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 6 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 7 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 8 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 9 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 10 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 11 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 12 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 13 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1be000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 14 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 15 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 16 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x037bdfff0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 17 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 18 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840155 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 19 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 20 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 21 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c042040 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 22 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040846000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 23 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 24 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 25 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4820000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 26 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 27 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 28 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4800000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 29 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 30 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 31 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 32 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 33 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 34 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 35 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 36 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 37 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 38 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 39 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 40 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00380 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 41 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 42 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 43 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 44 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 45 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 46 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 47 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 48 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 49 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 50 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 51 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 52 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 53 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 54 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x081090000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 55 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011200005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 56 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 57 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 58 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x025080001 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 59 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000e5 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 60 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 61 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 62 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 63 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 64 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 65 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 66 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 67 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 68 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 69 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 70 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Select a slot: / way = 0 / set = 0x5 / valid = 0 / line = 0x000000005 +****************** cycle 71 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00140 wdata = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 72 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 73 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 74 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 75 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 76 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 77 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 78 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0 +****************** cycle 79 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +****************** cycle 80 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000206573 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +****************** cycle 81 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0 + Write one word: address = 0x0bfc00154 / data = 0x75616320 / way = 0 / set = 0x5 / word = 0 +****************** cycle 82 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0x206573 / way = 0 / set = 0x5 / word = 0x1 +****************** cycle 83 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061622000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0x20637020 / way = 0 / set = 0x5 / word = 0x2 +****************** cycle 84 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020617664 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0x61622000 / way = 0 / set = 0x5 / word = 0x3 +****************** cycle 85 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061747300 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0x20617664 / way = 0 / set = 0x5 / word = 0x4 +****************** cycle 86 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a7472 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0x61747300 / way = 0 / set = 0x5 / word = 0x5 +****************** cycle 87 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x06d727375 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0xa7472 / way = 0 / set = 0x5 / word = 0x6 +****************** cycle 88 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00a65646f | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0x6d727375 / way = 0 / set = 0x5 / word = 0x7 +****************** cycle 89 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0xa65646f / way = 0 / set = 0x5 / word = 0x8 +****************** cycle 90 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0x9 +****************** cycle 91 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xa +****************** cycle 92 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xb +****************** cycle 93 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xc +****************** cycle 94 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xd +****************** cycle 95 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1 + Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xe +****************** cycle 96 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xf +****************** cycle 97 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 98 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 99 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 100 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 101 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 102 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 103 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 104 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000073 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 105 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 106 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 107 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 108 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 109 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 110 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 111 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 112 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 113 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 114 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 115 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000074 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 + HIT in dcache +****************** cycle 116 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 117 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 118 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 119 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 120 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 121 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 122 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 123 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 124 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 125 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 126 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000061 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 127 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 128 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 129 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 130 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 131 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 132 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 133 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 134 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 135 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 136 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 137 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000072 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 138 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 139 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 140 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 141 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 142 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 143 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 144 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 145 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 146 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 147 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 148 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000074 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 149 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 150 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 151 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 152 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 153 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 154 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 155 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 156 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 157 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 158 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 159 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x00000000a srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 160 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 161 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 162 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 163 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 164 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 165 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 166 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 167 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 168 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 169 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 170 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Select a slot: / way = 0 / set = 0 / valid = 0 / line = 0x000000000 +****************** cycle 171 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x000000000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 172 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 173 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 174 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d CMD VCI : RD @ = 0x000000000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 eop = 0x1 ack = 0 + Receive command from srcid 0x0000 / for address 0x000000000 +****************** cycle 175 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_READ | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d CMD VCI : RD @ = 0x000000000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 eop = 0x1 ack = 0x1 + Push into read_fifo: address = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 +****************** cycle 176 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Read request: srcid = 0 / address = 0 / nwords = 16 +****************** cycle 177 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_DIR_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Accessing directory: address = 0 / hit = 0 / count = 0 / is_cnt = 0 +****************** cycle 178 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Check TRT: hit_read = 0 / hit_write = 0 / full = 0 +****************** cycle 179 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_SET | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Write in Transaction Table: address = 0 / srcid = 0 +****************** cycle 180 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_REQ | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Request GET transaction for address 0 +****************** cycle 181 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 182 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Send a get request to xram +****************** cycle 183 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Response from XRAM to a get transaction +****************** cycle 184 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE +****************** cycle 185 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 0 / data = 0xdead +****************** cycle 186 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 1 / data = 0xbeef +****************** cycle 187 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 2 / data = 0x41200000 +****************** cycle 188 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 3 / data = 0 +****************** cycle 189 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 4 / data = 0 +****************** cycle 190 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 5 / data = 0 +****************** cycle 191 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 6 / data = 0 +****************** cycle 192 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 7 / data = 0 +****************** cycle 193 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 8 / data = 0 +****************** cycle 194 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 9 / data = 0 +****************** cycle 195 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 10 / data = 0 +****************** cycle 196 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 11 / data = 0 +****************** cycle 197 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 12 / data = 0 +****************** cycle 198 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 13 / data = 0 +****************** cycle 199 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 14 / data = 0 +****************** cycle 200 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 15 / data = 0 +****************** cycle 201 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Available cache line in TRT: index = 0 +****************** cycle 202 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK +****************** cycle 203 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK + Get access to directory +****************** cycle 204 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY +****************** cycle 205 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY + Select a slot: way = 0 / set = 0 / inval_required = 0 +****************** cycle 206 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK +****************** cycle 207 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK + Get acces to UPT +****************** cycle 208 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT + Directory update: way = 0 / set = 0 / count = 1 / is_cnt = 0 +****************** cycle 209 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP + Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0 / nwords = 16 +****************** cycle 210 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 211 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xdead / cpt = 0 +****************** cycle 212 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xbeef / cpt = 0x1 +****************** cycle 213 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0x41200000 / cpt = 0x2 +****************** cycle 214 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x3 +****************** cycle 215 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x4 +****************** cycle 216 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x5 +****************** cycle 217 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0xdead / way = 0 / set = 0 / word = 0 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x6 +****************** cycle 218 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0xbeef / way = 0 / set = 0 / word = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x7 +****************** cycle 219 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0x41200000 / way = 0 / set = 0 / word = 0x2 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x8 +****************** cycle 220 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x3 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x9 +****************** cycle 221 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x4 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xa +****************** cycle 222 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x5 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xb +****************** cycle 223 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x6 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xc +****************** cycle 224 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x7 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xd +****************** cycle 225 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x8 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xe +****************** cycle 226 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x9 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xf +****************** cycle 227 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xa +****************** cycle 228 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xb +****************** cycle 229 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xc +****************** cycle 230 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xd +****************** cycle 231 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xe +****************** cycle 232 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xf +****************** cycle 233 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 234 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 235 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 236 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 237 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 238 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00040 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 239 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 240 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 241 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 242 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 243 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 244 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 245 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00016 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 246 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00016 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 247 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046020003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 248 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 249 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 250 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 251 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00014 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 252 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 253 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000402021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 254 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 255 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 256 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 257 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 258 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000602021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 259 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 260 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 261 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02404000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 262 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 263 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 264 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 265 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 266 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 267 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 268 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 269 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 270 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 271 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 272 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 273 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc003c0 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 274 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 275 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 276 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 277 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 278 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 279 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 280 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 281 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 282 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090078 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 283 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 284 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 285 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 286 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c0af000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 287 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0010a5024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 288 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a5702 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 289 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0294b000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 290 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011600004 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 291 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 292 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 293 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000fe | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 294 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 295 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0037 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 296 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a34a0000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 297 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02129ffff | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 298 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 299 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 300 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 301 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 302 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 303 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 304 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 305 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 306 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 307 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 308 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 309 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 310 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 311 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 312 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 313 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 314 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000078 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 315 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 316 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00400 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 317 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 318 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 319 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 320 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 321 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 322 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 323 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 324 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 325 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 326 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000084100 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 327 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 328 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 329 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 330 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0bc00009c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 331 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 332 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 333 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 334 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 335 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 336 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 337 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 338 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 339 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 340 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 341 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 342 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 343 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 344 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 345 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 346 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 347 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 348 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 349 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 350 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 351 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 352 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 353 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 354 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 355 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 356 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 357 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 358 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 359 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 360 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 361 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 362 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 363 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 364 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 365 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 366 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 367 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 368 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 369 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 370 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 371 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 372 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 373 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 374 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 375 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 376 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 377 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 378 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 379 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 380 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 381 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 382 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 383 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 384 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 385 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 386 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 387 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 388 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 389 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 390 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 391 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 392 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 393 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 394 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 395 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 396 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 397 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 398 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 399 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 400 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 401 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 402 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 403 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 404 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 405 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 406 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 407 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 408 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 409 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 410 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 411 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 412 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 413 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 414 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 415 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 416 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 417 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 418 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 419 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 420 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 421 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 422 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 423 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 424 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 425 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 426 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 427 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 428 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 429 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 430 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 431 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 432 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 433 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 434 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 435 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 436 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 437 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 438 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 439 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 440 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 441 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 442 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 443 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 444 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 445 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 446 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 447 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000020 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 448 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 449 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 450 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 451 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 452 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 453 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 454 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 455 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 456 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 457 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 458 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 459 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 460 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 461 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 462 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 463 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 464 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 465 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 466 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 467 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 468 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 469 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000078 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 470 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 471 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 472 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 473 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 474 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 475 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 476 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 477 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 478 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 479 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 480 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 481 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 482 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 483 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 484 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 485 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 486 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 487 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 488 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 489 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 490 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 491 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 492 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 493 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 494 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 495 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 496 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 497 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 498 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 499 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 500 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 501 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 502 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 503 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 504 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 505 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 506 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 507 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 508 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 509 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 510 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 511 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 512 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 513 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 514 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 515 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 516 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 517 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 518 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 519 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 520 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 521 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 522 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 523 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 524 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 525 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 526 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 527 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 528 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 529 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 530 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 531 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 532 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 533 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 534 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 535 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 536 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 537 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 538 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 539 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 540 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 541 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 542 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 543 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 544 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 545 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 546 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 547 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 548 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 549 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 550 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 551 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 552 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 553 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 554 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 555 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 556 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 557 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 558 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 559 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 560 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 561 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 562 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 563 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 564 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 565 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 566 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 567 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00080 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 568 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 569 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 570 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 571 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 572 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x00000000a srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 573 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 574 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 575 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 576 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 577 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00022 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 578 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00022 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 579 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 580 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 581 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840138 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 582 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 583 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 584 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040046000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 585 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 586 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 587 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 588 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840140 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 589 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 590 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 591 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040046800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 592 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 593 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 594 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 595 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 596 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 597 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 598 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0e0000000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 599 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 600 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 601 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE + Data TLB + set way V L R C W X U G D B Z TAG PPN NLINE + Instruction TLB + set way V L R C W X U G D B Z TAG PPN NLINE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +vci_exit terminate simulation, status 0x000000000 Index: /trunk/softs/tests_cc_vcache/test_fpe_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpe_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpe_delayslot/test.S (revision 373) @@ -0,0 +1,92 @@ +/* + * trap test: check that a trap in a delay slot is + * properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV), enable cop1 */ + lui a0, 0x2040; + mtc0 a0, COP0_STATUS + + la a0, div1 + lwc1 $f2, 0(a0) + la a0, div2 + lwc1 $f0, 0(a0) + j exit + div.s $f0, $f0, $f2 + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 +div1: + .float 10.0 + .globl div2 +div2: + .float 0.0 Index: /trunk/softs/tests_cc_vcache/test_fpe_delayslot/test.elf.txt =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpe_delayslot/test.elf.txt (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpe_delayslot/test.elf.txt (revision 373) @@ -0,0 +1,185 @@ + +test.elf: file format elf32-littlemips + + +Disassembly of section .text: + +bfc00000 <_start>: +bfc00000: 3c1ad020 lui k0,0xd020 +bfc00004: 3c1be000 lui k1,0xe000 +bfc00008: 3c1d003f lui sp,0x3f +bfc0000c: 37bdfff0 ori sp,sp,0xfff0 +bfc00010: 3c04bfc0 lui a0,0xbfc0 +bfc00014: 24840155 addiu a0,a0,341 +bfc00018: 0ff000e4 jal bfc00390 +bfc0001c: 00000000 nop +bfc00020: 3c042040 lui a0,0x2040 +bfc00024: 40846000 mtc0 a0,c0_status +bfc00028: 3c040000 lui a0,0x0 +bfc0002c: 24840008 addiu a0,a0,8 +bfc00030: c4820000 lwc1 $f2,0(a0) +bfc00034: 3c040000 lui a0,0x0 +bfc00038: 2484000c addiu a0,a0,12 +bfc0003c: c4800000 lwc1 $f0,0(a0) +bfc00040: 0bf00016 j bfc00058 +bfc00044: 46020003 div.s $f0,$f0,$f2 +bfc00048: 24040002 li a0,2 +bfc0004c: af640000 sw a0,0(k1) +bfc00050: 0bf00014 j bfc00050 <_start+0x50> +bfc00054: 00000000 nop + +bfc00058 : +bfc00058: 00402021 move a0,v0 +bfc0005c: 0ff000ee jal bfc003b8 +bfc00060: 00000000 nop +bfc00064: 24040020 li a0,32 +bfc00068: a3440000 sb a0,0(k0) +bfc0006c: 00602021 move a0,v1 +bfc00070: 0ff000ee jal bfc003b8 +bfc00074: 00000000 nop +bfc00078: 2404000a li a0,10 +bfc0007c: a3440000 sb a0,0(k0) +bfc00080: 24040000 li a0,0 +bfc00084: af640000 sw a0,0(k1) +bfc00088: 0bf00022 j bfc00088 +bfc0008c: 00000000 nop + +bfc00090 : +bfc00090: 3c04bfc0 lui a0,0xbfc0 +bfc00094: 24840138 addiu a0,a0,312 +bfc00098: 0ff000e4 jal bfc00390 +bfc0009c: 00000000 nop +bfc000a0: 40046000 mfc0 a0,c0_status +bfc000a4: 0ff000ee jal bfc003b8 +bfc000a8: 00000000 nop +bfc000ac: 3c04bfc0 lui a0,0xbfc0 +bfc000b0: 24840140 addiu a0,a0,320 +bfc000b4: 0ff000e4 jal bfc00390 +bfc000b8: 00000000 nop +bfc000bc: 40046800 mfc0 a0,c0_cause +bfc000c0: 0ff000ee jal bfc003b8 +bfc000c4: 00000000 nop +bfc000c8: 3c04bfc0 lui a0,0xbfc0 +bfc000cc: 24840148 addiu a0,a0,328 +bfc000d0: 0ff000e4 jal bfc00390 +bfc000d4: 00000000 nop +bfc000d8: 40047000 mfc0 a0,c0_epc +bfc000dc: 0ff000ee jal bfc003b8 +bfc000e0: 00000000 nop +bfc000e4: 3c04bfc0 lui a0,0xbfc0 +bfc000e8: 2484014d addiu a0,a0,333 +bfc000ec: 0ff000e4 jal bfc00390 +bfc000f0: 00000000 nop +bfc000f4: 40044000 mfc0 a0,c0_badvaddr +bfc000f8: 0ff000ee jal bfc003b8 +bfc000fc: 00000000 nop +bfc00100: 2404000a li a0,10 +bfc00104: a3440000 sb a0,0(k0) +bfc00108: 3c04bfc0 lui a0,0xbfc0 +bfc0010c: 24840058 addiu a0,a0,88 +bfc00110: 40847000 mtc0 a0,c0_epc +bfc00114: 3402dead li v0,0xdead +bfc00118: 3403beef li v1,0xbeef +bfc0011c: 24070001 li a3,1 +bfc00120: 42000018 eret +bfc00124: 00000000 nop +bfc00128: 24040001 li a0,1 +bfc0012c: af640000 sw a0,0(k1) +bfc00130: 0bf0004c j bfc00130 +bfc00134: 00000000 nop + +bfc00138 : +bfc00138: 74617473 jalx b185d1cc <_stack+0xb145d1dc> +bfc0013c: 00207375 0x207375 + +bfc00140 : +bfc00140: 75616320 jalx b5858c80 <_stack+0xb5458c90> +bfc00144: 00206573 tltu at,zero,0x195 + +bfc00148 : +bfc00148: 20637020 addi v1,v1,28704 + ... + +bfc0014d : +bfc0014d: 6220 sw ra,128(sp) +bfc0014f: 6461 restore 8,ra,s0 +bfc00151: 6176 btnez bfc0023f +bfc00153: 0020 addiu s0,sp,128 + +bfc00155 : +bfc00155: 7473 cmpi a0,115 +bfc00157: 7261 cmpi v0,97 +bfc00159: 0a74 la v0,bfc00328 + ... + +bfc0015c : +bfc0015c: 6d727375 0x6d727375 +bfc00160: 0a65646f j b99591bc <_stack+0xb95591cc> +bfc00164: 00000000 nop + ... + +bfc00380 : +bfc00380: 0bf00024 j bfc00090 +bfc00384: 00000000 nop + ... + +bfc00390 : +bfc00390: 00804021 move t0,a0 +bfc00394: 81090000 lb t1,0(t0) +bfc00398: 11200005 beqz t1,bfc003b0 +bfc0039c: 00000000 nop +bfc003a0: a3490000 sb t1,0(k0) +bfc003a4: 25080001 addiu t0,t0,1 +bfc003a8: 0bf000e5 j bfc00394 +bfc003ac: 00000000 nop + +bfc003b0 : +bfc003b0: 03e00008 jr ra +bfc003b4: 00000000 nop + +bfc003b8 : +bfc003b8: 00804021 move t0,a0 +bfc003bc: 24090030 li t1,48 +bfc003c0: a3490000 sb t1,0(k0) +bfc003c4: 24090078 li t1,120 +bfc003c8: a3490000 sb t1,0(k0) +bfc003cc: 24090008 li t1,8 +bfc003d0: 3c0af000 lui t2,0xf000 +bfc003d4: 010a5024 and t2,t0,t2 +bfc003d8: 000a5702 srl t2,t2,0x1c +bfc003dc: 294b000a slti t3,t2,10 +bfc003e0: 11600004 beqz t3,bfc003f4 +bfc003e4: 00000000 nop +bfc003e8: 214a0030 addi t2,t2,48 +bfc003ec: 0bf000fe j bfc003f8 +bfc003f0: 00000000 nop +bfc003f4: 214a0037 addi t2,t2,55 +bfc003f8: a34a0000 sb t2,0(k0) +bfc003fc: 2129ffff addi t1,t1,-1 +bfc00400: 1d20fff3 bgtz t1,bfc003d0 +bfc00404: 00084100 sll t0,t0,0x4 +bfc00408: 03e00008 jr ra +bfc0040c: 00000000 nop + +Disassembly of section .reginfo: + +bfc00410 <.reginfo>: +bfc00410: bc00009c cache 0x0,156(zero) +bfc00414: 00000000 nop +bfc00418: 00000005 0x5 + ... +bfc00424: 00000010 mfhi zero + +Disassembly of section .data: + +00000000 : + 0: 0000dead 0xdead + +00000004 : + 4: 0000beef 0xbeef + +00000008 : + 8: 41200000 0x41200000 + +0000000c : + c: 00000000 nop Index: /trunk/softs/tests_cc_vcache/test_fpediv/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpediv/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpediv/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_fpediv/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpediv/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpediv/mtty0 (revision 373) @@ -0,0 +1,2 @@ +start +0x00008F80 Index: /trunk/softs/tests_cc_vcache/test_fpediv/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpediv/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpediv/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000038 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_fpediv/run.out =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpediv/run.out (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpediv/run.out (revision 373) @@ -0,0 +1,22 @@ + + SystemC 2.2.0 --- Apr 14 2011 18:52:40 + Copyright (c) 1996-2006 by all Contributors + ALL RIGHTS RESERVED +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + + + + +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + +Loading at 0xbfc00000 size 262144: .text .reginfo +Loading at 0 size 33554432: .data +start +0x00008F80 +vci_exit terminate simulation, status 0d2 Index: /trunk/softs/tests_cc_vcache/test_fpediv/subr.o.txt =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpediv/subr.o.txt (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpediv/subr.o.txt (revision 373) @@ -0,0 +1,49 @@ + +subr.o: file format elf32-littlemips + + +Disassembly of section .text: + +00000000 : + 0: 00804021 move t0,a0 + 4: 81090000 lb t1,0(t0) + 8: 11200005 beqz t1,20 + c: 00000000 nop + 10: a3490000 sb t1,0(k0) + 14: 25080001 addiu t0,t0,1 + 18: 08000001 j 4 + 1c: 00000000 nop + +00000020 : + 20: 03e00008 jr ra + 24: 00000000 nop + +00000028 : + 28: 00804021 move t0,a0 + 2c: 24090030 li t1,48 + 30: a3490000 sb t1,0(k0) + 34: 24090078 li t1,120 + 38: a3490000 sb t1,0(k0) + 3c: 24090008 li t1,8 + 40: 3c0af000 lui t2,0xf000 + 44: 010a5024 and t2,t0,t2 + 48: 000a5702 srl t2,t2,0x1c + 4c: 294b000a slti t3,t2,10 + 50: 11600004 beqz t3,64 + 54: 00000000 nop + 58: 214a0030 addi t2,t2,48 + 5c: 0800001a j 68 + 60: 00000000 nop + 64: 214a0037 addi t2,t2,55 + 68: a34a0000 sb t2,0(k0) + 6c: 2129ffff addi t1,t1,-1 + 70: 1d20fff3 bgtz t1,40 + 74: 00084100 sll t0,t0,0x4 + 78: 03e00008 jr ra + 7c: 00000000 nop + +Disassembly of section .reginfo: + +00000000 <.reginfo>: + 0: 84000f10 lh zero,3856(zero) + ... Index: /trunk/softs/tests_cc_vcache/test_fpediv/temp =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpediv/temp (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpediv/temp (revision 373) @@ -0,0 +1,4909 @@ +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + + + + +Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000 + + + + +Loading at 0xbfc00000 size 262144: .text .reginfo +Loading at 0 size 33554432: .data +****************** cycle 1 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 2 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 3 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 4 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 5 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 6 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 7 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 8 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 9 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 10 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 11 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 12 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 13 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1be000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 14 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 15 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 16 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x037bdfff0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 17 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 18 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840115 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 19 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 20 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 21 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c042040 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 22 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040846000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 23 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040f80 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 24 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x044c4f800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 25 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 26 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 27 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4820000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 28 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 29 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 30 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 31 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 32 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 33 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 34 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 35 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 36 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 37 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 38 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 39 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 40 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00380 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 41 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 42 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 43 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 44 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 45 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 46 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 47 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 48 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 49 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 50 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 51 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 52 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 53 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 54 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x081090000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 55 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011200005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 56 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 57 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 58 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x025080001 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 59 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000e5 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 60 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 61 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 62 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 63 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 64 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 65 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 66 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 67 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 68 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 69 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 70 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Select a slot: / way = 0 / set = 0x4 / valid = 0 / line = 0x000000004 +****************** cycle 71 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00100 wdata = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 72 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 73 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 74 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 75 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 76 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 77 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 78 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0 +****************** cycle 79 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +****************** cycle 80 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000206573 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +****************** cycle 81 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0 + Write one word: address = 0x0bfc00114 / data = 0x75616320 / way = 0 / set = 0x4 / word = 0 +****************** cycle 82 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0x206573 / way = 0 / set = 0x4 / word = 0x1 +****************** cycle 83 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061622000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0x20637020 / way = 0 / set = 0x4 / word = 0x2 +****************** cycle 84 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020617664 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0x61622000 / way = 0 / set = 0x4 / word = 0x3 +****************** cycle 85 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061747300 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0x20617664 / way = 0 / set = 0x4 / word = 0x4 +****************** cycle 86 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a7472 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0x61747300 / way = 0 / set = 0x4 / word = 0x5 +****************** cycle 87 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x06d727375 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0xa7472 / way = 0 / set = 0x4 / word = 0x6 +****************** cycle 88 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00a65646f | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0x6d727375 / way = 0 / set = 0x4 / word = 0x7 +****************** cycle 89 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0xa65646f / way = 0 / set = 0x4 / word = 0x8 +****************** cycle 90 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0x9 +****************** cycle 91 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xa +****************** cycle 92 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xb +****************** cycle 93 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xc +****************** cycle 94 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xd +****************** cycle 95 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1 + Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xe +****************** cycle 96 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xf +****************** cycle 97 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 98 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 99 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 100 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 101 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 102 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 103 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 104 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000073 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 105 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 106 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 107 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 108 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 109 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 110 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 111 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 112 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 113 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 114 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 115 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000074 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 + HIT in dcache +****************** cycle 116 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 117 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 118 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 119 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 120 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 121 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 122 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 123 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 124 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 125 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 126 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000061 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 127 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 128 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 129 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 130 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 131 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 132 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 133 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 134 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 135 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 136 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 137 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000072 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 138 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 139 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 140 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 141 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 142 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 143 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 144 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 145 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 146 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 147 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 148 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000074 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 149 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 150 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 151 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 152 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 153 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 154 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 155 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 156 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 157 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 158 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 159 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x00000000a srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 160 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 161 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 162 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 163 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 164 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 165 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 166 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 167 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 168 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 169 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 170 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 171 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 172 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Select a slot: / way = 0 / set = 0 / valid = 0 / line = 0x000000000 +****************** cycle 173 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x000000000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 174 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 175 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 176 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d CMD VCI : RD @ = 0x000000000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 eop = 0x1 ack = 0 + Receive command from srcid 0x0000 / for address 0x000000000 +****************** cycle 177 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_READ | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d CMD VCI : RD @ = 0x000000000 wdata = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 eop = 0x1 ack = 0x1 + Push into read_fifo: address = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040 +****************** cycle 178 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Read request: srcid = 0 / address = 0 / nwords = 16 +****************** cycle 179 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_DIR_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Accessing directory: address = 0 / hit = 0 / count = 0 / is_cnt = 0 +****************** cycle 180 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Check TRT: hit_read = 0 / hit_write = 0 / full = 0 +****************** cycle 181 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_SET | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Write in Transaction Table: address = 0 / srcid = 0 +****************** cycle 182 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_REQ | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Request GET transaction for address 0 +****************** cycle 183 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 184 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Send a get request to xram +****************** cycle 185 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Response from XRAM to a get transaction +****************** cycle 186 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE +****************** cycle 187 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 0 / data = 0xdead +****************** cycle 188 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 1 / data = 0xbeef +****************** cycle 189 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 2 / data = 0x41200000 +****************** cycle 190 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 3 / data = 0 +****************** cycle 191 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 4 / data = 0 +****************** cycle 192 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 5 / data = 0 +****************** cycle 193 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 6 / data = 0 +****************** cycle 194 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 7 / data = 0 +****************** cycle 195 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 8 / data = 0 +****************** cycle 196 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 9 / data = 0 +****************** cycle 197 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 10 / data = 0 +****************** cycle 198 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 11 / data = 0 +****************** cycle 199 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 12 / data = 0 +****************** cycle 200 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 13 / data = 0 +****************** cycle 201 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 14 / data = 0 +****************** cycle 202 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE + Writing a word in TRT : index = 0 / word = 15 / data = 0 +****************** cycle 203 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Available cache line in TRT: index = 0 +****************** cycle 204 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK +****************** cycle 205 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK + Get access to directory +****************** cycle 206 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY +****************** cycle 207 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY + Select a slot: way = 0 / set = 0 / inval_required = 0 +****************** cycle 208 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK +****************** cycle 209 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK + Get acces to UPT +****************** cycle 210 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT + Directory update: way = 0 / set = 0 / count = 1 / is_cnt = 0 +****************** cycle 211 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP + Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0 / nwords = 16 +****************** cycle 212 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 213 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xdead / cpt = 0 +****************** cycle 214 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xbeef / cpt = 0x1 +****************** cycle 215 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0x41200000 / cpt = 0x2 +****************** cycle 216 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x3 +****************** cycle 217 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x4 +****************** cycle 218 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x5 +****************** cycle 219 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0xdead / way = 0 / set = 0 / word = 0 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x6 +****************** cycle 220 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0xbeef / way = 0 / set = 0 / word = 0x1 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x7 +****************** cycle 221 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0x41200000 / way = 0 / set = 0 / word = 0x2 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x8 +****************** cycle 222 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x3 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x9 +****************** cycle 223 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x4 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xa +****************** cycle 224 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x5 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xb +****************** cycle 225 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x6 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xc +****************** cycle 226 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x7 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xd +****************** cycle 227 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x8 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xe +****************** cycle 228 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 +memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x9 + Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xf +****************** cycle 229 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xa +****************** cycle 230 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xb +****************** cycle 231 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xc +****************** cycle 232 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xd +****************** cycle 233 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1 + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xe +****************** cycle 234 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xf +****************** cycle 235 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 236 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 237 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 238 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00040 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 239 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 240 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 241 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 242 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 243 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 244 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 245 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 246 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 247 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4800000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 248 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046001003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 249 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046001003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 250 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x04444f800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 251 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 252 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 253 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02404000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 254 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 255 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 256 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 257 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 258 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 259 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 260 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0248400f8 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 261 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 262 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 263 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 264 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 265 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 266 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE + HIT in dcache +****************** cycle 267 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 268 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 269 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 270 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 271 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 272 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 273 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 274 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc003c0 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 275 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 276 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 277 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 278 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 279 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 280 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 281 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 282 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 283 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090078 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 284 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 285 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 286 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 287 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c0af000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 288 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0010a5024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 289 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a5702 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 290 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0294b000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 291 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011600004 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 292 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 293 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 294 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000fe | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 295 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 296 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0037 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 297 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a34a0000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 298 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02129ffff | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 299 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 300 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 301 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 302 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 303 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 304 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 305 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 306 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 307 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 308 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 309 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 310 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 311 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 312 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 313 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 314 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 315 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000078 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 316 ************************************************ +PROC proc + + + + + ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 317 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : RD @ = 0x0bfc00400 wdata = 0x000000000 srcid = 0x0000 trdid = 0x03 plen = 0x040 eop = 0x1 ack = 0x1 +****************** cycle 318 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 319 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 320 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 321 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 322 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 323 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 324 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 325 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 326 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 327 ************************************************ +PROC proc + + + + + ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000084100 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 328 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0 +****************** cycle 329 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 330 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 331 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0bc000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 332 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 333 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 334 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 335 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 336 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 337 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 338 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 339 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 340 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 341 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1 +****************** cycle 342 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1 +****************** cycle 343 ************************************************ +PROC proc + + + + + ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 344 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 345 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 346 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 347 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 348 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 349 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 350 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 351 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 352 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 353 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 354 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 355 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 356 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 357 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 358 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 359 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 360 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 361 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 362 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 363 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 364 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 365 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 366 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 367 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 368 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 369 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 370 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 371 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 372 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 373 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 374 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 375 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 376 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 377 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 378 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 379 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 380 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 381 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 382 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 383 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 384 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 385 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 386 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 387 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 388 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 389 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 390 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 391 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 392 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 393 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 394 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 395 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 396 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 397 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 398 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000038 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 399 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 400 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 401 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 402 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 403 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 404 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 405 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 406 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 407 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 408 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 409 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000046 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 410 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 411 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 412 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 413 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 414 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 415 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 416 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 417 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 418 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 419 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 420 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 421 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 422 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000038 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 423 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 424 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 425 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 426 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 427 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 428 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 429 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 430 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 431 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 432 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 433 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 434 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 435 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x000000030 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 436 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 437 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 438 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 439 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 440 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 441 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 442 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 443 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 444 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 445 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 446 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0d0200000 wdata = 0x00000000a srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 447 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 448 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 449 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 450 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 451 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 452 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 453 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0 +****************** cycle 454 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1 +****************** cycle 455 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 456 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 457 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +proc_ini_d CMD VCI : WR @ = 0x0e0000000 wdata = 0x000000002 srcid = 0x0000 trdid = 0x08 plen = 0x004 eop = 0x1 ack = 0x1 +****************** cycle 458 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 459 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +****************** cycle 460 ************************************************ +PROC proc + + + + + ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE +MEMC memc + TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE + INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE +vci_exit terminate simulation, status 0x000000002 Index: /trunk/softs/tests_cc_vcache/test_fpediv/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpediv/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpediv/test.S (revision 373) @@ -0,0 +1,81 @@ +/* + * trap test: check that a we can generate a trap from FPE instruction + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV), enable cop1 */ + lui a0, 0x2040; + mtc0 a0, COP0_STATUS + /* enable COP1 exceptions */ + li a0, 0x0f80 + ctc1 a0, $31 +#if 0 + li a0, 0xf000 + ctc1 a0, $26 +#endif + la a0, div1 + lwc1 $f2, 0(a0) + la a0, div2 + lwc1 $f0, 0(a0) + div.s $f0, $f2, $f0 + cfc1 a0, $31 + PRINTX + PUTCHAR('\n') + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl div1 +div1: + .float 10.0 + .globl div2 +div2: + .float 0.0 Index: /trunk/softs/tests_cc_vcache/test_fpediv/test.elf.txt =================================================================== --- /trunk/softs/tests_cc_vcache/test_fpediv/test.elf.txt (revision 373) +++ /trunk/softs/tests_cc_vcache/test_fpediv/test.elf.txt (revision 373) @@ -0,0 +1,167 @@ + +test.elf: file format elf32-littlemips + + +Disassembly of section .text: + +bfc00000 <_start>: +bfc00000: 3c1ad020 lui k0,0xd020 +bfc00004: 3c1be000 lui k1,0xe000 +bfc00008: 3c1d003f lui sp,0x3f +bfc0000c: 37bdfff0 ori sp,sp,0xfff0 +bfc00010: 3c04bfc0 lui a0,0xbfc0 +bfc00014: 24840115 addiu a0,a0,277 +bfc00018: 0ff000e4 jal bfc00390 +bfc0001c: 00000000 nop +bfc00020: 3c042040 lui a0,0x2040 +bfc00024: 40846000 mtc0 a0,c0_status +bfc00028: 24040f80 li a0,3968 +bfc0002c: 44c4f800 ctc1 a0,$31 +bfc00030: 3c040000 lui a0,0x0 +bfc00034: 24840008 addiu a0,a0,8 +bfc00038: c4820000 lwc1 $f2,0(a0) +bfc0003c: 3c040000 lui a0,0x0 +bfc00040: 2484000c addiu a0,a0,12 +bfc00044: c4800000 lwc1 $f0,0(a0) +bfc00048: 46001003 div.s $f0,$f2,$f0 +bfc0004c: 4444f800 cfc1 a0,$31 +bfc00050: 0ff000ee jal bfc003b8 +bfc00054: 00000000 nop +bfc00058: 2404000a li a0,10 +bfc0005c: a3440000 sb a0,0(k0) +bfc00060: 24040002 li a0,2 +bfc00064: af640000 sw a0,0(k1) +bfc00068: 0bf0001a j bfc00068 <_start+0x68> +bfc0006c: 00000000 nop + +bfc00070 : +bfc00070: 3c04bfc0 lui a0,0xbfc0 +bfc00074: 248400f8 addiu a0,a0,248 +bfc00078: 0ff000e4 jal bfc00390 +bfc0007c: 00000000 nop +bfc00080: 40046000 mfc0 a0,c0_status +bfc00084: 0ff000ee jal bfc003b8 +bfc00088: 00000000 nop +bfc0008c: 3c04bfc0 lui a0,0xbfc0 +bfc00090: 24840100 addiu a0,a0,256 +bfc00094: 0ff000e4 jal bfc00390 +bfc00098: 00000000 nop +bfc0009c: 40046800 mfc0 a0,c0_cause +bfc000a0: 0ff000ee jal bfc003b8 +bfc000a4: 00000000 nop +bfc000a8: 3c04bfc0 lui a0,0xbfc0 +bfc000ac: 24840108 addiu a0,a0,264 +bfc000b0: 0ff000e4 jal bfc00390 +bfc000b4: 00000000 nop +bfc000b8: 40047000 mfc0 a0,c0_epc +bfc000bc: 0ff000ee jal bfc003b8 +bfc000c0: 00000000 nop +bfc000c4: 3c04bfc0 lui a0,0xbfc0 +bfc000c8: 2484010d addiu a0,a0,269 +bfc000cc: 0ff000e4 jal bfc00390 +bfc000d0: 00000000 nop +bfc000d4: 40044000 mfc0 a0,c0_badvaddr +bfc000d8: 0ff000ee jal bfc003b8 +bfc000dc: 00000000 nop +bfc000e0: 2404000a li a0,10 +bfc000e4: a3440000 sb a0,0(k0) +bfc000e8: 24040000 li a0,0 +bfc000ec: af640000 sw a0,0(k1) +bfc000f0: 0bf0003c j bfc000f0 +bfc000f4: 00000000 nop + +bfc000f8 : +bfc000f8: 74617473 jalx b185d1cc <_stack+0xb145d1dc> +bfc000fc: 00207375 0x207375 + +bfc00100 : +bfc00100: 75616320 jalx b5858c80 <_stack+0xb5458c90> +bfc00104: 00206573 tltu at,zero,0x195 + +bfc00108 : +bfc00108: 20637020 addi v1,v1,28704 + ... + +bfc0010d : +bfc0010d: 6220 sw ra,128(sp) +bfc0010f: 6461 restore 8,ra,s0 +bfc00111: 6176 btnez bfc001ff +bfc00113: 0020 addiu s0,sp,128 + +bfc00115 : +bfc00115: 7473 cmpi a0,115 +bfc00117: 7261 cmpi v0,97 +bfc00119: 0a74 la v0,bfc002e8 + ... + +bfc0011c : +bfc0011c: 6d727375 0x6d727375 +bfc00120: 0a65646f j b99591bc <_stack+0xb95591cc> +bfc00124: 00000000 nop + ... + +bfc00380 : +bfc00380: 0bf0001c j bfc00070 +bfc00384: 00000000 nop + ... + +bfc00390 : +bfc00390: 00804021 move t0,a0 +bfc00394: 81090000 lb t1,0(t0) +bfc00398: 11200005 beqz t1,bfc003b0 +bfc0039c: 00000000 nop +bfc003a0: a3490000 sb t1,0(k0) +bfc003a4: 25080001 addiu t0,t0,1 +bfc003a8: 0bf000e5 j bfc00394 +bfc003ac: 00000000 nop + +bfc003b0 : +bfc003b0: 03e00008 jr ra +bfc003b4: 00000000 nop + +bfc003b8 : +bfc003b8: 00804021 move t0,a0 +bfc003bc: 24090030 li t1,48 +bfc003c0: a3490000 sb t1,0(k0) +bfc003c4: 24090078 li t1,120 +bfc003c8: a3490000 sb t1,0(k0) +bfc003cc: 24090008 li t1,8 +bfc003d0: 3c0af000 lui t2,0xf000 +bfc003d4: 010a5024 and t2,t0,t2 +bfc003d8: 000a5702 srl t2,t2,0x1c +bfc003dc: 294b000a slti t3,t2,10 +bfc003e0: 11600004 beqz t3,bfc003f4 +bfc003e4: 00000000 nop +bfc003e8: 214a0030 addi t2,t2,48 +bfc003ec: 0bf000fe j bfc003f8 +bfc003f0: 00000000 nop +bfc003f4: 214a0037 addi t2,t2,55 +bfc003f8: a34a0000 sb t2,0(k0) +bfc003fc: 2129ffff addi t1,t1,-1 +bfc00400: 1d20fff3 bgtz t1,bfc003d0 +bfc00404: 00084100 sll t0,t0,0x4 +bfc00408: 03e00008 jr ra +bfc0040c: 00000000 nop + +Disassembly of section .reginfo: + +bfc00410 <.reginfo>: +bfc00410: bc000010 cache 0x0,16(zero) +bfc00414: 00000000 nop +bfc00418: 00000005 0x5 + ... +bfc00424: 00000010 mfhi zero + +Disassembly of section .data: + +00000000 : + 0: 0000dead 0xdead + +00000004 : + 4: 0000beef 0xbeef + +00000008 : + 8: 41200000 0x41200000 + +0000000c : + c: 00000000 nop Index: /trunk/softs/tests_cc_vcache/test_icache_inval_pa/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_icache_inval_pa/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_icache_inval_pa/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_icache_inval_pa/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_icache_inval_pa/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_icache_inval_pa/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_icache_inval_pa/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_icache_inval_pa/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_icache_inval_pa/mtty0 (revision 373) @@ -0,0 +1,4 @@ +start +mmu started before DMA 0x0000DEAD +mmu started after DMA 0x0000BEEF +mmu started after FLUSH 0x0000BEEF Index: /trunk/softs/tests_cc_vcache/test_icache_inval_pa/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_icache_inval_pa/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_icache_inval_pa/run (revision 373) @@ -0,0 +1,38 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started before DMA 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started after DMA 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started after FLUSH 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 3 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_icache_inval_pa/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_icache_inval_pa/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_icache_inval_pa/test.S (revision 373) @@ -0,0 +1,167 @@ +/* + * cache inval test: check that VC_ICACHE_INVAL_PA does the job + * on a cc_vcache, the cache invalidation/update should be done by hardware + * and VC_ICACHE_INVAL_PA should not be needed. + */ +#include +#include +#include + +#define TEST_ADDRESS 0x200000 + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_a) + #copy 'doload' to TEST_ADDRESS + la a1, DMA_BASE + la a0, doload + sw a0, DMA_SRC(a1) + la a0, TEST_ADDRESS + sw a0, DMA_DST(a1) + li a0, 8 + sw a0, DMA_LEN(a1) /* start DMA */ +loop1: + lw a0, DMA_LEN(a1) + bne a0, zero, loop1; + nop + sw zero, DMA_RESET(a1) + + la a0, TEST_ADDRESS + jalr a0 + nop + PRINTX + PUTCHAR('\n') + #copy 'doload2' to TEST_ADDRESS + la a1, DMA_BASE + la a0, doload2 + sw a0, DMA_SRC(a1) + la a0, TEST_ADDRESS + sw a0, DMA_DST(a1) + li a0, 8 + sw a0, DMA_LEN(a1) /* start DMA */ +loop2: + lw a0, DMA_LEN(a1) + bne a0, zero, loop2; + nop + sw zero, DMA_RESET(a1) + + PRINT(mmustr_b) + la a0, TEST_ADDRESS + jalr a0 + nop + PRINTX + PUTCHAR('\n') + + la a0, TEST_ADDRESS + mtc2 a0, VC_DATA_LO + mtc2 zero, VC_DATA_HI + mtc2 zero, VC_ICACHE_INVAL_PA + addi a0, a0, 4 + mtc2 a0, VC_DATA_LO + mtc2 zero, VC_DATA_HI + mtc2 zero, VC_ICACHE_INVAL_PA + nop + + PRINT(mmustr_c) + la a0, TEST_ADDRESS + jalr a0 + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(2) + nop + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started before DMA \0" +mmustr_b: .ascii "mmu started after DMA \0" +mmustr_c: .ascii "mmu started after FLUSH \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1_a + (TEST_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (TEST_ADDRESS >> 21) /* map PA 0x200000 at VA 0x200000, read-only/exec */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + (DMA_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */ Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval/test.S (revision 373) @@ -0,0 +1,158 @@ +/* + * itlb inval: a write to a PTE2 should invalidate the corresponding + * itlb and dtlb entries. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + /* cause a DTLB miss */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + /* cause a itlb miss */ + jal doload + nop + PRINTX + PUTCHAR(' ') + + la t0, pte2_a + la a0, (BOOT_ADDRESS+0x2000) >> 12 + sw a0, 12(t0) /* change PTE2 */ + sync +1: + ll a0, 8(t0) + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 8(t0) + beqz a0, 1b + nop + + /* now we should get the second values */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + jal doload + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +roval: .word MAGIC2 + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop +roval2: .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PTP and + * check that the ITLB has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval2/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval2/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval2/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval2/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval2/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval2/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval2/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval2/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval2/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval2/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval2/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval2/test.S (revision 373) @@ -0,0 +1,160 @@ +/* + * itlb inval: a write to a PTE2 should invalidate the corresponding + * itlb and dtlb entries. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + /* cause a DTLB miss */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + /* cause a itlb miss */ + jal doload + nop + PRINTX + PUTCHAR(' ') + + la t0, pte2_a + mtc2 t0, VC_DTLB_INVAL /* force tlb miss on write */ + la a0, (BOOT_ADDRESS+0x2000) >> 12 + sw a0, 12(t0) /* change PTE2 */ + sync +1: + ll a0, 8(t0) + mtc2 t0, VC_DTLB_INVAL /* force tlb miss on write */ + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 8(t0) + beqz a0, 1b + nop + + /* now we should get the second values */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + jal doload + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +roval: .word MAGIC2 + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop +roval2: .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PTP and + * check that the ITLB has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval3/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval3/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval3/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval3/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval3/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval3/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval3/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval3/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval3/mtty0 (revision 373) @@ -0,0 +1,2 @@ +start +mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval3/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval3/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval3/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval3/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval3/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval3/test.S (revision 373) @@ -0,0 +1,162 @@ +/* + * itlb inval: a write to a PTE2 should invalidate the corresponding + * itlb and dtlb entries. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + /* cause a DTLB miss */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + /* cause a itlb miss */ + jal doload + nop + PRINTX + PUTCHAR(' ') + + la t0, pte2_a + mtc2 t0, VC_DATA_L /* force dcache miss on write */ + mtc2 zero, VC_DATA_H + mtc2 zero, VC_DCACHE_INVAL_PA + la a0, (BOOT_ADDRESS+0x2000) >> 12 + sw a0, 12(t0) /* change PTE2 */ + sync +1: + ll a0, 8(t0) + mtc2 t0, VC_DTLB_INVAL /* force tlb miss on write */ + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 8(t0) + beqz a0, 1b + nop + + /* now we should get the second values */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + jal doload + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +roval: .word MAGIC2 + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop +roval2: .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PTP and + * check that the ITLB has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval4/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval4/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval4/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval4/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval4/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval4/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval4/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval4/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval4/mtty0 (revision 373) @@ -0,0 +1,2 @@ +start +mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval4/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval4/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval4/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_idtlb_inval4/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_inval4/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_inval4/test.S (revision 373) @@ -0,0 +1,166 @@ +/* + * itlb inval: a write to a PTD1 should invalidate the corresponding + * itlb and dtlb entries. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + /* cause a DTLB miss */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + /* cause a itlb miss */ + jal doload + nop + PRINTX + PUTCHAR(' ') + + la t0, pte1_ac +1: + ll a0, 0(t0) + la a0, (0x2000 >> 12) | PTE1_V | PTE1_T /* check real address of pet2_b */ + sc a0, 0(t0) /* change PTD1 */ + beqz a0, 1b + nop + + /* now we should get the second values */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + jal doload + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +roval: .word MAGIC2 + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop +roval2: .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PD and + * check that the TLBs has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 /* address of doload */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte2_b: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x2000) >> 12 /* address of doload2 */ + .org pte2_b + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 +pte1_ac: + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started ptpr_b 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started ptpr_a 0x0000BEEF 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_idtlb_ptprinval/test.S (revision 373) @@ -0,0 +1,173 @@ +/* + * itlb inval on PTPR write: check that no stale entry exists in the itlb + * after MMU context swicth + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_b + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_b) + la t0, rodata + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + jal doload + nop + PRINTX + PUTCHAR('\n') + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop +#if 0 /* works with this - this shows the old pte2 address is cached */ + la a0, pte2_a + lw a1, 12(a0) + la a0, pte2_b + sw a1, 12(a0) +#endif + PRINT(mmustr_a) + la t0, rodata + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + jal doload + nop + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started ptpr_a \0" +mmustr_b: .ascii "mmu started ptpr_b \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +rodata: + .word MAGIC2 + .org doload + 0x1000 /* in the second page, mapped by pte1_b */ + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(2) + nop + .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * two PD with two different PTE2 for code: check that itlb points to + * the right one by executing 2 different code at the same address + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b +pte2_b: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x2000) >> 12 + .org pte2_b + 4092 + .word 0 + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 + .globl pte1_b +pte1_b: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_b + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */ + .org pte1_b + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_b + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_b + 8188 + .word 0 Index: /trunk/softs/tests_cc_vcache/test_interrupt/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_interrupt/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400103 cause 0x00000100 pc 0xBFC00038 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_interrupt/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt/test.S (revision 373) @@ -0,0 +1,80 @@ +/* + * Check that we can take an interrupt, and return from it. + * We use a software-triggerted interrupt. + */ +#include +#include + + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enbale soft interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0101; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* generate an interrupt */ + mfc0 a0, COP0_CAUSE + nop + ori a0, 0x0100 + mtc0 a0, COP0_CAUSE + li a0, MAGIC1 + PRINTX + PUTCHAR('\n') + /* we should end here after taking the exeption */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + xori a0, 0x100 + mtc0 a0, COP0_CAUSE + nop + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/Makefile (revision 373) @@ -0,0 +1,2 @@ +include ../Makefile.inc +CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY} Index: /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/mtty0 (revision 373) @@ -0,0 +1,3 @@ +start +status 0x00400403 cause 0x80000000 pc 0xBFC00054 badva 0x00000000 xicu 0x00000000 +end 0x0000DEAD Index: /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/run (revision 373) @@ -0,0 +1,36 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^end 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400403 cause 0x80000000 pc 0xBFC00054 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F][01][0-9A-F]00$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + + +for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70; do + make clean --quiet + make INTERRUPT_DELAY=$i --quiet || exit 1 + ${SIMUL} > run.out 2>&1 + if [ $? -eq 0 ]; then + if check_output; then + echo "test $i passed"; + make --quiet clean + exit 0; + fi + else + echo "test FAILED" + exit 1 + fi +done +echo "test FAILED" Index: /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_delayslot/test.S (revision 373) @@ -0,0 +1,112 @@ +/* + * Check that we can take an interrupt from the xicu timer0 + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + /* + * interrupt in INTERRUPT_DELAY cycles. + * Without cache this takes us to the delay slot of the jump. + */ + + li a0, INTERRUPT_DELAY + //li a0, 38 + sw a0, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + nop + nop + nop + j end + li s0, MAGIC1 + nop + /* we should not end there */ + EXIT(1) + +end: + PRINT(endstr) + move a0, s0 + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^eret$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400103 cause 0x00000100 pc 0xBFC00038 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_epc_modify/test.S (revision 373) @@ -0,0 +1,85 @@ +/* + * Check that we can take an interrupt, and return to a different address. + * We use a software-triggerted interrupt. + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enbale soft interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0101; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* generate an interrupt */ + mfc0 a0, COP0_CAUSE + nop + ori a0, 0x0100 + mtc0 a0, COP0_CAUSE + nop + /* we should not end there */ + EXIT(1) + +exret: + PRINT(eretstr) + EXIT(0) + + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + xori a0, 0x100 + mtc0 a0, COP0_CAUSE + nop + la a0, exret + mtc0 a0, COP0_EXPC + nop + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_interrupt_extended/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_extended/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_extended/Makefile (revision 373) @@ -0,0 +1,2 @@ +include ../Makefile.inc +CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY} Index: /trunk/softs/tests_cc_vcache/test_interrupt_extended/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_extended/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_extended/run (revision 373) @@ -0,0 +1,31 @@ +#!/bin/sh + +check_output() +{ + egrep "^end 0x0000DEAE$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep ^status run.out + return 0; +} +echo +for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70; do + echo -n " DELAY=$i: " + make INTERRUPT_DELAY=$i --quiet || exit 1 + ../platform/simulation.x > run.out 2>&1 + if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + else + echo "test FAILED" + exit 1 + fi + else + echo "test FAILED" + exit 1 + fi +done + Index: /trunk/softs/tests_cc_vcache/test_interrupt_extended/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_extended/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_extended/test.S (revision 373) @@ -0,0 +1,137 @@ +/* + * Check interrupt/return with interrup occuring at various points in + * the software. Cache is enabled to we have on interrupt/cycle + */ +#include +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + /* + * interrupt in INTERRUPT_DELAY cycles. + */ + li a0, INTERRUPT_DELAY + sw a0, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + li s0, MAGIC1 + addiu s0, s0, -1 + addiu s0, s0, -1 + addiu s0, s0, -1 + addiu s0, s0, -1 + nop + j end + addiu s0, s0, 5 + nop + /* we should not end there */ + EXIT(1) + +end: + PRINT(endstr) + move a0, s0 + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (XICU_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_interrupt_extended2/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_extended2/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_extended2/Makefile (revision 373) @@ -0,0 +1,2 @@ +include ../Makefile.inc +CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY} Index: /trunk/softs/tests_cc_vcache/test_interrupt_extended2/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_extended2/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_extended2/run (revision 373) @@ -0,0 +1,31 @@ +#!/bin/sh + +check_output() +{ + egrep "^end 0x0000DEAD 0x0000BEF0$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400403" run.out + return 0; +} +echo +for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99; do + echo -n " DELAY=$i: " + make INTERRUPT_DELAY=$i --quiet || exit 1 + ../platform/simulation.x > run.out 2>&1 + if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + else + echo "test FAILED" + exit 1 + fi + else + echo "test FAILED" + exit 1 + fi +done + Index: /trunk/softs/tests_cc_vcache/test_interrupt_extended2/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_extended2/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_extended2/test.S (revision 373) @@ -0,0 +1,181 @@ +/* + * Check interrupt/return with interrup occuring at various points in + * the software. Cache is enabled to we have on interrupt/cycle + */ +#include +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + + /* reset cop0 status (keep BEV), enable soft interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0101; + mtc0 a0, COP0_STATUS +#if 1 + /* trigger soft interrupt, so that exept is in cache */ + mfc0 a0, COP0_CAUSE + ori a0, 0x0100 + mtc0 a0, COP0_CAUSE + nop +#endif + + /* + * interrupt in INTERRUPT_DELAY cycles. + */ + la t0, XICU_BASE + li a0, INTERRUPT_DELAY + sw a0, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + li s0, MAGIC1 + li s1, MAGIC2 + addiu s0, s0, -1 + jal incr + nop + addiu s0, s0, -1 + jal incr + nop + addiu s0, s0, -1 + jal incr + nop + addiu s0, s0, -1 + jal incr + nop + j end + addiu s1, s1, 5 + nop + /* we should not end there */ + EXIT(1) + + .align 6 + nop +incr: + addiu s1, s1, -1 + j ra + addiu s0, s0, 1 + + .align 6 +end: + PRINT(endstr) + move a0, s0 + PRINTX + PUTCHAR(' ') + move a0, s1 + PRINTX + PUTCHAR('\n') + EXIT(0) +fail: + EXIT(4) + + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl excep +excep: + .set noreorder + move s2, ra + mfc0 a0, COP0_CAUSE + andi a0, a0, 0x0400 + beq a0, zero, softint + nop + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') +softint: + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + /* fluch cache line of incr */ + la a0, incr + mtc2 a0, VC_ICACHE_INVAL + //mtc2 a0, VC_ITLB_INVAL + move ra, s2 + la s2, fail + eret + /* we should not end there */ + EXIT(3) + .data +myvar: .word 0 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (XICU_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x0040CC03 cause 0x00000400 pc 0xBFC00088 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F]0001$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_external_mask/test.S (revision 373) @@ -0,0 +1,110 @@ +/* + * Check that we can mask an external interrupt + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + ori a0, 0xc801; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* interrupt in 10 cycles */ + li a0, 10 + sw a0, XICU_PTI_PER(0)(t0) + /* interrupts still disabled at the MIPS level */ + li a0, MAGIC1 + PRINTX + PUTCHAR('\n') + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + /* enable interrupt from timer0 */ + mfc0 a0, COP0_STATUS + ori a0, 0x0400 + mtc0 a0, COP0_STATUS + + nop + nop + +1: j 1b + nop + /* we should not end there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + /* we should end there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/run (revision 373) @@ -0,0 +1,12 @@ +#!/bin/sh + +make --quiet || exit 1 +../platform/simulation.x > run.out 2>&1 +if [ $? -eq 0 ]; then + echo "test passsed"; + make --quiet clean + exit 0; +fi +echo "test failed" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/run.out =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/run.out (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/run.out (revision 373) @@ -0,0 +1,41356 @@ + ____ _ ____ _ ____ ____ +/ ___| _ _ ___| |_ ___ _ __ ___ / ___| / \ / ___/ ___| +\___ \| | | / __| __/ _ \ '_ ` _ \| | / _ \ \___ \___ \ + ___) | |_| \__ \ || __/ | | | | | |___ / ___ \ ___) |__) | +|____/ \__, |___/\__\___|_| |_| |_|\____/_/ \_\____/____/ + |___/ + + Cycle Accurate System Simulator + ASIM/LIP6/UPMC + E-mail support: Richard.Buchmann@asim.lip6.fr + Contributors : Richard Buchmann, Sami Taktak, + Paul-Jerome Kingbo, Frédéric Pétrot, + Nicolas Pouillon + + Last change : Mar 10 2008 + +Loading at 0xbfc00000 size 4194304: .text .reginfo +Loading at 0 size 4194304: .data +mips0 executeNCycles( 1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00000 NPC: 0xbfc00004 Ins: 0x3c1ad020 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0xf (lui) + i rs: 0 rt: 0x1a i: 0xd020 + r rs: 0 rt: 26 rd: 26 sh: 0 func: 0x20 + V rs: 0 rt: 0 + 0: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: 00000000 27: 00000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00004 NPC: 0xbfc00008 Ins: 0x3c1be000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0xf (lui) + i rs: 0 rt: 0x1b i: 0xe000 + r rs: 0 rt: 27 rd: 28 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: 00000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00008 NPC: 0xbfc0000c Ins: 0x40806800 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x10 (cop0) + i rs: 0x4 rt: 0 i: 0x6800 + r rs: 4 rt: 0 rd: 13 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0000c NPC: 0xbfc00010 Ins: 0x3c040000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0 + r rs: 0 rt: 4 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00010 NPC: 0xbfc00014 Ins: 0x24842000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x2000 + r rs: 4 rt: 4 rd: 4 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00014 NPC: 0xbfc00018 Ins: 0x42342 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0x4 i: 0x2342 + r rs: 0 rt: 4 rd: 4 sh: 13 func: 0x2 + V rs: 0 rt: 0x2000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00002000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00018 NPC: 0xbfc0001c Ins: 0x48840000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x12 (cop2) + i rs: 0x4 rt: 0x4 i: 0 + r rs: 4 rt: 4 rd: 0 sh: 0 func: 0 + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0001c NPC: 0xbfc00020 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00020 NPC: 0xbfc00024 Ins: 0x2404000f + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0 rt: 0x4 i: 0xf + r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xf + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00024 NPC: 0xbfc00028 Ins: 0x48840800 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x12 (cop2) + i rs: 0x4 rt: 0x4 i: 0x800 + r rs: 4 rt: 4 rd: 1 sh: 0 func: 0 + V rs: 0xf rt: 0xf + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000f 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00028 NPC: 0xbfc0002c Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0xf + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000f 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc0002c m_jump_pc: 0xbfc00030 m_ifetch_addr: 0xbfc0002c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0002c NPC: 0xbfc00030 Ins: 0x24840248 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x248 + r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x8 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00030 m_jump_pc: 0xbfc00034 m_ifetch_addr: 0xbfc00030 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00030 NPC: 0xbfc00034 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000 +mips0 m_next_pc: 0xbfc00034 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00034 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00034 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00248 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00248 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00248 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00248 rt: 0xbfc00248 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00038 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00249 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x74 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +smips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x74 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00249 rt: 0xbfc00249 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00038 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0024a rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +tmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0024a rt: 0xbfc0024a + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00038 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0024b rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x72 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x72 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x72 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0024b rt: 0xbfc0024b + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00038 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0024c rt: 0x72 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x72 from_mem: 0x20000a74 mask: 0xffffffff new_data: 0x74 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x74 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +rmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0024c rt: 0xbfc0024c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00038 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0024d rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x74 from_mem: 0x20000a74 mask: 0xffffffff new_data: 0xa +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0xa rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0xa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +tmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0024d rt: 0xbfc0024d + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00038 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0024e rt: 0xa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0xa from_mem: 0x20000a74 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00038 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00038 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc00038 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00038 m_jump_pc: 0xbfc0003c m_ifetch_addr: 0xbfc00038 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00038 NPC: 0xbfc0003c Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0xbfc0024e + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc0003c m_jump_pc: 0xbfc00040 m_ifetch_addr: 0xbfc0003c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0003c NPC: 0xbfc00040 Ins: 0x8d040180 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x23 (lw) + i rs: 0x8 rt: 0x4 i: 0x180 + r rs: 8 rt: 4 rd: 0 sh: 6 func: 0 + V rs: 0xd8200000 rt: 0xbfc00248 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x4 +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x4 +mips0 setData: off: 0 count: 0x4 le: 0 old: 0xbfc00248 from_mem: 0 mask: 0xffffffff new_data: 0 +mips0 PC: 0xbfc00040 NPC: 0xbfc00044 Ins: 0x24040001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0 rt: 0x4 i: 0x1 + r rs: 0 rt: 4 rd: 0 sh: 0 func: 0x1 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00044 m_jump_pc: 0xbfc00048 m_ifetch_addr: 0xbfc00044 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00044 NPC: 0xbfc00048 Ins: 0xad040280 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x2b (sw) + i rs: 0x8 rt: 0x4 i: 0x280 + r rs: 8 rt: 4 rd: 0 sh: 10 func: 0 + V rs: 0xd8200000 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc00048 NPC: 0xbfc0004c Ins: 0x3410beef + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0xd (ori) + i rs: 0 rt: 0x10 i: 0xbeef + r rs: 0 rt: 16 rd: 23 sh: 27 func: 0x2f + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc0004c m_jump_pc: 0xbfc00050 m_ifetch_addr: 0xbfc0004c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0004c NPC: 0xbfc00050 Ins: 0x24120001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0 rt: 0x12 i: 0x1 + r rs: 0 rt: 18 rd: 0 sh: 0 func: 0x1 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00050 m_jump_pc: 0xbfc00054 m_ifetch_addr: 0xbfc00050 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00050 NPC: 0xbfc00054 Ins: 0xad120080 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x2b (sw) + i rs: 0x8 rt: 0x12 i: 0x80 + r rs: 8 rt: 18 rd: 0 sh: 2 func: 0 + V rs: 0xd8200000 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00054 m_jump_pc: 0xbfc00058 m_ifetch_addr: 0xbfc00054 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc00054 NPC: 0xbfc00058 Ins: 0x8d040180 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x23 (lw) + i rs: 0x8 rt: 0x4 i: 0x180 + r rs: 8 rt: 4 rd: 0 sh: 6 func: 0 + V rs: 0xd8200000 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x4 +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x4 +mips0 setData: off: 0 count: 0x4 le: 0 old: 0x1 from_mem: 0 mask: 0xffffffff new_data: 0 +mips0 PC: 0xbfc00058 NPC: 0xbfc0005c Ins: 0x3c040040 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0x40 + r rs: 0 rt: 4 rd: 0 sh: 1 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc0005c m_jump_pc: 0xbfc00060 m_ifetch_addr: 0xbfc0005c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc0005c NPC: 0xbfc00060 Ins: 0x24840401 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x401 + r rs: 4 rt: 4 rd: 0 sh: 16 func: 0x1 + V rs: 0x400000 rt: 0x400000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00060 m_jump_pc: 0xbfc00064 m_ifetch_addr: 0xbfc00060 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00060 NPC: 0xbfc00064 Ins: 0x40846000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004 + op: 0x10 (cop0) + i rs: 0x4 rt: 0x4 i: 0x6000 + r rs: 4 rt: 4 rd: 12 sh: 0 func: 0 + V rs: 0x400401 rt: 0x400401 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00064 m_jump_pc: 0xbfc00068 m_ifetch_addr: 0xbfc00064 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00064 NPC: 0xbfc00068 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 exception: 0 + m_ins: 0 epc: bfc00068 error_epc: 0 bar: d8200180 cause.xcode: 0 .bd: 0 .ip: 4 status.exl: 1 .erl: 0 exception address: bfc00380 +mips0 executeNCycles( 1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x4d + r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd + V rs: 0xbfc00038 rt: 0xbeef + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xbeef rt: 0xbeef + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0xd8200000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2b (sw) + i rs: 0x8 rt: 0 i: 0x80 + r rs: 8 rt: 0 rd: 0 sh: 2 func: 0 + V rs: 0xd8200000 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0x400401 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x224 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc00038 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038 +mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00224 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00224 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00224 rt: 0xbfc00224 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00225 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +smips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x74 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00225 rt: 0xbfc00225 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00226 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +tmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00226 rt: 0xbfc00226 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00227 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x74 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00227 rt: 0xbfc00227 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00228 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +tmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00228 rt: 0xbfc00228 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00229 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00229 rt: 0xbfc00229 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022a rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +smips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022a rt: 0xbfc0022a + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022b rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00150 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x6000 + r rs: 0 rt: 4 rd: 12 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00224 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc00150 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0x400403 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000030 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000030 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000078 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000078 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x400403 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x400403 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x4004030 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x4004030 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x40040300 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x40000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x4 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x40040300 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x403000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +4mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x403000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x4030000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x4030000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x40300000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x40000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x4 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x40300000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x3000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +4mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x3000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x30000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x30000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x3 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x33 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x30000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc0015c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0x400403 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +3mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x234 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc0015c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00234 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00234 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00234 rt: 0xbfc00234 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00235 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x70 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x70 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00235 rt: 0xbfc00235 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00236 rt: 0x70 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +pmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00236 rt: 0xbfc00236 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00237 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00237 rt: 0xbfc00237 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00238 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc0016c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x7000 + r rs: 0 rt: 4 rd: 14 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00234 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc0016c rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00068 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x33 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xbfc00068 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xb0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xb rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xb rt: 0xb + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x42 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xbfc00068 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00068 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x42 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xfc000680 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xf rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xf rt: 0xf + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x46 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xfc000680 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: fc000680 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x46 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Bmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xc0006800 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xc0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xc rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xc rt: 0xc + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x43 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xc0006800 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: c0006800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Fmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x43 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x68000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Cmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x68000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00068000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x680000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x680000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00680000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x6800000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x6800000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 06800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x68000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x60000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 60000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x6 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x36 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x68000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 68000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x36 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x80000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x80000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 80000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +6mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x8 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x38 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x80000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00178 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0xbfc00068 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +8mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x22c + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc00178 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc0022c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022c rt: 0xbfc0022c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022d rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022d rt: 0xbfc0022d + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022e rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022e rt: 0xbfc0022e + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022f rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022f rt: 0xbfc0022f + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00230 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00230 rt: 0xbfc00230 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00231 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x65 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x65 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +smips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00231 rt: 0xbfc00231 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00232 rt: 0x65 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +emips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00232 rt: 0xbfc00232 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00233 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00188 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x6800 + r rs: 0 rt: 4 rd: 13 sh: 0 func: 0 + V rs: 0 rt: 0xbfc0022c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc00188 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x38 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00194 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x239 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc00194 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00239 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00239 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00239 rt: 0xbfc00239 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023a rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x62 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x62 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023a rt: 0xbfc0023a + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023b rt: 0x62 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +bmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023b rt: 0xbfc0023b + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023c rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x64 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x64 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023c rt: 0xbfc0023c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023d rt: 0x64 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x76 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x76 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +dmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023d rt: 0xbfc0023d + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023e rt: 0x76 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +vmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023e rt: 0xbfc0023e + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023f rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023f rt: 0xbfc0023f + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00240 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001a4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x4000 + r rs: 0 rt: 4 rd: 8 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00239 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc001a4 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001b0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x241 + r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc001b0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00241 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00241 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00241 rt: 0xbfc00241 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00242 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x78 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00242 rt: 0xbfc00242 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00243 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x69 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x69 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00243 rt: 0xbfc00243 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00244 rt: 0x69 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +imips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00244 rt: 0xbfc00244 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00245 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00245 rt: 0xbfc00245 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00246 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00246 rt: 0xbfc00246 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00247 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001c0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0xbfc00247 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x23 (lw) + i rs: 0x8 rt: 0x4 i: 0x780 + r rs: 8 rt: 4 rd: 0 sh: 30 func: 0 + V rs: 0xd8200000 rt: 0xbfc00241 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x4 +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x4 +mips0 setData: off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0 +mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc001c0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001d0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x4 i: 0xa + r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x4 i: 0 + r rs: 26 rt: 4 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0xa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xc (andi) + i rs: 0x12 rt: 0x13 i: 0x1 + r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x13 rt: 0 i: 0x2 + r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e4 m_ifetch_addr: 0xbfc001e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001e0 NPC: 0xbfc001e4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001e4 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001e4 NPC: 0xbfc001e8 Ins: 0x26100001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0x1 + r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x1 + V rs: 0xbeee rt: 0xbeee + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x12 rt: 0x12 i: 0x1 + r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1 + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x13 i: 0x184 + r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4 + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x12 rt: 0x13 i: 0x8 + r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8 + V rs: 0x2 rt: 0x184 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000002 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x12 i: 0x9842 + r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2 + V rs: 0 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000002 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2b (sw) + i rs: 0x8 rt: 0x13 i: 0x80 + r rs: 8 rt: 19 rd: 0 sh: 2 func: 0 + V rs: 0xd8200000 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0x10 rt: 0 i: 0x18 + r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18 + V rs: 0xbeef rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 ERET exl jump_pc: bfc0006c +mips0 m_next_pc: 0xbfc00068 m_jump_pc: 0xbfc0006c m_ifetch_addr: 0xbfc00068 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00068 NPC: 0xbfc0006c Ins: 0x3410dead + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0xd (ori) + i rs: 0 rt: 0x10 i: 0xdead + r rs: 0 rt: 16 rd: 27 sh: 26 func: 0x2d + V rs: 0 rt: 0xbeef + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0006c m_jump_pc: 0xbfc00070 m_ifetch_addr: 0xbfc0006c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0006c NPC: 0xbfc00070 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdead rt: 0xdead + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00070 m_jump_pc: 0xbfc00074 m_ifetch_addr: 0xbfc00070 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00070 NPC: 0xbfc00074 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdeac rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00074 m_jump_pc: 0xbfc00078 m_ifetch_addr: 0xbfc00074 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00074 NPC: 0xbfc00078 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdeab rt: 0xdeab + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deab 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 exception: 0 + m_ins: 9 epc: bfc00078 error_epc: 0 bar: d8200080 cause.xcode: 0 .bd: 0 .ip: 4 status.exl: 1 .erl: 0 exception address: bfc00380 +mips0 executeNCycles( 1, , , 0x1) +mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x4d + r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd + V rs: 0xbfc001d0 rt: 0xdeaa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdeaa rt: 0xdeaa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0xd8200000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2b (sw) + i rs: 0x8 rt: 0 i: 0x80 + r rs: 8 rt: 0 rd: 0 sh: 2 func: 0 + V rs: 0xd8200000 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0xa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x224 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00224 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00224 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00224 rt: 0xbfc00224 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00225 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +smips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x74 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00225 rt: 0xbfc00225 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00226 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +tmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00226 rt: 0xbfc00226 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00227 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x74 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00227 rt: 0xbfc00227 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00228 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +tmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00228 rt: 0xbfc00228 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00229 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00229 rt: 0xbfc00229 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022a rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +smips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022a rt: 0xbfc0022a + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022b rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00150 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x6000 + r rs: 0 rt: 4 rd: 12 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00224 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc00150 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0x400403 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x400403 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x400403 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x4004030 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x4004030 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x40040300 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x40000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x4 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x40040300 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x403000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +4mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x403000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x4030000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x4030000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x40300000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x40000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x4 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x40300000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x3000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +4mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x3000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x30000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x30000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x3 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x33 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x30000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc0015c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0x400403 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +3mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x234 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc0015c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00234 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00234 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00234 rt: 0xbfc00234 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00235 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x70 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x70 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00235 rt: 0xbfc00235 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00236 rt: 0x70 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +pmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00236 rt: 0xbfc00236 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00237 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00237 rt: 0xbfc00237 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00238 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc0016c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x7000 + r rs: 0 rt: 4 rd: 14 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00234 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc0016c rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00078 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x33 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xbfc00078 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xb0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xb rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xb rt: 0xb + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x42 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xbfc00078 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00078 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x42 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xfc000780 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xf rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xf rt: 0xf + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x46 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xfc000780 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: fc000780 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x46 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Bmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xc0007800 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xc0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xc rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xc rt: 0xc + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x43 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xc0007800 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: c0007800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Fmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x43 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x78000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Cmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x78000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00078000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x780000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x780000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00780000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x7800000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x7800000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 07800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x78000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x70000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 70000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x7 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x37 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x78000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 78000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x37 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x80000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x80000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 80000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +7mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x8 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x38 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x80000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00178 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0xbfc00078 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +8mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x22c + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc00178 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc0022c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022c rt: 0xbfc0022c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022d rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022d rt: 0xbfc0022d + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022e rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022e rt: 0xbfc0022e + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022f rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022f rt: 0xbfc0022f + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00230 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00230 rt: 0xbfc00230 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00231 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x65 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x65 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +smips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00231 rt: 0xbfc00231 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00232 rt: 0x65 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +emips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00232 rt: 0xbfc00232 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00233 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00188 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x6800 + r rs: 0 rt: 4 rd: 13 sh: 0 func: 0 + V rs: 0 rt: 0xbfc0022c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc00188 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x38 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00194 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x239 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc00194 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00239 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00239 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00239 rt: 0xbfc00239 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023a rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x62 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x62 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023a rt: 0xbfc0023a + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023b rt: 0x62 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +bmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023b rt: 0xbfc0023b + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023c rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x64 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x64 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023c rt: 0xbfc0023c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023d rt: 0x64 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x76 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x76 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +dmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023d rt: 0xbfc0023d + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023e rt: 0x76 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +vmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023e rt: 0xbfc0023e + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023f rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023f rt: 0xbfc0023f + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00240 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001a4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x4000 + r rs: 0 rt: 4 rd: 8 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00239 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc001a4 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001b0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x241 + r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc001b0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00241 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00241 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00241 rt: 0xbfc00241 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00242 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x78 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00242 rt: 0xbfc00242 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00243 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x69 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x69 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00243 rt: 0xbfc00243 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00244 rt: 0x69 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +imips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00244 rt: 0xbfc00244 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00245 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00245 rt: 0xbfc00245 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00246 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00246 rt: 0xbfc00246 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00247 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001c0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0xbfc00247 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x23 (lw) + i rs: 0x8 rt: 0x4 i: 0x780 + r rs: 8 rt: 4 rd: 0 sh: 30 func: 0 + V rs: 0xd8200000 rt: 0xbfc00241 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x4 +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x4 +mips0 setData: off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0 +mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc001c0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001d0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x4 i: 0xa + r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x4 i: 0 + r rs: 26 rt: 4 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0xa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xc (andi) + i rs: 0x12 rt: 0x13 i: 0x1 + r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1 + V rs: 0x2 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x13 rt: 0 i: 0x2 + r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001e0 NPC: 0xbfc001e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x12 rt: 0x12 i: 0x1 + r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1 + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x13 i: 0x184 + r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000003 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x12 rt: 0x13 i: 0x8 + r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8 + V rs: 0x3 rt: 0x184 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000003 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x12 i: 0x9842 + r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2 + V rs: 0 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000003 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2b (sw) + i rs: 0x8 rt: 0x13 i: 0x80 + r rs: 8 rt: 19 rd: 0 sh: 2 func: 0 + V rs: 0xd8200000 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0x10 rt: 0 i: 0x18 + r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18 + V rs: 0xdea9 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 ERET exl jump_pc: bfc0007c +mips0 m_next_pc: 0xbfc00078 m_jump_pc: 0xbfc0007c m_ifetch_addr: 0xbfc00078 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00078 NPC: 0xbfc0007c Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdea9 rt: 0xdea9 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0007c m_jump_pc: 0xbfc00080 m_ifetch_addr: 0xbfc0007c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0007c NPC: 0xbfc00080 Ins: 0xbf00030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x30 + r rs: 31 rt: 16 rd: 0 sh: 0 func: 0x30 + V rs: 0xbfc001d0 rt: 0xdea8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea8 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00080 NPC: 0xbfc000c0 Ins: 0x26100005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0x5 + r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x5 + V rs: 0xdea8 rt: 0xdea8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dea8 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 exception: 0 + m_ins: 0x9 epc: 0xbfc000c0 error_epc: 0 bar: 0xd8200080 cause.xcode: 0 .bd: 0 .ip: 0x4 status.exl: 0x1 .erl: 0 exception address: 0xbfc00380 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x4d + r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd + V rs: 0xbfc001d0 rt: 0xdead + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdead rt: 0xdead + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0xd8200000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2b (sw) + i rs: 0x8 rt: 0 i: 0x80 + r rs: 8 rt: 0 rd: 0 sh: 2 func: 0 + V rs: 0xd8200000 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0xa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x224 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00224 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00224 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00224 rt: 0xbfc00224 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00225 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +smips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x74 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00225 rt: 0xbfc00225 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00226 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +tmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00226 rt: 0xbfc00226 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00227 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x74 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00227 rt: 0xbfc00227 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00228 rt: 0x74 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +tmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00228 rt: 0xbfc00228 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00229 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00229 rt: 0xbfc00229 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022a rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +smips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022a rt: 0xbfc0022a + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00150 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022b rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00150 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x6000 + r rs: 0 rt: 4 rd: 12 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00224 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc00150 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150 +mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0x400403 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x400403 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x400403 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x4004030 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x4004030 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x40040300 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x40000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x4 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x40040300 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x403000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +4mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x403000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x4030000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x4030000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x40300000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x40000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x4 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x40300000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x34 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x3000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +4mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x3000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0x30000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0x30000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0x3 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x33 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0x30000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc0015c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0x400403 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +3mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x234 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc0015c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c +mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00234 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00234 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00234 rt: 0xbfc00234 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00235 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x70 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x70 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00235 rt: 0xbfc00235 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00236 rt: 0x70 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +pmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00236 rt: 0xbfc00236 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00237 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00237 rt: 0xbfc00237 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc0016c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00238 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc0016c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x7000 + r rs: 0 rt: 4 rd: 14 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00234 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc0016c rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c +mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc000c0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x33 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xbfc000c0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xb0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xb rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xb rt: 0xb + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x42 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xbfc000c0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: bfc000c0 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x42 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xfc000c00 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xf rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xf rt: 0xf + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x46 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xfc000c00 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: fc000c00 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x46 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Bmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xc000c000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xc0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xc rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xc rt: 0xc + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x43 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xc000c000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c000c000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Fmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x43 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xc0000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Cmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xc0000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 000c0000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xc00000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00c00000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xc000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xc000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 0c000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0xc0000000 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0xc0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: c0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0xc rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: 0000000c 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x37 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37 + V rs: 0xc rt: 0xc + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x43 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000002 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0xc0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: c0000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x43 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +Cmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00178 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00178 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0xbfc000c0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x22c + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc00178 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178 +mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc0022c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022c rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022c rt: 0xbfc0022c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022d rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022d rt: 0xbfc0022d + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022e rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022e rt: 0xbfc0022e + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0022f rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0022f rt: 0xbfc0022f + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00230 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x73 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00230 rt: 0xbfc00230 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00231 rt: 0x73 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x65 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x65 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +smips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00231 rt: 0xbfc00231 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00232 rt: 0x65 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +emips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00232 rt: 0xbfc00232 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc00188 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00233 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00188 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x6800 + r rs: 0 rt: 4 rd: 13 sh: 0 func: 0 + V rs: 0 rt: 0xbfc0022c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc00188 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188 +mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc00194 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x239 + r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc00194 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194 +mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00239 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00239 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00239 rt: 0xbfc00239 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023a rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x62 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x62 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023a rt: 0xbfc0023a + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023b rt: 0x62 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +bmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023b rt: 0xbfc0023b + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023c rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x64 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x64 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023c rt: 0xbfc0023c + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023d rt: 0x64 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x76 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x76 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +dmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023d rt: 0xbfc0023d + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023e rt: 0x76 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x61 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +vmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023e rt: 0xbfc0023e + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc0023f rt: 0x61 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +amips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc0023f rt: 0xbfc0023f + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001a4 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00240 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001a4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0 rt: 0x4 i: 0x4000 + r rs: 0 rt: 4 rd: 8 sh: 0 func: 0 + V rs: 0 rt: 0xbfc00239 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc001a4 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4 +mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001b0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x4 rt: 0x4 i: 0x241 + r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1 + V rs: 0xbfc00000 rt: 0xbfc00000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xf0 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30 + V rs: 0xbfc001b0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0 +mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0xbfc00241 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00241 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00241 rt: 0xbfc00241 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00242 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x78 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00242 rt: 0xbfc00242 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00243 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x69 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x69 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00243 rt: 0xbfc00243 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00244 rt: 0x69 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x63 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +imips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00244 rt: 0xbfc00244 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00245 rt: 0x63 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x1 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x75 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +cmips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00245 rt: 0xbfc00245 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00246 rt: 0x75 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x2 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0x20 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +umips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x8 rt: 0x8 i: 0x1 + r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1 + V rs: 0xbfc00246 rt: 0xbfc00246 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0xf1 + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31 + V rs: 0xbfc001c0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x20 (lb) + i rs: 0x8 rt: 0x9 i: 0 + r rs: 8 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xbfc00247 rt: 0x20 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0x3 sign_ext: 0x1 dest: gp+0x9 +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0x1 dest: r_gp+0x9 +mips0 setData: off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x9 rt: 0 i: 0x5 + r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001c0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0xbfc00247 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x23 (lw) + i rs: 0x8 rt: 0x4 i: 0x780 + r rs: 8 rt: 4 rd: 0 sh: 30 func: 0 + V rs: 0xd8200000 rt: 0xbfc00241 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x4 +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x4 +mips0 setData: off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0 +mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x3 (jal) + i rs: 0x1f rt: 0x10 i: 0xfa + r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a + V rs: 0xbfc001c0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0 +mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x4 rt: 0 i: 0x4021 + r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x30 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x78 + r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x9 i: 0 + r rs: 26 rt: 9 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x9 i: 0x8 + r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8 + V rs: 0 rt: 0x78 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x8 rt: 0x8 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x7 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +xmips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x7 rt: 0x7 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x6 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x6 rt: 0x6 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x5 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x5 rt: 0x5 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x4 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x4 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x3 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x2 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x2 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0xa i: 0xf000 + r rs: 0 rt: 10 rd: 30 sh: 0 func: 0 + V rs: 0 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x8 rt: 0xa i: 0x5024 + r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24 + V rs: 0 rt: 0xf0000000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0xa i: 0x5702 + r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xa (slti) + i rs: 0xa rt: 0xb i: 0xa + r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0xb rt: 0 i: 0x4 + r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0xa rt: 0xa i: 0x30 + r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x10a + r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa + V rs: 0xbfc001d0 rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0xa i: 0 + r rs: 26 rt: 10 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0x30 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x8 (addi) + i rs: 0x9 rt: 0x9 i: 0xffff + r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f + V rs: 0x1 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x7 (bgtz) + i rs: 0x9 rt: 0 i: 0xfff3 + r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x8 i: 0x4100 + r rs: 0 rt: 8 rd: 8 sh: 4 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0x1f rt: 0 i: 0x8 + r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8 + V rs: 0xbfc001d0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x4 i: 0xa + r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +0mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x28 (sb) + i rs: 0x1a rt: 0x4 i: 0 + r rs: 26 rt: 4 rd: 0 sh: 0 func: 0 + V rs: 0xd0200000 rt: 0xa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xc (andi) + i rs: 0x12 rt: 0x13 i: 0x1 + r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1 + V rs: 0x3 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x13 rt: 0 i: 0x2 + r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2 + V rs: 0x1 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e4 m_ifetch_addr: 0xbfc001e0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001e0 NPC: 0xbfc001e4 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001e4 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001e4 NPC: 0xbfc001e8 Ins: 0x26100001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0x1 + r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x1 + V rs: 0xdeac rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x12 rt: 0x12 i: 0x1 + r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1 + V rs: 0x3 rt: 0x3 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0 rt: 0x13 i: 0x184 + r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4 + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000004 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x4 (beq) + i rs: 0x12 rt: 0x13 i: 0x8 + r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8 + V rs: 0x4 rt: 0x184 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000004 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0x12 i: 0x9842 + r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2 + V rs: 0 rt: 0x4 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000004 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 + +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2b (sw) + i rs: 0x8 rt: 0x13 i: 0x80 + r rs: 8 rt: 19 rd: 0 sh: 2 func: 0 + V rs: 0xd8200000 rt: 0x2 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x10 (cop0) + i rs: 0x10 rt: 0 i: 0x18 + r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18 + V rs: 0xdead rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 ERET exl jump_pc: bfc000c4 +mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc000c0 NPC: 0xbfc000c4 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdead rt: 0xdead + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc000c4 m_jump_pc: 0xbfc000c8 m_ifetch_addr: 0xbfc000c4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc000c4 NPC: 0xbfc000c8 Ins: 0x3411dead + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0xd (ori) + i rs: 0 rt: 0x11 i: 0xdead + r rs: 0 rt: 17 rd: 27 sh: 26 func: 0x2d + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc000c8 m_jump_pc: 0xbfc000cc m_ifetch_addr: 0xbfc000c8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc000c8 NPC: 0xbfc000cc Ins: 0x1211ffe9 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x4 (beq) + i rs: 0x10 rt: 0x11 i: 0xffe9 + r rs: 16 rt: 17 rd: 31 sh: 31 func: 0x29 + V rs: 0xdeac rt: 0xdead + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc000cc m_jump_pc: 0xbfc000d0 m_ifetch_addr: 0xbfc000cc +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc000cc NPC: 0xbfc000d0 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdeac rt: 0xdeac + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deac 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc000d0 m_jump_pc: 0xbfc000d4 m_ifetch_addr: 0xbfc000d0 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc000d0 NPC: 0xbfc000d4 Ins: 0x24040001 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x9 (addiu) + i rs: 0 rt: 0x4 i: 0x1 + r rs: 0 rt: 4 rd: 0 sh: 0 func: 0x1 + V rs: 0 rt: 0xa + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc000d4 m_jump_pc: 0xbfc000d8 m_ifetch_addr: 0xbfc000d4 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 PC: 0xbfc000d4 NPC: 0xbfc000d8 Ins: 0xaf640000 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401 + op: 0x2b (sw) + i rs: 0x1b rt: 0x4 i: 0 + r rs: 27 rt: 4 rd: 0 sh: 0 func: 0 + V rs: 0xe0000000 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0) +mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 exception: 0 + m_ins: 0x2 epc: 0xbfc000d8 error_epc: 0 bar: 0xe0000000 cause.xcode: 0 .bd: 0 .ip: 0x4 status.exl: 0x1 .erl: 0 exception address: 0xbfc00380 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380 +mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2 (j) + i rs: 0x1f rt: 0x10 i: 0x4d + r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd + V rs: 0xbfc001d0 rt: 0xdeab + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0 (special) + i rs: 0 rt: 0 i: 0 + r rs: 0 rt: 0 rd: 0 sh: 0 func: 0 + V rs: 0 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x9 (addiu) + i rs: 0x10 rt: 0x10 i: 0xffff + r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f + V rs: 0xdeab rt: 0xdeab + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x8 i: 0xd820 + r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20 + V rs: 0 rt: 0xd8200000 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0x2b (sw) + i rs: 0x8 rt: 0 i: 0x80 + r rs: 8 rt: 0 rd: 0 sh: 2 func: 0 + V rs: 0xd8200000 rt: 0 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 do_mem_access: off: 0 sign_ext: 0 dest: gp+0x15f561 +mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +mips0 executeNCycles( 0x1, , , 0x1) +mips0 setData: off: 0 sign_ext: 0 dest: r_gp+0x15f561 +mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0 + Cause.xcode: 0 + Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403 + op: 0xf (lui) + i rs: 0 rt: 0x4 i: 0xbfc0 + r rs: 0 rt: 4 rd: 23 sh: 31 func: 0 + V rs: 0 rt: 0x1 + 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000 + 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000 + 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000 + 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0 +mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144 +mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0 +vci_exit terminate simulation, status 0x1 Index: /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_loop_tmp/test.S (revision 373) @@ -0,0 +1,166 @@ +/* + * Check interrupt/return with interrup occuring at various points in + * the software. Cache is enabled to we have on interrupt/cycle + */ +#include +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + /* + * interrupt in INTERRUPT_DELAY cycles. + */ + li s2, 1 + sw s2, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + nop + li s0, MAGIC1 + addiu s0, s0, -1 +loop: + addiu s0, s0, -1 + addiu s0, s0, -1 + addiu s0, s0, -1 + j bla + addiu s0, s0, 5 + EXIT(1) + addiu s0, s0, -1 + .align 6 +bla: + addiu s0, s0, -1 + li s1, MAGIC1 + beq s0, s1, loop + addiu s0, s0, -1 + + /* we should not end there */ + EXIT(1) + + .align 6 +end: + PRINT(endstr) + move a0, s0 + PRINTX + PUTCHAR('\n') + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +perstr: .ascii " period \0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl excep +excep: + .set noreorder + addiu s0, s0, -10 + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + +// PRINT(perstr) +// move a0, s2 +// PRINTX +// + PUTCHAR('\n') + +#if 0 + andi s3, s2, 1 + beqz s3, noflush +#endif + addiu s0, s0, 10 + +#if 1 + // Flush cache of jump routine + la s3, bla + mtc2 s3, VC_ICACHE_INVAL + mtc2 s3, VC_ITLB_INVAL +#endif + +noflush: + addiu s2, s2, 1 + li s3, 194*2 + beq s2, s3, end2 + srl s3, s2, 1 + la t0, XICU_BASE + sw s3, XICU_PTI_PER(0)(t0) + eret + /* we should not end there */ + EXIT(1) +end2: + EXIT(0) + + .data +myvar: .word 0 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (XICU_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_interrupt_mask/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_mask/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_mask/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_interrupt_mask/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_mask/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_mask/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x0040FF03 cause 0x00000100 pc 0xBFC00074 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_interrupt_mask/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_interrupt_mask/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_interrupt_mask/test.S (revision 373) @@ -0,0 +1,95 @@ +/* + * Check that the interrupt mask in status is properly handled: + * we generate a software-triggerted interrupt with interrupt enabled but + * the software interrupt masked. Later we unmask it. + */ +#include +#include + + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enbale interrupts but mask IM0 */ + lui a0, 0x0040; + ori a0, 0xfe01; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* generate an interrupt */ + mfc0 a0, COP0_CAUSE + nop + ori a0, 0x0100 + mtc0 a0, COP0_CAUSE + li a0, MAGIC1 + PRINTX + PUTCHAR('\n') + nop + nop + nop + nop + nop + nop + /* unmask the interrupt */ + mfc0 a0, COP0_STATUS + nop + ori a0, 0x0100 + mtc0 a0, COP0_STATUS + /* we should end here after taking the exeption */ + li a0, MAGIC2 + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + xori a0, 0x100 + mtc0 a0, COP0_CAUSE + nop + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_itlb_inval/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_inval/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_inval/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_itlb_inval/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_inval/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_inval/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_itlb_inval/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_inval/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_inval/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000DEAD status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_itlb_inval/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_inval/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_inval/test.S (revision 373) @@ -0,0 +1,135 @@ +/* + * itlb inval: a write to VC_ITLB_INVAL should invalidate the corresponding + * itlb entry. On a ccvcache, VC_ITLB_INVAL should not be needed, and + * the first access after clearing pte2_a should fail + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + jal doload + nop + PRINTX + PUTCHAR(' ') + la a0, pte2_a + sw zero, 8(a0) /* invalidate PTE2 */ + sync + la a0, pte2_a /* make the sync synchronous */ + jal doload /* TLB entry not invalidated yet, we can do this */ + nop + PRINTX + PUTCHAR('\n') + la a0, doload + mtc2 a0, VC_ITLB_INVAL /* invalidate VA */ + jal doload /* this should fail now */ + nop + PRINTX + PUTCHAR('\n') + + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_itlb_inval2/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_inval2/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_inval2/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_itlb_inval2/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_inval2/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_inval2/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_itlb_inval2/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_inval2/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_inval2/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_itlb_inval2/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_inval2/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_inval2/test.S (revision 373) @@ -0,0 +1,142 @@ +/* + * itlb inval: a write to a PTE2 should invalidate the corresponding + * itlb entry. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + jal doload + nop + PRINTX + PUTCHAR(' ') + la t0, pte2_a + la a0, (BOOT_ADDRESS+0x2000) >> 12 + sw a0, 12(t0) /* change PTE2 */ + sync +1: + ll a0, 8(t0) + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 8(t0) + beqz a0, 1b + nop + + jal doload /* now we should get the second value */ + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PTP and + * check that the ITLB has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started ptpr_b 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started ptpr_a 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_itlb_ptprinval/test.S (revision 373) @@ -0,0 +1,162 @@ +/* + * itlb inval on PTPR write: check that no stale entry exists in the itlb + * after MMU context swicth + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_b + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_b) + jal doload + nop + PRINTX + PUTCHAR('\n') + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop +#if 0 /* works with this - this shows the old pte2 address is cached */ + la a0, pte2_a + lw a1, 12(a0) + la a0, pte2_b + sw a1, 12(a0) +#endif + PRINT(mmustr_a) + jal doload + nop + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started ptpr_a \0" +mmustr_b: .ascii "mmu started ptpr_b \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + .org doload + 0x1000 /* in the second page, mapped by pte1_b */ + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(2) + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * two PD with two different PTE2 for code: check that itlb points to + * the right one by executing 2 different code at the same address + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b +pte2_b: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x2000) >> 12 + .org pte2_b + 4092 + .word 0 + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 + .globl pte1_b +pte1_b: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_b + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */ + .org pte1_b + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_b + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_b + 8188 + .word 0 Index: /trunk/softs/tests_cc_vcache/test_llsc/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_llsc/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_llsc/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_llsc/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_llsc/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_llsc/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000DEAD 0x0000DEAD 0x0000BEEF 0x0000DEAD$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_llsc/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_llsc/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_llsc/test.S (revision 373) @@ -0,0 +1,113 @@ +/* + * Check interraction between cached read/write and ll/sc + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + /* make sure myvar is in cache */ + la s1, myvar + lw a0, 0(s1) + PRINTX + PUTCHAR(' ') + + /* now write to myvar via ll/sc */ + la s1, myvar +1: + ll a0, 0(s1) + li a1, MAGIC2 + sc a1, 0(s1) + beqz a1, 1b + nop + + PRINTX /* print what we read with ll */ + PUTCHAR(' ') + + la s1, myvar + lw a0, 0(s1) /* print the new value */ + PRINTX + PUTCHAR(' ') + + /* restore myvar value via normal write */ + la s1, myvar + li a1, MAGIC1 + sw a1, 0(s1) + + /* read myvar */ + lw a0, 0(s1) + PRINTX + PUTCHAR('\n'); + + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +myvar: .word MAGIC1 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_mmu_basic/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_mmu_basic/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_mmu_basic/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_mmu_basic/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_mmu_basic/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_mmu_basic/mtty0 (revision 373) @@ -0,0 +1,4 @@ +start +mmu started +0x00200000: 0x0000DEAD +0x00000000: status 0x00400006 cause 0x0000001C pc 0xBFC00098 badva 0x00000000 Index: /trunk/softs/tests_cc_vcache/test_mmu_basic/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_mmu_basic/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_mmu_basic/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00200000: 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^0x00000000: status 0x00400006 cause 0x0000001C pc 0xBFC00098 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_mmu_basic/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_mmu_basic/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_mmu_basic/test.S (revision 373) @@ -0,0 +1,102 @@ +/* + * Basic MMU checks: we can read mapped addresses, we can't read unmapped + * addresses + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + /* we can read our magic number at 0x00200000 */ + la s0, 0x00200000 + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + lw a0, 0(s0) + PRINTX + PUTCHAR('\n') + /* but not at 0x00000000 */ + la s0, 0x00000000 + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + lw a0, 0(s0) /* this should trigger the exception */ + PRINTX + + /* we shouldn't get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + li a0, '\n' + sb a0, 0(k0) + + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +testval: + .word MAGIC1 + .align 13 + .globl pte1 +pte1: + .word 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_pte2i_ref/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2i_ref/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2i_ref/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_pte2i_ref/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2i_ref/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2i_ref/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_pte2i_ref/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2i_ref/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2i_ref/mtty0 (revision 373) @@ -0,0 +1,2 @@ +start +mmu started 0x8A000000 0xAA000000 0xAA000000 Index: /trunk/softs/tests_cc_vcache/test_pte2i_ref/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2i_ref/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2i_ref/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_pte2i_ref/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2i_ref/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2i_ref/test.S (revision 373) @@ -0,0 +1,144 @@ +/* + * instruction fetch causes the PTE_L bit to be set + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 8(s0) + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + beq a0, a1, fail /* PTE2_L already set, not good */ + nop + jal doload /* cause page to be referenced */ + nop + lw s1, 8(s0) + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set not good */ + nop + /* check again, using ll */ + ll s1, 8(s0) + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set not good */ + nop + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_pte2ll_ref/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2ll_ref/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2ll_ref/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_pte2ll_ref/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2ll_ref/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2ll_ref/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_pte2ll_ref/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2ll_ref/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2ll_ref/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_pte2ll_ref/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2ll_ref/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2ll_ref/test.S (revision 373) @@ -0,0 +1,132 @@ +/* + * pte2d_ref: a ll to data should set referenced bit in PTE + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + beq a0, a1, fail /* PTE2_L already set, not good */ + nop + + la t0, testval + 0x00200000 + ll a0, 0(t0); /* cause page to be referenced */ + + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + /* check again, using ll */ + ll s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_pte2lw_ref/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2lw_ref/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2lw_ref/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_pte2lw_ref/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2lw_ref/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2lw_ref/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_pte2lw_ref/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2lw_ref/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2lw_ref/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_pte2lw_ref/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2lw_ref/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2lw_ref/test.S (revision 373) @@ -0,0 +1,132 @@ +/* + * pte2d_ref: a lw to data should set referenced bit in PTE + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + beq a0, a1, fail /* PTE2_L already set, not good */ + nop + + la t0, testval + 0x00200000 + lw a0, 0(t0); /* cause page to be referenced */ + + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + /* check again, using ll */ + ll s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/mtty0 (revision 373) @@ -0,0 +1,2 @@ +start +mmu started 0x8E000000 0xAE400000 0xAE400000 Index: /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8E000000 0xAE400000 0xAE400000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/test.S (revision 373) @@ -0,0 +1,137 @@ +/* + * pte2d_ref: a sc to data should set the dirty bits in PTE + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, zero, fail /* PTE2_L or PTE2_D already set, not good */ + nop + + la t0, testval + 0x00200000 + la a1, MAGIC3 +1: + ll a0, 0(t0) + sc a1, 0(t0); /* cause page to be referenced and dirty */ + beqz a1, 1b + nop + + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + /* check again, using ll */ + ll s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X | PTE2_W + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/vcitty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/vcitty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sc_dirty/vcitty0 (revision 373) @@ -0,0 +1,1 @@ +start Index: /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/Makefile (revision 373) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/ldscript =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/ldscript (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/ldscript (revision 373) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8E000000 0xAE400000 0xAE400000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte2sw_dirty/test.S (revision 373) @@ -0,0 +1,132 @@ +/* + * pte2d_ref: a sw to data should set referenced and dirty bits in PTE + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, zero, fail /* PTE2_L or PTE2_D already set, not good */ + nop + + la t0, testval + 0x00200000 + sw a0, 0(t0); /* cause page to be referenced and dirty */ + + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + /* check again, using ll */ + ll s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X | PTE2_W + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /trunk/softs/tests_cc_vcache/test_pte_llsc/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte_llsc/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte_llsc/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_pte_llsc/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte_llsc/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte_llsc/mtty0 (revision 373) @@ -0,0 +1,1 @@ +0x00000000 0xAC4000FF 0xAC4000FF 0x00000000 Index: /trunk/softs/tests_cc_vcache/test_pte_llsc/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte_llsc/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte_llsc/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000000 0xAC4000FF 0xAC4000FF 0x00000000$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_pte_llsc/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_pte_llsc/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_pte_llsc/test.S (revision 373) @@ -0,0 +1,124 @@ +/* + * Check that the MMU doens't clobber the OS bits in PTEs, and interraction + * with ll/sc + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + /* do a swap of pte2[0] to make the entry valid */ + la s0, pte2 + 0x00200000 +1: la a1, PTE2_V | PTE2_C | PTE2_W | PTE2_os + ll a0, 0(s0) + sc a1, 0(s0) + beqz a1, 1b + nop + PRINTX + PUTCHAR(' ') + /* now write to myvar via pte2[0] */ + li a0, MAGIC2 + la s1, myvar + 0x00200000 + sw a0, 0(s1) + /* + * and invalidate pte2[0], again using a swap + * check that we get the same value with lw and ll + */ + lw s1, 0(s0) +2: + move a1, zero + ll a0, 0(s0) + sc a1, 0(s0) + beqz a1, 2b + PRINTX + PUTCHAR(' ') + move a0, s1 + PRINTX + PUTCHAR(' ') + /* finally check what lw tells us now */ + lw a0, 0(s0) + PRINTX + PUTCHAR('\n') + + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +myvar: .word MAGIC1 + .globl pte1 +pte2: + .align 12 + .word 0 /* invalid for now */ + .word 0x0000 >> 12 /* check real value of myvar */ + .word PTE2_V | PTE2_C | PTE2_W | PTE2_os /* map pte2 too */ + .word 0x1000 >> 12 /* check real address of pte2 */ + .org pte2 + 4092 + .word 0 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_ri/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_ri/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ri/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_ri/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_ri/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ri/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000028 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_ri/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_ri/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ri/test.S (revision 373) @@ -0,0 +1,65 @@ +/* + * reserved instruction exception test: check that a reserved instruction + * generates an exception. + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + .word 0x60000000 + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_ri_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_ri_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ri_delayslot/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_ri_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_ri_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ri_delayslot/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000028 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_ri_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_ri_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_ri_delayslot/test.S (revision 373) @@ -0,0 +1,86 @@ +/* + * reserved instruction exception test: check that a reserved instruction + * in a delay slot is properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + j exit + .word 0x60000000 + nop + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_sanity/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_sanity/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sanity/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_sanity/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_sanity/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sanity/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^hello world 0x1234ABCD$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_sanity/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_sanity/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sanity/test.S (revision 373) @@ -0,0 +1,42 @@ +/* + * Basic sanity checks: + * we can run a program + * we can write to ram + * we can write to the tty + * we can make the simulator exit + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + la t0, value + lw t0, 0(t0) + la t1, myvar + sw t0, 0(t1) + + la a0, string + jal print + nop + + la t1, myvar + lw a0, 0(t1) + jal printx + nop + + li a0, '\n' + sb a0, 0(k0) + + EXIT(0) + + .rodata: +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_sc_no_ll/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_sc_no_ll/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sc_no_ll/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_sc_no_ll/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_sc_no_ll/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sc_no_ll/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000DEAD 0x00000000$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_sc_no_ll/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_sc_no_ll/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sc_no_ll/test.S (revision 373) @@ -0,0 +1,104 @@ +/* + * check that a sc without ll does fail + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + /* make sure myvar is in cache */ + la s1, myvar + lw a0, 0(s1) + PRINTX + PUTCHAR(' ') + + /* now write to myvar with sc, without ll first */ + la s1, myvar +1: + li a1, MAGIC2 + sc a1, 0(s1) + beqz a1, 2f + nop + + move a0, a1 + PRINTX + /* we should not get there */ + EXIT(1) + +2: + /* we jump here when the sc failed */ + move a0, a1 + PRINTX + PUTCHAR('\n'); + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +myvar: .word MAGIC1 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_sc_update_cache/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_sc_update_cache/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sc_update_cache/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_sc_update_cache/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_sc_update_cache/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sc_update_cache/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_sc_update_cache/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_sc_update_cache/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sc_update_cache/test.S (revision 373) @@ -0,0 +1,80 @@ +/* + * Check that lc also updates the local L1 cache. + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + /* enable caches */ + li a0, VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + /* fetch data in cache */ + la s0, myvar + lw a0, 0(s0) + /* write magic value */ + li a0, MAGIC1 + sw a0, 0(s0) + /* ll/sc another value on the same address */ +2: + ll a0, 0(s0) + PRINTX + PUTCHAR(' ') + li a0, MAGIC2 + sc a0, 0(s0) + beqz a0, 2b + /* now check that we got the right value in cache */ + lw a0, 0(s0) + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/test_sync/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_sync/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sync/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_sync/mtty0 =================================================================== --- /trunk/softs/tests_cc_vcache/test_sync/mtty0 (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sync/mtty0 (revision 373) @@ -0,0 +1,3 @@ +start +mmustated +@@@@@@ Index: /trunk/softs/tests_cc_vcache/test_sync/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_sync/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sync/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^@@@@@@$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_sync/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_sync/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_sync/test.S (revision 373) @@ -0,0 +1,101 @@ +/* + * sync test: we map the tty cached. If sync doesn't work some chars will be + * lost because writes are combined in the write buffer. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT_SYNC(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT_SYNC(mmustr) + + /* + * print several chars quickly: without sync not all of them will + * show up + */ +#define WRITE_TTY sb a0, 0(k0); sync + la a0, '@' + WRITE_TTY + WRITE_TTY + WRITE_TTY + WRITE_TTY + WRITE_TTY + WRITE_TTY + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 *cached!* */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /trunk/softs/tests_cc_vcache/test_syscall/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_syscall/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_syscall/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_syscall/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_syscall/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_syscall/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400012 cause 0x00000020 pc 0xBFC00050 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_syscall/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_syscall/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_syscall/test.S (revision 373) @@ -0,0 +1,91 @@ +/* + * syscall test: check that a syscall generates an exception, and we can + * return + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + /* switch to user mode */ + mfc0 a0, COP0_STATUS + ori a0, 0x10 + mtc0 a0, COP0_STATUS + nop + nop + nop + PRINT(usrstr) + syscall + bne a3, zero, exit + nop + /* we should not get there, a3 is not 0 */ + EXIT(2) +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + mfc0 a0, COP0_EXPC + addiu a0, a0, 4 + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_syscall_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_syscall_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_syscall_delayslot/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_syscall_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_syscall_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_syscall_delayslot/run (revision 373) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400012 cause 0x80000020 pc 0xBFC00050 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^usrmode$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_syscall_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_syscall_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_syscall_delayslot/test.S (revision 373) @@ -0,0 +1,90 @@ +/* + * syscall test: check that a syscall in a delay slot is properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + /* switch to user mode */ + mfc0 a0, COP0_STATUS + ori a0, 0x10 + mtc0 a0, COP0_STATUS + nop + nop + nop + PRINT(usrstr) + j exit + syscall + nop + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_trap/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_trap/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_trap/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_trap/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_trap/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_trap/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_trap/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_trap/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_trap/test.S (revision 373) @@ -0,0 +1,64 @@ +/* + * trap test: check that a we can generate a trap + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + teq zero, zero + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_trap_delayslot/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_trap_delayslot/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_trap_delayslot/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_trap_delayslot/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_trap_delayslot/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_trap_delayslot/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_trap_delayslot/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_trap_delayslot/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_trap_delayslot/test.S (revision 373) @@ -0,0 +1,85 @@ +/* + * trap test: check that a trap in a delay slot is + * properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + j exit + teq zero, zero + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /trunk/softs/tests_cc_vcache/test_xicu_timer/Makefile =================================================================== --- /trunk/softs/tests_cc_vcache/test_xicu_timer/Makefile (revision 373) +++ /trunk/softs/tests_cc_vcache/test_xicu_timer/Makefile (revision 373) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /trunk/softs/tests_cc_vcache/test_xicu_timer/run =================================================================== --- /trunk/softs/tests_cc_vcache/test_xicu_timer/run (revision 373) +++ /trunk/softs/tests_cc_vcache/test_xicu_timer/run (revision 373) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400403 cause 0x[08]0000400 pc 0xBFC00040 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F]0001$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /trunk/softs/tests_cc_vcache/test_xicu_timer/test.S =================================================================== --- /trunk/softs/tests_cc_vcache/test_xicu_timer/test.S (revision 373) +++ /trunk/softs/tests_cc_vcache/test_xicu_timer/test.S (revision 373) @@ -0,0 +1,89 @@ +/* + * Check that we can take an interrupt from the xicu timer0 + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* interrupt in 10 cycles */ + li a0, 10 + sw a0, XICU_PTI_PER(0)(t0) + +1: j 1b + nop + /* we should not end there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + /* we should end there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /trunk/softs/tests_cc_vcache/tmp =================================================================== --- /trunk/softs/tests_cc_vcache/tmp (revision 373) +++ /trunk/softs/tests_cc_vcache/tmp (revision 373) @@ -0,0 +1,72 @@ +-n test_sanity: +-n test_exceptions: +-n test_mmu_basic: +test FAILED +-n test_excep_ls: +test FAILED +-n test_excep_ls_delayslot: +-n test_excep_ls_llsc: +test FAILED +-n test_excep_if: +test FAILED +-n test_excep_if_delayslot: +test FAILED +-n test_excep_if_llsc: +test FAILED +-n test_exception_epc_modify: +-n test_dtlb_inval: +-n test_dtlb_inval2: +test FAILED +-n test_dtlb_inval3: +test FAILED +-n test_itlb_inval: +-n test_itlb_inval2: +test FAILED +-n test_idtlb_inval: +test FAILED +-n test_idtlb_inval2: +test FAILED +-n test_idtlb_inval3: +test FAILED +-n test_idtlb_inval4: +test FAILED +-n test_dtlb_ptprinval: +-n test_itlb_ptprinval: +-n test_idtlb_ptprinval: +test FAILED +-n test_sync: +-n test_sc_update_cache: +-n test_pte_llsc: +test FAILED +-n test_interrupt: +-n test_interrupt_epc_modify: +-n test_xicu_timer: +-n test_interrupt_delayslot: +test FAILED +-n test_interrupt_mask: +-n test_interrupt_external_mask: +-n test_excep_cop: +-n test_excep_cop_delayslot: +-n test_excep_cop1: +-n test_syscall: +-n test_syscall_delayslot: +-n test_breakpoint: +-n test_breakpoint_delayslot: +-n test_ri: +-n test_ri_delayslot: +-n test_ao: +-n test_ao_delayslot: +-n test_trap: +-n test_trap_delayslot: +-n test_fpe: +-n test_fpe_delayslot: +test FAILED +-n test_dcache_inval_pa: +test FAILED +-n test_icache_inval_pa: +test FAILED +-n test_pte2i_ref: +-n test_pte2lw_ref: +-n test_pte2ll_ref: +-n test_pte2sw_dirty: +-n test_pte2sc_dirty: Index: /trunk/softs/tsar_boot/Makefile =================================================================== --- /trunk/softs/tsar_boot/Makefile (revision 373) +++ /trunk/softs/tsar_boot/Makefile (revision 373) @@ -0,0 +1,105 @@ +ifndef PLATFORM_DIR +$(error please define PLATFORM_DIR 'make PLATFORM_DIR=foo') +else + +LD := mipsel-unknown-elf-ld +CC := mipsel-unknown-elf-gcc +AS := mipsel-unknown-elf-as +DU := mipsel-unknown-elf-objdump +RM := rm -rf +ECHO := echo +MKDIR := mkdir +DTC := dtc +HEXDUMP := hexdump + +BUILD_DIR := build +SRCS_DIR := src +INCS_DIR := include + +# ============================================================================= +# Include files paths +# ============================================================================= + +INCLUDE += -I. -I$(INCS_DIR) -I$(PLATFORM_DIR) + +# ============================================================================= +# Paths of sources in another directories +# ============================================================================= + +VPATH += $(SRCS_DIR) +VPATH += $(PLATFORM_DIR) + +# ============================================================================= +# Object files +# ============================================================================= + +CFLAGS := -Wall -mno-gpopt -ffreestanding -fomit-frame-pointer -mips32 \ + -ggdb -mlong-calls + +C_SRCS := boot_elf_loader.c boot_ioc.c boot_memcpy.c boot_tty.c exceptions.c +ifndef SOCLIB +C_SRCS += sdcard.c spi.c +endif + +S_SRCS := reset.S + +OBJS := $(subst .c,.o, $(notdir $(C_SRCS))) +OBJS += $(subst .S,.o, $(notdir $(S_SRCS))) +OBJS := $(addprefix $(BUILD_DIR)/, $(OBJS)) + +TARGET := bin.soft + +ifdef SOCLIB + +DEFS+= -DSOCLIB_IOC +DTS=platform_soclib.dts +$(info Making for $(PLATFORM_DIR), SocLib variant) + +else + +DTS=platform_fpga.dts +$(info Making for $(PLATFORM_DIR), FPGA variant) + +endif + +ifdef SYSCLK_FREQ +DEFS+= -DSYSCLK_FREQ +endif + + +all: $(TARGET) + +$(TARGET): $(BUILD_DIR) $(OBJS) $(PLATFORM_DIR)/ldscript $(BUILD_DIR)/platform.ld + $(ECHO) "[ LD ] $@" + $(LD) -o $@ -T $(PLATFORM_DIR)/ldscript $(OBJS) + $(DU) -D $@ > $@.txt + +$(BUILD_DIR)/platform.ld: $(BUILD_DIR)/platform.dtb + $(HEXDUMP) -v -e '"BYTE(0x" 1/1 "%02X" ")\n"' $< > $@ + +$(BUILD_DIR)/platform.dtb: $(DTS) + ${DTC} -O dtb -o $@ $< + +$(BUILD_DIR): + $(MKDIR) $@ + +clean: + $(RM) $(TARGET).txt $(TARGET) *~ $(BUILD_DIR) + +distclean: clean + +# ============================================================================= +# Implicit makefile rules + +$(BUILD_DIR)/%.o: %.c + $(ECHO) "[ CC ] $(notdir $<)" + $(CC) $(DEFS) $(CFLAGS) $(INCLUDE) -c -o $@ $< + $(DU) -D $@ > $@.txt + +$(BUILD_DIR)/%.o: %.S + $(ECHO) "[ AS ] $(notdir $<)" + $(CC) $(DEFS) ${INCLUDE} -g -mips32 -c -o $@ $< + $(DU) -D $@ > $@.txt + +.SILENT: +endif Index: /trunk/softs/tsar_boot/README.txt =================================================================== --- /trunk/softs/tsar_boot/README.txt (revision 373) +++ /trunk/softs/tsar_boot/README.txt (revision 373) @@ -0,0 +1,74 @@ +TSAR BOOT LOADER + +Files: +=============================================================================== +src/ Source files + The entry point of this boot loader is the file reset.S + +include/ Header files + +conf/ Platform specific files and ldscript. + For each platform, we must define a new directory. + + ---> defs_platform.h: + + This file is mandatory. This file defines the + NB_PROCS per cluster, the NB_CLUSTERS and the base address of + the TTY, IOC and XICU devices. + It defines also: + -> CACHE_COHERENCE + This constant is used by the boot_ioc_read function to know + if the buffer used to store the blocks from the block_device + must be invalidated in the dcache after the transfert has + finished. + 0 means invalidation must be made. + + -> CACHE_LINE_SIZE + This constant defines the size in bytes of a cache line. + + -> IRQ_PER_PROC + This constant is used to know how many XICU irq outputs are + connected to each processor. + + ---> platform_soclib.dts: + + Device tree file. It is mandatory if compiling + for a SOCLIB platform. If the application to execute does not use + a device tree file, create an empty one. + + ---> platform_fpga.dts: + Device tree file. It is mandatory if compiling + for a FPGA platform. If the application to execute does not use + a device tree file, create an empty one. + + ---> ldscript: + LD script defining the segments of this boot loader. + We define two segments: + seg_stack_base: Base address of the stack used by processor 0 + during the boot process. + + seg_boot_base: Base address of the code and data defined for + this loader + +Makefile Makefile for compile the boot loader. + Arguments to pass: + + ---> PLATFORM_DIR=conf/ + + Defines the directory where to find the plateform specific + files + + ---> SOCLIB=1 + + If using SOCLIB, define this flag to use the SOCLIB device + drivers + + ---> SYSCLK_FREQ= + + If not SOCLIB platform, this flag allows us to choose the + CLK frequency used in the hardware platform (i.e. FPGA). + This information is used to configurate the SPI device + which allow us to drive a SD card device. + + i.e. make PLATFORM_DIR=conf/ SYSCLK_FREQ=50000000 + make PLATFORM_DIR=conf/ SOCLIB=1 Index: /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h =================================================================== --- /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h (revision 373) +++ /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h (revision 373) @@ -0,0 +1,12 @@ +#define NB_PROCS 4 +#define NB_CLUSTERS 1 + +#define IRQ_PER_PROC 1 + +#define CACHE_COHERENCE 1 +#define CACHE_LINE_SIZE 64//bytes + +#define IOC_BASE 0xFB000000 +#define VCIBD_BASE 0xFB000000 +#define TTY_BASE 0xFC000000 +#define ICU_BASE 0xFD000000 Index: /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript =================================================================== --- /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript (revision 373) +++ /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript (revision 373) @@ -0,0 +1,29 @@ +/********************************************************** + File : ldscript + Author : Cesar Fuguet + Date : June 2011 +**********************************************************/ + +/* Definition of the base address for all segments */ + +seg_stack_base = 0x00100000; +seg_boot_base = 0xBFC00000; /* le code de boot */ + +/* Grouping sections into segments */ + +ENTRY(boot) +SECTIONS +{ + . = seg_boot_base; + .text : { + *(.boot) + *(.reset) + } + + .data ALIGN(0x4) : { + *(.reset_data) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; + } +} Index: /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts =================================================================== --- /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts (revision 373) +++ /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts (revision 373) @@ -0,0 +1,173 @@ +/dts-v1/; + +/ { + #address-cells = <0x1>; + #size-cells = <0x1>; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + Mips,32@0 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000000>; + }; + + Mips,32@1 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000001>; + }; + + Mips,32@2 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000002>; + }; + + Mips,32@3 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000003>; + }; + }; + + memory@0x00000000 { + cached = <0x1>; + device_type = "memory"; + reg = <0x00000000 0x07e00000>; + }; + + memory@0xbfc00000 { + cached = <0x1>; + device_type = "rom"; + reg = <0xbfc00000 0x00400000>; + }; + + tty@0xfc000000 { + device_type = "vci:tty"; + irq = <&{/xicu@0xfd000000} 0x0>; + reg = <0xfc000000 0x00000010>; + tty_count = <0x1>; + }; + + blockdevice@0xfb000000 { + device_type = "vci:ioc"; + irq = <&{/xicu@0xfd000000} 0x1>; + reg = <0xfb000000 0x00000020>; + }; + + fb@0x07e00000 { + device_type = "vci:vga"; + reg = <0x07e00000 0x200000 + 0xFA000000 0x001000>; + mode = <16>; + width = <640>; + height = <480>; + }; + + xicu@0xfd000000 { + device_type = "soclib:xicu:root"; + input_lines = <0x2>; + ipis = <0x4>; + reg = <0xfd000000 0x00001000>; + timers = <0x4>; + + out@0 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x0>; + output_line = <0x0>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@1 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x1>; + output_line = <0x1>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@2 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x2>; + output_line = <0x2>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@3 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x0>; + output_line = <0x3>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@4 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x1>; + output_line = <0x4>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@5 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x2>; + output_line = <0x5>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@6 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x0>; + output_line = <0x6>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@7 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x1>; + output_line = <0x7>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@8 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x2>; + output_line = <0x8>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@9 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x0>; + output_line = <0x9>; + parent = <&{/xicu@0xfd000000}>; + }; + out@10 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x1>; + output_line = <0xa>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@11 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x2>; + output_line = <0xb>; + parent = <&{/xicu@0xfd000000}>; + }; + + }; + topology { + #address-cells = <2>; + #size-cells = <0>; + cluster@0,0 { + reg = <0 0>; + devices = <&{/cpus/Mips,32@0} &{/cpus/Mips,32@1} &{/cpus/Mips,32@2} &{/cpus/Mips,32@3} &{/xicu@0xfd000000} &{/tty@0xfc000000} &{/blockdevice@0xfb000000} &{/fb@0x07e00000} >; + }; + }; +}; Index: /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts =================================================================== --- /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts (revision 373) +++ /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts (revision 373) @@ -0,0 +1,176 @@ +/dts-v1/; + +/ { + #address-cells = <0x1>; + #size-cells = <0x1>; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + Mips,32@0 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000000>; + }; + + Mips,32@1 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000001>; + }; + + Mips,32@2 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000002>; + }; + + Mips,32@3 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000003>; + }; + }; + + memory@0x00000000 { + cached = <0x1>; + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + memory@0xbfc00000 { + cached = <0x1>; + device_type = "rom"; + reg = <0xbfc00000 0x00400000>; + }; + + tty@0xfc000000 { + device_type = "soclib:tty"; + irq = <&{/xicu@0xfd000000} 0x0>; + reg = <0xfc000000 0x00000010>; + tty_count = <0x1>; + }; + simhelper@0xf1000000 { + device_type = "soclib:simhelper"; + reg = <0xf1000000 0x00000010>; + }; + + blockdevice@0xfb000000 { + device_type = "soclib:blockdevice"; + irq = <&{/xicu@0xfd000000} 0x1>; + reg = <0xfb000000 0x00000020>; + }; + + fb@0xf0000000 { + device_type = "soclib:frame_buffer"; + reg = <0xf0000000 0x400000>; + mode = <32>; + width = <640>; + height = <480>; + }; + + xicu@0xfd000000 { + device_type = "soclib:xicu:root"; + input_lines = <0x2>; + ipis = <0x4>; + reg = <0xfd000000 0x00001000>; + timers = <0x4>; + + out@0 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x0>; + output_line = <0x0>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@1 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x1>; + output_line = <0x1>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@2 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x2>; + output_line = <0x2>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@3 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x0>; + output_line = <0x3>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@4 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x1>; + output_line = <0x4>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@5 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x2>; + output_line = <0x5>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@6 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x0>; + output_line = <0x6>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@7 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x1>; + output_line = <0x7>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@8 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x2>; + output_line = <0x8>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@9 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x0>; + output_line = <0x9>; + parent = <&{/xicu@0xfd000000}>; + }; + out@10 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x1>; + output_line = <0xa>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@11 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x2>; + output_line = <0xb>; + parent = <&{/xicu@0xfd000000}>; + }; + + }; + topology { + #address-cells = <2>; + #size-cells = <0>; + cluster@0,0 { + reg = <0 0>; + devices = <&{/cpus/Mips,32@0} &{/cpus/Mips,32@1} &{/cpus/Mips,32@2} &{/cpus/Mips,32@3} &{/xicu@0xfd000000} &{/tty@0xfc000000} &{/simhelper@0xf1000000} &{/blockdevice@0xfb000000} &{/fb@0xf0000000} >; + }; + }; +}; Index: /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h =================================================================== --- /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h (revision 373) +++ /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h (revision 373) @@ -0,0 +1,12 @@ +#define NB_PROCS 4 +#define NB_CLUSTERS 1 + +#define IRQ_PER_PROC 1 + +#define CACHE_COHERENCE 0 +#define CACHE_LINE_SIZE 16//bytes + +#define ICU_BASE 0x00F00000 +#define IOC_BASE 0x00F10000 +#define VCIBD_BASE IOC_BASE +#define TTY_BASE 0x00F20000 Index: /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/ldscript =================================================================== --- /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/ldscript (revision 373) +++ /trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/ldscript (revision 373) @@ -0,0 +1,29 @@ +/********************************************************** + File : ldscript + Author : Cesar Fuguet + Date : June 2011 +**********************************************************/ + +/* Definition of the base address for all segments */ + +seg_stack_base = 0x00108000; +seg_boot_base = 0xBFC00000; /* le code de boot */ + +/* Grouping sections into segments */ + +ENTRY(boot) +SECTIONS +{ + . = seg_boot_base; + .text : { + *(.boot) + *(.reset) + } + + .data ALIGN(0x4) : { + *(.reset_data) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; + } +} Index: /trunk/softs/tsar_boot/include/block_device.h =================================================================== --- /trunk/softs/tsar_boot/include/block_device.h (revision 373) +++ /trunk/softs/tsar_boot/include/block_device.h (revision 373) @@ -0,0 +1,67 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * Nicolas Pouillon , 2007 + * + * Maintainers: nipo + */ +#ifndef BLOCK_DEVICE_REGS_H +#define BLOCK_DEVICE_REGS_H + +enum SoclibBlockDeviceRegisters { + BLOCK_DEVICE_BUFFER, + BLOCK_DEVICE_LBA, + BLOCK_DEVICE_COUNT, + BLOCK_DEVICE_OP, + BLOCK_DEVICE_STATUS, + BLOCK_DEVICE_IRQ_ENABLE, + BLOCK_DEVICE_SIZE, + BLOCK_DEVICE_BLOCK_SIZE, +}; + +enum SoclibBlockDeviceOp { + BLOCK_DEVICE_NOOP, + BLOCK_DEVICE_READ, + BLOCK_DEVICE_WRITE, +}; + +enum SoclibBlockDeviceStatus { + BLOCK_DEVICE_IDLE, + BLOCK_DEVICE_BUSY, + BLOCK_DEVICE_READ_SUCCESS, + BLOCK_DEVICE_WRITE_SUCCESS, + BLOCK_DEVICE_READ_ERROR, + BLOCK_DEVICE_WRITE_ERROR, + BLOCK_DEVICE_ERROR, +}; + +#endif /* BLOCK_DEVICE_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /trunk/softs/tsar_boot/include/boot_ioc.h =================================================================== --- /trunk/softs/tsar_boot/include/boot_ioc.h (revision 373) +++ /trunk/softs/tsar_boot/include/boot_ioc.h (revision 373) @@ -0,0 +1,65 @@ +#ifndef BOOT_IOC_H +#define BOOT_IOC_H + +#ifndef SOCLIB_IOC + #include + #include +#else + #include +#endif + +#include +#include +#include + +/** + * boot_ioc_read() + * + * Transfer data from a file on the block device to a memory buffer. + * + * \param lba : first block index on the disk + * \param buffer : base address of the memory buffer + * \param count : number of blocks to be transfered + * + * \note This is a blocking function. The function returns once the transfer + * has finished + */ +int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count); + +/** + * boot_ioc_init() + * + * Initialize the SPI controller use to access a SD card + */ +int boot_ioc_init(); + +/** + * boot_dbuf_invalidate() + * + * Invalidate all data cache lines corresponding to a memory buffer. + */ +#if (CACHE_COHERENCE == 0) +void boot_dbuf_invalidate( + const void * buffer, + unsigned int line_size, + unsigned int size); +#endif + +/** + * boot_ioc_write() + * + * Transfer data from a memory buffer to a file on the block_device. + * + * \param lba : first block index on the disk + * \param buffer : base address of the memory buffer + * \param count : number of blocks to be transfered + * + * \note The source buffer must be in user address space. + */ +//int boot_ioc_write(unsigned int lba, void* buffer, unsigned int count); + +#endif + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab + */ Index: /trunk/softs/tsar_boot/include/boot_memcpy.h =================================================================== --- /trunk/softs/tsar_boot/include/boot_memcpy.h (revision 373) +++ /trunk/softs/tsar_boot/include/boot_memcpy.h (revision 373) @@ -0,0 +1,6 @@ +#ifndef BOOT_MEMCPY_H +#define BOOT_MEMCPY_H + +void * boot_memcpy(void *_dst, const void *_src, unsigned int size); + +#endif Index: /trunk/softs/tsar_boot/include/boot_tty.h =================================================================== --- /trunk/softs/tsar_boot/include/boot_tty.h (revision 373) +++ /trunk/softs/tsar_boot/include/boot_tty.h (revision 373) @@ -0,0 +1,14 @@ +#ifndef BOOT_TTY_H +#define BOOT_TTY_H + +#include +#include + +void boot_exit(); +int boot_getc(char * c); +void boot_putc(const char c); +void boot_puts(const char *buffer); +void boot_putx(unsigned int val); +void boot_putd(unsigned int val); + +#endif Index: /trunk/softs/tsar_boot/include/defs.h =================================================================== --- /trunk/softs/tsar_boot/include/defs.h (revision 373) +++ /trunk/softs/tsar_boot/include/defs.h (revision 373) @@ -0,0 +1,8 @@ +#include + +#define BOOT_VERSION 0x00010001 + +#define BOOT_STACK_SIZE 0x8000 /* 32 KB */ +#define BOOT_LOADER_LBA 2 +#define PHDR_ARRAY_SIZE 16 + Index: /trunk/softs/tsar_boot/include/elf-types.h =================================================================== --- /trunk/softs/tsar_boot/include/elf-types.h (revision 373) +++ /trunk/softs/tsar_boot/include/elf-types.h (revision 373) @@ -0,0 +1,2645 @@ +/* This file defines standard ELF types, structures, and macros. + Copyright (C) 1995-2003,2004,2005,2006,2007 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +#ifndef _ELF_TYPES_H +#define _ELF_TYPES_H + +/* Type for a 16-bit quantity. */ +typedef unsigned short Elf32_Half; +typedef unsigned short Elf64_Half; + +/* Types for signed and unsigned 32-bit quantities. */ +typedef unsigned int Elf32_Word; +typedef int Elf32_Sword; +typedef unsigned int Elf64_Word; +typedef int Elf64_Sword; + +/* Types for signed and unsigned 64-bit quantities. */ +typedef unsigned long Elf32_Xword; +typedef long Elf32_Sxword; +typedef unsigned long Elf64_Xword; +typedef long Elf64_Sxword; + +/* Type of addresses. */ +typedef unsigned int Elf32_Addr; +typedef unsigned long Elf64_Addr; + +/* Type of file offsets. */ +typedef unsigned int Elf32_Off; +typedef unsigned long Elf64_Off; + +/* Type for section indices, which are 16-bit quantities. */ +typedef unsigned short Elf32_Section; +typedef unsigned short Elf64_Section; + +/* Type for version symbol information. */ +typedef Elf32_Half Elf32_Versym; +typedef Elf64_Half Elf64_Versym; + + +/* The ELF file header. This appears at the start of every ELF file. */ + +#define EI_NIDENT (16) + +typedef struct +{ + unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ + Elf32_Half e_type; /* Object file type */ + Elf32_Half e_machine; /* Architecture */ + Elf32_Word e_version; /* Object file version */ + Elf32_Addr e_entry; /* Entry point virtual address */ + Elf32_Off e_phoff; /* Program header table file offset */ + Elf32_Off e_shoff; /* Section header table file offset */ + Elf32_Word e_flags; /* Processor-specific flags */ + Elf32_Half e_ehsize; /* ELF header size in bytes */ + Elf32_Half e_phentsize; /* Program header table entry size */ + Elf32_Half e_phnum; /* Program header table entry count */ + Elf32_Half e_shentsize; /* Section header table entry size */ + Elf32_Half e_shnum; /* Section header table entry count */ + Elf32_Half e_shstrndx; /* Section header string table index */ +} Elf32_Ehdr; + +typedef struct +{ + unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ + Elf64_Half e_type; /* Object file type */ + Elf64_Half e_machine; /* Architecture */ + Elf64_Word e_version; /* Object file version */ + Elf64_Addr e_entry; /* Entry point virtual address */ + Elf64_Off e_phoff; /* Program header table file offset */ + Elf64_Off e_shoff; /* Section header table file offset */ + Elf64_Word e_flags; /* Processor-specific flags */ + Elf64_Half e_ehsize; /* ELF header size in bytes */ + Elf64_Half e_phentsize; /* Program header table entry size */ + Elf64_Half e_phnum; /* Program header table entry count */ + Elf64_Half e_shentsize; /* Section header table entry size */ + Elf64_Half e_shnum; /* Section header table entry count */ + Elf64_Half e_shstrndx; /* Section header string table index */ +} Elf64_Ehdr; + +/* Fields in the e_ident array. The EI_* macros are indices into the + array. The macros under each EI_* macro are the values the byte + may have. */ + +#define EI_MAG0 0 /* File identification byte 0 index */ +#define ELFMAG0 0x7f /* Magic number byte 0 */ + +#define EI_MAG1 1 /* File identification byte 1 index */ +#define ELFMAG1 'E' /* Magic number byte 1 */ + +#define EI_MAG2 2 /* File identification byte 2 index */ +#define ELFMAG2 'L' /* Magic number byte 2 */ + +#define EI_MAG3 3 /* File identification byte 3 index */ +#define ELFMAG3 'F' /* Magic number byte 3 */ + +/* Conglomeration of the identification bytes, for easy testing as a word. */ +#define ELFMAG "\177ELF" +#define SELFMAG 4 + +#define EI_CLASS 4 /* File class byte index */ +#define ELFCLASSNONE 0 /* Invalid class */ +#define ELFCLASS32 1 /* 32-bit objects */ +#define ELFCLASS64 2 /* 64-bit objects */ +#define ELFCLASSNUM 3 + +#define EI_DATA 5 /* Data encoding byte index */ +#define ELFDATANONE 0 /* Invalid data encoding */ +#define ELFDATA2LSB 1 /* 2's complement, little endian */ +#define ELFDATA2MSB 2 /* 2's complement, big endian */ +#define ELFDATANUM 3 + +#define EI_VERSION 6 /* File version byte index */ + /* Value must be EV_CURRENT */ + +#define EI_OSABI 7 /* OS ABI identification */ +#define ELFOSABI_NONE 0 /* UNIX System V ABI */ +#define ELFOSABI_SYSV 0 /* Alias. */ +#define ELFOSABI_HPUX 1 /* HP-UX */ +#define ELFOSABI_NETBSD 2 /* NetBSD. */ +#define ELFOSABI_LINUX 3 /* Linux. */ +#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ +#define ELFOSABI_AIX 7 /* IBM AIX. */ +#define ELFOSABI_IRIX 8 /* SGI Irix. */ +#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ +#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ +#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ +#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ +#define ELFOSABI_ARM 97 /* ARM */ +#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ + +#define EI_ABIVERSION 8 /* ABI version */ + +#define EI_PAD 9 /* Byte index of padding bytes */ + +/* Legal values for e_type (object file type). */ + +#define ET_NONE 0 /* No file type */ +#define ET_REL 1 /* Relocatable file */ +#define ET_EXEC 2 /* Executable file */ +#define ET_DYN 3 /* Shared object file */ +#define ET_CORE 4 /* Core file */ +#define ET_NUM 5 /* Number of defined types */ +#define ET_LOOS 0xfe00 /* OS-specific range start */ +#define ET_HIOS 0xfeff /* OS-specific range end */ +#define ET_LOPROC 0xff00 /* Processor-specific range start */ +#define ET_HIPROC 0xffff /* Processor-specific range end */ + +/* Legal values for e_machine (architecture). */ + +#define EM_NONE 0 /* No machine */ +#define EM_M32 1 /* AT&T WE 32100 */ +#define EM_SPARC 2 /* SUN SPARC */ +#define EM_386 3 /* Intel 80386 */ +#define EM_68K 4 /* Motorola m68k family */ +#define EM_88K 5 /* Motorola m88k family */ +#define EM_860 7 /* Intel 80860 */ +#define EM_MIPS 8 /* MIPS R3000 big-endian */ +#define EM_S370 9 /* IBM System/370 */ +#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ + +#define EM_PARISC 15 /* HPPA */ +#define EM_VPP500 17 /* Fujitsu VPP500 */ +#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ +#define EM_960 19 /* Intel 80960 */ +#define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* PowerPC 64-bit */ +#define EM_S390 22 /* IBM S390 */ + +#define EM_V800 36 /* NEC V800 series */ +#define EM_FR20 37 /* Fujitsu FR20 */ +#define EM_RH32 38 /* TRW RH-32 */ +#define EM_RCE 39 /* Motorola RCE */ +#define EM_ARM 40 /* ARM */ +#define EM_FAKE_ALPHA 41 /* Digital Alpha */ +#define EM_SH 42 /* Hitachi SH */ +#define EM_SPARCV9 43 /* SPARC v9 64-bit */ +#define EM_TRICORE 44 /* Siemens Tricore */ +#define EM_ARC 45 /* Argonaut RISC Core */ +#define EM_H8_300 46 /* Hitachi H8/300 */ +#define EM_H8_300H 47 /* Hitachi H8/300H */ +#define EM_H8S 48 /* Hitachi H8S */ +#define EM_H8_500 49 /* Hitachi H8/500 */ +#define EM_IA_64 50 /* Intel Merced */ +#define EM_MIPS_X 51 /* Stanford MIPS-X */ +#define EM_COLDFIRE 52 /* Motorola Coldfire */ +#define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ +#define EM_NDR1 57 /* Denso NDR1 microprocessor */ +#define EM_STARCORE 58 /* Motorola Start*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronic ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ +#define EM_X86_64 62 /* AMD x86-64 architecture */ +#define EM_PDSP 63 /* Sony DSP Processor */ + +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ +#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ +#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ +#define EM_VAX 75 /* Digital VAX */ +#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ +#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ +#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ +#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ +#define EM_HUANY 81 /* Harvard University machine-independent object files */ +#define EM_PRISM 82 /* SiTera Prism */ +#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ +#define EM_FR30 84 /* Fujitsu FR30 */ +#define EM_D10V 85 /* Mitsubishi D10V */ +#define EM_D30V 86 /* Mitsubishi D30V */ +#define EM_V850 87 /* NEC v850 */ +#define EM_M32R 88 /* Mitsubishi M32R */ +#define EM_MN10300 89 /* Matsushita MN10300 */ +#define EM_MN10200 90 /* Matsushita MN10200 */ +#define EM_PJ 91 /* picoJava */ +#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ +#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ +#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ +#define EM_NUM 95 + +/* If it is necessary to assign new unofficial EM_* values, please + pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the + chances of collision with official or non-GNU unofficial values. */ + +#define EM_ALPHA 0x9026 + +/* Legal values for e_version (version). */ + +#define EV_NONE 0 /* Invalid ELF version */ +#define EV_CURRENT 1 /* Current version */ +#define EV_NUM 2 + +/* Section header. */ + +typedef struct +{ + Elf32_Word sh_name; /* Section name (string tbl index) */ + Elf32_Word sh_type; /* Section type */ + Elf32_Word sh_flags; /* Section flags */ + Elf32_Addr sh_addr; /* Section virtual addr at execution */ + Elf32_Off sh_offset; /* Section file offset */ + Elf32_Word sh_size; /* Section size in bytes */ + Elf32_Word sh_link; /* Link to another section */ + Elf32_Word sh_info; /* Additional section information */ + Elf32_Word sh_addralign; /* Section alignment */ + Elf32_Word sh_entsize; /* Entry size if section holds table */ +} Elf32_Shdr; + +typedef struct +{ + Elf64_Word sh_name; /* Section name (string tbl index) */ + Elf64_Word sh_type; /* Section type */ + Elf64_Xword sh_flags; /* Section flags */ + Elf64_Addr sh_addr; /* Section virtual addr at execution */ + Elf64_Off sh_offset; /* Section file offset */ + Elf64_Xword sh_size; /* Section size in bytes */ + Elf64_Word sh_link; /* Link to another section */ + Elf64_Word sh_info; /* Additional section information */ + Elf64_Xword sh_addralign; /* Section alignment */ + Elf64_Xword sh_entsize; /* Entry size if section holds table */ +} Elf64_Shdr; + +/* Special section indices. */ + +#define SHN_UNDEF 0 /* Undefined section */ +#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ +#define SHN_LOPROC 0xff00 /* Start of processor-specific */ +#define SHN_BEFORE 0xff00 /* Order section before all others + (Solaris). */ +#define SHN_AFTER 0xff01 /* Order section after all others + (Solaris). */ +#define SHN_HIPROC 0xff1f /* End of processor-specific */ +#define SHN_LOOS 0xff20 /* Start of OS-specific */ +#define SHN_HIOS 0xff3f /* End of OS-specific */ +#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ +#define SHN_COMMON 0xfff2 /* Associated symbol is common */ +#define SHN_XINDEX 0xffff /* Index is in extra table. */ +#define SHN_HIRESERVE 0xffff /* End of reserved indices */ + +/* Legal values for sh_type (section type). */ + +#define SHT_NULL 0 /* Section header table entry unused */ +#define SHT_PROGBITS 1 /* Program data */ +#define SHT_SYMTAB 2 /* Symbol table */ +#define SHT_STRTAB 3 /* String table */ +#define SHT_RELA 4 /* Relocation entries with addends */ +#define SHT_HASH 5 /* Symbol hash table */ +#define SHT_DYNAMIC 6 /* Dynamic linking information */ +#define SHT_NOTE 7 /* Notes */ +#define SHT_NOBITS 8 /* Program space with no data (bss) */ +#define SHT_REL 9 /* Relocation entries, no addends */ +#define SHT_SHLIB 10 /* Reserved */ +#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ +#define SHT_INIT_ARRAY 14 /* Array of constructors */ +#define SHT_FINI_ARRAY 15 /* Array of destructors */ +#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ +#define SHT_GROUP 17 /* Section group */ +#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ +#define SHT_NUM 19 /* Number of defined types. */ +#define SHT_LOOS 0x60000000 /* Start OS-specific. */ +#define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ +#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ +#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ +#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ +#define SHT_SUNW_move 0x6ffffffa +#define SHT_SUNW_COMDAT 0x6ffffffb +#define SHT_SUNW_syminfo 0x6ffffffc +#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ +#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ +#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ +#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ +#define SHT_HIOS 0x6fffffff /* End OS-specific type */ +#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ +#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ +#define SHT_LOUSER 0x80000000 /* Start of application-specific */ +#define SHT_HIUSER 0x8fffffff /* End of application-specific */ + +/* Legal values for sh_flags (section flags). */ + +#define SHF_WRITE (1 << 0) /* Writable */ +#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ +#define SHF_EXECINSTR (1 << 2) /* Executable */ +#define SHF_MERGE (1 << 4) /* Might be merged */ +#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ +#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ +#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ +#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling + required */ +#define SHF_GROUP (1 << 9) /* Section is member of a group. */ +#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ +#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ +#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ +#define SHF_ORDERED (1 << 30) /* Special ordering requirement + (Solaris). */ +#define SHF_EXCLUDE (1 << 31) /* Section is excluded unless + referenced or allocated (Solaris).*/ + +/* Section group handling. */ +#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ + +/* Symbol table entry. */ + +typedef struct +{ + Elf32_Word st_name; /* Symbol name (string tbl index) */ + Elf32_Addr st_value; /* Symbol value */ + Elf32_Word st_size; /* Symbol size */ + unsigned char st_info; /* Symbol type and binding */ + unsigned char st_other; /* Symbol visibility */ + Elf32_Section st_shndx; /* Section index */ +} Elf32_Sym; + +typedef struct +{ + Elf64_Word st_name; /* Symbol name (string tbl index) */ + unsigned char st_info; /* Symbol type and binding */ + unsigned char st_other; /* Symbol visibility */ + Elf64_Section st_shndx; /* Section index */ + Elf64_Addr st_value; /* Symbol value */ + Elf64_Xword st_size; /* Symbol size */ +} Elf64_Sym; + +/* The syminfo section if available contains additional information about + every dynamic symbol. */ + +typedef struct +{ + Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ + Elf32_Half si_flags; /* Per symbol flags */ +} Elf32_Syminfo; + +typedef struct +{ + Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ + Elf64_Half si_flags; /* Per symbol flags */ +} Elf64_Syminfo; + +/* Possible values for si_boundto. */ +#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ +#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ +#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ + +/* Possible bitmasks for si_flags. */ +#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ +#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ +#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ +#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy + loaded */ +/* Syminfo version values. */ +#define SYMINFO_NONE 0 +#define SYMINFO_CURRENT 1 +#define SYMINFO_NUM 2 + + +/* How to extract and insert information held in the st_info field. */ + +#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) +#define ELF32_ST_TYPE(val) ((val) & 0xf) +#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) + +/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ +#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) +#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) +#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) + +/* Legal values for ST_BIND subfield of st_info (symbol binding). */ + +#define STB_LOCAL 0 /* Local symbol */ +#define STB_GLOBAL 1 /* Global symbol */ +#define STB_WEAK 2 /* Weak symbol */ +#define STB_NUM 3 /* Number of defined types. */ +#define STB_LOOS 10 /* Start of OS-specific */ +#define STB_HIOS 12 /* End of OS-specific */ +#define STB_LOPROC 13 /* Start of processor-specific */ +#define STB_HIPROC 15 /* End of processor-specific */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_NOTYPE 0 /* Symbol type is unspecified */ +#define STT_OBJECT 1 /* Symbol is a data object */ +#define STT_FUNC 2 /* Symbol is a code object */ +#define STT_SECTION 3 /* Symbol associated with a section */ +#define STT_FILE 4 /* Symbol's name is file name */ +#define STT_COMMON 5 /* Symbol is a common data object */ +#define STT_TLS 6 /* Symbol is thread-local data object*/ +#define STT_NUM 7 /* Number of defined types. */ +#define STT_LOOS 10 /* Start of OS-specific */ +#define STT_HIOS 12 /* End of OS-specific */ +#define STT_LOPROC 13 /* Start of processor-specific */ +#define STT_HIPROC 15 /* End of processor-specific */ + + +/* Symbol table indices are found in the hash buckets and chain table + of a symbol hash table section. This special index value indicates + the end of a chain, meaning no further symbols are found in that bucket. */ + +#define STN_UNDEF 0 /* End of a chain. */ + + +/* How to extract and insert information held in the st_other field. */ + +#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) + +/* For ELF64 the definitions are the same. */ +#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) + +/* Symbol visibility specification encoded in the st_other field. */ +#define STV_DEFAULT 0 /* Default symbol visibility rules */ +#define STV_INTERNAL 1 /* Processor specific hidden class */ +#define STV_HIDDEN 2 /* Sym unavailable in other modules */ +#define STV_PROTECTED 3 /* Not preemptible, not exported */ + + +/* Relocation table entry without addend (in section of type SHT_REL). */ + +typedef struct +{ + Elf32_Addr r_offset; /* Address */ + Elf32_Word r_info; /* Relocation type and symbol index */ +} Elf32_Rel; + +/* I have seen two different definitions of the Elf64_Rel and + Elf64_Rela structures, so we'll leave them out until Novell (or + whoever) gets their act together. */ +/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ + +typedef struct +{ + Elf64_Addr r_offset; /* Address */ + Elf64_Xword r_info; /* Relocation type and symbol index */ +} Elf64_Rel; + +/* Relocation table entry with addend (in section of type SHT_RELA). */ + +typedef struct +{ + Elf32_Addr r_offset; /* Address */ + Elf32_Word r_info; /* Relocation type and symbol index */ + Elf32_Sword r_addend; /* Addend */ +} Elf32_Rela; + +typedef struct +{ + Elf64_Addr r_offset; /* Address */ + Elf64_Xword r_info; /* Relocation type and symbol index */ + Elf64_Sxword r_addend; /* Addend */ +} Elf64_Rela; + +/* How to extract and insert information held in the r_info field. */ + +#define ELF32_R_SYM(val) ((val) >> 8) +#define ELF32_R_TYPE(val) ((val) & 0xff) +#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) + +#define ELF64_R_SYM(i) ((i) >> 32) +#define ELF64_R_TYPE(i) ((i) & 0xffffffff) +#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) + +/* Program segment header. */ + +typedef struct +{ + Elf32_Word p_type; /* Segment type */ + Elf32_Off p_offset; /* Segment file offset */ + Elf32_Addr p_vaddr; /* Segment virtual address */ + Elf32_Addr p_paddr; /* Segment physical address */ + Elf32_Word p_filesz; /* Segment size in file */ + Elf32_Word p_memsz; /* Segment size in memory */ + Elf32_Word p_flags; /* Segment flags */ + Elf32_Word p_align; /* Segment alignment */ +} Elf32_Phdr; + +typedef struct +{ + Elf64_Word p_type; /* Segment type */ + Elf64_Word p_flags; /* Segment flags */ + Elf64_Off p_offset; /* Segment file offset */ + Elf64_Addr p_vaddr; /* Segment virtual address */ + Elf64_Addr p_paddr; /* Segment physical address */ + Elf64_Xword p_filesz; /* Segment size in file */ + Elf64_Xword p_memsz; /* Segment size in memory */ + Elf64_Xword p_align; /* Segment alignment */ +} Elf64_Phdr; + +/* Legal values for p_type (segment type). */ + +#define PT_NULL 0 /* Program header table entry unused */ +#define PT_LOAD 1 /* Loadable program segment */ +#define PT_DYNAMIC 2 /* Dynamic linking information */ +#define PT_INTERP 3 /* Program interpreter */ +#define PT_NOTE 4 /* Auxiliary information */ +#define PT_SHLIB 5 /* Reserved */ +#define PT_PHDR 6 /* Entry for header table itself */ +#define PT_TLS 7 /* Thread-local storage segment */ +#define PT_NUM 8 /* Number of defined types */ +#define PT_LOOS 0x60000000 /* Start of OS-specific */ +#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ +#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ +#define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ +#define PT_LOSUNW 0x6ffffffa +#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ +#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ +#define PT_HISUNW 0x6fffffff +#define PT_HIOS 0x6fffffff /* End of OS-specific */ +#define PT_LOPROC 0x70000000 /* Start of processor-specific */ +#define PT_HIPROC 0x7fffffff /* End of processor-specific */ + +/* Legal values for p_flags (segment flags). */ + +#define PF_X (1 << 0) /* Segment is executable */ +#define PF_W (1 << 1) /* Segment is writable */ +#define PF_R (1 << 2) /* Segment is readable */ +#define PF_MASKOS 0x0ff00000 /* OS-specific */ +#define PF_MASKPROC 0xf0000000 /* Processor-specific */ + +/* Legal values for note segment descriptor types for core files. */ + +#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ +#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ +#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ +#define NT_PRXREG 4 /* Contains copy of prxregset struct */ +#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ +#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ +#define NT_AUXV 6 /* Contains copy of auxv array */ +#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ +#define NT_ASRS 8 /* Contains copy of asrset struct */ +#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ +#define NT_PSINFO 13 /* Contains copy of psinfo struct */ +#define NT_PRCRED 14 /* Contains copy of prcred struct */ +#define NT_UTSNAME 15 /* Contains copy of utsname struct */ +#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ +#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ +#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ +#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ + +/* Legal values for the note segment descriptor types for object files. */ + +#define NT_VERSION 1 /* Contains a version string. */ + + +/* Dynamic section entry. */ + +typedef struct +{ + Elf32_Sword d_tag; /* Dynamic entry type */ + union + { + Elf32_Word d_val; /* Integer value */ + Elf32_Addr d_ptr; /* Address value */ + } d_un; +} Elf32_Dyn; + +typedef struct +{ + Elf64_Sxword d_tag; /* Dynamic entry type */ + union + { + Elf64_Xword d_val; /* Integer value */ + Elf64_Addr d_ptr; /* Address value */ + } d_un; +} Elf64_Dyn; + +/* Legal values for d_tag (dynamic entry type). */ + +#define DT_NULL 0 /* Marks end of dynamic section */ +#define DT_NEEDED 1 /* Name of needed library */ +#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ +#define DT_PLTGOT 3 /* Processor defined value */ +#define DT_HASH 4 /* Address of symbol hash table */ +#define DT_STRTAB 5 /* Address of string table */ +#define DT_SYMTAB 6 /* Address of symbol table */ +#define DT_RELA 7 /* Address of Rela relocs */ +#define DT_RELASZ 8 /* Total size of Rela relocs */ +#define DT_RELAENT 9 /* Size of one Rela reloc */ +#define DT_STRSZ 10 /* Size of string table */ +#define DT_SYMENT 11 /* Size of one symbol table entry */ +#define DT_INIT 12 /* Address of init function */ +#define DT_FINI 13 /* Address of termination function */ +#define DT_SONAME 14 /* Name of shared object */ +#define DT_RPATH 15 /* Library search path (deprecated) */ +#define DT_SYMBOLIC 16 /* Start symbol search here */ +#define DT_REL 17 /* Address of Rel relocs */ +#define DT_RELSZ 18 /* Total size of Rel relocs */ +#define DT_RELENT 19 /* Size of one Rel reloc */ +#define DT_PLTREL 20 /* Type of reloc in PLT */ +#define DT_DEBUG 21 /* For debugging; unspecified */ +#define DT_TEXTREL 22 /* Reloc might modify .text */ +#define DT_JMPREL 23 /* Address of PLT relocs */ +#define DT_BIND_NOW 24 /* Process relocations of object */ +#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ +#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ +#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ +#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ +#define DT_RUNPATH 29 /* Library search path */ +#define DT_FLAGS 30 /* Flags for the object being loaded */ +#define DT_ENCODING 32 /* Start of encoded range */ +#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ +#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ +#define DT_NUM 34 /* Number used */ +#define DT_LOOS 0x6000000d /* Start of OS-specific */ +#define DT_HIOS 0x6ffff000 /* End of OS-specific */ +#define DT_LOPROC 0x70000000 /* Start of processor-specific */ +#define DT_HIPROC 0x7fffffff /* End of processor-specific */ +#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ + +/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the + Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's + approach. */ +#define DT_VALRNGLO 0x6ffffd00 +#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ +#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ +#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ +#define DT_CHECKSUM 0x6ffffdf8 +#define DT_PLTPADSZ 0x6ffffdf9 +#define DT_MOVEENT 0x6ffffdfa +#define DT_MOVESZ 0x6ffffdfb +#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ +#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting + the following DT_* entry. */ +#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ +#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ +#define DT_VALRNGHI 0x6ffffdff +#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ +#define DT_VALNUM 12 + +/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the + Dyn.d_un.d_ptr field of the Elf*_Dyn structure. + + If any adjustment is made to the ELF object after it has been + built these entries will need to be adjusted. */ +#define DT_ADDRRNGLO 0x6ffffe00 +#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ +#define DT_TLSDESC_PLT 0x6ffffef6 +#define DT_TLSDESC_GOT 0x6ffffef7 +#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ +#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ +#define DT_CONFIG 0x6ffffefa /* Configuration information. */ +#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ +#define DT_AUDIT 0x6ffffefc /* Object auditing. */ +#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ +#define DT_MOVETAB 0x6ffffefe /* Move table. */ +#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ +#define DT_ADDRRNGHI 0x6ffffeff +#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ +#define DT_ADDRNUM 11 + +/* The versioning entry types. The next are defined as part of the + GNU extension. */ +#define DT_VERSYM 0x6ffffff0 + +#define DT_RELACOUNT 0x6ffffff9 +#define DT_RELCOUNT 0x6ffffffa + +/* These were chosen by Sun. */ +#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ +#define DT_VERDEF 0x6ffffffc /* Address of version definition + table */ +#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ +#define DT_VERNEED 0x6ffffffe /* Address of table with needed + versions */ +#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ +#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ +#define DT_VERSIONTAGNUM 16 + +/* Sun added these machine-independent extensions in the "processor-specific" + range. Be compatible. */ +#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ +#define DT_FILTER 0x7fffffff /* Shared object to get values from */ +#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) +#define DT_EXTRANUM 3 + +/* Values of `d_un.d_val' in the DT_FLAGS entry. */ +#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ +#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ +#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ +#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ +#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ + +/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 + entry in the dynamic section. */ +#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ +#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ +#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ +#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ +#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ +#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ +#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ +#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ +#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ +#define DF_1_TRANS 0x00000200 +#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ +#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ +#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ +#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ +#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ +#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ +#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ + +/* Flags for the feature selection in DT_FEATURE_1. */ +#define DTF_1_PARINIT 0x00000001 +#define DTF_1_CONFEXP 0x00000002 + +/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ +#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ +#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not + generally available. */ + +/* Version definition sections. */ + +typedef struct +{ + Elf32_Half vd_version; /* Version revision */ + Elf32_Half vd_flags; /* Version information */ + Elf32_Half vd_ndx; /* Version Index */ + Elf32_Half vd_cnt; /* Number of associated aux entries */ + Elf32_Word vd_hash; /* Version name hash value */ + Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ + Elf32_Word vd_next; /* Offset in bytes to next verdef + entry */ +} Elf32_Verdef; + +typedef struct +{ + Elf64_Half vd_version; /* Version revision */ + Elf64_Half vd_flags; /* Version information */ + Elf64_Half vd_ndx; /* Version Index */ + Elf64_Half vd_cnt; /* Number of associated aux entries */ + Elf64_Word vd_hash; /* Version name hash value */ + Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ + Elf64_Word vd_next; /* Offset in bytes to next verdef + entry */ +} Elf64_Verdef; + + +/* Legal values for vd_version (version revision). */ +#define VER_DEF_NONE 0 /* No version */ +#define VER_DEF_CURRENT 1 /* Current version */ +#define VER_DEF_NUM 2 /* Given version number */ + +/* Legal values for vd_flags (version information flags). */ +#define VER_FLG_BASE 0x1 /* Version definition of file itself */ +#define VER_FLG_WEAK 0x2 /* Weak version identifier */ + +/* Versym symbol index values. */ +#define VER_NDX_LOCAL 0 /* Symbol is local. */ +#define VER_NDX_GLOBAL 1 /* Symbol is global. */ +#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ +#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ + +/* Auxialiary version information. */ + +typedef struct +{ + Elf32_Word vda_name; /* Version or dependency names */ + Elf32_Word vda_next; /* Offset in bytes to next verdaux + entry */ +} Elf32_Verdaux; + +typedef struct +{ + Elf64_Word vda_name; /* Version or dependency names */ + Elf64_Word vda_next; /* Offset in bytes to next verdaux + entry */ +} Elf64_Verdaux; + + +/* Version dependency section. */ + +typedef struct +{ + Elf32_Half vn_version; /* Version of structure */ + Elf32_Half vn_cnt; /* Number of associated aux entries */ + Elf32_Word vn_file; /* Offset of filename for this + dependency */ + Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ + Elf32_Word vn_next; /* Offset in bytes to next verneed + entry */ +} Elf32_Verneed; + +typedef struct +{ + Elf64_Half vn_version; /* Version of structure */ + Elf64_Half vn_cnt; /* Number of associated aux entries */ + Elf64_Word vn_file; /* Offset of filename for this + dependency */ + Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ + Elf64_Word vn_next; /* Offset in bytes to next verneed + entry */ +} Elf64_Verneed; + + +/* Legal values for vn_version (version revision). */ +#define VER_NEED_NONE 0 /* No version */ +#define VER_NEED_CURRENT 1 /* Current version */ +#define VER_NEED_NUM 2 /* Given version number */ + +/* Auxiliary needed version information. */ + +typedef struct +{ + Elf32_Word vna_hash; /* Hash value of dependency name */ + Elf32_Half vna_flags; /* Dependency specific information */ + Elf32_Half vna_other; /* Unused */ + Elf32_Word vna_name; /* Dependency name string offset */ + Elf32_Word vna_next; /* Offset in bytes to next vernaux + entry */ +} Elf32_Vernaux; + +typedef struct +{ + Elf64_Word vna_hash; /* Hash value of dependency name */ + Elf64_Half vna_flags; /* Dependency specific information */ + Elf64_Half vna_other; /* Unused */ + Elf64_Word vna_name; /* Dependency name string offset */ + Elf64_Word vna_next; /* Offset in bytes to next vernaux + entry */ +} Elf64_Vernaux; + + +/* Legal values for vna_flags. */ +#define VER_FLG_WEAK 0x2 /* Weak version identifier */ + + +/* Auxiliary vector. */ + +/* This vector is normally only used by the program interpreter. The + usual definition in an ABI supplement uses the name auxv_t. The + vector is not usually defined in a standard file, but it + can't hurt. We rename it to avoid conflicts. The sizes of these + types are an arrangement between the exec server and the program + interpreter, so we don't fully specify them here. */ + +typedef struct +{ + unsigned int a_type; /* Entry type */ + union + { + unsigned int a_val; /* Integer value */ + /* We use to have pointer elements added here. We cannot do that, + though, since it does not work when using 32-bit definitions + on 64-bit platforms and vice versa. */ + } a_un; +} Elf32_auxv_t; + +typedef struct +{ + unsigned long a_type; /* Entry type */ + union + { + unsigned long a_val; /* Integer value */ + /* We use to have pointer elements added here. We cannot do that, + though, since it does not work when using 32-bit definitions + on 64-bit platforms and vice versa. */ + } a_un; +} Elf64_auxv_t; + +/* Legal values for a_type (entry type). */ + +#define AT_NULL 0 /* End of vector */ +#define AT_IGNORE 1 /* Entry should be ignored */ +#define AT_EXECFD 2 /* File descriptor of program */ +#define AT_PHDR 3 /* Program headers for program */ +#define AT_PHENT 4 /* Size of program header entry */ +#define AT_PHNUM 5 /* Number of program headers */ +#define AT_PAGESZ 6 /* System page size */ +#define AT_BASE 7 /* Base address of interpreter */ +#define AT_FLAGS 8 /* Flags */ +#define AT_ENTRY 9 /* Entry point of program */ +#define AT_NOTELF 10 /* Program is not ELF */ +#define AT_UID 11 /* Real uid */ +#define AT_EUID 12 /* Effective uid */ +#define AT_GID 13 /* Real gid */ +#define AT_EGID 14 /* Effective gid */ +#define AT_CLKTCK 17 /* Frequency of times() */ + +/* Some more special a_type values describing the hardware. */ +#define AT_PLATFORM 15 /* String identifying platform. */ +#define AT_HWCAP 16 /* Machine dependent hints about + processor capabilities. */ + +/* This entry gives some information about the FPU initialization + performed by the kernel. */ +#define AT_FPUCW 18 /* Used FPU control word. */ + +/* Cache block sizes. */ +#define AT_DCACHEBSIZE 19 /* Data cache block size. */ +#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ +#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ + +/* A special ignored value for PPC, used by the kernel to control the + interpretation of the AUXV. Must be > 16. */ +#define AT_IGNOREPPC 22 /* Entry should be ignored. */ + +#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ + +/* Pointer to the global system page used for system calls and other + nice things. */ +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 + +/* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains + log2 of line size; mask those to get cache size. */ +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 +#define AT_L3_CACHESHAPE 37 + +/* Note section contents. Each entry in the note section begins with + a header of a fixed form. */ + +typedef struct +{ + Elf32_Word n_namesz; /* Length of the note's name. */ + Elf32_Word n_descsz; /* Length of the note's descriptor. */ + Elf32_Word n_type; /* Type of the note. */ +} Elf32_Nhdr; + +typedef struct +{ + Elf64_Word n_namesz; /* Length of the note's name. */ + Elf64_Word n_descsz; /* Length of the note's descriptor. */ + Elf64_Word n_type; /* Type of the note. */ +} Elf64_Nhdr; + +/* Known names of notes. */ + +/* Solaris entries in the note section have this name. */ +#define ELF_NOTE_SOLARIS "SUNW Solaris" + +/* Note entries for GNU systems have this name. */ +#define ELF_NOTE_GNU "GNU" + + +/* Defined types of notes for Solaris. */ + +/* Value of descriptor (one word) is desired pagesize for the binary. */ +#define ELF_NOTE_PAGESIZE_HINT 1 + + +/* Defined note types for GNU systems. */ + +/* ABI information. The descriptor consists of words: + word 0: OS descriptor + word 1: major version of the ABI + word 2: minor version of the ABI + word 3: subminor version of the ABI +*/ +#define NT_GNU_ABI_TAG 1 +#define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ + +/* Known OSes. These values can appear in word 0 of an + NT_GNU_ABI_TAG note section entry. */ +#define ELF_NOTE_OS_LINUX 0 +#define ELF_NOTE_OS_GNU 1 +#define ELF_NOTE_OS_SOLARIS2 2 +#define ELF_NOTE_OS_FREEBSD 3 + +/* Synthetic hwcap information. The descriptor begins with two words: + word 0: number of entries + word 1: bitmask of enabled entries + Then follow variable-length entries, one byte followed by a + '\0'-terminated hwcap name string. The byte gives the bit + number to test if enabled, (1U << bit) & bitmask. */ +#define NT_GNU_HWCAP 2 + +/* Build ID bits as generated by ld --build-id. + The descriptor consists of any nonzero number of bytes. */ +#define NT_GNU_BUILD_ID 3 + + +/* Move records. */ +typedef struct +{ + Elf32_Xword m_value; /* Symbol value. */ + Elf32_Word m_info; /* Size and index. */ + Elf32_Word m_poffset; /* Symbol offset. */ + Elf32_Half m_repeat; /* Repeat count. */ + Elf32_Half m_stride; /* Stride info. */ +} Elf32_Move; + +typedef struct +{ + Elf64_Xword m_value; /* Symbol value. */ + Elf64_Xword m_info; /* Size and index. */ + Elf64_Xword m_poffset; /* Symbol offset. */ + Elf64_Half m_repeat; /* Repeat count. */ + Elf64_Half m_stride; /* Stride info. */ +} Elf64_Move; + +/* Macro to construct move records. */ +#define ELF32_M_SYM(info) ((info) >> 8) +#define ELF32_M_SIZE(info) ((unsigned char) (info)) +#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) + +#define ELF64_M_SYM(info) ELF32_M_SYM (info) +#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) +#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) + + +/* Motorola 68k specific definitions. */ + +/* Values for Elf32_Ehdr.e_flags. */ +#define EF_CPU32 0x00810000 + +/* m68k relocs. */ + +#define R_68K_NONE 0 /* No reloc */ +#define R_68K_32 1 /* Direct 32 bit */ +#define R_68K_16 2 /* Direct 16 bit */ +#define R_68K_8 3 /* Direct 8 bit */ +#define R_68K_PC32 4 /* PC relative 32 bit */ +#define R_68K_PC16 5 /* PC relative 16 bit */ +#define R_68K_PC8 6 /* PC relative 8 bit */ +#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ +#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ +#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ +#define R_68K_GOT32O 10 /* 32 bit GOT offset */ +#define R_68K_GOT16O 11 /* 16 bit GOT offset */ +#define R_68K_GOT8O 12 /* 8 bit GOT offset */ +#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ +#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ +#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ +#define R_68K_PLT32O 16 /* 32 bit PLT offset */ +#define R_68K_PLT16O 17 /* 16 bit PLT offset */ +#define R_68K_PLT8O 18 /* 8 bit PLT offset */ +#define R_68K_COPY 19 /* Copy symbol at runtime */ +#define R_68K_GLOB_DAT 20 /* Create GOT entry */ +#define R_68K_JMP_SLOT 21 /* Create PLT entry */ +#define R_68K_RELATIVE 22 /* Adjust by program base */ +/* Keep this the last entry. */ +#define R_68K_NUM 23 + +/* Intel 80386 specific definitions. */ + +/* i386 relocs. */ + +#define R_386_NONE 0 /* No reloc */ +#define R_386_32 1 /* Direct 32 bit */ +#define R_386_PC32 2 /* PC relative 32 bit */ +#define R_386_GOT32 3 /* 32 bit GOT entry */ +#define R_386_PLT32 4 /* 32 bit PLT address */ +#define R_386_COPY 5 /* Copy symbol at runtime */ +#define R_386_GLOB_DAT 6 /* Create GOT entry */ +#define R_386_JMP_SLOT 7 /* Create PLT entry */ +#define R_386_RELATIVE 8 /* Adjust by program base */ +#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ +#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ +#define R_386_32PLT 11 +#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ +#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS + block offset */ +#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block + offset */ +#define R_386_TLS_LE 17 /* Offset relative to static TLS + block */ +#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of + general dynamic thread local data */ +#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of + local dynamic thread local data + in LE code */ +#define R_386_16 20 +#define R_386_PC16 21 +#define R_386_8 22 +#define R_386_PC8 23 +#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic + thread local data */ +#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ +#define R_386_TLS_GD_CALL 26 /* Relocation for call to + __tls_get_addr() */ +#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ +#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic + thread local data in LE code */ +#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ +#define R_386_TLS_LDM_CALL 30 /* Relocation for call to + __tls_get_addr() in LDM code */ +#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ +#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ +#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS + block offset */ +#define R_386_TLS_LE_32 34 /* Negated offset relative to static + TLS block */ +#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ +#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ +#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ +/* Keep this the last entry. */ +#define R_386_NUM 38 + +/* SUN SPARC specific definitions. */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ + +/* Values for Elf64_Ehdr.e_flags. */ + +#define EF_SPARCV9_MM 3 +#define EF_SPARCV9_TSO 0 +#define EF_SPARCV9_PSO 1 +#define EF_SPARCV9_RMO 2 +#define EF_SPARC_LEDATA 0x800000 /* little endian data */ +#define EF_SPARC_EXT_MASK 0xFFFF00 +#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ +#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ +#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ +#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ + +/* SPARC relocs. */ + +#define R_SPARC_NONE 0 /* No reloc */ +#define R_SPARC_8 1 /* Direct 8 bit */ +#define R_SPARC_16 2 /* Direct 16 bit */ +#define R_SPARC_32 3 /* Direct 32 bit */ +#define R_SPARC_DISP8 4 /* PC relative 8 bit */ +#define R_SPARC_DISP16 5 /* PC relative 16 bit */ +#define R_SPARC_DISP32 6 /* PC relative 32 bit */ +#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ +#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ +#define R_SPARC_HI22 9 /* High 22 bit */ +#define R_SPARC_22 10 /* Direct 22 bit */ +#define R_SPARC_13 11 /* Direct 13 bit */ +#define R_SPARC_LO10 12 /* Truncated 10 bit */ +#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ +#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ +#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ +#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ +#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ +#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ +#define R_SPARC_COPY 19 /* Copy symbol at runtime */ +#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ +#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ +#define R_SPARC_RELATIVE 22 /* Adjust by program base */ +#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ + +/* Additional Sparc64 relocs. */ + +#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ +#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ +#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ +#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ +#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ +#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ +#define R_SPARC_10 30 /* Direct 10 bit */ +#define R_SPARC_11 31 /* Direct 11 bit */ +#define R_SPARC_64 32 /* Direct 64 bit */ +#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ +#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ +#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ +#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ +#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ +#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ +#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ +#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ +#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ +#define R_SPARC_7 43 /* Direct 7 bit */ +#define R_SPARC_5 44 /* Direct 5 bit */ +#define R_SPARC_6 45 /* Direct 6 bit */ +#define R_SPARC_DISP64 46 /* PC relative 64 bit */ +#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ +#define R_SPARC_HIX22 48 /* High 22 bit complemented */ +#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ +#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ +#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ +#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ +#define R_SPARC_REGISTER 53 /* Global register usage */ +#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ +#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ +#define R_SPARC_TLS_GD_HI22 56 +#define R_SPARC_TLS_GD_LO10 57 +#define R_SPARC_TLS_GD_ADD 58 +#define R_SPARC_TLS_GD_CALL 59 +#define R_SPARC_TLS_LDM_HI22 60 +#define R_SPARC_TLS_LDM_LO10 61 +#define R_SPARC_TLS_LDM_ADD 62 +#define R_SPARC_TLS_LDM_CALL 63 +#define R_SPARC_TLS_LDO_HIX22 64 +#define R_SPARC_TLS_LDO_LOX10 65 +#define R_SPARC_TLS_LDO_ADD 66 +#define R_SPARC_TLS_IE_HI22 67 +#define R_SPARC_TLS_IE_LO10 68 +#define R_SPARC_TLS_IE_LD 69 +#define R_SPARC_TLS_IE_LDX 70 +#define R_SPARC_TLS_IE_ADD 71 +#define R_SPARC_TLS_LE_HIX22 72 +#define R_SPARC_TLS_LE_LOX10 73 +#define R_SPARC_TLS_DTPMOD32 74 +#define R_SPARC_TLS_DTPMOD64 75 +#define R_SPARC_TLS_DTPOFF32 76 +#define R_SPARC_TLS_DTPOFF64 77 +#define R_SPARC_TLS_TPOFF32 78 +#define R_SPARC_TLS_TPOFF64 79 +/* Keep this the last entry. */ +#define R_SPARC_NUM 80 + +/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ + +#define DT_SPARC_REGISTER 0x70000001 +#define DT_SPARC_NUM 2 + +/* Bits present in AT_HWCAP on SPARC. */ + +#define HWCAP_SPARC_FLUSH 1 /* The CPU supports flush insn. */ +#define HWCAP_SPARC_STBAR 2 +#define HWCAP_SPARC_SWAP 4 +#define HWCAP_SPARC_MULDIV 8 +#define HWCAP_SPARC_V9 16 /* The CPU is v9, so v8plus is ok. */ +#define HWCAP_SPARC_ULTRA3 32 +#define HWCAP_SPARC_BLKINIT 64 /* Sun4v with block-init/load-twin. */ +#define HWCAP_SPARC_N2 128 + +/* MIPS R3000 specific definitions. */ + +/* Legal values for e_flags field of Elf32_Ehdr. */ + +#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ +#define EF_MIPS_PIC 2 /* Contains PIC code */ +#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ +#define EF_MIPS_XGOT 8 +#define EF_MIPS_64BIT_WHIRL 16 +#define EF_MIPS_ABI2 32 +#define EF_MIPS_ABI_ON32 64 +#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ + +/* Legal values for MIPS architecture level. */ + +#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ +#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ +#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ +#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ +#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ +#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ +#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ + +/* The following are non-official names and should not be used. */ + +#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ +#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ +#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ +#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ +#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ +#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ +#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ + +/* Special section indices. */ + +#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ +#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ +#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ +#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ +#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ + +/* Legal values for sh_type field of Elf32_Shdr. */ + +#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ +#define SHT_MIPS_MSYM 0x70000001 +#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ +#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ +#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ +#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ +#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ +#define SHT_MIPS_PACKAGE 0x70000007 +#define SHT_MIPS_PACKSYM 0x70000008 +#define SHT_MIPS_RELD 0x70000009 +#define SHT_MIPS_IFACE 0x7000000b +#define SHT_MIPS_CONTENT 0x7000000c +#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ +#define SHT_MIPS_SHDR 0x70000010 +#define SHT_MIPS_FDESC 0x70000011 +#define SHT_MIPS_EXTSYM 0x70000012 +#define SHT_MIPS_DENSE 0x70000013 +#define SHT_MIPS_PDESC 0x70000014 +#define SHT_MIPS_LOCSYM 0x70000015 +#define SHT_MIPS_AUXSYM 0x70000016 +#define SHT_MIPS_OPTSYM 0x70000017 +#define SHT_MIPS_LOCSTR 0x70000018 +#define SHT_MIPS_LINE 0x70000019 +#define SHT_MIPS_RFDESC 0x7000001a +#define SHT_MIPS_DELTASYM 0x7000001b +#define SHT_MIPS_DELTAINST 0x7000001c +#define SHT_MIPS_DELTACLASS 0x7000001d +#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ +#define SHT_MIPS_DELTADECL 0x7000001f +#define SHT_MIPS_SYMBOL_LIB 0x70000020 +#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ +#define SHT_MIPS_TRANSLATE 0x70000022 +#define SHT_MIPS_PIXIE 0x70000023 +#define SHT_MIPS_XLATE 0x70000024 +#define SHT_MIPS_XLATE_DEBUG 0x70000025 +#define SHT_MIPS_WHIRL 0x70000026 +#define SHT_MIPS_EH_REGION 0x70000027 +#define SHT_MIPS_XLATE_OLD 0x70000028 +#define SHT_MIPS_PDR_EXCEPTION 0x70000029 + +/* Legal values for sh_flags field of Elf32_Shdr. */ + +#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ +#define SHF_MIPS_MERGE 0x20000000 +#define SHF_MIPS_ADDR 0x40000000 +#define SHF_MIPS_STRINGS 0x80000000 +#define SHF_MIPS_NOSTRIP 0x08000000 +#define SHF_MIPS_LOCAL 0x04000000 +#define SHF_MIPS_NAMES 0x02000000 +#define SHF_MIPS_NODUPE 0x01000000 + + +/* Symbol tables. */ + +/* MIPS specific values for `st_other'. */ +#define STO_MIPS_DEFAULT 0x0 +#define STO_MIPS_INTERNAL 0x1 +#define STO_MIPS_HIDDEN 0x2 +#define STO_MIPS_PROTECTED 0x3 +#define STO_MIPS_SC_ALIGN_UNUSED 0xff + +/* MIPS specific values for `st_info'. */ +#define STB_MIPS_SPLIT_COMMON 13 + +/* Entries found in sections of type SHT_MIPS_GPTAB. */ + +typedef union +{ + struct + { + Elf32_Word gt_current_g_value; /* -G value used for compilation */ + Elf32_Word gt_unused; /* Not used */ + } gt_header; /* First entry in section */ + struct + { + Elf32_Word gt_g_value; /* If this value were used for -G */ + Elf32_Word gt_bytes; /* This many bytes would be used */ + } gt_entry; /* Subsequent entries in section */ +} Elf32_gptab; + +/* Entry found in sections of type SHT_MIPS_REGINFO. */ + +typedef struct +{ + Elf32_Word ri_gprmask; /* General registers used */ + Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ + Elf32_Sword ri_gp_value; /* $gp register value */ +} Elf32_RegInfo; + +/* Entries found in sections of type SHT_MIPS_OPTIONS. */ + +typedef struct +{ + unsigned char kind; /* Determines interpretation of the + variable part of descriptor. */ + unsigned char size; /* Size of descriptor, including header. */ + Elf32_Section section; /* Section header index of section affected, + 0 for global options. */ + Elf32_Word info; /* Kind-specific information. */ +} Elf_Options; + +/* Values for `kind' field in Elf_Options. */ + +#define ODK_NULL 0 /* Undefined. */ +#define ODK_REGINFO 1 /* Register usage information. */ +#define ODK_EXCEPTIONS 2 /* Exception processing options. */ +#define ODK_PAD 3 /* Section padding options. */ +#define ODK_HWPATCH 4 /* Hardware workarounds performed */ +#define ODK_FILL 5 /* record the fill value used by the linker. */ +#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ +#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ +#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ + +/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ + +#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ +#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ +#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ +#define OEX_SMM 0x20000 /* Force sequential memory mode? */ +#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ +#define OEX_PRECISEFP OEX_FPDBUG +#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ + +#define OEX_FPU_INVAL 0x10 +#define OEX_FPU_DIV0 0x08 +#define OEX_FPU_OFLO 0x04 +#define OEX_FPU_UFLO 0x02 +#define OEX_FPU_INEX 0x01 + +/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ + +#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ +#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ +#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ +#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ + +#define OPAD_PREFIX 0x1 +#define OPAD_POSTFIX 0x2 +#define OPAD_SYMBOL 0x4 + +/* Entry found in `.options' section. */ + +typedef struct +{ + Elf32_Word hwp_flags1; /* Extra flags. */ + Elf32_Word hwp_flags2; /* Extra flags. */ +} Elf_Options_Hw; + +/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ + +#define OHWA0_R4KEOP_CHECKED 0x00000001 +#define OHWA1_R4KEOP_CLEAN 0x00000002 + +/* MIPS relocs. */ + +#define R_MIPS_NONE 0 /* No reloc */ +#define R_MIPS_16 1 /* Direct 16 bit */ +#define R_MIPS_32 2 /* Direct 32 bit */ +#define R_MIPS_REL32 3 /* PC relative 32 bit */ +#define R_MIPS_26 4 /* Direct 26 bit shifted */ +#define R_MIPS_HI16 5 /* High 16 bit */ +#define R_MIPS_LO16 6 /* Low 16 bit */ +#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ +#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ +#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ +#define R_MIPS_PC16 10 /* PC relative 16 bit */ +#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ +#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ + +#define R_MIPS_SHIFT5 16 +#define R_MIPS_SHIFT6 17 +#define R_MIPS_64 18 +#define R_MIPS_GOT_DISP 19 +#define R_MIPS_GOT_PAGE 20 +#define R_MIPS_GOT_OFST 21 +#define R_MIPS_GOT_HI16 22 +#define R_MIPS_GOT_LO16 23 +#define R_MIPS_SUB 24 +#define R_MIPS_INSERT_A 25 +#define R_MIPS_INSERT_B 26 +#define R_MIPS_DELETE 27 +#define R_MIPS_HIGHER 28 +#define R_MIPS_HIGHEST 29 +#define R_MIPS_CALL_HI16 30 +#define R_MIPS_CALL_LO16 31 +#define R_MIPS_SCN_DISP 32 +#define R_MIPS_REL16 33 +#define R_MIPS_ADD_IMMEDIATE 34 +#define R_MIPS_PJUMP 35 +#define R_MIPS_RELGOT 36 +#define R_MIPS_JALR 37 +#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ +#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ +#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ +#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ +#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ +#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ +#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ +#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ +#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ +#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ +#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ +#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ +#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ +#define R_MIPS_GLOB_DAT 51 +/* Keep this the last entry. */ +#define R_MIPS_NUM 52 + +/* Legal values for p_type field of Elf32_Phdr. */ + +#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ +#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ +#define PT_MIPS_OPTIONS 0x70000002 + +/* Special program header types. */ + +#define PF_MIPS_LOCAL 0x10000000 + +/* Legal values for d_tag field of Elf32_Dyn. */ + +#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ +#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ +#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ +#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ +#define DT_MIPS_FLAGS 0x70000005 /* Flags */ +#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ +#define DT_MIPS_MSYM 0x70000007 +#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ +#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ +#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ +#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ +#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ +#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ +#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ +#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ +#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ +#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ +#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ +#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in + DT_MIPS_DELTA_CLASS. */ +#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ +#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in + DT_MIPS_DELTA_INSTANCE. */ +#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ +#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in + DT_MIPS_DELTA_RELOC. */ +#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta + relocations refer to. */ +#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in + DT_MIPS_DELTA_SYM. */ +#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the + class declaration. */ +#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in + DT_MIPS_DELTA_CLASSSYM. */ +#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ +#define DT_MIPS_PIXIE_INIT 0x70000023 +#define DT_MIPS_SYMBOL_LIB 0x70000024 +#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 +#define DT_MIPS_LOCAL_GOTIDX 0x70000026 +#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 +#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 +#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ +#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ +#define DT_MIPS_DYNSTR_ALIGN 0x7000002b +#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ +#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve + function stored in GOT. */ +#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added + by rld on dlopen() calls. */ +#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ +#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ +#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ +#define DT_MIPS_NUM 0x32 + +/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ + +#define RHF_NONE 0 /* No flags */ +#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ +#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ +#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ +#define RHF_NO_MOVE (1 << 3) +#define RHF_SGI_ONLY (1 << 4) +#define RHF_GUARANTEE_INIT (1 << 5) +#define RHF_DELTA_C_PLUS_PLUS (1 << 6) +#define RHF_GUARANTEE_START_INIT (1 << 7) +#define RHF_PIXIE (1 << 8) +#define RHF_DEFAULT_DELAY_LOAD (1 << 9) +#define RHF_REQUICKSTART (1 << 10) +#define RHF_REQUICKSTARTED (1 << 11) +#define RHF_CORD (1 << 12) +#define RHF_NO_UNRES_UNDEF (1 << 13) +#define RHF_RLD_ORDER_SAFE (1 << 14) + +/* Entries found in sections of type SHT_MIPS_LIBLIST. */ + +typedef struct +{ + Elf32_Word l_name; /* Name (string table index) */ + Elf32_Word l_time_stamp; /* Timestamp */ + Elf32_Word l_checksum; /* Checksum */ + Elf32_Word l_version; /* Interface version */ + Elf32_Word l_flags; /* Flags */ +} Elf32_Lib; + +typedef struct +{ + Elf64_Word l_name; /* Name (string table index) */ + Elf64_Word l_time_stamp; /* Timestamp */ + Elf64_Word l_checksum; /* Checksum */ + Elf64_Word l_version; /* Interface version */ + Elf64_Word l_flags; /* Flags */ +} Elf64_Lib; + + +/* Legal values for l_flags. */ + +#define LL_NONE 0 +#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ +#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ +#define LL_REQUIRE_MINOR (1 << 2) +#define LL_EXPORTS (1 << 3) +#define LL_DELAY_LOAD (1 << 4) +#define LL_DELTA (1 << 5) + +/* Entries found in sections of type SHT_MIPS_CONFLICT. */ + +typedef Elf32_Addr Elf32_Conflict; + + +/* HPPA specific definitions. */ + +/* Legal values for e_flags field of Elf32_Ehdr. */ + +#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ +#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ +#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ +#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ +#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch + prediction. */ +#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ +#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ + +/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ + +#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ +#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ +#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ + +/* Additional section indeces. */ + +#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared + symbols in ANSI C. */ +#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ + +/* Legal values for sh_type field of Elf32_Shdr. */ + +#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ +#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ +#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ + +/* Legal values for sh_flags field of Elf32_Shdr. */ + +#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ +#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ +#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ + +#define STT_HP_OPAQUE (STT_LOOS + 0x1) +#define STT_HP_STUB (STT_LOOS + 0x2) + +/* HPPA relocs. */ + +#define R_PARISC_NONE 0 /* No reloc. */ +#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ +#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ +#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ +#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ +#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ +#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ +#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ +#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ +#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ +#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ +#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ +#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ +#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ +#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ +#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ +#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ +#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ +#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ +#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ +#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ +#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ +#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ +#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ +#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ +#define R_PARISC_FPTR64 64 /* 64 bits function address. */ +#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ +#define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ +#define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ +#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ +#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ +#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ +#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ +#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ +#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ +#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ +#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ +#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ +#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ +#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ +#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ +#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ +#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ +#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ +#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ +#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ +#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ +#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ +#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ +#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ +#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ +#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ +#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ +#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ +#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ +#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ +#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ +#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ +#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ +#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ +#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ +#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LORESERVE 128 +#define R_PARISC_COPY 128 /* Copy relocation. */ +#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ +#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ +#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ +#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ +#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ +#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ +#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ +#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ +#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ +#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ +#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_GNU_VTENTRY 232 +#define R_PARISC_GNU_VTINHERIT 233 +#define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ +#define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ +#define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ +#define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ +#define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ +#define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ +#define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ +#define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ +#define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ +#define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ +#define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ +#define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ +#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L +#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R +#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L +#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R +#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 +#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 +#define R_PARISC_HIRESERVE 255 + +/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ + +#define PT_HP_TLS (PT_LOOS + 0x0) +#define PT_HP_CORE_NONE (PT_LOOS + 0x1) +#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) +#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) +#define PT_HP_CORE_COMM (PT_LOOS + 0x4) +#define PT_HP_CORE_PROC (PT_LOOS + 0x5) +#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) +#define PT_HP_CORE_STACK (PT_LOOS + 0x7) +#define PT_HP_CORE_SHM (PT_LOOS + 0x8) +#define PT_HP_CORE_MMF (PT_LOOS + 0x9) +#define PT_HP_PARALLEL (PT_LOOS + 0x10) +#define PT_HP_FASTBIND (PT_LOOS + 0x11) +#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) +#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) +#define PT_HP_STACK (PT_LOOS + 0x14) + +#define PT_PARISC_ARCHEXT 0x70000000 +#define PT_PARISC_UNWIND 0x70000001 + +/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ + +#define PF_PARISC_SBP 0x08000000 + +#define PF_HP_PAGE_SIZE 0x00100000 +#define PF_HP_FAR_SHARED 0x00200000 +#define PF_HP_NEAR_SHARED 0x00400000 +#define PF_HP_CODE 0x01000000 +#define PF_HP_MODIFY 0x02000000 +#define PF_HP_LAZYSWAP 0x04000000 +#define PF_HP_SBP 0x08000000 + + +/* Alpha specific definitions. */ + +/* Legal values for e_flags field of Elf64_Ehdr. */ + +#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ +#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ + +/* Legal values for sh_type field of Elf64_Shdr. */ + +/* These two are primerily concerned with ECOFF debugging info. */ +#define SHT_ALPHA_DEBUG 0x70000001 +#define SHT_ALPHA_REGINFO 0x70000002 + +/* Legal values for sh_flags field of Elf64_Shdr. */ + +#define SHF_ALPHA_GPREL 0x10000000 + +/* Legal values for st_other field of Elf64_Sym. */ +#define STO_ALPHA_NOPV 0x80 /* No PV required. */ +#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ + +/* Alpha relocs. */ + +#define R_ALPHA_NONE 0 /* No reloc */ +#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ +#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ +#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ +#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ +#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ +#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ +#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ +#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ +#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ +#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ +#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ +#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ +#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ +#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ +#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ +#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ +#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ +#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ +#define R_ALPHA_TLS_GD_HI 28 +#define R_ALPHA_TLSGD 29 +#define R_ALPHA_TLS_LDM 30 +#define R_ALPHA_DTPMOD64 31 +#define R_ALPHA_GOTDTPREL 32 +#define R_ALPHA_DTPREL64 33 +#define R_ALPHA_DTPRELHI 34 +#define R_ALPHA_DTPRELLO 35 +#define R_ALPHA_DTPREL16 36 +#define R_ALPHA_GOTTPREL 37 +#define R_ALPHA_TPREL64 38 +#define R_ALPHA_TPRELHI 39 +#define R_ALPHA_TPRELLO 40 +#define R_ALPHA_TPREL16 41 +/* Keep this the last entry. */ +#define R_ALPHA_NUM 46 + +/* Magic values of the LITUSE relocation addend. */ +#define LITUSE_ALPHA_ADDR 0 +#define LITUSE_ALPHA_BASE 1 +#define LITUSE_ALPHA_BYTOFF 2 +#define LITUSE_ALPHA_JSR 3 +#define LITUSE_ALPHA_TLS_GD 4 +#define LITUSE_ALPHA_TLS_LDM 5 + +/* Legal values for d_tag of Elf64_Dyn. */ +#define DT_ALPHA_PLTRO (DT_LOPROC + 0) +#define DT_ALPHA_NUM 1 + +/* PowerPC specific declarations */ + +/* Values for Elf32/64_Ehdr.e_flags. */ +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ + +/* Cygnus local bits below */ +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib + flag */ + +/* PowerPC relocations defined by the ABIs */ +#define R_PPC_NONE 0 +#define R_PPC_ADDR32 1 /* 32bit absolute address */ +#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ +#define R_PPC_ADDR16 3 /* 16bit absolute address */ +#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ +#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ +#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ +#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 /* PC relative 26 bit */ +#define R_PPC_REL14 11 /* PC relative 16 bit */ +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 + +/* PowerPC relocations defined for the TLS access ABI. */ +#define R_PPC_TLS 67 /* none (sym+add)@tls */ +#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ +#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ +#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ +#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ +#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ +#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ +#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ +#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ +#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ +#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ +#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ +#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ +#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ +#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ +#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ +#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ +#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ +#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ +#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ +#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ +#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ +#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ +#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ +#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ +#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ +#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ +#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ + +/* Keep this the last entry. */ +#define R_PPC_NUM 95 + +/* The remaining relocs are from the Embedded ELF ABI, and are not + in the SVR4 ELF ABI. */ +#define R_PPC_EMB_NADDR32 101 +#define R_PPC_EMB_NADDR16 102 +#define R_PPC_EMB_NADDR16_LO 103 +#define R_PPC_EMB_NADDR16_HI 104 +#define R_PPC_EMB_NADDR16_HA 105 +#define R_PPC_EMB_SDAI16 106 +#define R_PPC_EMB_SDA2I16 107 +#define R_PPC_EMB_SDA2REL 108 +#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ +#define R_PPC_EMB_MRKREF 110 +#define R_PPC_EMB_RELSEC16 111 +#define R_PPC_EMB_RELST_LO 112 +#define R_PPC_EMB_RELST_HI 113 +#define R_PPC_EMB_RELST_HA 114 +#define R_PPC_EMB_BIT_FLD 115 +#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ + +/* Diab tool relocations. */ +#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ +#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ +#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ +#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ +#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ +#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ + +/* GNU relocs used in PIC code sequences. */ +#define R_PPC_REL16 249 /* word32 (sym-.) */ +#define R_PPC_REL16_LO 250 /* half16 (sym-.)@l */ +#define R_PPC_REL16_HI 251 /* half16 (sym-.)@h */ +#define R_PPC_REL16_HA 252 /* half16 (sym-.)@ha */ + +/* This is a phony reloc to handle any old fashioned TOC16 references + that may still be in object files. */ +#define R_PPC_TOC16 255 + +/* PowerPC specific values for the Dyn d_tag field. */ +#define DT_PPC_GOT (DT_LOPROC + 0) +#define DT_PPC_NUM 1 + +/* PowerPC64 relocations defined by the ABIs */ +#define R_PPC64_NONE R_PPC_NONE +#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ +#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ +#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ +#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ +#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ +#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ +#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ +#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN +#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN +#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ +#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ +#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN +#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN +#define R_PPC64_GOT16 R_PPC_GOT16 +#define R_PPC64_GOT16_LO R_PPC_GOT16_LO +#define R_PPC64_GOT16_HI R_PPC_GOT16_HI +#define R_PPC64_GOT16_HA R_PPC_GOT16_HA + +#define R_PPC64_COPY R_PPC_COPY +#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT +#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT +#define R_PPC64_RELATIVE R_PPC_RELATIVE + +#define R_PPC64_UADDR32 R_PPC_UADDR32 +#define R_PPC64_UADDR16 R_PPC_UADDR16 +#define R_PPC64_REL32 R_PPC_REL32 +#define R_PPC64_PLT32 R_PPC_PLT32 +#define R_PPC64_PLTREL32 R_PPC_PLTREL32 +#define R_PPC64_PLT16_LO R_PPC_PLT16_LO +#define R_PPC64_PLT16_HI R_PPC_PLT16_HI +#define R_PPC64_PLT16_HA R_PPC_PLT16_HA + +#define R_PPC64_SECTOFF R_PPC_SECTOFF +#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO +#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI +#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA +#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ +#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ +#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ +#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ +#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ +#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ +#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ +#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ +#define R_PPC64_PLT64 45 /* doubleword64 L + A */ +#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ +#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ +#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ +#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ +#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ +#define R_PPC64_TOC 51 /* doubleword64 .TOC */ +#define R_PPC64_PLTGOT16 52 /* half16* M + A */ +#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ +#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ +#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ + +#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ +#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ +#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ +#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ +#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ +#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ +#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ +#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ +#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ +#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ +#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ + +/* PowerPC64 relocations defined for the TLS access ABI. */ +#define R_PPC64_TLS 67 /* none (sym+add)@tls */ +#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ +#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ +#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ +#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ +#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ +#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ +#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ +#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ +#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ +#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ +#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ +#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ +#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ +#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ +#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ +#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ +#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ +#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ +#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ +#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ +#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ +#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ +#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ +#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ +#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ +#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ +#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ +#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ +#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ +#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ +#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ +#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ +#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ +#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ +#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ +#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ +#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ +#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ +#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ + +/* Keep this the last entry. */ +#define R_PPC64_NUM 107 + +/* PowerPC64 specific values for the Dyn d_tag field. */ +#define DT_PPC64_GLINK (DT_LOPROC + 0) +#define DT_PPC64_OPD (DT_LOPROC + 1) +#define DT_PPC64_OPDSZ (DT_LOPROC + 2) +#define DT_PPC64_NUM 3 + + +/* ARM specific declarations */ + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_ARM_INTERWORK 0x04 +#define EF_ARM_APCS_26 0x08 +#define EF_ARM_APCS_FLOAT 0x10 +#define EF_ARM_PIC 0x20 +#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ +#define EF_ARM_NEW_ABI 0x80 +#define EF_ARM_OLD_ABI 0x100 + +/* Other constants defined in the ARM ELF spec. version B-01. */ +/* NB. These conflict with values defined above. */ +#define EF_ARM_SYMSARESORTED 0x04 +#define EF_ARM_DYNSYMSUSESEGIDX 0x08 +#define EF_ARM_MAPSYMSFIRST 0x10 +#define EF_ARM_EABIMASK 0XFF000000 + +#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) +#define EF_ARM_EABI_UNKNOWN 0x00000000 +#define EF_ARM_EABI_VER1 0x01000000 +#define EF_ARM_EABI_VER2 0x02000000 + +/* Additional symbol types for Thumb */ +#define STT_ARM_TFUNC 0xd + +/* ARM-specific values for sh_flags */ +#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ +#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined + in the input to a link step */ + +/* ARM-specific program header flags */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location + addressed by the static base */ + +/* Processor specific values for the Phdr p_type field. */ +#define PT_ARM_EXIDX 0x70000001 /* .ARM.exidx segment */ + +/* ARM relocs. */ + +#define R_ARM_NONE 0 /* No reloc */ +#define R_ARM_PC24 1 /* PC relative 26 bit branch */ +#define R_ARM_ABS32 2 /* Direct 32 bit */ +#define R_ARM_REL32 3 /* PC relative 32 bit */ +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 /* Direct 16 bit */ +#define R_ARM_ABS12 6 /* Direct 12 bit */ +#define R_ARM_THM_ABS5 7 +#define R_ARM_ABS8 8 /* Direct 8 bit */ +#define R_ARM_SBREL32 9 +#define R_ARM_THM_PC22 10 +#define R_ARM_THM_PC8 11 +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 +#define R_ARM_THM_SWI8 14 +#define R_ARM_XPC25 15 +#define R_ARM_THM_XPC22 16 +#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ +#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ +#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ +#define R_ARM_COPY 20 /* Copy symbol at runtime */ +#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ +#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ +#define R_ARM_RELATIVE 23 /* Adjust by program base */ +#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ +#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ +#define R_ARM_GOT32 26 /* 32 bit GOT entry */ +#define R_ARM_PLT32 27 /* 32 bit PLT address */ +#define R_ARM_ALU_PCREL_7_0 32 +#define R_ARM_ALU_PCREL_15_8 33 +#define R_ARM_ALU_PCREL_23_15 34 +#define R_ARM_LDR_SBREL_11_0 35 +#define R_ARM_ALU_SBREL_19_12 36 +#define R_ARM_ALU_SBREL_27_20 37 +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ +#define R_ARM_THM_PC9 103 /* thumb conditional branch */ +#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic + thread local data */ +#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic + thread local data */ +#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS + block */ +#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of + static TLS block offset */ +#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static + TLS block */ +#define R_ARM_RXPC25 249 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS22 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 +/* Keep this the last entry. */ +#define R_ARM_NUM 256 + +/* IA-64 specific declarations. */ + +/* Processor specific flags for the Ehdr e_flags field. */ +#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ +#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ +#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ + +/* Processor specific values for the Phdr p_type field. */ +#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ +#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ +#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) +#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) +#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) + +/* Processor specific flags for the Phdr p_flags field. */ +#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ + +/* Processor specific values for the Shdr sh_type field. */ +#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ + +/* Processor specific flags for the Shdr sh_flags field. */ +#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ +#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ + +/* Processor specific values for the Dyn d_tag field. */ +#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) +#define DT_IA_64_NUM 1 + +/* IA-64 relocations. */ +#define R_IA64_NONE 0x00 /* none */ +#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ +#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ +#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ +#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ +#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ +#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ +#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ +#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ +#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ +#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ +#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ +#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ +#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ +#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ +#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ +#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ +#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ +#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ +#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ +#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ +#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ +#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ +#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ +#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ +#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ +#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ +#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ +#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ +#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ +#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ +#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ +#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ +#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ +#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ +#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ +#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ +#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ +#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ +#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ +#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ +#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ +#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ +#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ +#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ +#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ +#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ +#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ +#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ +#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ +#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ +#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ +#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ +#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ +#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ +#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ +#define R_IA64_COPY 0x84 /* copy relocation */ +#define R_IA64_SUB 0x85 /* Addend and symbol difference */ +#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ +#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ +#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ +#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ +#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ +#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ +#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ +#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ +#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ +#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ +#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ +#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ +#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ +#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ +#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ +#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ +#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ + +/* SH specific declarations */ + +/* SH relocs. */ +#define R_SH_NONE 0 +#define R_SH_DIR32 1 +#define R_SH_REL32 2 +#define R_SH_DIR8WPN 3 +#define R_SH_IND12W 4 +#define R_SH_DIR8WPL 5 +#define R_SH_DIR8WPZ 6 +#define R_SH_DIR8BP 7 +#define R_SH_DIR8W 8 +#define R_SH_DIR8L 9 +#define R_SH_SWITCH16 25 +#define R_SH_SWITCH32 26 +#define R_SH_USES 27 +#define R_SH_COUNT 28 +#define R_SH_ALIGN 29 +#define R_SH_CODE 30 +#define R_SH_DATA 31 +#define R_SH_LABEL 32 +#define R_SH_SWITCH8 33 +#define R_SH_GNU_VTINHERIT 34 +#define R_SH_GNU_VTENTRY 35 +#define R_SH_TLS_GD_32 144 +#define R_SH_TLS_LD_32 145 +#define R_SH_TLS_LDO_32 146 +#define R_SH_TLS_IE_32 147 +#define R_SH_TLS_LE_32 148 +#define R_SH_TLS_DTPMOD32 149 +#define R_SH_TLS_DTPOFF32 150 +#define R_SH_TLS_TPOFF32 151 +#define R_SH_GOT32 160 +#define R_SH_PLT32 161 +#define R_SH_COPY 162 +#define R_SH_GLOB_DAT 163 +#define R_SH_JMP_SLOT 164 +#define R_SH_RELATIVE 165 +#define R_SH_GOTOFF 166 +#define R_SH_GOTPC 167 +/* Keep this the last entry. */ +#define R_SH_NUM 256 + +/* Additional s390 relocs */ + +#define R_390_NONE 0 /* No reloc. */ +#define R_390_8 1 /* Direct 8 bit. */ +#define R_390_12 2 /* Direct 12 bit. */ +#define R_390_16 3 /* Direct 16 bit. */ +#define R_390_32 4 /* Direct 32 bit. */ +#define R_390_PC32 5 /* PC relative 32 bit. */ +#define R_390_GOT12 6 /* 12 bit GOT offset. */ +#define R_390_GOT32 7 /* 32 bit GOT offset. */ +#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ +#define R_390_COPY 9 /* Copy symbol at runtime. */ +#define R_390_GLOB_DAT 10 /* Create GOT entry. */ +#define R_390_JMP_SLOT 11 /* Create PLT entry. */ +#define R_390_RELATIVE 12 /* Adjust by program base. */ +#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ +#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ +#define R_390_GOT16 15 /* 16 bit GOT offset. */ +#define R_390_PC16 16 /* PC relative 16 bit. */ +#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ +#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ +#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ +#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ +#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ +#define R_390_64 22 /* Direct 64 bit. */ +#define R_390_PC64 23 /* PC relative 64 bit. */ +#define R_390_GOT64 24 /* 64 bit GOT offset. */ +#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ +#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ +#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ +#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ +#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ +#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ +#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ +#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ +#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ +#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ +#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ +#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ +#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ +#define R_390_TLS_GDCALL 38 /* Tag for function call in general + dynamic TLS code. */ +#define R_390_TLS_LDCALL 39 /* Tag for function call in local + dynamic TLS code. */ +#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic + thread local data. */ +#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic + thread local data. */ +#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic + thread local data in LE code. */ +#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic + thread local data in LE code. */ +#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to + static TLS block. */ +#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to + static TLS block. */ +#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS + block. */ +#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS + block. */ +#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ +#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ +#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS + block. */ +#define R_390_20 57 /* Direct 20 bit. */ +#define R_390_GOT20 58 /* 20 bit GOT offset. */ +#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ +#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS + block offset. */ +/* Keep this the last entry. */ +#define R_390_NUM 61 + + +/* CRIS relocations. */ +#define R_CRIS_NONE 0 +#define R_CRIS_8 1 +#define R_CRIS_16 2 +#define R_CRIS_32 3 +#define R_CRIS_8_PCREL 4 +#define R_CRIS_16_PCREL 5 +#define R_CRIS_32_PCREL 6 +#define R_CRIS_GNU_VTINHERIT 7 +#define R_CRIS_GNU_VTENTRY 8 +#define R_CRIS_COPY 9 +#define R_CRIS_GLOB_DAT 10 +#define R_CRIS_JUMP_SLOT 11 +#define R_CRIS_RELATIVE 12 +#define R_CRIS_16_GOT 13 +#define R_CRIS_32_GOT 14 +#define R_CRIS_16_GOTPLT 15 +#define R_CRIS_32_GOTPLT 16 +#define R_CRIS_32_GOTREL 17 +#define R_CRIS_32_PLT_GOTREL 18 +#define R_CRIS_32_PLT_PCREL 19 + +#define R_CRIS_NUM 20 + + +/* AMD x86-64 relocations. */ +#define R_X86_64_NONE 0 /* No reloc */ +#define R_X86_64_64 1 /* Direct 64 bit */ +#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ +#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ +#define R_X86_64_PLT32 4 /* 32 bit PLT address */ +#define R_X86_64_COPY 5 /* Copy symbol at runtime */ +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative + offset to GOT */ +#define R_X86_64_32 10 /* Direct 32 bit zero extended */ +#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ +#define R_X86_64_16 12 /* Direct 16 bit zero extended */ +#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ +#define R_X86_64_8 14 /* Direct 8 bit sign extended */ +#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ +#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ +#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ +#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ +#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset + to two GOT entries for GD symbol */ +#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset + to two GOT entries for LD symbol */ +#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ +#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset + to GOT entry for IE symbol */ +#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ + +#define R_X86_64_NUM 24 + + +/* AM33 relocations. */ +#define R_MN10300_NONE 0 /* No reloc. */ +#define R_MN10300_32 1 /* Direct 32 bit. */ +#define R_MN10300_16 2 /* Direct 16 bit. */ +#define R_MN10300_8 3 /* Direct 8 bit. */ +#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ +#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ +#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ +#define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ +#define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ +#define R_MN10300_24 9 /* Direct 24 bit. */ +#define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ +#define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ +#define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ +#define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ +#define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ +#define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ +#define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ +#define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ +#define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ +#define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ +#define R_MN10300_COPY 20 /* Copy symbol at runtime. */ +#define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ +#define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ +#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ + +#define R_MN10300_NUM 24 + + +/* M32R relocs. */ +#define R_M32R_NONE 0 /* No reloc. */ +#define R_M32R_16 1 /* Direct 16 bit. */ +#define R_M32R_32 2 /* Direct 32 bit. */ +#define R_M32R_24 3 /* Direct 24 bit. */ +#define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ +#define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ +#define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ +#define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ +#define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ +#define R_M32R_LO16 9 /* Low 16 bit. */ +#define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ +#define R_M32R_GNU_VTINHERIT 11 +#define R_M32R_GNU_VTENTRY 12 +/* M32R relocs use SHT_RELA. */ +#define R_M32R_16_RELA 33 /* Direct 16 bit. */ +#define R_M32R_32_RELA 34 /* Direct 32 bit. */ +#define R_M32R_24_RELA 35 /* Direct 24 bit. */ +#define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ +#define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ +#define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ +#define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ +#define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ +#define R_M32R_LO16_RELA 41 /* Low 16 bit */ +#define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ +#define R_M32R_RELA_GNU_VTINHERIT 43 +#define R_M32R_RELA_GNU_VTENTRY 44 +#define R_M32R_REL32 45 /* PC relative 32 bit. */ + +#define R_M32R_GOT24 48 /* 24 bit GOT entry */ +#define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ +#define R_M32R_COPY 50 /* Copy symbol at runtime */ +#define R_M32R_GLOB_DAT 51 /* Create GOT entry */ +#define R_M32R_JMP_SLOT 52 /* Create PLT entry */ +#define R_M32R_RELATIVE 53 /* Adjust by program base */ +#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ +#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ +#define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned + low */ +#define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed + low */ +#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ +#define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to + GOT with unsigned low */ +#define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to + GOT with signed low */ +#define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to + GOT */ +#define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT + with unsigned low */ +#define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT + with signed low */ +#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ +#define R_M32R_NUM 256 /* Keep this the last entry. */ + +#endif /* elf.h */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /trunk/softs/tsar_boot/include/io.h =================================================================== --- /trunk/softs/tsar_boot/include/io.h (revision 373) +++ /trunk/softs/tsar_boot/include/io.h (revision 373) @@ -0,0 +1,64 @@ +/** + * \file io.h + * \date 5 September 2012 + * \author Cesar Fuguet + * + * Utility functions to write or read memory mapped hardware registers + */ +#ifndef IO_H +#define IO_H + +/** + * Read an 32 bits memory mapped hardware register + */ +static inline unsigned int ioread32(void * addr) +{ + return *(volatile unsigned int *) addr; +} + +/** + * Read an 16 bits memory mapped hardware register + */ +static inline unsigned short ioread16(void * addr) +{ + return *(volatile unsigned short *) addr; +} + +/** + * Read an 8 bits memory mapped hardware register + */ +static inline unsigned char ioread8(void * addr) +{ + return *(volatile unsigned char *) addr; +} + +/** + * Write an 32 bits memory mapped hardware register + */ +static inline void iowrite32(void * addr, unsigned int value) +{ + *(volatile unsigned int *) addr = value; + asm volatile("sync"); +} + +/** + * Write an 16 bits memory mapped hardware register + */ +static inline void iowrite16(void * addr, unsigned short value) +{ + *(volatile unsigned short *) addr = value; + asm volatile("sync"); +} + +/** + * Write an 8 bits memory mapped hardware register + */ +static inline void iowrite8(void * addr, unsigned char value) +{ + *(volatile unsigned char *) addr = value; + asm volatile("sync"); +} + +#undef in_reset + +#endif Index: /trunk/softs/tsar_boot/include/mips32_registers.h =================================================================== --- /trunk/softs/tsar_boot/include/mips32_registers.h (revision 373) +++ /trunk/softs/tsar_boot/include/mips32_registers.h (revision 373) @@ -0,0 +1,56 @@ +/********************************************************************************/ +/* File : mips32_registers.h */ +/* Author : Alain Greiner */ +/* Date : 26/03/2012 */ +/* Modified by : Cesar Fuguet 10/02/2013 */ +/********************************************************************************/ +/* We define mnemonics for MIPS32 registers */ +/********************************************************************************/ + +#ifndef _MIPS32_REGISTERS_H +#define _MIPS32_REGISTERS_H + +/* processor registers */ + +#define zero $0 +#define at $at +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 + +/* CP0 registers */ + +#define CP0_COUNT $9 +#define CP0_STATUS $12,0 +#define CP0_CAUSE $13,0 +#define CP0_EPC $14,0 +#define CP0_EBASE $15,1 + +#endif Index: /trunk/softs/tsar_boot/include/sdcard.h =================================================================== --- /trunk/softs/tsar_boot/include/sdcard.h (revision 373) +++ /trunk/softs/tsar_boot/include/sdcard.h (revision 373) @@ -0,0 +1,185 @@ +/** + * \file sdcard.h + * \date 30 August 2012 + * \author Cesar fuguet + * + * This file defines the driver of a SD Card device using an SPI controller + */ + +#ifndef SDCARD_H +#define SDCARD_H + +#include + +/** + * \brief SD Card type definition + */ +struct sdcard_dev +{ + /** + * SPI controller pointer + */ + struct spi_dev * spi; + + /** + * Capacity of the SDCARD in terms of bytes + */ + unsigned int capacity; + + /** + * Block length of the SDCARD + */ + unsigned int block_length; + + /** + * Access pointer representing the offset in bytes used + * to read or write in the SDCARD. + * + * \note this driver is for cards SDSD, therefore this offset + * must be multiple of the block length + */ + unsigned int access_pointer; + + /** + * Slave ID. This ID represents the number of the slave select signal + * used in the hardware platform + */ + int slave_id; +}; + +/** + * \param sdcard : uninitialized pointer. This parameter will contain + * a pointer to the initialized block device or NULL otherwise + * \param spi : initialized pointer to the spi controller + * \param ss : slave select signal number + * + * \return 0 when initialization succeeds or an error code value otherwise. + * The error codes are defined in this header file. + * + * \brief Initialize the block device + */ +int sdcard_dev_open(struct sdcard_dev * sdcard, struct spi_dev * spi, int ss); + +/** + * \param sdcard : Pointer to the initialized block device + * \param buf : Pointer to a memory segment wherein store + * \param count : number of bytes to read + * + * \return 0 when read succeeds or an error code value otherwise. + * The error codes are defined in this header file. + * + * \brief Read in the block device + * + * The read is made in the current block device access pointer. + * In the read succeeds, the block device access pointer is + * relocated to the next block. + */ +int sdcard_dev_read(struct sdcard_dev * sdcard, void * buf, unsigned int count); + +/** + * \param sdcard : Pointer to the initialized block device + * \param buf : Pointer to a memory segment wherein the + * \param count : number of blocks to write + * + * \return 0 when write succeeds or an error code value otherwise. + * The error codes are defined in this header file. + * + * \brief Write in the block device + * + * The write is made in the current block device access pointer. + * In the write succeeds, the block device access pointer is + * relocated to the next block. + */ +unsigned int sdcard_dev_write(struct sdcard_dev * sdcard, void * buf, unsigned int count); + +/** + * \param sdcard : Pointer to the initialized block device + * \param pos : Position where the block device access + * pointer must be move + * + * \return void + * + * \brief Change block device access pointer position + * + * The block device access pointer is relocated in terms of blocks + */ +void sdcard_dev_lseek(struct sdcard_dev * sdcard, unsigned int pos); + +/** + * \param sdcard : Pointer to the initialized block device + * + * \return block device capacity + * + * \brief Get the block device capacity + * + * The block device access pointer is relocated in terms of blocks + */ +unsigned int sdcard_dev_get_capacity(struct sdcard_dev * sdcard); + +/** + * \param sdcard : Pointer to the initialized block device + * \param len : Block device length to set + * + * \return 0 when succeed or error code value otherwise + * + * \brief Set the block length of the device + */ +int sdcard_dev_set_blocklen(struct sdcard_dev * sdcard, unsigned int len); + +/** + * SD Card constants + */ + +/** Number of retries after an unacknowledge command */ +#define SDCARD_COMMAND_TIMEOUT 100 + +/** This command is a simple SD commmand */ +#define SDCARD_CMD 0 + +/** This is an application specific command */ +#define SDCARD_ACMD 1 + +/** The transmition is done in the negative edge of the clock */ +#define SDCARD_TX_NEGEDGE 0 + +/** The transmition is done in the positive edge of the clock */ +#define SDCARD_TX_POSEDGE 1 + +/** The reception is done in the negative edge of the clock */ +#define SDCARD_RX_NEGEDGE 0 + +/** The reception is done in the positive edge of the clock */ +#define SDCARD_RX_POSEDGE 1 + +/** + * SD Card macros + */ + +/** Check if the response is valid */ +#define SDCARD_CHECK_R1_VALID(x) (~x & SDCARD_R1_RSP_VALID) ? 1 : 0 + +/** + * Check if there is an error in the response + * + * \note this macro must be used after verify that the response is + * valid + */ +#define SDCARD_CHECK_R1_ERROR(x) ( x & 0x7E) ? 1 : 0 + +/** + * SD Card Response 1 (R1) format constants + */ +#define SDCARD_R1_IN_IDLE_STATE ( 1 << 0 ) /**< \brief R1 bit 0 */ +#define SDCARD_R1_ERASE_RESET ( 1 << 1 ) /**< \brief R1 bit 1 */ +#define SDCARD_R1_ILLEGAL_CMD ( 1 << 2 ) /**< \brief R1 bit 2 */ +#define SDCARD_R1_COM_CRC_ERR ( 1 << 3 ) /**< \brief R1 bit 3 */ +#define SDCARD_R1_ERASE_SEQ_ERR ( 1 << 4 ) /**< \brief R1 bit 4 */ +#define SDCARD_R1_ADDRESS_ERR ( 1 << 5 ) /**< \brief R1 bit 5 */ +#define SDCARD_R1_PARAMETER_ERR ( 1 << 6 ) /**< \brief R1 bit 6 */ +#define SDCARD_R1_RSP_VALID ( 1 << 7 ) /**< \brief R1 bit 7 */ + +#endif + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4 + */ Index: /trunk/softs/tsar_boot/include/spi.h =================================================================== --- /trunk/softs/tsar_boot/include/spi.h (revision 373) +++ /trunk/softs/tsar_boot/include/spi.h (revision 373) @@ -0,0 +1,136 @@ +/** + * \file : spi.h + * \date : 30 August 2012 + * \author: Cesar Fuguet + * + * This file contains the definition of a driver for the SPI controller + */ + +#ifndef SPI_H +#define SPI_H + +#include + +/** + * SPI type definition + */ +struct spi_dev +{ + /** + * RX/TX registers of the SPI controller + */ + unsigned int rx_tx[4]; + + /** + * Control register of the SPI controller + */ + unsigned int ctrl; + + /** + * Divider register for the SPI controller generated clock signal + */ + unsigned int divider; + + /** + * Slave select register of the SPI controller + */ + unsigned int ss; +}; + +/** + * \param spi : initialized pointer to a SPI controller. + * \param byte : Byte to send to the SPI controller + * \param index : index of the TX register in the SPI (TX[index]) + * + * \return void + * + * \brief Send a byte to one of the tx buffer registers of the + * SPI controller + */ +void spi_put_tx(struct spi_dev * spi, unsigned char byte, int index); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param index : index of the RX register in the SPI (RX[index]) + * + * \return byte from the RX[index] register + * + * \brief Get a byte from one of the rx buffer registers of the + * SPI controller + */ +inline volatile unsigned char spi_get_rx(struct spi_dev * spi, int index); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param index : index of the slave select signal to assert + * + * \return void + * + * \brief Set the index selected slave select signal (ss[index] <= '0') + */ +inline void spi_ss_assert(struct spi_dev * spi, int index); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param index : index of the slave select signal to deassert + * + * \return void + * + * \brief Unset the index selected slave select signal (ss[index] <= '0') + */ +inline void spi_ss_deassert(struct spi_dev * spi, int index); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param spi_freq : SPI Master to Slave clock frequency (in Hz) + * \param sys_freq : System clock frequency (in Hz) + * \param char_len : number to bits to transmit in one transfer + * \param tx_edge : when 0, the Master Out Slave In signal is changed + * on the falling edge of the clock + * \param rx_edge : when 0, the Master In Slave Out signal is latched + * on the falling edge of the clock + * + * \return void + * + * \brief Configure the SPI controller + * \note Any of the arguments can be less than 0 if you want to keep the old value + */ +void spi_dev_config ( + struct spi_dev * spi, + int spi_freq , + int sys_freq , + int char_len , + int tx_edge , + int rx_edge ); + +/** + * SPI macros and constants + */ +#define SPI_TX_POSEDGE 1 /**< MOSI is changed on neg edge */ +#define SPI_TX_NEGEDGE 0 /**< MOSI is changed on pos edge */ +#define SPI_RX_POSEDGE 1 /**< MISO is latched on pos edge */ +#define SPI_RX_NEGEDGE 0 /**< MISO is latched on neg edge */ + +#define SPI_CTRL_ASS_EN ( 1 << 13 ) /**< Auto Slave Sel Assertion */ +#define SPI_CTRL_IE_EN ( 1 << 12 ) /**< Interrupt Enable */ +#define SPI_CTRL_LSB_EN ( 1 << 11 ) /**< LSB are sent first */ +#define SPI_CTRL_TXN_EN ( 1 << 10 ) /**< MOSI is changed on neg edge */ +#define SPI_CTRL_RXN_EN ( 1 << 9 ) /**< MISO is latched on neg edge */ +#define SPI_CTRL_GO_BSY ( 1 << 8 ) /**< Start the transfer */ +#define SPI_CTRL_CHAR_LEN_MASK ( 0xFF ) /**< Bits transmited in 1 transfer */ +#define SPI_RXTX_MASK ( 0xFF ) /**< Mask for the an RX/TX value */ + + /** + * \param x : Initialized pointer to the SPI controller + * + * \return 1 if there is an unfinished transfer in the SPI controller + * + * Check the GO_BUSY bit of the SPI Controller + */ +#define SPI_IS_BUSY(x) ((ioread32(&x->ctrl) & SPI_CTRL_GO_BSY) != 0) ? 1 : 0 + +#endif + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4 + */ Index: /trunk/softs/tsar_boot/include/tty.h =================================================================== --- /trunk/softs/tsar_boot/include/tty.h (revision 373) +++ /trunk/softs/tsar_boot/include/tty.h (revision 373) @@ -0,0 +1,23 @@ +#ifndef TTY_REGS_H +#define TTY_REGS_H + +enum SoclibTtyRegisters { + TTY_WRITE = 0, + TTY_STATUS = 1, + TTY_READ = 2, + TTY_CONFIG = 3, + /**/ + TTY_SPAN = 4, +}; + +#endif + +// Local Variables: +// tab-width: 4; +// c-basic-offset: 4; +// c-file-offsets:((innamespace . 0)(inline-open . 0)); +// indent-tabs-mode: nil; +// End: +// +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /trunk/softs/tsar_boot/src/boot_elf_loader.c =================================================================== --- /trunk/softs/tsar_boot/src/boot_elf_loader.c (revision 373) +++ /trunk/softs/tsar_boot/src/boot_elf_loader.c (revision 373) @@ -0,0 +1,266 @@ +/** + * \file : boot_loader_entry.c + * \date : August 2012 + * \author : Cesar Fuguet + * + * This file defines an elf file loader which reads an executable elf file + * starting at a sector passed as argument of a disk and copy the different + * ELF program segments in the appropriate memory address using as information + * the virtual address read from the elf file. + */ + +#include +#include +#include +#include +#include + +void * boot_elf_loader(unsigned int lba) +{ + /** + * Temporary variables used by the boot loader + */ + unsigned char boot_elf_loader_buffer[512]; + Elf32_Ehdr elf_header; + Elf32_Phdr elf_pht[PHDR_ARRAY_SIZE]; + + unsigned char * buffer_ptr; + Elf32_Ehdr * elf_header_ptr; + Elf32_Phdr * elf_pht_ptr; + + unsigned int nb_available; + unsigned int nb_rest; + unsigned int nb_read; + unsigned int nb_block; + unsigned int offset; + unsigned int pseg; + unsigned int i; + unsigned int segment_req; + + /* + * Loader state machine definition + */ + enum + { + ELF_HEADER_STATE, + ELF_PROGRAM_HEADER_STATE, + ELF_OFFSET_STATE, + ELF_SEGMENT_STATE, + ELF_END_STATE + } init_state; + + boot_puts("Starting boot_elf_loader function...\n\r"); + + nb_block = lba; + + pseg = 0; + nb_available = 0; + nb_rest = sizeof(Elf32_Ehdr); + offset = 0; + + elf_header_ptr = (Elf32_Ehdr *) &elf_header; + elf_pht_ptr = (Elf32_Phdr *) &elf_pht[0]; + + init_state = ELF_HEADER_STATE; + + while(init_state != ELF_END_STATE) + { + if (nb_available == 0) + { + buffer_ptr = &boot_elf_loader_buffer[0]; + + if ( boot_ioc_read(nb_block , buffer_ptr, 1) ) + { + boot_puts ( + "ERROR: " + "IOC_FAILED" + "\n" + ); + + boot_exit(); + } + + nb_block += 1; + nb_available = 512; + } + + nb_read = (nb_rest <= nb_available) ? nb_rest : nb_available; + offset += nb_read; + + switch(init_state) + { + /** + * Reading ELF executable header + */ + case ELF_HEADER_STATE: + boot_memcpy(elf_header_ptr, buffer_ptr, nb_read); + + nb_rest -= nb_read; + + if(nb_rest == 0) + { + nb_rest = elf_header_ptr->e_phnum * elf_header_ptr->e_phentsize; + + /* Verification of ELF Magic Number */ + if ( + (elf_header_ptr->e_ident[EI_MAG0] != ELFMAG0) || + (elf_header_ptr->e_ident[EI_MAG1] != ELFMAG1) || + (elf_header_ptr->e_ident[EI_MAG2] != ELFMAG2) || + (elf_header_ptr->e_ident[EI_MAG3] != ELFMAG3) ) + { + boot_puts( + "ERROR: " + "Input file does not use ELF format" + "\n" + ); + + boot_exit(); + } + + /* + * Verification of Program Headers table size. It must be + * smaller than the work size allocated for the + * elf_pht[PHDR_ARRAY_SIZE] array + **/ + if (elf_header_ptr->e_phnum > PHDR_ARRAY_SIZE) + { + boot_puts( + "ERROR: " + "ELF PHDR table size is bigger than " + "the allocated work space" + "\n" + ); + + boot_exit(); + } + + init_state = ELF_PROGRAM_HEADER_STATE; + } + + break; + + /** + * Reading ELF program headers + */ + case ELF_PROGRAM_HEADER_STATE: + boot_memcpy(elf_pht_ptr, buffer_ptr, nb_read); + + elf_pht_ptr = (Elf32_Phdr *)((unsigned char *) elf_pht_ptr + nb_read); + nb_rest -= nb_read; + + if(nb_rest == 0) + { + elf_pht_ptr = (Elf32_Phdr *) &elf_pht[0]; + + /* + * Search the first not NULL segment in the ELF file + */ + for (pseg = 0; pseg < elf_header_ptr->e_phnum; pseg++) + { + if(elf_pht_ptr[pseg].p_type == PT_LOAD) + { + nb_rest = elf_pht_ptr[pseg].p_offset - offset; + break; + } + } + + init_state = ELF_OFFSET_STATE; + } + + break; + + /** + * Go to the offset of the first not null program segment in the ELF file + */ + case ELF_OFFSET_STATE: + nb_rest -= nb_read; + + if (nb_rest == 0) + { + nb_rest = elf_pht_ptr[pseg].p_filesz; + init_state = ELF_SEGMENT_STATE; + } + + break; + + /** + * Reading ELF segments + */ + case ELF_SEGMENT_STATE: + /** + * Copying ELF segment data in memory segments using the virtual + * address got from the ELF file + */ + segment_req = ((elf_pht_ptr[pseg].p_vaddr & 0xBFC00000) != 0xBFC00000); + + if ( segment_req ) + { + boot_memcpy((unsigned char *) elf_pht_ptr[pseg].p_vaddr + + (elf_pht_ptr[pseg].p_filesz - nb_rest), + buffer_ptr, + nb_read); + } + + nb_rest -= nb_read; + + if ( nb_rest == 0 ) + { + if ( segment_req ) + { + boot_puts("Copied segment at address "); + boot_putx(elf_pht_ptr[pseg].p_vaddr); + boot_puts("\n"); + + /* + * Fill remaining bytes with zeros (filesz < memsz) + */ + for ( i = 0 ; + i < (elf_pht_ptr[pseg].p_memsz - elf_pht_ptr[pseg].p_filesz) ; + i-- ) + { + *(unsigned char *) + (elf_pht_ptr[pseg].p_vaddr + elf_pht_ptr[pseg].p_filesz + i) = 0; + } + } + + /* + * Search the first not NULL segment in the ELF file + */ + for ( pseg = pseg + 1; pseg < elf_header_ptr->e_phnum; pseg++) { + if(elf_pht_ptr[pseg].p_type == PT_LOAD) + { + nb_rest = elf_pht_ptr[pseg].p_offset - offset; + break; + } + } + + /* + * Program loading finished + */ + if(pseg == elf_header_ptr->e_phnum) + { + init_state = ELF_END_STATE; + break; + } + + init_state = ELF_OFFSET_STATE; + } + break; + + default: + break; + } + + buffer_ptr += nb_read; + nb_available -= nb_read; + } + + boot_puts ( + "Finishing boot_elf_loader function.\n" + "Entry point address: " + ); + boot_putx(elf_header_ptr->e_entry); + boot_puts("\n"); + + return ((void *) elf_header_ptr->e_entry); +} Index: /trunk/softs/tsar_boot/src/boot_ioc.c =================================================================== --- /trunk/softs/tsar_boot/src/boot_ioc.c (revision 373) +++ /trunk/softs/tsar_boot/src/boot_ioc.c (revision 373) @@ -0,0 +1,197 @@ +#include + +#ifndef SOCLIB_IOC + +#ifndef SYSCLK_FREQ +#warning "Using default value for SYSCLK_FREQ = 50000000" +#define SYSCLK_FREQ 50000000U +#endif + +static struct sdcard_dev _sdcard_device; +static struct spi_dev * _spi_device = ( struct spi_dev * )IOC_BASE; +#endif + + +int boot_ioc_init() +{ +#ifdef SOCLIB_IOC + return 0; +#else + unsigned char sdcard_rsp; + + boot_puts("Initializing block device\n\r"); + + /** + * Initializing the SPI controller + */ + spi_dev_config ( + _spi_device , + 200000 , /**< SPI_clk: 200 Khz */ + SYSCLK_FREQ , /**< Sys_clk */ + 8 , /**< Charlen: 8 */ + SPI_TX_NEGEDGE, + SPI_RX_POSEDGE + ); + + /** + * Initializing the SD Card + */ + if ( (sdcard_rsp = sdcard_dev_open(&_sdcard_device, _spi_device, 0)) ) + return sdcard_rsp; + + if ( (sdcard_rsp = sdcard_dev_set_blocklen(&_sdcard_device, 512)) ) + return sdcard_rsp; + + /** + * Incrementing SDCARD clock frequency for normal function + */ + spi_dev_config ( + _spi_device , + 10000000 , /**< SPI_clkL 10 Mhz */ + SYSCLK_FREQ , /**< Sys_clk */ + -1 , /**< Charlen: 8 */ + -1 , + -1 + ); + + boot_puts("Finish block device initialization\n\r"); + + return 0; +#endif +} + +/** + * _boot_ioc_completed() + * + * This blocking function checks completion of an I/O transfer and reports errors. + * + * \note It returns 0 if the transfer is successfully completed. + * It returns -1 if an error has been reported. + */ +#ifdef SOCLIB_IOC +static int _boot_ioc_completed() +{ + unsigned int status = 0; + + + unsigned int * ioc_address = ( unsigned int * )VCIBD_BASE; + + while ( 1 ) + { + status = ioread32(&ioc_address[BLOCK_DEVICE_STATUS]); + + if (( status == BLOCK_DEVICE_READ_SUCCESS ) || + ( status == BLOCK_DEVICE_READ_ERROR )) + break; + } + + return status; +} +#endif + +/** + * boot_ioc_read() + * + * Transfer data from a file on the block device to a memory buffer. + * + * \param lba : first block index on the disk + * \param buffer : base address of the memory buffer + * \param count : number of blocks to be transfered + * + * \note This is a blocking function. The function returns once the transfer + * has finished + */ + +#ifdef SOCLIB_IOC +/////////////////////////////////////////////////////////////////////////////// +// SOCLIB version of the boot_ioc_read function + +int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count) +{ + + unsigned int * ioc_address = (unsigned int*)VCIBD_BASE; + + // block_device configuration + iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], + ( unsigned int ) buffer ); + + iowrite32( &ioc_address[BLOCK_DEVICE_COUNT], + ( unsigned int ) count ); + + iowrite32( &ioc_address[BLOCK_DEVICE_LBA], + ( unsigned int ) lba ); + + iowrite32( &ioc_address[BLOCK_DEVICE_IRQ_ENABLE], + ( unsigned int ) 0 ); + + iowrite32( &ioc_address[BLOCK_DEVICE_OP], + ( unsigned int ) BLOCK_DEVICE_READ ); + + _boot_ioc_completed(); + +#if (CACHE_COHERENCE == 0) + boot_dbuf_invalidate(buffer, CACHE_LINE_SIZE, count * 512); +#endif + return 0; +} + +#else +/////////////////////////////////////////////////////////////////////////////// +// FPGA version of the boot_ioc_read function + +int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count) +{ + unsigned int sdcard_rsp; + + sdcard_dev_lseek(&_sdcard_device, lba); + + unsigned int i; + for(i = 0; i < count; i++) + { + if (( sdcard_rsp = sdcard_dev_read ( + &_sdcard_device, + (unsigned char *) buffer + (512 * i), + 512 + ) + )) + { + boot_puts("ERROR during read on the SDCARD device. Code: "); + boot_putx(sdcard_rsp); + boot_puts("\n\r"); + + return 1; + } + } + + return 0; +} +#endif + +/** + * _dcache_buf_invalidate() + * + * Invalidate all data cache lines corresponding to a memory + * buffer (identified by an address and a size). + */ +#if (CACHE_COHERENCE == 0) +void boot_dbuf_invalidate ( + const void * buffer, + unsigned int line_size, + unsigned int size) +{ + unsigned int i; + + // iterate on cache lines + for (i = 0; i < size; i += line_size) { + asm volatile( + " cache %0, %1" + :// no outputs + :"i" (0x11), "R" (*((unsigned char *) buffer + i)) + ); + } +} +#endif + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab + */ Index: /trunk/softs/tsar_boot/src/boot_memcpy.c =================================================================== --- /trunk/softs/tsar_boot/src/boot_memcpy.c (revision 373) +++ /trunk/softs/tsar_boot/src/boot_memcpy.c (revision 373) @@ -0,0 +1,21 @@ +#include + +void * boot_memcpy(void *_dst, const void *_src, unsigned int size) +{ + unsigned int *dst = _dst; + const unsigned int *src = _src; + if ( ! ((unsigned int)dst & 3) && ! ((unsigned int)src & 3) ) + while (size > 3) { + *dst++ = *src++; + size -= 4; + } + + unsigned char *cdst = (unsigned char*) dst; + unsigned char *csrc = (unsigned char*) src; + + while (size--) { + *cdst++ = *csrc++; + } + return _dst; +} + Index: /trunk/softs/tsar_boot/src/boot_tty.c =================================================================== --- /trunk/softs/tsar_boot/src/boot_tty.c (revision 373) +++ /trunk/softs/tsar_boot/src/boot_tty.c (revision 373) @@ -0,0 +1,91 @@ +#include +#include + +int boot_getc(char *c) +{ + unsigned int* tty_address = (unsigned int*) TTY_BASE; + if (ioread32(&tty_address[TTY_STATUS]) == 0) + return 0; + + *c = ioread32(&tty_address[TTY_READ]); + return 1; +} + +void boot_putc(const char c) +{ + unsigned int* tty_address = (unsigned int*) TTY_BASE; + iowrite32(&tty_address[TTY_WRITE], (unsigned int)c); + + if (c == '\n') + { + iowrite32(&tty_address[TTY_WRITE], (unsigned int)'\r'); + } +} + +void boot_puts(const char *buffer) +{ + unsigned int n; + + for ( n=0; n<100; n++) + { + if (buffer[n] == 0) break; + + boot_putc(buffer[n]); + } +} + +void boot_putx(unsigned int val) +{ + static const char HexaTab[] = "0123456789ABCDEF"; + char buf[11]; + unsigned int c; + + buf[0] = '0'; + buf[1] = 'x'; + buf[10] = 0; + + for ( c = 0 ; c < 8 ; c++ ) + { + buf[9-c] = HexaTab[val&0xF]; + val = val >> 4; + } + boot_puts(buf); +} + +void boot_putd(unsigned int val) +{ + static const char DecTab[] = "0123456789"; + char buf[11]; + unsigned int i; + unsigned int first = 0; + + buf[10] = 0; + + for ( i = 0 ; i < 10 ; i++ ) + { + if ((val != 0) || (i == 0)) + { + buf[9-i] = DecTab[val % 10]; + first = 9-i; + } + else + { + break; + } + val /= 10; + } + boot_puts( &buf[first] ); +} + +void boot_exit() +{ + register int pid; + asm volatile( "mfc0 %0, $15, 1": "=r"(pid) ); + + boot_puts("\n!!! Exit Processor "); + boot_putx(pid); + boot_puts(" !!!\n"); + + while(1) asm volatile("nop"); // infinite loop... +} + Index: /trunk/softs/tsar_boot/src/exceptions.c =================================================================== --- /trunk/softs/tsar_boot/src/exceptions.c (revision 373) +++ /trunk/softs/tsar_boot/src/exceptions.c (revision 373) @@ -0,0 +1,23 @@ +/** + * \file : exceptions.c + * \date : December 2012 + * \author : Manuel Bouyer + * + * This file defines a simple exeptions handler + */ + +#include + +void handle_except(int status, int cause, int epc) +{ + boot_puts("boot (default) exeption handler called: \r\n status "); + boot_putx(status); + boot_puts("\r\n cause "); + boot_putx(cause); + boot_puts(" (exeption "); + boot_putx((cause >> 2) & 0x1f); + boot_puts(")\r\n epc "); + boot_putx(epc); + boot_puts("\r\n"); + while (1); +} Index: /trunk/softs/tsar_boot/src/reset.S =================================================================== --- /trunk/softs/tsar_boot/src/reset.S (revision 373) +++ /trunk/softs/tsar_boot/src/reset.S (revision 373) @@ -0,0 +1,218 @@ +/** + * \file : reset.S + * \date : 01/12/2012 + * \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner + * + * This is a boot code for a generic multi-clusters / multi-processors + * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). + * There is one XICU, one TTY, one DMA and one stack segment per cluster. + * segment base adresses = base + cluster_segment_increment*cluster_id + * + * - Each processor initializes the Status Register (SR) to disable interrupts. + * - Each processor initializes the Count Register. + * - Each processor initialises its private XICU Write Triggered Interruption + * mask register. + * - Only processor 0 initializes the stack pointer ($29). + * - Only processor 0 (boot processor) executes the boot_load_elf function to + * load in memory the boot loader stored in the block BOOT_LOADER_LBA of + * the disk. + * - All non-boot processors wait in a low power consumption mode that the + * processor 0 wakes them using the IPI (Inter Processor Interruption) + * functionality of the XICU device. + */ + + #include + #include + + .section .boot,"ax",@progbits + + .extern seg_stack_base + + .extern dtb_addr + .extern boot_putc + .extern boot_getc + .extern boot_ioc_read + .extern boot_elf_loader + .extern boot_memcpy + .extern boot_puts + .extern boot_putx + .extern boot_putd + .extern boot_ioc_init + + .globl boot /* Make reset an external symbol */ + .ent boot + + .align 2 + .set noreorder + +boot: + b _boot /* 0xbfc0000 */ + nop /* 0xbfc0004 */ + + /* Addresses of the functions provided by this pre-loader */ + + .word BOOT_VERSION /* 0xbfc0008 */ + .word dtb_addr /* 0xbfc000c */ + .word boot_putc /* 0xbfc0010 */ + .word boot_getc /* 0xbfc0014 */ + .word boot_ioc_read /* 0xbfc0018 */ + .word boot_elf_loader /* 0xbfc001C */ + .word boot_memcpy /* 0xbfc0020 */ + .word boot_puts /* 0xbfc0024 */ + .word boot_putx /* 0xbfc0028 */ + .word boot_putd /* 0xbfc002C */ + +_boot: + /* Disable interruptions, keep STATUSbev enabled */ + + li k0, (1 << 22) + mtc0 k0, CP0_STATUS + + /* Computes proc_id, local_id, cluster_id, and cluster_increment */ + + mfc0 k0, CP0_EBASE + andi t0, k0, 0x3FF /* t0 <= proc_id (at most 1024 processors) */ + + move t3, t0 + + la k0, NB_PROCS /* k0 <= number of processors per cluster */ + divu t3, k0 + mfhi t1 /* t1 <= local_id = proc_id % NB_PROCS */ + mflo t2 /* t2 <= cluster_id = proc_id / NB_PROCS */ + + la k0, NB_CLUSTERS + li t3, 0x80000000 + divu t3, k0 + mflo t4 + sll t4, 1 /* t4 <= cluster_increment = 4G / NB_CLUSTERS */ + + mult t4, t2 + mflo t5 /* t5 <= cluster_id * cluster_increment */ + + /* Initialization of the count register in the coprocessor 0 */ + + mtc0 zero, CP0_COUNT + + /* In each cluster, the ICU base address depends on the cluster_id */ + + la t3, ICU_BASE + addu t3, t3, t5 /* t3 <= ICU_BASE + */ + /* (cluster_id * cluster_increment) */ + + /** + * Compute the output index for the Write Triggered Interruption mask. + * Each processor enable the WTI for its irq output + * Each processor may have IRQ_PER_PROC private irq outputs from + * the XICU + */ + + move t4, t1 /* t4 <= local_id */ + li t5, IRQ_PER_PROC /* t5 <= IRQ_PER_PROC */ + multu t4, t5 + mflo t6 /* t6 <= IRQ_PER_PROC * local_id */ + sll t4, t6, 2 /* t4 <= OUT_INDEX = t6 * 4 */ + + li t5, (0xC << 7) /* t5 <= FUNC = XICU_MSK_WTI */ + or t4, t4, t5 /* t4 <= FUNC | INDEX | 00 */ + or t5, t3, t4 /* t5 <= &XICU[MSK_WTI][OUT_INDEX] */ + + /* Compute and set WTI mask */ + + li t4, 1 + sllv t4, t4, t1 /* Set XICU[MSK_WTI][INDEX][local_id] */ + sw t4, 0(t5) /* XICU[MSK_WTI][INDEX] <= t4 */ + + /** + * We have: + * t0: global id + * t1: local id + * t2: cluster id + * t3: xicu base address + * + * Only processor 0 in cluster 0 executes the boot loader + */ + + bne zero, t0, _reset_wait + nop + + /* Initializes stack pointer */ + + la k1, seg_stack_base + li k0, BOOT_STACK_SIZE + addu sp, k1, k0 /* sp <= seg_stack_base + BOOT_STACK_SIZE */ + +#ifndef SOCLIB_IOC + + /* Initialize the block device */ + + la k0, boot_ioc_init + jalr k0 + nop + +#endif + + /** + * Jump to the boot elf loader routine + * Passing as argument the block number in which it must be + * the executable elf file to load + */ + + la k0, boot_elf_loader + li a0, BOOT_LOADER_LBA + jalr k0 + nop + + /** + * We jump to the entry point address defined in the + * ELF file. This address is returned by boot_elf_loader function. + * All function arguments are 0 + */ + + move a0, zero + move a1, zero + move a2, zero + move a3, zero + jr v0 + nop + +/** + * Wait in low power consumption mode until the application wakes us. + * The application wakes up the non-boot CPUs using a IPI with a non-0 + * value in the mailbox. This non-0 value is the address to jump to. + */ + +_reset_wait: + /** + * We have: + * t0: global id + * t1: local id + * t2: cluster id + * t3: xicu base address + */ + + sll t4, t1, 2 /* t4 <= local_id * 4 */ + addu t5, t4, t3 /* t5 <= &XICU[WTI_REG][local_id] */ + + wait + + lw k0, 0(t5) /* k0 <= XICU[WTI_REG][local_id] */ + jr k0 + nop + +/* Exception entry point */ +.org 0x0380 +_excep: + mfc0 a0, CP0_STATUS /* first arg is status */ + mfc0 a1, CP0_CAUSE /* second arg is cause */ + mfc0 a2, CP0_EPC /* third argc is epc */ + nop + j handle_except + nop + + .end boot + + .set reorder + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab + */ Index: /trunk/softs/tsar_boot/src/sdcard.c =================================================================== --- /trunk/softs/tsar_boot/src/sdcard.c (revision 373) +++ /trunk/softs/tsar_boot/src/sdcard.c (revision 373) @@ -0,0 +1,291 @@ +/** + * \file : sdcard.c + * \date : 30 August 2012 + * \author : Cesar Fuguet + * + * This file defines the driver of a SD Card device using an SPI controller + */ + +#include + +/** + * \param sdcard: Initialized pointer to the block device + * + * \return void + * + * \brief Enable SD Card select signal + */ +static void _sdcard_enable(struct sdcard_dev * sdcard) +{ + spi_ss_assert(sdcard->spi, sdcard->slave_id); +} + +/** + * \param sdcard: Initialized pointer to the block device + * + * \return void + * + * \brief Disable SD Card select signal + */ +static void _sdcard_disable(struct sdcard_dev * sdcard) +{ + spi_ss_deassert(sdcard->spi, sdcard->slave_id); +} + +/** + * \param tick_count: SD Card clock ticks number + * + * \return void + * + * \brief Enable SD Card clock + * The tick count is byte measured (1 tick, 8 clock) + */ +static void _sdcard_gen_tick(struct sdcard_dev * sdcard, unsigned int tick_count) +{ + volatile register int i = 0; + while(i++ < tick_count) spi_put_tx(sdcard->spi, 0xFF, 0); +} + +/** + * \param sdcard: Initialized pointer to the block device + * + * \return char from the SD card + * + * \brief Get a byte from the SD Card + */ +static unsigned char _sdcard_receive_char(struct sdcard_dev * sdcard) +{ + _sdcard_gen_tick(sdcard, 1); + + return spi_get_rx(sdcard->spi, 0); +} + +/** + * \param sdcard: Initialized pointer to the block device + * + * \return sdcard response + * + * \brief Wait for a valid response after the send of a command + * This function can return if one of the next two conditions are true: + * 1. Bit valid received + * 2. Timeout (not valid bit received after SDCARD_COMMAND_TIMEOUT + * wait ticks) + */ +static unsigned char _sdcard_wait_response(struct sdcard_dev * sdcard) +{ + unsigned char sdcard_rsp; + register int iter; + + iter = 0; + sdcard_rsp = _sdcard_receive_char(sdcard); + while ( + (iter < SDCARD_COMMAND_TIMEOUT) && + !SDCARD_CHECK_R1_VALID(sdcard_rsp) + ) + { + sdcard_rsp = _sdcard_receive_char(sdcard); + iter++; + } + + return sdcard_rsp; +} + +/** + * \params sdcard: Initialized pointer to the block device + * + * \return void + * + * \brief Wait data block start marker + */ +static void _sdcard_wait_data_block(struct sdcard_dev * sdcard) +{ + while (_sdcard_receive_char(sdcard) != 0xFE); +} + +/** + * \param sdcard : Initialized pointer to block device + * \param index : SD card CMD index + * \param app : Type of command, 0 for normal command or 1 for application specific + * \param args : SD card CMD arguments + * + * \return response first byte + * + * \brief Send command to the SD card + */ +static int _sdcard_send_command ( + struct sdcard_dev * sdcard , + int index , + int app , + void * args , + unsigned crc7 ) +{ + unsigned char sdcard_rsp; + unsigned char * _args; + + _sdcard_gen_tick(sdcard, 5); + + if (app == SDCARD_ACMD) + { + spi_put_tx(sdcard->spi, 0x40 | 55 , 0 );/* CMD and START bit */ + spi_put_tx(sdcard->spi, 0x00 , 0 );/* Argument[0] */ + spi_put_tx(sdcard->spi, 0x00 , 0 );/* Argument[1] */ + spi_put_tx(sdcard->spi, 0x00 , 0 );/* Argument[2] */ + spi_put_tx(sdcard->spi, 0x00 , 0 );/* Argument[3] */ + spi_put_tx(sdcard->spi, 0x01 | (crc7 << 1), 0 );/* END bit */ + + sdcard_rsp = _sdcard_wait_response(sdcard); + if (SDCARD_CHECK_R1_ERROR(sdcard_rsp)) + { + return sdcard_rsp; + } + } + + _args = (unsigned char *) args; + + _sdcard_gen_tick(sdcard, 1); + + spi_put_tx(sdcard->spi, 0x40 | index , 0 ); + spi_put_tx(sdcard->spi, _args[0] , 0 ); + spi_put_tx(sdcard->spi, _args[1] , 0 ); + spi_put_tx(sdcard->spi, _args[2] , 0 ); + spi_put_tx(sdcard->spi, _args[3] , 0 ); + spi_put_tx(sdcard->spi, 0x01 | (crc7 << 1), 0 ); + + return _sdcard_wait_response(sdcard); +} + +int sdcard_dev_open(struct sdcard_dev * sdcard, struct spi_dev * spi, int ss) +{ + unsigned char args[4]; + unsigned char sdcard_rsp; + unsigned int iter; + + sdcard->spi = spi; + sdcard->slave_id = ss; + + /* + * Supply SD card ramp up time (min 74 cycles) + */ + _sdcard_gen_tick(sdcard, 10); + + /* + * Assert slave select signal + * Send CMD0 (Reset Command) + * Deassert slave select signal + */ + _sdcard_enable(sdcard); + + args[0] = 0; + args[1] = 0; + args[2] = 0; + args[3] = 0; + sdcard_rsp = _sdcard_send_command(sdcard, 0, SDCARD_CMD, args, 0x4A); + if ( sdcard_rsp != 0x01 ) + { + return sdcard_rsp; + } + + _sdcard_disable(sdcard); + _sdcard_enable(sdcard); + + iter = 0; + while( iter++ < SDCARD_COMMAND_TIMEOUT ) + { + sdcard_rsp = _sdcard_send_command(sdcard, 41, SDCARD_ACMD, args, 0x00); + if( sdcard_rsp == 0x01 ) + { + continue; + } + + break; + } + + _sdcard_disable(sdcard); + + return sdcard_rsp; +} + +int sdcard_dev_read(struct sdcard_dev * sdcard, void * buf, unsigned int count) +{ + unsigned char args[4]; + unsigned char sdcard_rsp; + register int i; + + for (i = 0; i < 4; i++) + args[i] = (sdcard->access_pointer >> (32 - (i+1)*8)) & 0xFF; + + _sdcard_enable(sdcard); + + sdcard_rsp = _sdcard_send_command(sdcard, 17, SDCARD_CMD, args, 0x00); + if ( SDCARD_CHECK_R1_ERROR(sdcard_rsp) ) + { + _sdcard_disable(sdcard); + return sdcard_rsp; + } + + _sdcard_wait_data_block(sdcard); + + for ( i = 0; i < count; i++ ) + { + *((char *) buf + i) = _sdcard_receive_char(sdcard); + } + + /* + * Get the remainder of the block bytes and the CRC16 (comes + * at the end of the data block) + */ + while( i++ < (sdcard->block_length + 2) ) _sdcard_receive_char(sdcard); + + _sdcard_disable(sdcard); + + /* + * Move the access pointer to the next block + */ + sdcard->access_pointer += sdcard->block_length; + + return 0; +} + +unsigned int sdcard_dev_write(struct sdcard_dev *sdcard, void * buf, unsigned int count) +{ + return 0; +} + +void sdcard_dev_lseek(struct sdcard_dev * sdcard, unsigned int blk_pos) +{ + sdcard->access_pointer = sdcard->block_length * blk_pos; +} + +unsigned int sdcard_dev_get_capacity(struct sdcard_dev * sdcard) +{ + return sdcard->capacity; +} + +int sdcard_dev_set_blocklen(struct sdcard_dev * sdcard, unsigned int len) +{ + unsigned char args[4]; + unsigned char sdcard_rsp; + register int i; + + for (i = 0; i < 4; i++) + args[i] = (len >> (32 - (i+1)*8)) & 0xFF; + + _sdcard_enable(sdcard); + + sdcard_rsp = _sdcard_send_command(sdcard, 16, SDCARD_CMD, args, 0x00); + if ( SDCARD_CHECK_R1_ERROR(sdcard_rsp) ) + { + _sdcard_disable(sdcard); + return sdcard_rsp; + } + + _sdcard_disable(sdcard); + + sdcard->block_length = len; + + return 0; +} + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4 + */ Index: /trunk/softs/tsar_boot/src/spi.c =================================================================== --- /trunk/softs/tsar_boot/src/spi.c (revision 373) +++ /trunk/softs/tsar_boot/src/spi.c (revision 373) @@ -0,0 +1,111 @@ +/* + * \file spi.c + * \data 31 August 2012 + * \author Cesar Fuguet + */ +#include + +/** + * \param spi : Initialized pointer to the SPI controller + * + * \brief Wait until the SPI controller has finished a transfer + * + * Wait until the GO_BUSY bit of the SPI controller be deasserted + */ +static void _spi_wait_if_busy(struct spi_dev * spi) +{ + volatile register int delay; + + while(SPI_IS_BUSY(spi)) + { + for (delay = 0; delay < 10000; delay++); + } +} + +/** + * \param spi : Initialized pointer to the SPI controller + * + * \return void + * + * \brief Init transfer of the tx registers to the selected slaves + */ +static void _spi_init_transfer(struct spi_dev * spi) +{ + unsigned int spi_ctrl = ioread32(&spi->ctrl); + + iowrite32(&spi->ctrl, spi_ctrl | SPI_CTRL_GO_BSY); +} + +/** + * \param spi_freq : Desired frequency for the generated clock from the SPI + * controller + * \param sys_freq : System clock frequency + * + * \brief Calculated the value for the divider register in order to obtain the SPI + * desired clock frequency + */ +static unsigned int _spi_calc_divider_value ( + unsigned int spi_freq , + unsigned int sys_freq ) +{ + return ((sys_freq / (spi_freq * 2)) - 1); +} + +void spi_put_tx(struct spi_dev * spi, unsigned char byte, int index) +{ + _spi_wait_if_busy(spi); + { + iowrite8(&spi->rx_tx[index % 4], byte); + _spi_init_transfer(spi); + + asm volatile("sync"); + } + _spi_wait_if_busy(spi); +} + +volatile unsigned char spi_get_rx(struct spi_dev * spi, int index) +{ + return ioread8(&spi->rx_tx[index % 4]); +} + +void spi_ss_assert(struct spi_dev * spi, int index) +{ + unsigned int spi_ss = ioread32(&spi->ss); + + iowrite32(&spi->ss, spi_ss | (1 << index)); +} + +void spi_ss_deassert(struct spi_dev * spi, int index) +{ + unsigned int spi_ss = ioread32(&spi->ss); + + iowrite32(&spi->ss, spi_ss & ~(1 << index)); +} + +void spi_dev_config ( + struct spi_dev * spi, + int spi_freq , + int sys_freq , + int char_len , + int tx_edge , + int rx_edge ) +{ + unsigned int spi_ctrl = ioread32(&spi->ctrl); + + if ( tx_edge == 0 ) spi_ctrl |= SPI_CTRL_TXN_EN; + else if ( tx_edge == 1 ) spi_ctrl &= ~SPI_CTRL_TXN_EN; + if ( rx_edge == 0 ) spi_ctrl |= SPI_CTRL_RXN_EN; + else if ( rx_edge == 1 ) spi_ctrl &= ~SPI_CTRL_RXN_EN; + if ( char_len > 0 ) spi_ctrl = (spi_ctrl & ~SPI_CTRL_CHAR_LEN_MASK) | + (char_len & SPI_CTRL_CHAR_LEN_MASK); + + iowrite32(&spi->ctrl, spi_ctrl); + + if (spi_freq > 0 && sys_freq > 0) + iowrite32(&spi->divider, _spi_calc_divider_value(spi_freq, sys_freq)); + +} + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4 + */