Index: /trunk/platforms/tsar_generic_xbar/Makefile =================================================================== --- /trunk/platforms/tsar_generic_xbar/Makefile (revision 378) +++ /trunk/platforms/tsar_generic_xbar/Makefile (revision 378) @@ -0,0 +1,6 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x tty* Index: /trunk/platforms/tsar_generic_xbar/soclib.conf =================================================================== --- /trunk/platforms/tsar_generic_xbar/soclib.conf (revision 378) +++ /trunk/platforms/tsar_generic_xbar/soclib.conf (revision 378) @@ -0,0 +1,3 @@ +config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI']) + +config.addDescPath("/dsk/l1/misc/joannou/tsar/trunk/") Index: /trunk/platforms/tsar_generic_xbar/top.cpp =================================================================== --- /trunk/platforms/tsar_generic_xbar/top.cpp (revision 378) +++ /trunk/platforms/tsar_generic_xbar/top.cpp (revision 378) @@ -0,0 +1,872 @@ +///////////////////////////////////////////////////////////////////////// +// File: top.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : august 2012 +// This program is released under the GNU public license +///////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture with virtual memory. +// The physical address space is 32 bits. +// The number of clusters cannot be larger than 256. +// The number of processors per cluster cannot be larger than 8. +// +// - It uses four dspin_local_crossbar per cluster as local interconnect +// - It uses two virtual_dspin routers per cluster as global interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains one vci_xicu and one vci_multi_dma per cluster. +// +// All clusters are identical, but the cluster containing address +// 0xBFC00000 (called io_cluster), contains 5 extra components: +// - the boot rom (BROM) +// - the disk controller (BDEV) +// - the multi-channel network controller (MNIC) +// - the multi-channel tty controller (MTTY) +// - the frame buffer controller (FBUF) +// +// It is build with one single component implementing a cluster: +// The Tsarv4ClusterMmu component is defined in files +// tsarv4_cluster_mmu.* (with * = cpp, h, sd) +// +// The IRQs are connected to XICUs as follow: +// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. +// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. +// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. +// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. +// +// The main hardware parameters must be defined in the hard_config.h file : +// - CLUSTER_X : number of clusters in a row (power of 2) +// - CLUSTER_Y : number of clusters in a column (power of 2) +// - CLUSTER_SIZE : size of the segment allocated to a cluster +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_DMAS_MAX : number of DMA channels per cluster (< 9) +// - NB_TTYS : number of TTY channels in I/O cluster (< 16) +// - NB_NICS : number of NIC channels in I/O cluster (< 9) +// +// Some secondary hardware parameters must be defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - BDEV_SECTOR_SIZE : block size for block drvice +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_TIMEOUT : max number of cycles before closing a container +// +// General policy for 32 bits physical address decoding: +// All segments base addresses are multiple of 64 Kbytes +// Therefore the 16 address MSB bits completely define the target: +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the 8 LSB bits define the local index: +// | X_ID | Y_ID |---| LADR | OFFSET | +// |x_width|y_width|---| 8 | 16 | +// +// General policy for hardware component indexing: +// Each component is identified by (x_id,y_id,l_id) tuple. +// | X_ID | Y_ID | L_ID | +// |x_width|y_width| 4 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "tsar_xbar_cluster.h" +#include "alloc_elems.h" + +/////////////////////////////////////////////////// +// OS +/////////////////////////////////////////////////// +#define USE_ALMOS 0 + +#define almos_bootloader_pathname "bootloader.bin" +#define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" +#define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// +#define USE_OPENMP 0 + +#if USE_OPENMP +#include +#endif + +// cluster index (computed from x,y coordinates) +#define cluster(x,y) (y + CLUSTER_Y*x) + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define cmd_width 40 +#define rsp_width 33 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// + +#define cell_width 4 +#define address_width 32 +#define plen_width 8 +#define error_width 2 +#define clen_width 1 +#define rflag_width 1 +#define srcid_width 14 +#define pktid_width 4 +#define trdid_width 4 +#define wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Main Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#include "giet_vm/hard_config.h" + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 + +#define BDEV_SECTOR_SIZE 512 +#define BDEV_IMAGE_NAME "giet_vm/display/images.raw" + +#define NIC_RX_NAME "giet_vm/nic/rx_data.txt" +#define NIC_TX_NAME "giet_vm/nic/tx_data.txt" +#define NIC_TIMEOUT 10000 + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM & RAM +//////////////////////i///////////////////////////////////// + +#define BOOT_SOFT_NAME "giet_vm/soft.elf" + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////i///////////////////////////////////// + +#define MAX_FROZEN_CYCLES 10000 + +#define TRACE_MEMC_ID 0 +#define TRACE_PROC_ID 0 + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// +// There is 3 segments replicated in all clusters +// and 5 specific segments in the "IO" cluster +// (containing address 0xBF000000) +///////////////////////////////////////////////////////// + +// specific segments in "IO" cluster : absolute physical address + +#define BROM_BASE 0xBFC00000 +#define BROM_SIZE 0x00100000 // 1 Mbytes + +#define FBUF_BASE 0xBFD00000 +#define FBUF_SIZE 0x00200000 // 2 Mbytes + +#define BDEV_BASE 0xBFF10000 +#define BDEV_SIZE 0x00001000 // 4 Kbytes + +#define MTTY_BASE 0xBFF20000 +#define MTTY_SIZE 0x00001000 // 4 Kbytes + +#define MNIC_BASE 0xBFF80000 +#define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes + +// replicated segments : address is incremented by a cluster offset +// offset = cluster(x,y) << (address_width-x_width-y_width); + +#define MEMC_BASE 0x00000000 +#define MEMC_SIZE 0x00C00000 // 12 Mbytes + +#define XICU_BASE 0x00F00000 +#define XICU_SIZE 0x00001000 // 4 Kbytes + +#define CDMA_BASE 0x00F30000 +#define CDMA_SIZE 0x00001000 * NB_DMAS_MAX // 4 Kbytes per channel + +//////////////////////////////////////////////////////////////////// +// TGTID definition in direct space +// For all components: global TGTID = global SRCID = cluster_index +//////////////////////////////////////////////////////////////////// + +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define CDMA_TGTID 2 +#define MTTY_TGTID 3 +#define FBUF_TGTID 4 +#define BROM_TGTID 5 +#define BDEV_TGTID 6 +#define MNIC_TGTID 7 + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + + char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code + size_t ncycles = 1000000000; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) + size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1 vci_param; + + // Define parameters depending on mesh size + size_t cluster_io_id; + size_t x_width; + size_t y_width; + + if (CLUSTER_X == 1) x_width = 0; + else if (CLUSTER_X == 2) x_width = 1; + else if (CLUSTER_X <= 4) x_width = 2; + else if (CLUSTER_X <= 8) x_width = 3; + else x_width = 4; + + if (CLUSTER_Y == 1) y_width = 0; + else if (CLUSTER_Y == 2) y_width = 1; + else if (CLUSTER_Y <= 4) y_width = 2; + else if (CLUSTER_Y <= 8) y_width = 3; + else y_width = 4; + + cluster_io_id = 0xBF >> (8 - x_width - y_width); + + ///////////////////// + // Mapping Tables + ///////////////////// + + // direct network + MappingTable maptabd(address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, srcid_width - x_width - y_width), + 0x00FF0000); + + for (size_t x = 0; x < CLUSTER_X; x++) + { + for (size_t y = 0; y < CLUSTER_Y; y++) + { + sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); + + std::ostringstream sh; + sh << "d_seg_memc_" << x << "_" << y; + maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); + + std::ostringstream si; + si << "d_seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); + + std::ostringstream sd; + sd << "d_seg_mdma_" << x << "_" << y; + maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); + + if ( cluster(x,y) == cluster_io_id ) + { + maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); + maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); + maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); + maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false)); + maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); + } + } + } + std::cout << maptabd << std::endl; + +/* + WE DONT NEED any COHERENCE MAPPING TABLE, AS THE DIRECT NETWORK + USES DIRECT ADRESSING (XID,YID,LID) + + // coherence network + // - tgtid_c_proc = srcid_c_proc = local procid + // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX + MappingTable maptabc(address_width, + IntTab(x_width + y_width, srcid_width - x_width - y_width), + IntTab(x_width + y_width, srcid_width - x_width - y_width), + 0x00FF0000); + + for (size_t x = 0; x < CLUSTER_X; x++) + { + for (size_t y = 0; y < CLUSTER_Y; y++) + { + sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); + + // cleanup requests must be routed to the memory cache + std::ostringstream sh; + sh << "c_seg_memc_" << x << "_" << y; + maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset, + 0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false)); + + // update & invalidate requests must be routed to the proper processor + for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++) + { + std::ostringstream sp; + sp << "c_seg_proc_" << x << "_" << y << "_" << p; + maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , + 0x10 , IntTab(cluster(x,y), p) , false)); + } + } + } + std::cout << maptabc << std::endl; + +*/ + + // external network + MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); + + for (size_t x = 0; x < CLUSTER_X; x++) + { + for (size_t y = 0; y < CLUSTER_Y ; y++) + { + sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); + std::ostringstream sh; + sh << "x_seg_memc_" << x << "_" << y; + maptabx.add(Segment(sh.str(), MEMC_BASE+offset, + MEMC_SIZE, IntTab(cluster(x,y)), false)); + } + } + std::cout << maptabx << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + // Horizontal inter-clusters DSPIN signals + DspinSignals*** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2); + DspinSignals*** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2); + DspinSignals*** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2); + DspinSignals*** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2); + + // Vertical inter-clusters DSPIN signals + DspinSignals*** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2); + DspinSignals*** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2); + DspinSignals*** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2); + DspinSignals*** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2); + + // Mesh boundaries DSPIN signals + DspinSignals**** signal_dspin_false_cmd_in = + alloc_elems >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4); + DspinSignals**** signal_dspin_false_cmd_out = + alloc_elems >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4); + DspinSignals**** signal_dspin_false_rsp_in = + alloc_elems >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4); + DspinSignals**** signal_dspin_false_rsp_out = + alloc_elems >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4); + + + //////////////////////////// + // Loader + //////////////////////////// + +#if USE_ALMOS + soclib::common::Loader loader(almos_bootloader_pathname, + almos_archinfo_pathname, + almos_kernel_pathname); +#else + soclib::common::Loader loader(soft_name); +#endif + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////// + // Clusters construction + //////////////////////////// + + TsarXbarCluster* clusters[CLUSTER_X][CLUSTER_Y]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for(size_t i = 0; i < (CLUSTER_X * CLUSTER_Y); i++) + { + size_t x = i / CLUSTER_Y; + size_t y = i % CLUSTER_Y; + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarXbarCluster + ( + sc.str().c_str(), + NB_PROCS_MAX, + NB_TTYS, + NB_DMAS_MAX, + x, + y, + cluster(x,y), + maptabd, + maptabx, + x_width, + y_width, + srcid_width - x_width - y_width, // l_id width, + MEMC_TGTID, + XICU_TGTID, + CDMA_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + MNIC_TGTID, + BDEV_TGTID, + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + XRAM_LATENCY, + (cluster(x,y) == cluster_io_id), + FBUF_X_SIZE, + FBUF_Y_SIZE, + disk_name, + BDEV_SECTOR_SIZE, + NB_NICS, + nic_rx_name, + nic_tx_name, + NIC_TIMEOUT, + loader, + frozen_cycles, + debug_from, + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id) + ); + + std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + /////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////// + + // Clock & RESET + for (size_t x = 0; x < (CLUSTER_X); x++){ + for (size_t y = 0; y < CLUSTER_Y; y++){ + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (CLUSTER_X > 1){ + for (size_t x = 0; x < (CLUSTER_X-1); x++){ + for (size_t y = 0; y < CLUSTER_Y; y++){ + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); + clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); + } + } + } + } + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (CLUSTER_Y > 1) { + for (size_t y = 0; y < (CLUSTER_Y-1); y++){ + for (size_t x = 0; x < CLUSTER_X; x++){ + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); + clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); + } + } + } + } + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < CLUSTER_Y; y++) + { + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); + clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); + clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); + clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); + + clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]); + } + } + + // North & South boundary clusters connections + for (size_t x = 0; x < CLUSTER_X; x++) + { + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); + clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); + clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); + clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); + + clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]); + } + } + + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // network boundaries signals + for (size_t x = 0; x < CLUSTER_X ; x++){ + for (size_t y = 0; y < CLUSTER_Y ; y++){ + for (size_t k = 0; k < 2; k++){ + for (size_t a = 0; a < 4; a++){ + signal_dspin_false_cmd_in[x][y][k][a].write = false; + signal_dspin_false_cmd_in[x][y][k][a].read = true; + signal_dspin_false_cmd_out[x][y][k][a].write = false; + signal_dspin_false_cmd_out[x][y][k][a].read = true; + + signal_dspin_false_rsp_in[x][y][k][a].write = false; + signal_dspin_false_rsp_in[x][y][k][a].read = true; + signal_dspin_false_rsp_out[x][y][k][a].write = false; + signal_dspin_false_rsp_out[x][y][k][a].read = true; + } + } + } + } + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + for (size_t n = 1; n < ncycles; n++) + { + + if (debug_ok and (n > debug_from) and (n % debug_period == 0)) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ************************************************" << std::endl; +/* + clusters[0][0]->proc[0]->print_trace(); + clusters[0][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_0_0 vci_ini"); + clusters[0][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_0_0"); + clusters[0][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_0_0"); + clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_0_0"); + clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_0_0"); + clusters[0][0]->memc->print_trace(); + clusters[0][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_0_vci_tgt"); + clusters[0][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_0"); + clusters[0][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_0"); + clusters[0][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_0"); + clusters[0][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_0"); + clusters[0][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_0"); + clusters[0][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_0"); + clusters[0][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_0"); + + clusters[0][1]->proc[0]->print_trace(); + clusters[0][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_1_0 vci_ini"); + clusters[0][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_1_0"); + clusters[0][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_1_0"); + clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_1_0"); + clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_1_0"); + clusters[0][1]->memc->print_trace(); + clusters[0][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_1_vci_tgt"); + clusters[0][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_1"); + clusters[0][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_1"); + clusters[0][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_1"); + clusters[0][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_1"); + clusters[0][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_1"); + clusters[0][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_1"); + clusters[0][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_1"); + + clusters[1][0]->proc[0]->print_trace(); + clusters[1][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_0_0 vci_ini"); + clusters[1][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_0_0"); + clusters[1][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_0_0"); + clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_0_0"); + clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_0_0"); + clusters[1][0]->memc->print_trace(); + clusters[1][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_0_vci_tgt"); + clusters[1][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_0"); + clusters[1][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_0"); + clusters[1][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_0"); + clusters[1][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_0"); + clusters[1][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_0"); + clusters[1][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_0"); + clusters[1][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_0"); + + clusters[1][1]->proc[0]->print_trace(); + clusters[1][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_1_0 vci_ini"); + clusters[1][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_1_0"); + clusters[1][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_1_0"); + clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_1_0"); + clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_1_0"); + clusters[1][1]->memc->print_trace(); + clusters[1][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_1_vci_tgt"); + clusters[1][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_1"); + clusters[1][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_1"); + clusters[1][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_1"); + clusters[1][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_1"); + clusters[1][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_1"); + clusters[1][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_1"); + clusters[1][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_1"); +*/ +/* + // trace proc[debug_proc_id] + if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) + { + size_t proc_x = debug_proc_id / CLUSTER_Y; + size_t proc_y = debug_proc_id % CLUSTER_Y; + + clusters[proc_x][proc_y]->proc[0]->print_trace(); + clusters[proc_x][proc_y]->signal_vci_ini_proc[0].print_trace("proc_0"); + } + + // trace memc[debug_memc_id] + if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) + { + size_t memc_x = debug_memc_id / CLUSTER_Y; + size_t memc_y = debug_memc_id % CLUSTER_Y; + + clusters[memc_x][memc_y]->memc->print_trace(); + clusters[memc_x][memc_y]->signal_vci_tgt_memc.print_trace("memc"); + } +*/ +// clusters[0][0]->signal_vci_tgt_xicu.print_trace("xicu_0_0"); +// clusters[0][1]->signal_vci_tgt_xicu.print_trace("xicu_0_1"); +// clusters[1][0]->signal_vci_tgt_xicu.print_trace("xicu_1_0"); +// clusters[1][1]->signal_vci_tgt_xicu.print_trace("xicu_1_1"); + +// if ( clusters[1][1]->signal_irq_mdma[0].read() ) +// std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; +// if ( clusters[1][1]->signal_proc_it[0].read() ) +// std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; + +// trace ioc component +// size_t io_x = cluster_io_id / CLUSTER_Y; +// size_t io_y = cluster_io_id % CLUSTER_Y; +// clusters[io_x][io_y]->bdev->print_trace(); +// clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("bdev_tgt "); +// clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("bdev_ini "); + +// clusters[1][1]->mdma->print_trace(); +// clusters[1][1]->signal_vci_tgt_mdma.print_trace("mdma_1_1_tgt "); +// clusters[1][1]->signal_vci_ini_mdma.print_trace("mdma_1_1_ini "); + + } + + sc_start(sc_core::sc_time(1, SC_NS)); + } + return EXIT_SUCCESS; +} + +int sc_main (int argc, char *argv[]) +{ + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 + + + + Index: /trunk/platforms/tsar_generic_xbar/top.desc =================================================================== --- /trunk/platforms/tsar_generic_xbar/top.desc (revision 378) +++ /trunk/platforms/tsar_generic_xbar/top.desc (revision 378) @@ -0,0 +1,24 @@ + +# -*- python -*- + +todo = Platform('caba', 'top.cpp', + uses = [ + Uses('caba:tsar_xbar_cluster', + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el', + cmd_width = 40, + rsp_width = 33), + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + cell_size = 4, + plen_size = 8, + addr_size = 32, + rerror_size = 2, + clen_size = 1, + rflag_size = 1, + srcid_size = 14, + pktid_size = 4, + trdid_size = 4, + wrplen_size = 1, +) Index: /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd =================================================================== --- /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 378) +++ /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 378) @@ -0,0 +1,55 @@ + +# -*- python -*- + +Module('caba:tsar_xbar_cluster', + classname = 'soclib::caba::TsarXbarCluster', + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + parameter.Module('iss_t'), + parameter.Int('cmd_width'), + parameter.Int('rsp_width'), + ], + header_files = [ '../source/include/tsar_xbar_cluster.h', ], + implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + Uses('caba:vci_cc_vcache_wrapper', + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + Uses('caba:vci_mem_cache'), + Uses('caba:vci_simple_ram'), + Uses('caba:vci_xicu'), + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('cmd_width')), + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('rsp_width')), + Uses('caba:vci_dspin_initiator_wrapper', + dspin_cmd_width = parameter.Reference('cmd_width'), + dspin_rsp_width = parameter.Reference('rsp_width')), + Uses('caba:vci_dspin_target_wrapper', + dspin_cmd_width = parameter.Reference('cmd_width'), + dspin_rsp_width = parameter.Reference('rsp_width')), + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('cmd_width')), + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('rsp_width')), + Uses('caba:vci_multi_tty'), + Uses('caba:vci_framebuffer'), + Uses('caba:vci_multi_nic'), + Uses('caba:vci_block_device_tsar'), + Uses('caba:vci_multi_dma'), + Uses('common:elf_file_loader'), + ], + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), + Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), + Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), + ], +) + + Index: /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h =================================================================== --- /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 378) +++ /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 378) @@ -0,0 +1,210 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_xbar_cluster_mmu.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2011 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_XBAR_CLUSTER_H +#define SOCLIB_CABA_TSAR_XBAR_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_xicu.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "virtual_dspin_router.h" +#include "vci_multi_tty.h" +#include "vci_multi_nic.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "vci_multi_dma.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template +class TsarXbarCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + + public: + + // Ports + sc_in p_clk; + sc_in p_resetn; + soclib::caba::DspinOutput **p_cmd_out; + soclib::caba::DspinInput **p_cmd_in; + soclib::caba::DspinOutput **p_rsp_out; + soclib::caba::DspinInput **p_rsp_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_it[8]; + sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_mtty[23]; + sc_signal signal_irq_mnic_rx[8]; // unused + sc_signal signal_irq_mnic_tx[8]; // unused + sc_signal signal_irq_bdev; + + // DSPIN signals between DSPIN routers and local_crossbars + DspinSignals signal_dspin_cmd_l2g_d; + DspinSignals signal_dspin_cmd_g2l_d; + DspinSignals signal_dspin_m2p_l2g_c; + DspinSignals signal_dspin_m2p_g2l_c; + DspinSignals signal_dspin_rsp_l2g_d; + DspinSignals signal_dspin_rsp_g2l_d; + DspinSignals signal_dspin_p2m_l2g_c; + DspinSignals signal_dspin_p2m_g2l_c; + + // Direct VCI signals to VCI/DSPIN wrappers + VciSignals signal_vci_ini_proc[8]; + VciSignals signal_vci_ini_mdma; + VciSignals signal_vci_ini_bdev; + + VciSignals signal_vci_tgt_memc; + VciSignals signal_vci_tgt_xicu; + VciSignals signal_vci_tgt_mdma; + VciSignals signal_vci_tgt_mtty; + VciSignals signal_vci_tgt_bdev; + VciSignals signal_vci_tgt_brom; + VciSignals signal_vci_tgt_fbuf; + VciSignals signal_vci_tgt_mnic; + + // Direct DSPIN signals to local crossbars + DspinSignals signal_dspin_cmd_proc_i[8]; + DspinSignals signal_dspin_rsp_proc_i[8]; + DspinSignals signal_dspin_cmd_mdma_i; + DspinSignals signal_dspin_rsp_mdma_i; + DspinSignals signal_dspin_cmd_bdev_i; + DspinSignals signal_dspin_rsp_bdev_i; + + DspinSignals signal_dspin_cmd_memc_t; + DspinSignals signal_dspin_rsp_memc_t; + DspinSignals signal_dspin_cmd_xicu_t; + DspinSignals signal_dspin_rsp_xicu_t; + DspinSignals signal_dspin_cmd_mdma_t; + DspinSignals signal_dspin_rsp_mdma_t; + DspinSignals signal_dspin_cmd_mtty_t; + DspinSignals signal_dspin_rsp_mtty_t; + DspinSignals signal_dspin_cmd_bdev_t; + DspinSignals signal_dspin_rsp_bdev_t; + DspinSignals signal_dspin_cmd_brom_t; + DspinSignals signal_dspin_rsp_brom_t; + DspinSignals signal_dspin_cmd_fbuf_t; + DspinSignals signal_dspin_rsp_fbuf_t; + DspinSignals signal_dspin_cmd_mnic_t; + DspinSignals signal_dspin_rsp_mnic_t; + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[8]; + DspinSignals signal_dspin_p2m_proc[8]; + + // external RAM VCI signal + VciSignals signal_vci_xram; + + // Components + + VciCcVCacheWrapper* proc[8]; + VciDspinInitiatorWrapper* wi_proc[4]; + + VciMemCache* memc; + VciDspinTargetWrapper* wt_memc; + + VciXicu* xicu; + VciDspinTargetWrapper* wt_xicu; + + VciMultiDma* mdma; + VciDspinInitiatorWrapper* wi_mdma; + VciDspinTargetWrapper* wt_mdma; + + VciSimpleRam* xram; + VciDspinTargetWrapper* wt_xram; + + VciSimpleRam* brom; + VciDspinTargetWrapper* wt_brom; + + VciMultiTty* mtty; + VciDspinTargetWrapper* wt_mtty; + + VciFrameBuffer* fbuf; + VciDspinTargetWrapper* wt_fbuf; + + VciMultiNic* mnic; + VciDspinTargetWrapper* wt_mnic; + + VciBlockDeviceTsar* bdev; + VciDspinInitiatorWrapper* wi_bdev; + VciDspinTargetWrapper* wt_bdev; + + DspinLocalCrossbar* xbar_cmd_d; + DspinLocalCrossbar* xbar_rsp_d; + DspinLocalCrossbar* xbar_m2p_c; + DspinLocalCrossbar* xbar_p2m_c; + + VirtualDspinRouter* router_cmd; + VirtualDspinRouter* router_rsp; + + TsarXbarCluster( sc_module_name insname, + size_t nb_procs, // number of processors + size_t nb_ttys, // number of TTY terminals + size_t nb_dmas, // number of DMA channels + size_t x, // x coordinate + size_t y, // y coordinate + size_t cluster, // y + ymax*x + const soclib::common::MappingTable &mtd, // direct mapping table + const soclib::common::MappingTable &mtx, // xram mapping table + size_t x_width, // x field number of bits + size_t y_width, // y field number of bits + size_t l_width, // l field number of bits + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mdma, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_mnic, + size_t tgtid_bdev, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, // external ram latency + bool io, // I/O cluster if true + size_t xfb, // frame buffer pixels + size_t yfb, // frame buffer lines + char* disk_name, // virtual disk for BDEV + size_t block_size, // block size for BDEV + size_t nic_channels, // number of channels + char* nic_rx_name, // file name rx packets + char* nic_tx_name, // file name tx packets + uint32_t nic_timeout, // number of cycles + const Loader &loader, // loader for BROM + uint32_t frozen_cycles, // max frozen cycles + uint32_t start_debug_cycle, + bool memc_debug_ok, + bool proc_debug_ok); + + ~TsarXbarCluster(); +}; +}} + +#endif Index: /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp =================================================================== --- /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 378) +++ /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 378) @@ -0,0 +1,730 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_xbar_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2011 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// This file define a TSAR cluster architecture with virtual memory: +// - It uses two virtual_dspin_router as distributed global interconnect +// - It uses four dspin_local_crossbar as local interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains a private RAM with a variable latency to emulate the L3 cache +// - It can contains 1, 2 or 4 processors +// - Each processor has a private dma channel (vci_multi_dma) +// - It uses the vci_xicu interrupt controller +// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in the cluster +// containing address 0xBFC00000. +// - The Multi-TTY component controls up to 15 terminals. +// - Each Multi-DMA component controls up to 8 DMA channels. +// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15] +// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30] +// - The BDEV IRQ is connected to IRQ_IN[31] +////////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_xbar_cluster.h" + +namespace soclib { +namespace caba { + +////////////////////////////////////////////////////////////////////////// +// Constructor +////////////////////////////////////////////////////////////////////////// +template +TsarXbarCluster::TsarXbarCluster( + sc_module_name insname, + size_t nb_procs, + size_t nb_ttys, + size_t nb_dmas, + size_t x_id, + size_t y_id, + size_t cluster_id, + const soclib::common::MappingTable &mtd, + const soclib::common::MappingTable &mtx, + size_t x_width, + size_t y_width, + size_t l_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mdma, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_mnic, + size_t tgtid_bdev, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + bool io, + size_t xfb, + size_t yfb, + char* disk_name, + size_t block_size, + size_t nic_channels, + char* nic_rx_name, + char* nic_tx_name, + uint32_t nic_timeout, + const Loader &loader, + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok) + : soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn") + +{ + // Vectors of ports definition + + p_cmd_in = alloc_elems >("p_cmd_in", 2, 4); + p_cmd_out = alloc_elems >("p_cmd_out", 2, 4); + p_rsp_in = alloc_elems >("p_rsp_in", 2, 4); + p_rsp_out = alloc_elems >("p_rsp_out", 2, 4); + + // Components definition + + // on direct network : local srcid[proc] in [0..nb_procs-1] + // on direct network : local srcid[mdma] = nb_procs + // on direct network : local srcid[bdev] = nb_procs + 1 + + // on coherence network : local srcid[proc] in [0...nb_procs-1] + // on coherence network : local srcid[memc] = nb_procs + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; + + for (size_t p = 0; p < nb_procs; p++) + { + std::ostringstream sproc; + sproc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper( + sproc.str().c_str(), + cluster_id*nb_procs + p, // GLOBAL PROC_ID + mtd, // Mapping Table + IntTab(cluster_id,p), // SRCID + (cluster_id << l_width) + p, // CC_GLOBAL_ID + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways,l1_i_sets,16, // ICACHE size + l1_d_ways,l1_d_sets,16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + frozen_cycles, // max frozen cycles + debug_start_cycle, + proc_debug_ok); + + std::ostringstream swip; + swip << "wi_proc_" << x_id << "_" << y_id << p; + wi_proc[p] = new VciDspinInitiatorWrapper( + swip.str().c_str(), + x_width + y_width + l_width); + } + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; + + std::ostringstream smemc; + smemc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + smemc.str().c_str(), + mtd, // Mapping Table direct space + mtx, // Mapping Table external space + IntTab(cluster_id), // SRCID external space + IntTab(cluster_id, tgtid_memc), // TGTID direct space + (cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + debug_start_cycle, + memc_debug_ok ); + + std::ostringstream swtm; + swtm << "wt_memc_" << x_id << "_" << y_id; + wt_memc = new VciDspinTargetWrapper( + swtm.str().c_str(), + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sxram; + sxram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + sxram.str().c_str(), + IntTab(cluster_id), + mtx, + loader, + xram_latency); +/* + std::ostringstream swtx; + swtx << "wt_xram_" << x_id << "_" << y_id; + wt_xram = new VciDspinTargetWrapper( + swtx.str().c_str(), + x_width + y_width ); +*/ + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sicu; + sicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + sicu.str().c_str(), + mtd, // mapping table + IntTab(cluster_id, tgtid_xicu), // TGTID_D + nb_procs, // number of timer IRQs + 32, // number of hard IRQs + 0, // number of soft IRQs + nb_procs); // number of output IRQs + + std::ostringstream swtu; + swtu << "wt_xicu_" << x_id << "_" << y_id; + wt_xicu = new VciDspinTargetWrapper( + swtu.str().c_str(), + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building mdma_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sdma; + sdma << "dma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( + sdma.str().c_str(), + mtd, + IntTab(cluster_id, nb_procs), // SRCID + IntTab(cluster_id, tgtid_mdma), // TGTID + 64, // burst size + nb_dmas); // number of IRQs + + std::ostringstream swta; + swta << "wt_mdma_" << x_id << "_" << y_id; + wt_mdma = new VciDspinTargetWrapper( + swtu.str().c_str(), + x_width + y_width + l_width); + + std::ostringstream swia; + swia << "wi_mdma_" << x_id << "_" << y_id; + wi_mdma = new VciDspinInitiatorWrapper( + swtu.str().c_str(), + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building xbar_cmd_d_" << x_id << "_" << y_id << std::endl; + + size_t nb_direct_initiators = nb_procs + 1; + size_t nb_direct_targets = 3; + if ( io ) + { + nb_direct_initiators = nb_procs + 2; + nb_direct_targets = 8; + } + + std::ostringstream sdcmd; + sdcmd << "xbar_cmd_d_" << x_id << "_" << y_id; + xbar_cmd_d = new DspinLocalCrossbar( + sdcmd.str().c_str(), + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + nb_direct_initiators, // number of local of sources + nb_direct_targets, // number of local dests + 2, 2, // fifo depths + true, // use local routing table + false ); // no broacast + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building xbar_rsp_d_" << x_id << "_" << y_id << std::endl; + + std::ostringstream sdrsp; + sdrsp << "xbar_rsp_d_" << x_id << "_" << y_id; + xbar_rsp_d = new DspinLocalCrossbar( + sdrsp.str().c_str(), + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + nb_direct_targets, // number of local sources + nb_direct_initiators, // number of local dests + 2, 2, // fifo depths + false, // don't use local routing table + false ); // no broacast + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building xbar_m2p_c" << x_id << "_" << y_id << std::endl; + + std::ostringstream sccmd; + sccmd << "xbar_m2p_c_" << x_id << "_" << y_id; + xbar_m2p_c = new DspinLocalCrossbar( + sccmd.str().c_str(), + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 2, 2, // fifo depths + false, // don't use local routing table + true ); // broacast + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building xbar_p2m_c_" << x_id << "_" << y_id << std::endl; + + std::ostringstream scrsp; + scrsp << "xbar_p2m_c_" << x_id << "_" << y_id; + xbar_p2m_c = new DspinLocalCrossbar( + scrsp.str().c_str(), + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // l_width unused on the network going from proc to memc (only X and Y identifie the cluster) + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // don't use local routing table + false ); // no broacast + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building router_cmd_" << x_id << "_" << y_id << std::endl; + + std::ostringstream scmdr; + scmdr << "router_cmd_" << x_id << "_" << y_id; + router_cmd = new VirtualDspinRouter( + scmdr.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + ///////////////////////////////////////////////////////////////////////////// + std::cout << " - building router_rsp_" << x_id << "_" << y_id << std::endl; + + std::ostringstream srspr; + srspr << "router_rsp_" << x_id << "_" << y_id; + router_rsp = new VirtualDspinRouter( + srspr.str().c_str(), + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + // IO cluster components + if ( io ) + { + ///////////////////////////////////////////// + std::cout << " - building brom" << std::endl; + + brom = new VciSimpleRam( + "brom", + IntTab(cluster_id, tgtid_brom), + mtd, + loader); + + wt_brom = new VciDspinTargetWrapper("wt_brom", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + std::cout << " - building fbuf" << std::endl; + + fbuf = new VciFrameBuffer( + "fbuf", + IntTab(cluster_id, tgtid_fbuf), + mtd, + xfb, yfb); + + wt_fbuf = new VciDspinTargetWrapper("wt_fbuf", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + std::cout << " - building bdev" << std::endl; + + bdev = new VciBlockDeviceTsar( + "bdev", + mtd, + IntTab(cluster_id, nb_procs+1), + IntTab(cluster_id, tgtid_bdev), + disk_name, + block_size, + 64); // burst size + + wt_bdev = new VciDspinTargetWrapper("wt_bdev", + x_width + y_width + l_width); + wi_bdev = new VciDspinInitiatorWrapper("wi_bdev", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + std::cout << " - building mnic" << std::endl; + + mnic = new VciMultiNic( + "mnic", + IntTab(cluster_id, tgtid_mnic), + mtd, + nic_channels, + nic_rx_name, + nic_tx_name, + 0, // mac_4 address + 0 ); // mac_2 address + + wt_mnic = new VciDspinTargetWrapper("wt_mnic", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + std::cout << " - building mtty" << std::endl; + + std::vector vect_names; + for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ ) + { + std::ostringstream term_name; + term_name << "term" << tid; + vect_names.push_back(term_name.str().c_str()); + } + mtty = new VciMultiTty( + "mtty", + IntTab(cluster_id, tgtid_mtty), + mtd, + vect_names); + + wt_mtty = new VciDspinTargetWrapper("wt_mtty", + x_width + y_width + l_width); + + } + + std::cout << std::endl; + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + //////////////////////// CMD ROUTER and RSP ROUTER + router_cmd->p_clk (this->p_clk); + router_cmd->p_resetn (this->p_resetn); + router_rsp->p_clk (this->p_clk); + router_rsp->p_resetn (this->p_resetn); + for (int x = 0; x < 2; x++) + { + for(int y = 0; y < 4; y++) + { + router_cmd->p_out[x][y] (this->p_cmd_out[x][y]); + router_cmd->p_in[x][y] (this->p_cmd_in[x][y]); + router_rsp->p_out[x][y] (this->p_rsp_out[x][y]); + router_rsp->p_in[x][y] (this->p_rsp_in[x][y]); + } + } + + router_cmd->p_out[0][4] (signal_dspin_cmd_g2l_d); + router_cmd->p_out[1][4] (signal_dspin_m2p_g2l_c); + router_cmd->p_in[0][4] (signal_dspin_cmd_l2g_d); + router_cmd->p_in[1][4] (signal_dspin_m2p_l2g_c); + + router_rsp->p_out[0][4] (signal_dspin_rsp_g2l_d); + router_rsp->p_out[1][4] (signal_dspin_p2m_g2l_c); + router_rsp->p_in[0][4] (signal_dspin_rsp_l2g_d); + router_rsp->p_in[1][4] (signal_dspin_p2m_l2g_c); + + std::cout << " - CMD & RSP routers connected" << std::endl; + + ///////////////////// CMD DSPIN local crossbar direct + xbar_cmd_d->p_clk (this->p_clk); + xbar_cmd_d->p_resetn (this->p_resetn); + xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d); + xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d); + + xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t); + xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t); + xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t); + + xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i); + + for (size_t p = 0; p < nb_procs; p++) + xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]); + + if ( io ) + { + xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t); + xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t); + xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t); + xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t); + xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t); + + xbar_cmd_d->p_local_in[nb_procs+1] (signal_dspin_cmd_bdev_i); + } + + std::cout << " - Command Direct crossbar connected" << std::endl; + + //////////////////////// RSP DSPIN local crossbar direct + xbar_rsp_d->p_clk (this->p_clk); + xbar_rsp_d->p_resetn (this->p_resetn); + xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d); + xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d); + + xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t); + xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t); + xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t); + + xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i); + + for (size_t p = 0; p < nb_procs; p++) + xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]); + + if ( io ) + { + xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t); + xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t); + xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t); + xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t); + xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t); + + xbar_rsp_d->p_local_out[nb_procs+1] (signal_dspin_rsp_bdev_i); + } + + std::cout << " - Response Direct crossbar connected" << std::endl; + + ////////////////////// M2P DSPIN local crossbar coherence + xbar_m2p_c->p_clk (this->p_clk); + xbar_m2p_c->p_resetn (this->p_resetn); + xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c); + xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c); + xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]); + + std::cout << " - M2P Coherence crossbar connected" << std::endl; + + ////////////////////////// P2M DSPIN local crossbar coherence + xbar_p2m_c->p_clk (this->p_clk); + xbar_p2m_c->p_resetn (this->p_resetn); + xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c); + xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c); + xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]); + + std::cout << " - P2M Coherence crossbar connected" << std::endl; + + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_vci_ini_proc[p]); + proc[p]->p_dspin_in (signal_dspin_m2p_proc[p]); + proc[p]->p_dspin_out (signal_dspin_p2m_proc[p]); + proc[p]->p_irq[0] (signal_proc_it[p]); + for ( size_t j = 1 ; j < 6 ; j++) + { + proc[p]->p_irq[j] (signal_false); + } + + wi_proc[p]->p_clk (this->p_clk); + wi_proc[p]->p_resetn (this->p_resetn); + wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]); + wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]); + wi_proc[p]->p_vci (signal_vci_ini_proc[p]); + } + + std::cout << " - Processors connected" << std::endl; + + ///////////////////////////////////// XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_vci_tgt_xicu); + for ( size_t p=0 ; pp_irq[p] (signal_proc_it[p]); + } + for ( size_t i=0 ; i<32 ; i++) + { + if ( io ) // I/O cluster + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]); + else if (i < 16) xicu->p_hwi[i] (signal_false); + else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]); + else if (i < 31) xicu->p_hwi[i] (signal_false); + else xicu->p_hwi[i] (signal_irq_bdev); + } + else // other clusters + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]); + else xicu->p_hwi[i] (signal_false); + } + } + + // wrapper XICU + wt_xicu->p_clk (this->p_clk); + wt_xicu->p_resetn (this->p_resetn); + wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t); + wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t); + wt_xicu->p_vci (signal_vci_tgt_xicu); + + std::cout << " - XICU connected" << std::endl; + + //////////////////////////////////////////////// MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_vci_ixr (signal_vci_xram); + memc->p_vci_tgt (signal_vci_tgt_memc); + memc->p_dspin_in (signal_dspin_p2m_memc); + memc->p_dspin_out (signal_dspin_m2p_memc); + + // wrapper MEMC + wt_memc->p_clk (this->p_clk); + wt_memc->p_resetn (this->p_resetn); + wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t); + wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t); + wt_memc->p_vci (signal_vci_tgt_memc); + + std::cout << " - MEMC connected" << std::endl; + + /////////////////////////////////////////////// XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_vci_xram); + + std::cout << " - XRAM connected" << std::endl; + + ////////////////////////////////////////////// MDMA + mdma->p_clk (this->p_clk); + mdma->p_resetn (this->p_resetn); + mdma->p_vci_target (signal_vci_tgt_mdma); + mdma->p_vci_initiator (signal_vci_ini_mdma); + for (size_t i=0 ; ip_irq[i] (signal_irq_mdma[i]); + + // wrapper tgt MDMA + wt_mdma->p_clk (this->p_clk); + wt_mdma->p_resetn (this->p_resetn); + wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t); + wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t); + wt_mdma->p_vci (signal_vci_tgt_mdma); + + // wrapper ini MDMA + wi_mdma->p_clk (this->p_clk); + wi_mdma->p_resetn (this->p_resetn); + wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i); + wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i); + wi_mdma->p_vci (signal_vci_ini_mdma); + + std::cout << " - MDMA connected" << std::endl; + + /////////////////////////////// Components in I/O cluster + + if ( io ) + { + // BDEV + bdev->p_clk (this->p_clk); + bdev->p_resetn (this->p_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_bdev); + bdev->p_vci_initiator (signal_vci_ini_bdev); + + // wrapper tgt BDEV + wt_bdev->p_clk (this->p_clk); + wt_bdev->p_resetn (this->p_resetn); + wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t); + wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t); + wt_bdev->p_vci (signal_vci_tgt_bdev); + + // wrapper ini BDEV + wi_bdev->p_clk (this->p_clk); + wi_bdev->p_resetn (this->p_resetn); + wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i); + wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i); + wi_bdev->p_vci (signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // FBUF + fbuf->p_clk (this->p_clk); + fbuf->p_resetn (this->p_resetn); + fbuf->p_vci (signal_vci_tgt_fbuf); + + // wrapper tgt FBUF + wt_fbuf->p_clk (this->p_clk); + wt_fbuf->p_resetn (this->p_resetn); + wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t); + wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t); + wt_fbuf->p_vci (signal_vci_tgt_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // MNIC + mnic->p_clk (this->p_clk); + mnic->p_resetn (this->p_resetn); + mnic->p_vci (signal_vci_tgt_mnic); + for ( size_t i=0 ; ip_rx_irq[i] (signal_irq_mnic_rx[i]); + mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + // wrapper tgt MNIC + wt_mnic->p_clk (this->p_clk); + wt_mnic->p_resetn (this->p_resetn); + wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t); + wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t); + wt_mnic->p_vci (signal_vci_tgt_mnic); + + std::cout << " - MNIC connected" << std::endl; + + // BROM + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_vci_tgt_brom); + + // wrapper tgt BROM + wt_brom->p_clk (this->p_clk); + wt_brom->p_resetn (this->p_resetn); + wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t); + wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t); + wt_brom->p_vci (signal_vci_tgt_brom); + + std::cout << " - BROM connected" << std::endl; + + // MTTY + mtty->p_clk (this->p_clk); + mtty->p_resetn (this->p_resetn); + mtty->p_vci (signal_vci_tgt_mtty); + for ( size_t i=0 ; ip_irq[i] (signal_irq_mtty[i]); + } + + // wrapper tgt MTTY + wt_mtty->p_clk (this->p_clk); + wt_mtty->p_resetn (this->p_resetn); + wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t); + wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t); + wt_mtty->p_vci (signal_vci_tgt_mtty); + + std::cout << " - MTTY connected" << std::endl; + } +} // end constructor + +/////////////////////////////////////////////////////////////////////////// +// destructor +/////////////////////////////////////////////////////////////////////////// +template +TsarXbarCluster::~TsarXbarCluster() {} + +} +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 + + +