Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 377)
+++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 385)
@@ -40,18 +40,18 @@
 /////////////////////////////////////////////////////////////////////////////////
 
-#define DEBUG_MEMC_GLOBAL   0 // synthetic trace of all FSMs
-#define DEBUG_MEMC_READ     1 // detailed trace of READ FSM
-#define DEBUG_MEMC_WRITE    1 // detailed trace of WRITE FSM
-#define DEBUG_MEMC_CAS      1 // detailed trace of CAS FSM
-#define DEBUG_MEMC_IXR_CMD  1 // detailed trace of IXR_RSP FSM
-#define DEBUG_MEMC_IXR_RSP  1 // detailed trace of IXR_RSP FSM
-#define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM
-#define DEBUG_MEMC_CC_SEND 1 // detailed trace of CC_SEND FSM
+#define DEBUG_MEMC_GLOBAL    0 // synthetic trace of all FSMs
+#define DEBUG_MEMC_READ      1 // detailed trace of READ FSM
+#define DEBUG_MEMC_WRITE     1 // detailed trace of WRITE FSM
+#define DEBUG_MEMC_CAS       1 // detailed trace of CAS FSM
+#define DEBUG_MEMC_IXR_CMD   1 // detailed trace of IXR_RSP FSM
+#define DEBUG_MEMC_IXR_RSP   1 // detailed trace of IXR_RSP FSM
+#define DEBUG_MEMC_XRAM_RSP  1 // detailed trace of XRAM_RSP FSM
+#define DEBUG_MEMC_CC_SEND   1 // detailed trace of CC_SEND FSM
 #define DEBUG_MEMC_MULTI_ACK 1 // detailed trace of MULTI_ACK FSM
-#define DEBUG_MEMC_TGT_CMD  1 // detailed trace of TGT_CMD FSM
-#define DEBUG_MEMC_TGT_RSP  1 // detailed trace of TGT_RSP FSM
-#define DEBUG_MEMC_CLEANUP  1 // detailed trace of CLEANUP FSM
-
-#define RANDOMIZE_CAS       1
+#define DEBUG_MEMC_TGT_CMD   1 // detailed trace of TGT_CMD FSM
+#define DEBUG_MEMC_TGT_RSP   1 // detailed trace of TGT_RSP FSM
+#define DEBUG_MEMC_CLEANUP   1 // detailed trace of CLEANUP FSM
+
+#define RANDOMIZE_CAS        1
 
 namespace soclib
@@ -273,6 +273,9 @@
 
 #define tmpl(x) \
-  template<typename vci_param> x \
-  VciMemCache<vci_param>
+  template<typename vci_param_int, \
+           typename vci_param_ext, \
+           size_t dspin_in_width,  \
+           size_t dspin_out_width> x \
+  VciMemCache<vci_param_int, vci_param_ext, dspin_in_width, dspin_out_width>
 
 using namespace soclib::common;
@@ -311,5 +314,5 @@
     m_nseg( 0 ),
     m_srcid_x( mtx.indexForId(srcid_x) ),
-    m_initiators( 1 << vci_param::S ),
+    m_initiators( 1 << vci_param_int::S ),
     m_heap_size( heap_size ),
     m_ways( nways ),
@@ -323,5 +326,5 @@
     m_upt_lines(upt_lines),
     m_upt(upt_lines),
-    m_cache_directory(nways, nsets, nwords, vci_param::N),
+    m_cache_directory(nways, nsets, nwords, vci_param_int::N),
     m_cache_data(nways, nsets, nwords),
     m_heap(m_heap_size),
@@ -332,6 +335,6 @@
     m_x(L2(m_words), 2),
     m_y(L2(m_sets), L2(m_words) + 2),
-    m_z(vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
-    m_nline(vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+    m_z(vci_param_int::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline(vci_param_int::N - L2(m_words) - 2, L2(m_words) + 2),
 #undef L2
 
@@ -420,7 +423,18 @@
 
     // check Transaction table size
-    assert((uint32_log2(trt_lines) <= vci_param::T) and
-         "Need more bits for VCI TRDID field");
-
+    assert((uint32_log2(trt_lines) <= vci_param_ext::T) and
+         "MEMC ERROR : Need more bits for VCI TRDID field");
+
+    // check internal and external data width
+    assert( (vci_param_int::B == 4 ) and
+         "MEMC ERROR : VCI internal data width must be 32 bits");
+          
+    assert( (vci_param_ext::B == 8 ) and
+         "MEMC ERROR : VCI external data width must be 32 or 64 bits");
+
+    // Check coherence between internal & external addresses
+    assert( (vci_param_int::N == vci_param_ext::N) and
+         "MEMC ERROR : VCI internal & external addresses must have the same width");
+          
     // Get the segments associated to the MemCache
     std::list<soclib::common::Segment>::iterator seg;
@@ -475,5 +489,5 @@
 
 ///////////////////////////////////////////////////////////////////////
-tmpl(void) ::start_monitor(vci_addr_t addr, vci_addr_t length)
+tmpl(void) ::start_monitor(addr_t addr, addr_t length)
 ///////////////////////////////////////////////////////////////////////
 {
@@ -490,30 +504,25 @@
 }
 
-///////////////////////////////////////////////////////////////////////
-tmpl(void) ::check_monitor(const char *buf, vci_addr_t addr, data_t data)
-///////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////
+tmpl(void) ::check_monitor( const char  *buf, 
+                            addr_t      addr, 
+                            data_t      data,
+                            bool        read )
+////////////////////////////////////////////////
 {
   if((addr >= m_monitor_base) and
       (addr < m_monitor_base + m_monitor_length))
   {
-    std::cout << " MEMC Write Monitor : " << buf << " Address = " << std::hex << addr
-              << " / Data = " << data << " at cycle " << std::dec << m_cpt_cycles << std::endl;
+    if ( read ) std::cout << " MEMC Read Monitor ";
+    else        std::cout << " MEMC Write Monitor "; 
+    std::cout << buf 
+              << " Address = " << std::hex << addr
+              << " / Data = " << data 
+              << " at cycle " << std::dec << m_cpt_cycles << std::endl;
   }
 }
 
-///////////////////////////////////////////////////////////////////////
-tmpl(void) ::check_monitor_read(const char *buf, vci_addr_t addr)
-///////////////////////////////////////////////////////////////////////
-{
-  if((addr >= m_monitor_base) and
-      (addr < m_monitor_base + m_monitor_length))
-  {
-    std::cout << " MEMC Read Monitor : " << buf << " Address = " << std::hex << addr
-              << std::endl;
-  }
-}
-
 /////////////////////////////////////////////////////
-tmpl(void) ::copies_monitor(vci_addr_t addr)
+tmpl(void) ::copies_monitor(addr_t addr)
 /////////////////////////////////////////////////////
 {
@@ -632,6 +641,6 @@
     m_debug_tgt_cmd_fsm    = false;
     m_debug_tgt_rsp_fsm    = false;
-    m_debug_cc_send_fsm  = false;
-    m_debug_cc_receive_fsm  = false;
+    m_debug_cc_send_fsm    = false;
+    m_debug_cc_receive_fsm = false;
     m_debug_multi_ack_fsm  = false;
     m_debug_read_fsm       = false;
@@ -864,5 +873,5 @@
           std::cout
               << "  <MEMC " << name()
-              << ".TGT_CMD_IDLE> Receive command from srcid "
+              << " TGT_CMD_IDLE> Receive command from srcid "
               << std::dec << p_vci_tgt.srcid.read()
               << " / for address "
@@ -872,5 +881,5 @@
 #endif
         // checking segmentation violation
-        vci_addr_t  address = p_vci_tgt.address.read();
+        addr_t  address = p_vci_tgt.address.read();
         uint32_t    plen    = p_vci_tgt.plen.read();
         bool found = false;
@@ -878,5 +887,5 @@
         {
           if(m_seg[seg_id]->contains(address) &&
-              m_seg[seg_id]->contains(address + plen - vci_param::B))
+              m_seg[seg_id]->contains(address + plen - vci_param_int::B))
           {
             found = true;
@@ -893,5 +902,5 @@
         }
 
-        if(p_vci_tgt.cmd.read() == vci_param::CMD_READ)
+        if(p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
         {
           // check that the pktid is either :
@@ -906,5 +915,5 @@
           r_tgt_cmd_fsm = TGT_CMD_READ;
         }
-        else if(p_vci_tgt.cmd.read() == vci_param::CMD_WRITE)
+        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
         {
           // check that the pktid is TYPE_WRITE
@@ -915,5 +924,5 @@
           r_tgt_cmd_fsm = TGT_CMD_WRITE;
         }
-        else if(p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ)
+        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
         {
           // check that the pktid is TYPE_LL
@@ -924,5 +933,5 @@
           r_tgt_cmd_fsm = TGT_CMD_READ;
         }
-        else if(p_vci_tgt.cmd.read() == vci_param::CMD_NOP)
+        else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)
         {
           // check that the pktid is either :
@@ -954,5 +963,6 @@
       // This test checks that the read does not cross a cache line limit.
       // It must not be taken into account when dealing with an LL CMD.
-      if(((m_x[(vci_addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) && (p_vci_tgt.cmd.read() != vci_param::CMD_LOCKED_READ))
+      if(((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) && 
+          (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ))
       {
         std::cout
@@ -973,5 +983,5 @@
         exit(0);
       }
-      if((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) && (p_vci_tgt.plen.read() != 8))
+      if((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) && (p_vci_tgt.plen.read() != 8))
       {
         std::cout
@@ -990,5 +1000,5 @@
         if(m_debug_tgt_cmd_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".TGT_CMD_READ> Push into read_fifo:"
+          std::cout << "  <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:"
                     << " address = " << std::hex << p_vci_tgt.address.read()
                     << " srcid = " << std::dec << p_vci_tgt.srcid.read()
@@ -999,5 +1009,5 @@
 #endif
         cmd_read_fifo_put = true;
-        if(p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ)
+        if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
           m_cpt_ll++;
         else
@@ -1015,5 +1025,5 @@
         if(m_debug_tgt_cmd_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".TGT_CMD_WRITE> Push into write_fifo:"
+          std::cout << "  <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:"
                     << " address = " << std::hex << p_vci_tgt.address.read()
                     << " srcid = " << std::dec << p_vci_tgt.srcid.read()
@@ -1048,5 +1058,5 @@
         if(m_debug_tgt_cmd_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
+          std::cout << "  <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
                     << " address = " << std::hex << p_vci_tgt.address.read()
                     << " srcid = " << std::dec << p_vci_tgt.srcid.read()
@@ -1153,5 +1163,5 @@
           std::cout
             <<  "  <MEMC " << name()
-            << ".MULTI_ACK_IDLE> Response for UPT entry "
+            << " MULTI_ACK_IDLE> Response for UPT entry "
             << updt_index
             << std::endl;
@@ -1195,5 +1205,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:"
+            << " MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:"
             << " entry = "       << r_multi_ack_upt_index.read()
             << " / rsp_count = " << std::dec << count
@@ -1240,5 +1250,5 @@
           std::cout
             <<  "  <MEMC " << name()
-            << ".MULTI_ACK_UPT_CLEAR> Clear UPT entry "
+            << " MULTI_ACK_UPT_CLEAR> Clear UPT entry "
             << r_multi_ack_upt_index.read()
             << std::endl;
@@ -1265,5 +1275,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".MULTI_ACK_WRITE_RSP> Request TGT_RSP FSM to send a response to srcid "
+            << " MULTI_ACK_WRITE_RSP> Request TGT_RSP FSM to send a response to srcid "
             << r_multi_ack_srcid.read()
             << std::endl;
@@ -1309,5 +1319,5 @@
         if(m_debug_read_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".READ_IDLE> Read request:"
+          std::cout << "  <MEMC " << name() << " READ_IDLE> Read request:"
                     << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
                     << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
@@ -1334,5 +1344,5 @@
       {
         std::cout
-            << "  <MEMC " << name() << ".READ_DIR_REQ> Requesting DIR lock "
+            << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock "
             << std::endl;
       }
@@ -1393,5 +1403,5 @@
         {
           std::cout
-              << "  <MEMC " << name() << ".READ_DIR_LOCK> Accessing directory: "
+              << "  <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: "
               << " address = " << std::hex << m_cmd_read_addr_fifo.read()
               << " / hit = " << std::dec << entry.valid
@@ -1401,5 +1411,5 @@
           {
             std::cout
-                << "  <MEMC " << name() << ".READ_DIR_LOCK> global_llsc_table LL access" << std::endl;
+                << "  <MEMC " << name() << " READ_DIR_LOCK> global_llsc_table LL access" << std::endl;
           }
         }
@@ -1441,5 +1451,5 @@
 
         // read data in the cache
-        size_t set        = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        size_t set        = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
         size_t way        = r_read_way.read();
 
@@ -1451,5 +1461,5 @@
         entry.is_cnt  = is_cnt;
         entry.dirty   = r_read_dirty.read();
-        entry.tag   = r_read_tag.read();
+        entry.tag     = r_read_tag.read();
         entry.lock    = r_read_lock.read();
         entry.ptr     = r_read_ptr.read();
@@ -1489,5 +1499,5 @@
         {
           std::cout
-              << "  <MEMC " << name() << ".READ_DIR_HIT> Update directory entry:"
+              << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
               << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
               << " / set = " << std::dec << set
@@ -1499,12 +1509,14 @@
         }
 #endif
-/**/
+
           if(m_monitor_ok)
           {
             char buf[80];
-            snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", m_cmd_read_srcid_fifo.read(), ((m_cmd_read_pktid_fifo.read()&0x2)!=0));
-            check_monitor_read(buf, m_cmd_read_addr_fifo.read());
+            snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", 
+                     (int)m_cmd_read_srcid_fifo.read(), 
+                     (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0));
+            check_monitor(buf, m_cmd_read_addr_fifo.read(), r_read_data[0], true);
           }
-/**/
+
 
         m_cache_directory.write(set, way, entry);
@@ -1518,12 +1530,4 @@
       // Get the lock to the HEAP directory
     {
-/**/
-          if(m_monitor_ok)
-          {
-            char buf[80];
-            snprintf(buf, 80, "READ_HEAP_REQ srcid %d, ins %d", m_cmd_read_srcid_fifo.read(), ((m_cmd_read_pktid_fifo.read()&0x2)!=0));
-            check_monitor_read(buf, m_cmd_read_addr_fifo.read());
-          }
-/**/
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
       {
@@ -1535,5 +1539,5 @@
       {
         std::cout
-            << "  <MEMC " << name() << ".READ_HEAP_REQ> Requesting HEAP lock "
+            << "  <MEMC " << name() << " READ_HEAP_REQ> Requesting HEAP lock "
             << std::endl;
       }
@@ -1553,5 +1557,5 @@
 
         // read data in the cache
-        size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
         size_t way = r_read_way.read();
 
@@ -1625,5 +1629,5 @@
         if(m_debug_read_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".READ_HEAP_LOCK> Update directory:"
+          std::cout << "  <MEMC " << name() << " READ_HEAP_LOCK> Update directory:"
                     << " tag = " << std::hex << entry.tag
                     << " set = " << std::dec << set
@@ -1677,5 +1681,5 @@
         {
           std::cout
-              << "  <MEMC " << name() << ".READ_HEAP_WRITE> Add an entry in the heap:"
+              << "  <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:"
               << " owner_id = " << heap_entry.owner.srcid
               << " owner_ins = " << heap_entry.owner.inst << std::endl;
@@ -1763,5 +1767,5 @@
       {
         for(size_t i=0 ; i<m_words ; i++)  r_read_to_tgt_rsp_data[i] = r_read_data[i];
-        r_read_to_tgt_rsp_word   = m_x[(vci_addr_t) m_cmd_read_addr_fifo.read()];
+        r_read_to_tgt_rsp_word   = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
         r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
         r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
@@ -1776,5 +1780,5 @@
         if(m_debug_read_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".READ_RSP> Request the TGT_RSP FSM to return data:"
+          std::cout << "  <MEMC " << name() << " READ_RSP> Request the TGT_RSP FSM to return data:"
                     << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read()
                     << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
@@ -1792,5 +1796,5 @@
       {
         size_t      index     = 0;
-        vci_addr_t  addr      = (vci_addr_t) m_cmd_read_addr_fifo.read();
+        addr_t      addr      = (addr_t) m_cmd_read_addr_fifo.read();
         bool        hit_read  = m_trt.hit_read(m_nline[addr], index);
         bool        hit_write = m_trt.hit_write(m_nline[addr]);
@@ -1813,5 +1817,5 @@
         if(m_debug_read_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".READ_TRT_LOCK> Check TRT:"
+          std::cout << "  <MEMC " << name() << " READ_TRT_LOCK> Check TRT:"
                     << " hit_read = " << hit_read
                     << " / hit_write = " << hit_write
@@ -1830,5 +1834,5 @@
         m_trt.set(r_read_trt_index.read(),
                               true,
-                              m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                              m_nline[(addr_t)(m_cmd_read_addr_fifo.read())],
                               m_cmd_read_srcid_fifo.read(),
                               m_cmd_read_trdid_fifo.read(),
@@ -1836,5 +1840,5 @@
                               true,
                               m_cmd_read_length_fifo.read(),
-                              m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                              m_x[(addr_t)(m_cmd_read_addr_fifo.read())],
                               std::vector<be_t> (m_words,0),
                               std::vector<data_t> (m_words,0),
@@ -1843,5 +1847,5 @@
         if(m_debug_read_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".READ_TRT_SET> Write in Transaction Table: " << std::hex
+          std::cout << "  <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table: " << std::hex
                     << " address = " << std::hex << m_cmd_read_addr_fifo.read()
                     << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
@@ -1864,5 +1868,5 @@
         cmd_read_fifo_get       = true;
         r_read_to_ixr_cmd_req   = true;
-        r_read_to_ixr_cmd_nline = m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
         r_read_to_ixr_cmd_trdid = r_read_trt_index.read();
         r_read_fsm              = READ_IDLE;
@@ -1872,5 +1876,5 @@
         {
           std::cout
-              << "  <MEMC " << name() << ".READ_TRT_REQ> Request GET transaction for address "
+              << "  <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address "
               << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
         }
@@ -1929,5 +1933,5 @@
         // consume a word in the FIFO & write it in the local buffer
         cmd_write_fifo_get  = true;
-        size_t index        = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+        size_t index        = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
 
         r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
@@ -1959,5 +1963,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_IDLE> Write request "
+          std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
                     << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
                     << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
@@ -1979,5 +1983,5 @@
         {
           std::cout << "  <MEMC " << name()
-                    << ".WRITE_NEXT> Write another word in local buffer"
+                    << " WRITE_NEXT> Write another word in local buffer"
                     << std::endl;
         }
@@ -1986,6 +1990,6 @@
 
         // check that the next word is in the same cache line
-        if((m_nline[(vci_addr_t)(r_write_address.read())]       !=
-            m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())]))
+        if((m_nline[(addr_t)(r_write_address.read())]       !=
+            m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]))
         {
           std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_NEXT state" << std::endl
@@ -2063,5 +2067,5 @@
       {
         std::cout
-            << "  <MEMC " << name() << ".WRITE_DIR_REQ> Requesting DIR lock "
+            << "  <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "
             << std::endl;
       }
@@ -2112,5 +2116,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> Check the directory: "
+          std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
                     << " address = " << std::hex << r_write_address.read()
                     << " hit = " << std::dec << entry.valid
@@ -2118,7 +2122,7 @@
                     << " is_cnt = " << entry.is_cnt << std::endl;
           if((r_write_pktid.read() & 0x7) == TYPE_SC)
-            std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> global_llsc_table SC access" << std::endl;
+            std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_table SC access" << std::endl;
           else
-            std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> global_llsc_table SW access" << std::endl;
+            std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_table SW access" << std::endl;
         }
 #endif
@@ -2140,5 +2144,5 @@
     {
       // update local buffer
-      size_t set  = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t set  = m_y[(addr_t)(r_write_address.read())];
       size_t way  = r_write_way.read();
       for(size_t word=0 ; word<m_words ; word++)
@@ -2162,5 +2166,5 @@
       if(m_debug_write_fsm)
       {
-        std::cout << "  <MEMC " << name() << ".WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
+        std::cout << "  <MEMC " << name() << " WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
       }
 #endif
@@ -2187,5 +2191,5 @@
       entry.ptr            = r_write_ptr.read();
 
-      size_t set           = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t set           = m_y[(addr_t)(r_write_address.read())];
       size_t way           = r_write_way.read();
 
@@ -2213,8 +2217,9 @@
           if(m_monitor_ok)
           {
-            vci_addr_t address = (r_write_address.read() & ~(vci_addr_t) 0x3F) | word<<2;
+            addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
             char buf[80];
-            snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", r_write_srcid.read());
-            check_monitor(buf, address, r_write_data[word].read());
+            snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", 
+                     (int)r_write_srcid.read());
+            check_monitor(buf, address, r_write_data[word].read(), false);
           }
         }
@@ -2250,10 +2255,10 @@
         if(no_update)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Write into cache / No coherence transaction"
+          std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
                     << std::endl;
         }
         else
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Coherence update required:"
+          std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"
                     << " is_cnt = " << r_write_is_cnt.read()
                     << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
@@ -2276,7 +2281,7 @@
         size_t      trdid      = r_write_trdid.read();
         size_t      pktid      = r_write_pktid.read();
-        addr_t      nline      = m_nline[(vci_addr_t)(r_write_address.read())];
+        addr_t      nline      = m_nline[(addr_t)(r_write_address.read())];
         size_t      nb_copies  = r_write_count.read();
-        size_t      set        = m_y[(vci_addr_t)(r_write_address.read())];
+        size_t      set        = m_y[(addr_t)(r_write_address.read())];
         size_t      way        = r_write_way.read();
 
@@ -2294,12 +2299,16 @@
           for(size_t word=0 ; word<m_words ; word++)
           {
-            m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
+            m_cache_data.write(way, 
+                               set, 
+                               word, 
+                               r_write_data[word].read(), 
+                               r_write_be[word].read());
 
             if(m_monitor_ok)
             {
-              vci_addr_t address = (r_write_address.read() & ~(vci_addr_t) 0x3F) | word<<2;
+              addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
               char buf[80];
-              snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", srcid);
-              check_monitor(buf, address, r_write_data[word].read());
+              snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", (int)srcid);
+              check_monitor(buf, address, r_write_data[word].read(), false);
             }
           }
@@ -2311,5 +2320,5 @@
           if(wok)
           {
-            std::cout << "  <MEMC " << name() << ".WRITE_UPT_LOCK> Register the multicast update in UPT / "
+            std::cout << "  <MEMC " << name() << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
                       << " nb_copies = " << r_write_count.read() << std::endl;
           }
@@ -2333,5 +2342,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
+          std::cout << "  <MEMC " << name() << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
         }
 #endif
@@ -2353,5 +2362,5 @@
         r_write_to_cc_send_brdcast_req  = false;
         r_write_to_cc_send_trdid        = r_write_upt_index.read();
-        r_write_to_cc_send_nline        = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_cc_send_nline        = m_nline[(addr_t)(r_write_address.read())];
         r_write_to_cc_send_index        = r_write_word_index.read();
         r_write_to_cc_send_count        = r_write_word_count.read();
@@ -2397,5 +2406,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_UPT_REQ> Post first request to CC_SEND FSM"
+          std::cout << "  <MEMC " << name() << " WRITE_UPT_REQ> Post first request to CC_SEND FSM"
                     << " / srcid = " << std::dec << r_write_copy.read()
                     << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
@@ -2441,5 +2450,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Post another request to CC_SEND FSM"
+          std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM"
                     << " / heap_index = " << std::dec << r_write_ptr.read()
                     << " / srcid = " << std::dec << r_write_copy.read()
@@ -2457,5 +2466,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
+          std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
                     << " / heap_index = " << std::dec << r_write_ptr.read()
                     << " / srcid = " << std::dec << r_write_copy.read()
@@ -2535,5 +2544,5 @@
           // consume a word in the FIFO & write it in the local buffer
           cmd_write_fifo_get  = true;
-          size_t index        = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+          size_t index        = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
 
           r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
@@ -2570,5 +2579,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
+          std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
                     << std::dec << r_write_srcid.read() << std::endl;
           if(m_cmd_write_addr_fifo.rok())
@@ -2594,10 +2603,10 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
+          std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
         }
 #endif
         size_t  hit_index = 0;
         size_t  wok_index = 0;
-        vci_addr_t  addr  = (vci_addr_t) r_write_address.read();
+        addr_t  addr  = (addr_t) r_write_address.read();
         bool    hit_read  = m_trt.hit_read(m_nline[addr], hit_index);
         bool    hit_write = m_trt.hit_write(m_nline[addr]);
@@ -2631,5 +2640,5 @@
       if(m_debug_write_fsm)
       {
-        std::cout << "  <MEMC " << name() << ".WRITE_WAIT> Releases the locks before retry" << std::endl;
+        std::cout << "  <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl;
       }
 #endif
@@ -2654,5 +2663,5 @@
         m_trt.set(r_write_trt_index.read(),
                               true,     // read request to XRAM
-                              m_nline[(vci_addr_t)(r_write_address.read())],
+                              m_nline[(addr_t)(r_write_address.read())],
                               r_write_srcid.read(),
                               r_write_trdid.read(),
@@ -2668,5 +2677,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
+          std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
         }
 #endif
@@ -2697,5 +2706,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
+          std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
           m_trt.print(r_write_trt_index.read());
         }
@@ -2712,5 +2721,5 @@
         r_write_to_ixr_cmd_req   = true;
         r_write_to_ixr_cmd_write = false;
-        r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_ixr_cmd_nline = m_nline[(addr_t)(r_write_address.read())];
         r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
         r_write_fsm              = WRITE_RSP;
@@ -2719,5 +2728,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
+          std::cout << "  <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
         }
 #endif
@@ -2746,5 +2755,5 @@
         if(m_debug_write_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".WRITE_BC_TRT_LOCK> Check TRT : wok = "
+          std::cout << "  <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT : wok = "
                     << wok << " / index = " << wok_index << std::endl;
         }
@@ -2764,5 +2773,5 @@
         size_t      trdid     = r_write_trdid.read();
         size_t      pktid     = r_write_pktid.read();
-        addr_t      nline     = m_nline[(vci_addr_t)(r_write_address.read())];
+        addr_t      nline     = m_nline[(addr_t)(r_write_address.read())];
         size_t      nb_copies = r_write_count.read();
 
@@ -2782,5 +2791,5 @@
           if(wok)
           {
-            std::cout << "  <MEMC " << name() << ".WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "
+            std::cout << "  <MEMC " << name() << " WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "
                       << " nb_copies = " << r_write_count.read() << std::endl;
           }
@@ -2812,5 +2821,5 @@
       m_trt.set(r_write_trt_index.read(),
                             false,    // write request to XRAM
-                            m_nline[(vci_addr_t)(r_write_address.read())],
+                            m_nline[(addr_t)(r_write_address.read())],
                             0,
                             0,
@@ -2836,5 +2845,5 @@
       entry.ptr           = 0;
       entry.count         = 0;
-      size_t set          = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t set          = m_y[(addr_t)(r_write_address.read())];
       size_t way          = r_write_way.read();
 
@@ -2844,5 +2853,5 @@
       if(m_debug_write_fsm)
       {
-        std::cout << "  <MEMC " << name() << ".WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
+        std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
                   << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
       }
@@ -2860,5 +2869,5 @@
         r_write_to_cc_send_brdcast_req = true;
         r_write_to_cc_send_trdid       = r_write_upt_index.read();
-        r_write_to_cc_send_nline       = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_cc_send_nline       = m_nline[(addr_t)(r_write_address.read())];
         r_write_to_cc_send_index       = 0;
         r_write_to_cc_send_count       = 0;
@@ -2872,8 +2881,9 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
-        }
+if(m_debug_write_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
+}
 #endif
       }
@@ -2888,5 +2898,5 @@
         r_write_to_ixr_cmd_req     = true;
         r_write_to_ixr_cmd_write   = true;
-        r_write_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_ixr_cmd_nline   = m_nline[(addr_t)(r_write_address.read())];
         r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
 
@@ -2896,8 +2906,9 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
-        }
+if(m_debug_write_fsm)
+{
+     std::cout << "  <MEMC " << name() 
+               << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
+}
 #endif
       }
@@ -2910,4 +2921,7 @@
   ///////////////////////////////////////////////////////////////////////
   // The IXR_CMD fsm controls the command packets to the XRAM :
+  // It handles requests from the READ, WRITE, CAS & XRAM_RSP FSMs
+  // with a round-robin priority.
+  //
   // - It sends a single cell VCI read request to the XRAM in case of MISS
   // posted by the READ, WRITE or CAS FSMs : the TRDID field contains
@@ -2915,9 +2929,8 @@
   // The VCI response is a multi-cell packet : the N cells contain
   // the N data words.
+  //
   // - It sends a multi-cell VCI write when the XRAM_RSP FSM, WRITE FSM
   // or CAS FSM request to save a dirty line to the XRAM.
   // The VCI response is a single cell packet.
-  // This FSM handles requests from the READ, WRITE, CAS & XRAM_RSP FSMs
-  // with a round-robin priority.
   ////////////////////////////////////////////////////////////////////////
 
@@ -2926,5 +2939,5 @@
       ////////////////////////
     case IXR_CMD_READ_IDLE:
-      if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+      if     (r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
       else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
       else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
@@ -2933,20 +2946,20 @@
       ////////////////////////
     case IXR_CMD_WRITE_IDLE:
-      if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
+      if(r_cas_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
       else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
       else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
       break;
       ////////////////////////
     case IXR_CMD_CAS_IDLE:
-      if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+      if(r_xram_rsp_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
       else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
       else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
       break;
       ////////////////////////
     case IXR_CMD_XRAM_IDLE:
-      if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+      if(r_read_to_ixr_cmd_req)          r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
       else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
       else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
@@ -2960,8 +2973,9 @@
 
 #if DEBUG_MEMC_IXR_CMD
-        if(m_debug_ixr_cmd_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
-        }
+if(m_debug_ixr_cmd_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
+}
 #endif
       }
@@ -2971,7 +2985,7 @@
       if(p_vci_ixr.cmdack)
       {
-        if(r_write_to_ixr_cmd_write.read())
-        {
-          if(r_ixr_cmd_cpt.read() == (m_words - 1))
+        if(r_write_to_ixr_cmd_write.read())   // PUT
+        {
+          if(r_ixr_cmd_cpt.read() == (m_words - 2))
           {
             r_ixr_cmd_cpt = 0;
@@ -2981,15 +2995,16 @@
           else
           {
-            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
           }
 
 #if DEBUG_MEMC_IXR_CMD
-          if(m_debug_ixr_cmd_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
-          }
-#endif
-        }
-        else
+if(m_debug_ixr_cmd_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
+}
+#endif
+        }
+        else                                  // GET
         {
           r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
@@ -2997,8 +3012,9 @@
 
 #if DEBUG_MEMC_IXR_CMD
-          if(m_debug_ixr_cmd_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
-          }
+if(m_debug_ixr_cmd_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
+}
 #endif
         }
@@ -3009,7 +3025,7 @@
       if(p_vci_ixr.cmdack)
       {
-        if(r_cas_to_ixr_cmd_write.read())
-        {
-          if(r_ixr_cmd_cpt.read() == (m_words - 1))
+        if(r_cas_to_ixr_cmd_write.read()) // PUT
+        {
+          if(r_ixr_cmd_cpt.read() == (m_words - 2))
           {
             r_ixr_cmd_cpt = 0;
@@ -3019,15 +3035,16 @@
           else
           {
-            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
           }
 
 #if DEBUG_MEMC_IXR_CMD
-          if(m_debug_ixr_cmd_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_CMD_CAS_NLINE> Send a put request to xram" << std::endl;
-          }
-#endif
-        }
-        else
+if(m_debug_ixr_cmd_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " IXR_CMD_CAS_NLINE> Send a put request to xram" << std::endl;
+}
+#endif
+        }
+        else                            // GET
         {
           r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE;
@@ -3035,8 +3052,9 @@
 
 #if DEBUG_MEMC_IXR_CMD
-          if(m_debug_ixr_cmd_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_CMD_CAS_NLINE> Send a get request to xram" << std::endl;
-          }
+if(m_debug_ixr_cmd_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " IXR_CMD_CAS_NLINE> Send a get request to xram" << std::endl;
+}
 #endif
         }
@@ -3047,5 +3065,5 @@
       if(p_vci_ixr.cmdack)
       {
-        if(r_ixr_cmd_cpt.read() == (m_words - 1))
+        if(r_ixr_cmd_cpt.read() == (m_words - 2))
         {
           r_ixr_cmd_cpt = 0;
@@ -3055,12 +3073,13 @@
         else
         {
-          r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+          r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
         }
 
 #if DEBUG_MEMC_IXR_CMD
-        if(m_debug_ixr_cmd_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
-        }
+if(m_debug_ixr_cmd_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
+}
 #endif
       }
@@ -3090,6 +3109,6 @@
   switch(r_ixr_rsp_fsm.read())
   {
-      //////////////////
-    case IXR_RSP_IDLE:  // test if it's a get or a put transaction
+    //////////////////
+    case IXR_RSP_IDLE:  // test transaction type: PUT/GET
     {
       if(p_vci_ixr.rspval.read())
@@ -3097,39 +3116,41 @@
         r_ixr_rsp_cpt   = 0;
         r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
-        if(p_vci_ixr.reop.read() && !(p_vci_ixr.rerror.read() &0x1))   // put transaction
+        if(p_vci_ixr.reop.read() && !(p_vci_ixr.rerror.read() &0x1))   // PUT transaction
         {
           r_ixr_rsp_fsm = IXR_RSP_ACK;
 
 #if DEBUG_MEMC_IXR_RSP
-          if(m_debug_ixr_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
-          }
-#endif
-        }
-        else                     // get transaction
+if(m_debug_ixr_rsp_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
+}
+#endif
+        }
+        else                                                         // GET transaction
         {
           r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
 
 #if DEBUG_MEMC_IXR_RSP
-          if(m_debug_ixr_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
-          }
-#endif
-        }
-      }
-      break;
-    }
-    ////////////////////////
-    case IXR_RSP_ACK:        // Aknowledge the VCI response
+if(m_debug_ixr_rsp_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
+}
+#endif
+        }
+      }
+      break;
+    }
+    /////////////////
+    case IXR_RSP_ACK:        // Aknowledge the VCI response for a PUT
     {
       if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
 
 #if DEBUG_MEMC_IXR_RSP
-      if(m_debug_ixr_rsp_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".IXR_RSP_ACK>" << std::endl;
-      }
+if(m_debug_ixr_rsp_fsm)
+{
+    std::cout << "  <MEMC " << name() << " IXR_RSP_ACK>" << std::endl;
+}
 #endif
       break;
@@ -3144,7 +3165,7 @@
 
 #if DEBUG_MEMC_IXR_RSP
-        if(m_debug_ixr_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_ERASE> Erase TRT entry "
+if(m_debug_ixr_rsp_fsm)
+{
+          std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry "
                     << r_ixr_rsp_trt_index.read() << std::endl;
         }
@@ -3153,20 +3174,24 @@
       break;
     }
-    ///////////////////////
-    case IXR_RSP_TRT_READ:    // write data in the TRT
+    //////////////////////
+    case IXR_RSP_TRT_READ:    // write a 64 bits data in the TRT
     {
       if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval)
       {
-        size_t index    = r_ixr_rsp_trt_index.read();
-        bool   eop    = p_vci_ixr.reop.read();
-        data_t data   = p_vci_ixr.rdata.read();
-        bool   error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
-        assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || p_vci_ixr.rerror.read())
+        size_t      index    = r_ixr_rsp_trt_index.read();
+        bool        eop      = p_vci_ixr.reop.read();
+        wide_data_t data     = p_vci_ixr.rdata.read();
+        bool        error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
+
+        assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) || p_vci_ixr.rerror.read())
                and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
-        m_trt.write_rsp(index,
-                                    r_ixr_rsp_cpt.read(),
-                                    data,
-                                    error);
-        r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+
+        m_trt.write_rsp( index,
+                         r_ixr_rsp_cpt.read(),
+                         data,
+                         error);
+
+        r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 2;
+
         if(eop)
         {
@@ -3176,11 +3201,11 @@
 
 #if DEBUG_MEMC_IXR_RSP
-        if(m_debug_ixr_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_READ> Writing a word in TRT : "
-                    << " index = " << std::dec << index
-                    << " / word = " << r_ixr_rsp_cpt.read()
-                    << " / data = " << std::hex << data << std::endl;
-        }
+if(m_debug_ixr_rsp_fsm)
+{
+    std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : "
+              << " index = " << std::dec << index
+              << " / word = " << r_ixr_rsp_cpt.read()
+              << " / data = " << std::hex << data << std::endl;
+}
 #endif
       }
@@ -3231,5 +3256,5 @@
           if(m_debug_xram_rsp_fsm)
           {
-            std::cout << "  <MEMC " << name() << ".XRAM_RSP_IDLE> Available cache line in TRT:"
+            std::cout << "  <MEMC " << name() << " XRAM_RSP_IDLE> Available cache line in TRT:"
                       << " index = " << std::dec << index << std::endl;
           }
@@ -3258,8 +3283,9 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
-        }
+if(m_debug_xram_rsp_fsm)
+{
+    std::cout << "  <MEMC " << name() 
+              << " XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
+}
 #endif
       }
@@ -3274,5 +3300,5 @@
         // selects & extracts a victim line from cache
         size_t way = 0;
-        size_t set = m_y[(vci_addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)];
+        size_t set = m_y[(addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)];
 
         DirectoryEntry victim(m_cache_directory.select(set, way));
@@ -3309,5 +3335,5 @@
         if(m_debug_xram_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_COPY> Select a slot: "
+          std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY> Select a slot: "
                     << " way = " << std::dec << way
                     << " / set = " << set
@@ -3339,5 +3365,5 @@
           if(m_debug_xram_rsp_fsm)
           {
-            std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
+            std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
                       << " but an invalidation is already registered at this address" << std::endl;
             m_upt.print();
@@ -3353,5 +3379,5 @@
           if(m_debug_xram_rsp_fsm)
           {
-            std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
+            std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
                       << " but the table is full" << std::endl;
             m_upt.print();
@@ -3366,5 +3392,5 @@
           if(m_debug_xram_rsp_fsm)
           {
-            std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
+            std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
           }
 #endif
@@ -3402,6 +3428,6 @@
         if(m_monitor_ok)
         {
-          vci_addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
-          check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word]);
+          addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
+          check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word], false);
         }
       }
@@ -3465,5 +3491,5 @@
       if(m_debug_xram_rsp_fsm)
       {
-        std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_UPDT> Directory update: "
+        std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_UPDT> Directory update: "
                   << " way = " << std::dec << way
                   << " / set = " << set
@@ -3510,5 +3536,5 @@
         if(m_debug_xram_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
+          std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
                     << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
         }
@@ -3543,5 +3569,5 @@
         if(m_debug_xram_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:"
+          std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:"
                     << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid
                     << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
@@ -3581,5 +3607,5 @@
         if(m_debug_xram_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL> Send an inval request to CC_SEND FSM:"
+          std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL> Send an inval request to CC_SEND FSM:"
                     << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
         }
@@ -3607,5 +3633,5 @@
         if(m_debug_xram_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:"
+          std::cout << "  <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:"
                     << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
         }
@@ -3628,5 +3654,5 @@
       {
         std::cout
-            << "  <MEMC " << name() << ".XRAM_RSP_HEAP_REQ> Requesting HEAP lock "
+            << "  <MEMC " << name() << " XRAM_RSP_HEAP_REQ> Requesting HEAP lock "
             << std::endl;
       }
@@ -3669,5 +3695,5 @@
         if(m_debug_xram_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_ERASE> Erase the list of copies:"
+          std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_ERASE> Erase the list of copies:"
                     << " srcid = " << std::dec << entry.owner.srcid
                     << " / inst = " << std::dec << entry.owner.inst << std::endl;
@@ -3712,5 +3738,5 @@
       if(m_debug_xram_rsp_fsm)
       {
-        std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
+        std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
       }
 #endif
@@ -3729,5 +3755,5 @@
       if(m_debug_xram_rsp_fsm)
       {
-        std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
+        std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
       }
 #endif
@@ -3753,5 +3779,5 @@
         if(m_debug_xram_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
+          std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
                     << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
         }
@@ -3821,5 +3847,5 @@
         std::cout
             << "  <MEMC "         << name()
-            << ".CLEANUP_IDLE> Cleanup request:" << std::hex
+            << " CLEANUP_IDLE> Cleanup request:" << std::hex
             << " / owner_id = "   << srcid
             << " / owner_ins = "  << (type == DspinDhccpParam::TYPE_CLEANUP_INST)
@@ -3858,5 +3884,5 @@
         std::cout
             << "  <MEMC "         << name()
-            << ".CLEANUP_GET_NLINE> Cleanup request:"
+            << " CLEANUP_GET_NLINE> Cleanup request:"
             << std::hex
             << " / address = "    << nline * m_words * 4
@@ -3878,5 +3904,5 @@
       {
         std::cout
-            << "  <MEMC " << name() << ".CLEANUP_DIR_REQ> Requesting DIR lock "
+            << "  <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock "
             << std::endl;
       }
@@ -3950,5 +3976,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_DIR_LOCK> Test directory status: "
+            << " CLEANUP_DIR_LOCK> Test directory status: "
             << std::hex
             << " line = "         << cleanup_address
@@ -3980,5 +4006,5 @@
 
       size_t way         = r_cleanup_way.read();
-      size_t set         = m_y[(vci_addr_t)(r_cleanup_nline.read()*m_words*4)];
+      size_t set         = m_y[(addr_t)(r_cleanup_nline.read()*m_words*4)];
       bool   match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read());
 
@@ -4026,5 +4052,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_DIR_WRITE> Update directory:"
+            << " CLEANUP_DIR_WRITE> Update directory:"
             << std::hex
             << " address = "   << r_cleanup_nline.read() * m_words * 4
@@ -4052,5 +4078,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_HEAP_REQ> HEAP lock acquired "
+            << " CLEANUP_HEAP_REQ> HEAP lock acquired "
             << std::endl;
       }
@@ -4075,5 +4101,5 @@
 
       size_t way            = r_cleanup_way.read();
-      size_t set            = m_y[(vci_addr_t)(r_cleanup_nline.read() *m_words*4)];
+      size_t set            = m_y[(addr_t)(r_cleanup_nline.read() *m_words*4)];
 
       HeapEntry heap_entry  = m_heap.read(r_cleanup_ptr.read());
@@ -4204,5 +4230,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_HEAP_LOCK> Checks matching:"
+            << " CLEANUP_HEAP_LOCK> Checks matching:"
             << " address = "      << r_cleanup_nline.read() * m_words * 4
             << " / dir_id = "     << r_cleanup_copy.read()
@@ -4283,5 +4309,5 @@
           std::cout
               << "  <MEMC " << name()
-              << ".CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
+              << " CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
               << std::endl;
         }
@@ -4290,5 +4316,5 @@
           std::cout
               << "  <MEMC " << name()
-              << ".CLEANUP_HEAP_SEARCH> Matching copy found:"
+              << " CLEANUP_HEAP_SEARCH> Matching copy found:"
               << std::endl;
         }
@@ -4350,5 +4376,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_HEAP_SEARCH> Remove the copy in the linked list"
+            << " CLEANUP_HEAP_SEARCH> Remove the copy in the linked list"
             << std::endl;
       }
@@ -4399,5 +4425,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_HEAP_SEARCH> Update the list of free entries"
+            << " CLEANUP_HEAP_SEARCH> Update the list of free entries"
             << std::endl;
       }
@@ -4427,5 +4453,5 @@
           std::cout
               << "  <MEMC " << name()
-              << ".CLEANUP_UPT_LOCK> Unexpected cleanup"
+              << " CLEANUP_UPT_LOCK> Unexpected cleanup"
               << " with no corresponding UPT entry:"
               << " address = " << std::hex
@@ -4451,5 +4477,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_UPT_LOCK> Cleanup matching pending"
+            << " CLEANUP_UPT_LOCK> Cleanup matching pending"
             << " invalidate transaction on UPT:"
             << std::hex
@@ -4496,5 +4522,5 @@
         std::cout
             << "  <MEMC "      << name()
-            << ".CLEANUP_UPT_DECREMENT> Decrement response counter in UPT:"
+            << " CLEANUP_UPT_DECREMENT> Decrement response counter in UPT:"
             << " UPT_index = " << r_cleanup_index.read()
             << " rsp_count = " << count
@@ -4535,5 +4561,5 @@
         std::cout
             << "  <MEMC "      << name()
-            << ".CLEANUP_UPT_CLEAR> Clear entry in UPT:"
+            << " CLEANUP_UPT_CLEAR> Clear entry in UPT:"
             << " UPT_index = " << r_cleanup_index.read()
             << std::endl;
@@ -4562,5 +4588,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_WRITE_RSP> Send a response to a previous"
+            << " CLEANUP_WRITE_RSP> Send a response to a previous"
             << " write request waiting for coherence transaction completion: "
             << " rsrcid = "   << std::dec << r_cleanup_write_srcid.read()
@@ -4592,5 +4618,5 @@
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_SEND_ACK> Send the response to a cleanup request:"
+            << " CLEANUP_SEND_ACK> Send the response to a cleanup request:"
             << " srcid = " << std::dec << r_cleanup_srcid.read()
             << std::endl;
@@ -4637,5 +4663,5 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_IDLE> CAS command: " << std::hex
+          std::cout << "  <MEMC " << name() << " CAS_IDLE> CAS command: " << std::hex
                     << " srcid = " <<  std::dec << m_cmd_cas_srcid_fifo.read()
                     << " addr = " << std::hex << m_cmd_cas_addr_fifo.read()
@@ -4688,5 +4714,5 @@
       {
         std::cout
-            << "  <MEMC " << name() << ".CAS_DIR_REQ> Requesting DIR lock "
+            << "  <MEMC " << name() << " CAS_DIR_REQ> Requesting DIR lock "
             << std::endl;
       }
@@ -4721,5 +4747,5 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_DIR_LOCK> Directory acces"
+          std::cout << "  <MEMC " << name() << " CAS_DIR_LOCK> Directory acces"
                     << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
                     << " / hit = " << std::dec << entry.valid
@@ -4746,5 +4772,5 @@
     {
       size_t way  = r_cas_way.read();
-      size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+      size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
       // update directory (lock & dirty bits)
@@ -4774,5 +4800,5 @@
       {
         std::cout
-          << "  <MEMC " << name() << ".CAS_DIR_HIT_READ> Read data from "
+          << "  <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from "
           << " cache and store it in buffer"
           << std::endl;
@@ -4784,5 +4810,5 @@
     case CAS_DIR_HIT_COMPARE:
     {
-      size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+      size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
       // Read data in buffer & check data change
@@ -4810,5 +4836,5 @@
       if(m_debug_cas_fsm)
       {
-        std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_COMPARE> Compare the old"
+        std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old"
                   << " and the new data"
                   << " / expected value = " << r_cas_rdata[0].read()
@@ -4846,6 +4872,6 @@
       {
         size_t way  = r_cas_way.read();
-        size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-        size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
+        size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
         // cache update
@@ -4859,11 +4885,12 @@
         if(m_monitor_ok)
         {
-          vci_addr_t address = m_cmd_cas_addr_fifo.read();
+          addr_t address = m_cmd_cas_addr_fifo.read();
           char buf[80];
-          snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
-          check_monitor(buf, address, r_cas_wdata.read());
+          snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 
+                   (int)m_cmd_cas_srcid_fifo.read());
+          check_monitor(buf, address, r_cas_wdata.read(), false);
 
           if(r_cas_cpt.read() == 4)
-            check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read());
+            check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
         }
 
@@ -4871,5 +4898,5 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_WRITE> Update cache:"
+          std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:"
                     << " way = " << std::dec << way
                     << " / set = " << set
@@ -4878,5 +4905,5 @@
                     << " / count = " << r_cas_count.read() << std::endl;
           std::cout << "  <MEMC "
-                    << name() << ".CAS_DIR_HIT_WRITE> global_llsc_table SW access" << std::endl;
+                    << name() << " CAS_DIR_HIT_WRITE> global_llsc_table SW access" << std::endl;
         }
 #endif
@@ -4896,5 +4923,5 @@
         size_t      trdid      = m_cmd_cas_trdid_fifo.read();
         size_t      pktid      = m_cmd_cas_pktid_fifo.read();
-        addr_t      nline      = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        addr_t      nline      = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
         size_t      nb_copies  = r_cas_count.read();
 
@@ -4912,6 +4939,6 @@
           // cache update
           size_t way  = r_cas_way.read();
-          size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-          size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
           m_cache_data.write(way, set, word, r_cas_wdata.read());
@@ -4925,11 +4952,12 @@
           if(m_monitor_ok)
           {
-            vci_addr_t address = m_cmd_cas_addr_fifo.read();
+            addr_t address = m_cmd_cas_addr_fifo.read();
             char buf[80];
-            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
-            check_monitor(buf, address, r_cas_wdata.read());
+            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 
+                     (int)m_cmd_cas_srcid_fifo.read());
+            check_monitor(buf, address, r_cas_wdata.read(), false);
 
             if(r_cas_cpt.read() ==4)
-              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read());
+              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
           }
         }
@@ -4943,5 +4971,5 @@
         {
           std::cout << "  <MEMC " << name()
-                    << ".CAS_UPT_LOCK> Register multi-update transaction in UPT"
+                    << " CAS_UPT_LOCK> Register multi-update transaction in UPT"
                     << " / wok = " << wok
                     << " / nline  = " << std::hex << nline
@@ -4960,5 +4988,5 @@
       {
         std::cout << "  <MEMC " << name()
-                  << ".CAS_WAIT> Release all locks" << std::endl;
+                  << " CAS_WAIT> Release all locks" << std::endl;
       }
 #endif
@@ -4976,5 +5004,5 @@
         {
           std::cout << "  <MEMC " << name()
-                    << ".CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
+                    << " CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
         }
 #endif
@@ -4993,6 +5021,6 @@
         r_cas_to_cc_send_brdcast_req  = false;
         r_cas_to_cc_send_trdid        = r_cas_upt_index.read();
-        r_cas_to_cc_send_nline        = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-        r_cas_to_cc_send_index        = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        r_cas_to_cc_send_nline        = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
+        r_cas_to_cc_send_index        = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
         r_cas_to_cc_send_wdata        = r_cas_wdata.read();
 
@@ -5031,5 +5059,5 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_UPT_REQ> Send the first update request to CC_SEND FSM "
+          std::cout << "  <MEMC " << name() << " CAS_UPT_REQ> Send the first update request to CC_SEND FSM "
                     << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
                     << " / wdata = " << std::hex << r_cas_wdata.read()
@@ -5071,5 +5099,5 @@
       if(m_debug_cas_fsm)
       {
-        std::cout << "  <MEMC " << name() << ".CAS_UPT_NEXT> Send the next update request to CC_SEND FSM "
+        std::cout << "  <MEMC " << name() << " CAS_UPT_NEXT> Send the next update request to CC_SEND FSM "
                   << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
                   << " / wdata = " << std::hex << r_cas_wdata.read()
@@ -5088,5 +5116,5 @@
         {
           // fill the data buffer
-          size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
           for(size_t i = 0; i<m_words; i++)
           {
@@ -5134,5 +5162,5 @@
         size_t      trdid     = m_cmd_cas_trdid_fifo.read();
         size_t      pktid     = m_cmd_cas_pktid_fifo.read();
-        addr_t      nline     = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        addr_t      nline     = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
         size_t      nb_copies = r_cas_count.read();
 
@@ -5152,6 +5180,6 @@
           // cache update
           size_t way  = r_cas_way.read();
-          size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-          size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
           m_cache_data.write(way, set, word, r_cas_wdata.read());
@@ -5162,10 +5190,11 @@
           if(m_monitor_ok)
           {
-            vci_addr_t address = m_cmd_cas_addr_fifo.read();
+            addr_t address = m_cmd_cas_addr_fifo.read();
             char buf[80];
-            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
-            check_monitor(buf, address, r_cas_wdata.read());
+            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 
+                     (int)m_cmd_cas_srcid_fifo.read());
+            check_monitor(buf, address, r_cas_wdata.read(), false);
             if(r_cas_cpt.read() ==4)
-              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read());
+              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
           }
           r_cas_upt_index = index;
@@ -5174,5 +5203,5 @@
           if(m_debug_cas_fsm)
           {
-            std::cout << "  <MEMC " << name() << ".CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
+            std::cout << "  <MEMC " << name() << " CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
                       << " / nline = " << nline
                       << " / count = " << nb_copies
@@ -5198,5 +5227,5 @@
         m_trt.set(r_cas_trt_index.read(),
                               false,    // PUT request to XRAM
-                              m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())],
+                              m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],
                               0,
                               0,
@@ -5222,5 +5251,5 @@
         entry.owner.inst    = false;
         entry.ptr           = 0;
-        size_t set          = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        size_t set          = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
         size_t way          = r_cas_way.read();
         m_cache_directory.write(set, way, entry);
@@ -5231,6 +5260,6 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
-                    << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]
+          std::cout << "  <MEMC " << name() << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
+                    << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]
                     << " / set = " << std::dec << set << " / way = " << way << std::endl;
         }
@@ -5252,5 +5281,5 @@
         r_cas_to_cc_send_brdcast_req  = true;
         r_cas_to_cc_send_trdid        = r_cas_upt_index.read();
-        r_cas_to_cc_send_nline        = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        r_cas_to_cc_send_nline        = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
         r_cas_to_cc_send_index        = 0;
         r_cas_to_cc_send_wdata        = 0;
@@ -5267,5 +5296,5 @@
         r_cas_to_ixr_cmd_req     = true;
         r_cas_to_ixr_cmd_write   = true;
-        r_cas_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        r_cas_to_ixr_cmd_nline   = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
         r_cas_to_ixr_cmd_trdid   = r_cas_trt_index.read();
         r_cas_fsm                = CAS_IDLE;
@@ -5276,6 +5305,6 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
-                    << " / nline = " << m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]
+          std::cout << "  <MEMC " << name() << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
+                    << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
                     << " / trt_index = " << r_cas_trt_index.read() << std::endl;
         }
@@ -5306,5 +5335,5 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
+          std::cout << "  <MEMC " << name() << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
         }
 #endif
@@ -5329,5 +5358,5 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
+          std::cout << "  <MEMC " << name() << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
         }
 #endif
@@ -5342,7 +5371,7 @@
         size_t   index = 0;
         bool hit_read = m_trt.hit_read(
-                          m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()],index);
+                          m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index);
         bool hit_write = m_trt.hit_write(
-                           m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]);
+                           m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]);
         bool wok = !m_trt.full(index);
 
@@ -5350,5 +5379,5 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_MISS_TRT_LOCK> Check TRT state"
+          std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_LOCK> Check TRT state"
                     << " / hit_read = "  << hit_read
                     << " / hit_write = " << hit_write
@@ -5387,5 +5416,5 @@
         m_trt.set(r_cas_trt_index.read(),
                               true,   // read request
-                              m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()],
+                              m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],
                               m_cmd_cas_srcid_fifo.read(),
                               m_cmd_cas_trdid_fifo.read(),
@@ -5401,6 +5430,6 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
-                    << " / nline = " << m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]
+          std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
+                    << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
                     << " / trt_index = " << r_cas_trt_index.read() << std::endl;
         }
@@ -5417,5 +5446,5 @@
         r_cas_to_ixr_cmd_write      = false;
         r_cas_to_ixr_cmd_trdid      = r_cas_trt_index.read();
-        r_cas_to_ixr_cmd_nline      = m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()];
+        r_cas_to_ixr_cmd_nline      = m_nline[(addr_t) m_cmd_cas_addr_fifo.read()];
         r_cas_fsm                   = CAS_WAIT;
 
@@ -5423,6 +5452,6 @@
         if(m_debug_cas_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
-                    << " / nline = " << m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]
+          std::cout << "  <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
+                    << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
                     << " / trt_index = " << r_cas_trt_index.read() << std::endl;
         }
@@ -5699,5 +5728,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid "
+            << " CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid "
             << r_cleanup_to_cc_send_srcid.read()
             << std::endl;
@@ -5742,5 +5771,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".CC_SEND_XRAM_RSP_INVAL_NLINE> Broadcast-Inval for line "
+            << " CC_SEND_XRAM_RSP_INVAL_NLINE> Broadcast-Inval for line "
             << r_xram_rsp_to_cc_send_nline.read()
             << std::endl;
@@ -5774,5 +5803,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".CC_SEND_XRAM_RSP_BRDCAST_NLINE> Broadcast-Inval for line "
+            << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> Broadcast-Inval for line "
             << r_xram_rsp_to_cc_send_nline.read()
             << std::endl;
@@ -5806,5 +5835,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".CC_SEND_WRITE_BRDCAST_NLINE> Broadcast-Inval for line "
+            << " CC_SEND_WRITE_BRDCAST_NLINE> Broadcast-Inval for line "
             << r_write_to_cc_send_nline.read()
             << std::endl;
@@ -5849,5 +5878,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".CC_SEND_WRITE_UPDT_NLINE> Multicast-Update for line "
+            << " CC_SEND_WRITE_UPDT_NLINE> Multicast-Update for line "
             << r_write_to_cc_send_nline.read()
             << std::endl;
@@ -5897,5 +5926,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for line "
+            << " CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for line "
             << r_cas_to_cc_send_nline.read()
             << std::endl;
@@ -5941,5 +5970,5 @@
           std::cout
             << "  <MEMC " << name()
-            << ".CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line "
+            << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line "
             << r_cas_to_cc_send_nline.read()
             << std::endl;
@@ -6204,5 +6233,5 @@
 {
   std::cout
-    << "  <MEMC " << name() << ".TGT_RSP_READ> Read response"
+    << "  <MEMC " << name() << " TGT_RSP_READ> Read response"
     << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read()
     << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read()
@@ -6247,5 +6276,5 @@
         if(m_debug_tgt_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".TGT_RSP_WRITE> Write response"
+          std::cout << "  <MEMC " << name() << " TGT_RSP_WRITE> Write response"
                     << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read()
                     << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read()
@@ -6267,5 +6296,5 @@
         if(m_debug_tgt_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".TGT_RSP_CLEANUP> Cleanup response"
+          std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
                     << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read()
                     << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
@@ -6287,5 +6316,5 @@
         if(m_debug_tgt_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".TGT_RSP_CAS> CAS response"
+          std::cout << "  <MEMC " << name() << " TGT_RSP_CAS> CAS response"
                     << " / rsrcid = " << std::dec << r_cas_to_tgt_rsp_srcid.read()
                     << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read()
@@ -6309,5 +6338,5 @@
 {
   std::cout 
-    << "  <MEMC " << name() << ".TGT_RSP_XRAM> Response following XRAM access"
+    << "  <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access"
     << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read()
     << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
@@ -6353,5 +6382,5 @@
         if(m_debug_tgt_rsp_fsm)
         {
-          std::cout << "  <MEMC " << name() << ".TGT_RSP_INIT> Write response after coherence transaction"
+          std::cout << "  <MEMC " << name() << " TGT_RSP_INIT> Write response after coherence transaction"
                     << " / rsrcid = " << std::dec << r_multi_ack_to_tgt_rsp_srcid.read()
                     << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read()
@@ -7171,5 +7200,5 @@
   ////////////////////////////////////////////////////////////
 
-  p_vci_ixr.be      = 0xF;
+  p_vci_ixr.be      = 0xFF;   // nor transmited to external ram
   p_vci_ixr.pktid   = 0;
   p_vci_ixr.srcid   = m_srcid_x;
@@ -7179,14 +7208,14 @@
   p_vci_ixr.clen    = 0;
   p_vci_ixr.cfixed  = false;
+  p_vci_ixr.plen    = 64;
 
   if(r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE)
   {
-    p_vci_ixr.cmd     = vci_param::CMD_READ;
-    p_vci_ixr.cmdval  = true;
-    p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read() *m_words*4);
-    p_vci_ixr.plen    = m_words*4;
-    p_vci_ixr.wdata   = 0x00000000;
-    p_vci_ixr.trdid   = r_read_to_ixr_cmd_trdid.read();
-    p_vci_ixr.eop     = true;
+    p_vci_ixr.cmd       = vci_param_ext::CMD_READ;
+    p_vci_ixr.cmdval    = true;
+    p_vci_ixr.address   = (addr_t)(r_read_to_ixr_cmd_nline.read() * m_words * 4);
+    p_vci_ixr.wdata     = 0;
+    p_vci_ixr.trdid     = r_read_to_ixr_cmd_trdid.read();
+    p_vci_ixr.eop       = true;
   }
   else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS_NLINE)
@@ -7194,19 +7223,19 @@
     if(r_cas_to_ixr_cmd_write.read())
     {
-      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      size_t word       = r_ixr_cmd_cpt.read();
+      p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
       p_vci_ixr.cmdval  = true;
-      p_vci_ixr.address = (addr_t)((r_cas_to_ixr_cmd_nline.read() *m_words+r_ixr_cmd_cpt.read()) *4);
-      p_vci_ixr.plen    = m_words*4;
-      p_vci_ixr.wdata   = r_cas_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.address = (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words + word) * 4 );
+      p_vci_ixr.wdata   = ((wide_data_t)(r_cas_to_ixr_cmd_data[word].read()))  |
+                          ((wide_data_t)(r_cas_to_ixr_cmd_data[word+1].read()) << 32);
       p_vci_ixr.trdid   = r_cas_to_ixr_cmd_trdid.read();
-      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-2));
     }
     else
     {
-      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmd     = vci_param_ext::CMD_READ;
       p_vci_ixr.cmdval  = true;
       p_vci_ixr.address = (addr_t)(r_cas_to_ixr_cmd_nline.read() *m_words*4);
-      p_vci_ixr.plen    = m_words*4;
-      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.wdata   = 0;
       p_vci_ixr.trdid   = r_cas_to_ixr_cmd_trdid.read();
       p_vci_ixr.eop     = true;
@@ -7217,19 +7246,19 @@
     if(r_write_to_ixr_cmd_write.read())
     {
-      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
       p_vci_ixr.cmdval  = true;
-      p_vci_ixr.address = (addr_t)((r_write_to_ixr_cmd_nline.read() *m_words+r_ixr_cmd_cpt.read()) *4);
-      p_vci_ixr.plen    = m_words*4;
-      p_vci_ixr.wdata   = r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.address = (addr_t)( (r_write_to_ixr_cmd_nline.read() * m_words +
+                                     r_ixr_cmd_cpt.read()) * 4 );
+      p_vci_ixr.wdata   = (wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read() |
+                                        r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read());
       p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
-      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-2));
     }
     else
     {
-      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmd     = vci_param_ext::CMD_READ;
       p_vci_ixr.cmdval  = true;
       p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read() *m_words*4);
-      p_vci_ixr.plen    = m_words*4;
-      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.wdata   = 0;
       p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
       p_vci_ixr.eop     = true;
@@ -7238,20 +7267,21 @@
   else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA)
   {
-    p_vci_ixr.cmd     = vci_param::CMD_WRITE;
-    p_vci_ixr.cmdval  = true;
-    p_vci_ixr.address = (addr_t)((r_xram_rsp_to_ixr_cmd_nline.read() *m_words+r_ixr_cmd_cpt.read()) *4);
-    p_vci_ixr.plen    = m_words*4;
-    p_vci_ixr.wdata   = r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
-    p_vci_ixr.trdid   = r_xram_rsp_to_ixr_cmd_trdid.read();
-    p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+    p_vci_ixr.cmd       = vci_param_ext::CMD_WRITE;
+    p_vci_ixr.cmdval    = true;
+    p_vci_ixr.address   = (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words +
+                                   r_ixr_cmd_cpt.read()) * 4 );
+    p_vci_ixr.wdata     = (wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read() |
+                                        r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read());
+    p_vci_ixr.trdid     = r_xram_rsp_to_ixr_cmd_trdid.read();
+    p_vci_ixr.eop       = (r_ixr_cmd_cpt == (m_words-2));
   }
   else
   {
-    p_vci_ixr.cmdval  = false;
-    p_vci_ixr.address = 0;
-    p_vci_ixr.plen    = 0;
-    p_vci_ixr.wdata   = 0;
-    p_vci_ixr.trdid   = 0;
-    p_vci_ixr.eop = false;
+    p_vci_ixr.cmdval    = false;
+    p_vci_ixr.cmd       = vci_param_ext::CMD_READ;
+    p_vci_ixr.address   = 0;
+    p_vci_ixr.wdata     = 0;
+    p_vci_ixr.trdid     = 0;
+    p_vci_ixr.eop       = false;
   }
 
@@ -7446,5 +7476,5 @@
         uint64_t dest =
           r_cleanup_to_cc_send_srcid.read() << 
-          (DspinDhccpParam::SRCID_WIDTH - vci_param::S);
+          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
 
         DspinDhccpParam::dspin_set(
@@ -7496,5 +7526,5 @@
         uint64_t dest =
           m_xram_rsp_to_cc_send_srcid_fifo.read() << 
-          (DspinDhccpParam::SRCID_WIDTH - vci_param::S);
+          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
 
         DspinDhccpParam::dspin_set(
@@ -7649,5 +7679,5 @@
         uint64_t dest =
           m_write_to_cc_send_srcid_fifo.read() << 
-          (DspinDhccpParam::SRCID_WIDTH - vci_param::S);
+          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
 
         DspinDhccpParam::dspin_set(
@@ -7756,5 +7786,5 @@
         uint64_t dest =
           m_cas_to_cc_send_srcid_fifo.read() << 
-          (DspinDhccpParam::SRCID_WIDTH - vci_param::S);
+          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
 
         DspinDhccpParam::dspin_set(
