Changeset 386 for trunk/modules
- Timestamp:
- May 1, 2013, 4:21:29 PM (12 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper/caba
- Files:
-
- 3 edited
-
metadata/vci_cc_vcache_wrapper.sd (modified) (2 diffs)
-
source/include/vci_cc_vcache_wrapper.h (modified) (2 diffs)
-
source/src/vci_cc_vcache_wrapper.cpp (modified) (20 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd
r351 r386 6 6 7 7 tmpl_parameters = [ 8 parameter.Module('vci_param', default = 'caba:vci_param'), 8 parameter.Module('vci_param'), 9 parameter.Int('dspin_in_width'), 10 parameter.Int('dspin_out_width'), 9 11 parameter.Module('iss_t') 10 12 ], … … 20 22 Uses('caba:multi_write_buffer'), 21 23 Uses('caba:generic_fifo'), 22 Uses( 23 'caba:generic_cache_tsar', 24 Uses('caba:generic_cache_tsar', 24 25 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 25 parameter.Reference('addr_size')) 26 ), 27 Uses( 28 'caba:generic_tlb', 26 parameter.Reference('addr_size'))), 27 Uses('caba:generic_tlb', 29 28 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 30 parameter.Reference('addr_size')) 31 ), 32 Uses( 33 'common:address_masking_table', 29 parameter.Reference('addr_size'))), 30 Uses('common:address_masking_table', 34 31 data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 35 32 parameter.Reference('addr_size')) 36 33 ), 37 Uses( 38 'caba:dspin_dhccp_param' 39 ), 34 Uses('caba:dspin_dhccp_param'), 40 35 ], 41 36 42 37 ports = [ 43 Port('caba:vci_initiator', 'p_vci_ini_d'), 44 Port('caba:dspin_input', 'p_dspin_in', dspin_data_size = 40), 45 Port('caba:dspin_output', 'p_dspin_out', dspin_data_size = 33), 38 Port('caba:vci_initiator', 'p_vci'), 39 Port('caba:dspin_input', 'p_dspin_in', 40 dspin_data_size = parameter.Reference('dspin_in_width')), 41 Port('caba:dspin_output', 'p_dspin_out', 42 dspin_data_size = parameter.Reference('dspin_out_width')), 46 43 Port('caba:bit_in','p_irq', parameter.Constant('n_irq')), 47 44 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), -
trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r351 r386 55 55 56 56 //////////////////////////////////////////// 57 template<typename vci_param, typename iss_t> 57 template<typename vci_param, 58 size_t dspin_in_width, 59 size_t dspin_out_width, 60 typename iss_t> 58 61 class VciCcVCacheWrapper 59 62 //////////////////////////////////////////// … … 283 286 284 287 public: 285 sc_in<bool> p_clk;286 sc_in<bool> p_resetn;287 sc_in<bool> p_irq[iss_t::n_irq];288 soclib::caba::VciInitiator<vci_param> p_vci;289 soclib::caba::DspinInput < 40>p_dspin_in;290 soclib::caba::DspinOutput< 33>p_dspin_out;288 sc_in<bool> p_clk; 289 sc_in<bool> p_resetn; 290 sc_in<bool> p_irq[iss_t::n_irq]; 291 soclib::caba::VciInitiator<vci_param> p_vci; 292 soclib::caba::DspinInput <dspin_in_width> p_dspin_in; 293 soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; 291 294 292 295 private: -
trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r384 r386 160 160 } 161 161 162 #define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t> 162 #define tmpl(...) \ 163 template<typename vci_param, \ 164 size_t dspin_in_width, \ 165 size_t dspin_out_width, \ 166 typename iss_t> __VA_ARGS__ \ 167 VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t> 163 168 164 169 using namespace soclib::common; … … 494 499 ////////////////////////////////////////// 495 500 { 496 size_t cache_way;497 size_t cache_set;498 size_t cache_word;501 size_t cache_way; 502 size_t cache_set; 503 size_t cache_word; 499 504 uint32_t cache_rdata; 500 bool cache_hit = r_dcache.read_neutral( addr,501 &cache_rdata,502 &cache_way,503 &cache_set,504 &cache_word );505 bool cache_hit = r_dcache.read_neutral( addr, 506 &cache_rdata, 507 &cache_way, 508 &cache_set, 509 &cache_word ); 505 510 bool icache_hit = r_icache.read_neutral( addr, 506 511 &cache_rdata, … … 1151 1156 // we request a VCI transaction 1152 1157 r_icache_fsm = ICACHE_MISS_SELECT; 1153 r_icache_miss_req = true; 1158 #if DEBUG_ICACHE 1159 if ( m_debug_icache_fsm ) 1160 { 1161 std::cout << " <PROC " << name() 1162 << " ICACHE_IDLE> READ MISS in icache" 1163 << " : PADDR = " << std::hex << paddr << std::endl; 1164 } 1165 #endif 1166 r_icache_miss_req = true; 1154 1167 } 1155 1168 else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup … … 1168 1181 m_irsp.instruction = cache_inst; 1169 1182 r_icache_fsm = ICACHE_IDLE; 1183 #if DEBUG_ICACHE 1184 if ( m_debug_icache_fsm ) 1185 { 1186 std::cout << " <PROC " << name() 1187 << " ICACHE_IDLE> READ HIT in icache" 1188 << " : PADDR = " << std::hex << paddr << std::endl; 1189 } 1190 #endif 1170 1191 } 1171 1192 } … … 1174 1195 r_icache_unc_req = true; 1175 1196 r_icache_fsm = ICACHE_UNC_WAIT; 1197 1198 #if DEBUG_ICACHE 1199 if ( m_debug_icache_fsm ) 1200 { 1201 std::cout << " <PROC " << name() 1202 << " ICACHE_IDLE> READ UNCACHEABLE in icache" 1203 << " : PADDR = " << std::hex << paddr << std::endl; 1204 } 1205 #endif 1176 1206 } 1177 1207 } // end if m_ireq.valid … … 2604 2634 { 2605 2635 std::cout << " <PROC " << name() 2606 << ".DCACHE_IDLE> READ MISS in dcache" << std::endl; 2636 << " DCACHE_IDLE> READ MISS in dcache" 2637 << " : PADDR = " << std::hex << paddr << std::endl; 2607 2638 } 2608 2639 #endif … … 2626 2657 { 2627 2658 std::cout << " <PROC " << name() 2628 << ".DCACHE_IDLE> READ HIT in dcache" << std::endl; 2659 << " DCACHE_IDLE> READ HIT in dcache" 2660 << " : PADDR = " << std::hex << paddr << std::endl; 2629 2661 } 2630 2662 #endif … … 2641 2673 { 2642 2674 std::cout << " <PROC " << name() 2643 << ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl; 2675 << " DCACHE_IDLE> READ UNCACHEABLE in dcache" 2676 << " : PADDR = " << std::hex << paddr << std::endl; 2644 2677 } 2645 2678 #endif … … 3185 3218 { 3186 3219 std::cout << " <PROC " << name() 3187 << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE isunmapped"3220 << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped" 3188 3221 << " PTE_FLAGS = " << std::hex << pte_flags 3189 3222 << " PTE_PPN = " << std::hex << pte_ppn << std::endl; … … 3204 3237 if ( m_debug_dcache_fsm ) 3205 3238 { 3206 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:" 3239 std::cout << " <PROC " << name() 3240 << " DCACHE_TLB_PTE2_GET> HIT in dcache:" 3207 3241 << " PTE_FLAGS = " << std::hex << pte_flags 3208 3242 << " PTE_PPN = " << std::hex << pte_ppn << std::endl; … … 3215 3249 // stalled until cleanup is acknowledged 3216 3250 r_dcache_fsm = DCACHE_TLB_PTE2_GET; 3251 3252 #if DEBUG_DCACHE 3253 if ( m_debug_dcache_fsm ) 3254 { 3255 std::cout << " <PROC " << name() 3256 << " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack" 3257 << std::endl; 3258 } 3259 #endif 3217 3260 } 3218 3261 else // we must load the missing cache line in dcache … … 4015 4058 std::cout << " <PROC " << name() 4016 4059 << " DCACHE_MISS_DATA_UPDT> Write one word:" 4017 << " / DATA = " << r_vci_rsp_fifo_dcache.read()4060 << " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read() 4018 4061 << " / WAY = " << std::dec << r_dcache_miss_way.read() 4019 4062 << " / SET = " << r_dcache_miss_set.read() … … 4104 4147 << " / SET = " << r_dcache_miss_set.read() << std::endl; 4105 4148 4106 r_dcache.printTrace();4149 // r_dcache.printTrace(); 4107 4150 4108 4151 … … 5259 5302 // we first check for the last client and listen for // 5260 5303 // a request of the other, then update the client // 5304 // r_cc_send_last_client : 0 dcache / 1 icache 5261 5305 /////////////////////////////////////////////////////// 5262 // r_cc_send_last_client : 0 dcache / 1 icache5263 5306 bool update_last_client = r_cc_send_last_client.read(); 5264 5307 if ( r_cc_send_last_client.read() == 0 ) // last client was dcache … … 5277 5320 if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read()) 5278 5321 { 5279 // test if the new client is dcache and has a cleanup request 5280 if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) 5322 // the new client is dcache and has a cleanup request 5323 if ( (update_last_client == 0) and 5324 (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) 5281 5325 r_cc_send_fsm = CC_SEND_CLEANUP_1; 5282 // test if the new client is dcache and has a multi acknowledgement request 5283 else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) 5326 // the new client is dcache and has a multi acknowledgement request 5327 else if ( (update_last_client == 0) and 5328 (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) 5284 5329 r_cc_send_fsm = CC_SEND_MULTI_ACK; 5285 // test if the new client is icache and has a cleanup request 5286 else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) 5330 // the new client is icache and has a cleanup request 5331 else if ( (update_last_client == 1) and 5332 (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) 5287 5333 r_cc_send_fsm = CC_SEND_CLEANUP_1; 5288 // test if the new client is icache and has a multi acknowledgement request 5289 else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) 5334 // the new client is icache and has a multi acknowledgement request 5335 else if ( (update_last_client == 1) and 5336 (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) 5290 5337 r_cc_send_fsm = CC_SEND_MULTI_ACK; 5291 5338 } … … 5357 5404 uint64_t receive_data = p_dspin_in.data.read(); 5358 5405 // initialize coherence packet type 5359 uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE); 5406 uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, 5407 DspinDhccpParam::FROM_MC_TYPE); 5360 5408 // initialize data/ins flip_flop (0 data / 1 ins) 5361 5409 r_cc_receive_data_ins = (bool)(receive_type & 0x1); … … 5392 5440 5393 5441 // for data CLACK, wait for dcache to take the request 5394 if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) 5442 if ((r_cc_receive_data_ins.read() == 0) and 5443 not (r_cc_receive_dcache_req.read())) 5395 5444 { 5396 5445 // request dcache to handle the CLACK 5397 5446 r_cc_receive_dcache_req = true; 5398 r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); 5399 r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); 5447 r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data, 5448 DspinDhccpParam::CLEANUP_ACK_SET) & 5449 ((1ULL<<(uint32_log2(m_dcache_sets)))-1); 5450 r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data, 5451 DspinDhccpParam::CLEANUP_ACK_WAY) & 5452 ((1ULL<<(uint32_log2(m_dcache_ways)))-1); 5400 5453 r_cc_receive_dcache_type = CC_TYPE_CLACK; 5401 5454 // get back to idle state … … 5404 5457 } 5405 5458 // for ins CLACK, wait for icache to take the request 5406 if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())) 5459 if ((r_cc_receive_data_ins.read() == 1) and 5460 not (r_cc_receive_icache_req.read())) 5407 5461 { 5408 5462 // request icache to handle the CLACK 5409 5463 r_cc_receive_icache_req = true; 5410 r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1); 5411 r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1); 5464 r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data, 5465 DspinDhccpParam::CLEANUP_ACK_SET) & 5466 ((1ULL<<(uint32_log2(m_icache_sets)))-1); 5467 r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data, 5468 DspinDhccpParam::CLEANUP_ACK_WAY) & 5469 ((1ULL<<(uint32_log2(m_icache_ways)))-1); 5412 5470 r_cc_receive_icache_type = CC_TYPE_CLACK; 5413 5471 // get back to idle state … … 5434 5492 // not to actually post a request to an available cache => need a 5435 5493 // flip_flop to check that ? 5436 if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read())) 5494 if (not (r_cc_receive_icache_req.read()) and 5495 not (r_cc_receive_dcache_req.read()) and 5496 (p_dspin_in.write.read())) 5437 5497 { 5438 5498 // request dcache to handle the BROADCAST 5439 5499 r_cc_receive_dcache_req = true; 5440 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE); 5500 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, 5501 DspinDhccpParam::BROADCAST_NLINE); 5441 5502 r_cc_receive_dcache_type = CC_TYPE_BRDCAST; 5442 5503 // request icache to handle the BROADCAST 5443 5504 r_cc_receive_icache_req = true; 5444 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE); 5505 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data, 5506 DspinDhccpParam::BROADCAST_NLINE); 5445 5507 r_cc_receive_icache_type = CC_TYPE_BRDCAST; 5446 5508 // get back to idle state … … 5457 5519 uint64_t receive_data = p_dspin_in.data.read(); 5458 5520 // for data INVAL, wait for dcache to take the request 5459 if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) 5460 { 5461 r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); 5521 if ((r_cc_receive_data_ins.read() == 0) and 5522 not (r_cc_receive_dcache_req.read())) 5523 { 5524 r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data, 5525 DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); 5462 5526 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE; 5463 5527 break; 5464 5528 } 5465 5529 // for ins INVAL, wait for icache to take the request 5466 if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())) 5467 { 5468 r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); 5530 if ((r_cc_receive_data_ins.read() == 1) and 5531 not (r_cc_receive_icache_req.read())) 5532 { 5533 r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data, 5534 DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); 5469 5535 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE; 5470 5536 break;
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