Index: trunk/platforms/tsar_generic_xbar/Makefile =================================================================== --- trunk/platforms/tsar_generic_xbar/Makefile (revision 379) +++ trunk/platforms/tsar_generic_xbar/Makefile (revision 389) @@ -1,4 +1,4 @@ simul.x: top.cpp top.desc - soclib-cc -P -p top.desc -I. -o simul.x + soclib-cc -j8 -P -p top.desc -I. -o simul.x clean: Index: trunk/platforms/tsar_generic_xbar/top.cpp =================================================================== --- trunk/platforms/tsar_generic_xbar/top.cpp (revision 379) +++ trunk/platforms/tsar_generic_xbar/top.cpp (revision 389) @@ -116,19 +116,4 @@ #define rsp_width 33 -/////////////////////////////////////////////////////////// -// VCI parameters -/////////////////////////////////////////////////////////// - -#define cell_width 4 -#define address_width 32 -#define plen_width 8 -#define error_width 2 -#define clen_width 1 -#define rflag_width 1 -#define srcid_width 14 -#define pktid_width 4 -#define trdid_width 4 -#define wrplen_width 1 - //////////////////////////////////////////////////////////// // Main Hardware Parameters values @@ -357,16 +342,4 @@ #endif - // Define VCI parameters - typedef soclib::caba::VciParams vci_param; - // Define parameters depending on mesh size size_t cluster_io_id; @@ -378,5 +351,5 @@ else if (CLUSTER_X <= 4) x_width = 2; else if (CLUSTER_X <= 8) x_width = 3; - else x_width = 4; + else x_width = 4; if (CLUSTER_Y == 1) y_width = 0; @@ -384,5 +357,5 @@ else if (CLUSTER_Y <= 4) y_width = 2; else if (CLUSTER_Y <= 8) y_width = 3; - else y_width = 4; + else y_width = 4; cluster_io_id = 0xBF >> (8 - x_width - y_width); @@ -448,5 +421,5 @@ /////////////////// - sc_clock signal_clk("clk"); + sc_clock signal_clk("clk"); sc_signal signal_resetn("resetn"); @@ -501,5 +474,7 @@ //////////////////////////// - TsarXbarCluster* clusters[CLUSTER_X][CLUSTER_Y]; + TsarXbarCluster< + proc_iss, cmd_width, rsp_width + > * clusters[CLUSTER_X][CLUSTER_Y]; #if USE_OPENMP @@ -517,47 +492,30 @@ { #endif + bool is_io_cluster = (cluster(x,y) == cluster_io_id); + std::ostringstream sc; sc << "cluster_" << x << "_" << y; - clusters[x][y] = new TsarXbarCluster + clusters[x][y] = new TsarXbarCluster< + proc_iss, cmd_width, rsp_width + > ( sc.str().c_str(), - NB_PROCS_MAX, - NB_TTYS, - NB_DMAS_MAX, - x, - y, - cluster(x,y), - maptabd, - maptabx, - x_width, - y_width, - srcid_width - x_width - y_width, // l_id width, - MEMC_TGTID, - XICU_TGTID, - CDMA_TGTID, - FBUF_TGTID, - MTTY_TGTID, - BROM_TGTID, - MNIC_TGTID, - BDEV_TGTID, - MEMC_WAYS, - MEMC_SETS, - L1_IWAYS, - L1_ISETS, - L1_DWAYS, - L1_DSETS, - XRAM_LATENCY, - (cluster(x,y) == cluster_io_id), - FBUF_X_SIZE, - FBUF_Y_SIZE, - disk_name, - BDEV_SECTOR_SIZE, - NB_NICS, - nic_rx_name, - nic_tx_name, - NIC_TIMEOUT, - loader, + NB_PROCS_MAX , NB_TTYS , NB_DMAS_MAX , // cluster params + x , y , cluster(x,y), // mesh coordinates + maptabd , maptabx , // mapping tables + x_width , y_width , srcid_width - x_width - y_width, // srcid width, + MEMC_TGTID , XICU_TGTID , CDMA_TGTID , // + FBUF_TGTID , MTTY_TGTID , BROM_TGTID , // targets ids + MNIC_TGTID , BDEV_TGTID, // + MEMC_WAYS , MEMC_SETS , // MC params + L1_IWAYS , L1_ISETS , L1_DWAYS , L1_DSETS, // L1 params + XRAM_LATENCY , // + is_io_cluster, // is IO cluster ? + FBUF_X_SIZE , FBUF_Y_SIZE , // FB params + disk_name , BDEV_SECTOR_SIZE, // IOC params + NB_NICS , nic_rx_name , nic_tx_name , NIC_TIMEOUT, // NIC params + loader , frozen_cycles, - debug_from, + debug_from , debug_ok and (cluster(x,y) == debug_memc_id), debug_ok and (cluster(x,y) == debug_proc_id) @@ -583,6 +541,6 @@ for (size_t x = 0; x < (CLUSTER_X); x++){ for (size_t y = 0; y < CLUSTER_Y; y++){ - clusters[x][y]->p_clk (signal_clk); - clusters[x][y]->p_resetn (signal_resetn); + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); } } @@ -631,13 +589,13 @@ for (size_t k = 0; k < 2; k++) { - clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); - clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); - clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); - clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); - - clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]); - clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]); - clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]); - clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]); + clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); + clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); + clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); + clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); + + clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]); + clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]); } } @@ -648,13 +606,13 @@ for (size_t k = 0; k < 2; k++) { - clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); - clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); - clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); - clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); - - clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]); - clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]); - clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]); - clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); + clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); + clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); + clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); + + clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]); + clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]); } } @@ -673,13 +631,13 @@ for (size_t k = 0; k < 2; k++){ for (size_t a = 0; a < 4; a++){ - signal_dspin_false_cmd_in[x][y][k][a].write = false; - signal_dspin_false_cmd_in[x][y][k][a].read = true; + signal_dspin_false_cmd_in [x][y][k][a].write = false; + signal_dspin_false_cmd_in [x][y][k][a].read = true; signal_dspin_false_cmd_out[x][y][k][a].write = false; - signal_dspin_false_cmd_out[x][y][k][a].read = true; - - signal_dspin_false_rsp_in[x][y][k][a].write = false; - signal_dspin_false_rsp_in[x][y][k][a].read = true; + signal_dspin_false_cmd_out[x][y][k][a].read = true; + + signal_dspin_false_rsp_in [x][y][k][a].write = false; + signal_dspin_false_rsp_in [x][y][k][a].read = true; signal_dspin_false_rsp_out[x][y][k][a].write = false; - signal_dspin_false_rsp_out[x][y][k][a].read = true; + signal_dspin_false_rsp_out[x][y][k][a].read = true; } } @@ -692,5 +650,4 @@ for (size_t n = 1; n < ncycles; n++) { - if (debug_ok and (n > debug_from) and (n % debug_period == 0)) { @@ -828,6 +785,2 @@ // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 - - - - Index: trunk/platforms/tsar_generic_xbar/top.desc =================================================================== --- trunk/platforms/tsar_generic_xbar/top.desc (revision 379) +++ trunk/platforms/tsar_generic_xbar/top.desc (revision 389) @@ -3,22 +3,34 @@ todo = Platform('caba', 'top.cpp', - uses = [ + uses = [ Uses('caba:tsar_xbar_cluster', - iss_t = 'common:gdb_iss', - gdb_iss_t = 'common:mips32el', - cmd_width = 40, - rsp_width = 33), - Uses('common:elf_file_loader'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el', + cmd_width = 40, + rsp_width = 33 + ), + Uses('common:elf_file_loader'), Uses('common:plain_file_loader'), - ], - cell_size = 4, - plen_size = 8, - addr_size = 32, - rerror_size = 2, - clen_size = 1, - rflag_size = 1, - srcid_size = 14, - pktid_size = 4, - trdid_size = 4, - wrplen_size = 1, + ], + cell_size_bis = 8, + plen_size_bis = 8, + addr_size_bis = 32, + rerror_size_bis = 2, + clen_size_bis = 1, + rflag_size_bis = 1, + srcid_size_bis = 14, + pktid_size_bis = 4, + trdid_size_bis = 4, + wrplen_size_bis = 1, + + cell_size = 4, + plen_size = 8, + addr_size = 32, + rerror_size = 2, + clen_size = 1, + rflag_size = 1, + srcid_size = 14, + pktid_size = 4, + trdid_size = 4, + wrplen_size = 1, ) Index: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd =================================================================== --- trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 379) +++ trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 389) @@ -3,52 +3,71 @@ Module('caba:tsar_xbar_cluster', - classname = 'soclib::caba::TsarXbarCluster', - tmpl_parameters = [ - parameter.Module('vci_param', default = 'caba:vci_param'), - parameter.Module('iss_t'), - parameter.Int('cmd_width'), - parameter.Int('rsp_width'), - ], - header_files = [ '../source/include/tsar_xbar_cluster.h', ], - implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], - uses = [ - Uses('caba:base_module'), - Uses('common:mapping_table'), - Uses('common:iss2'), - Uses('caba:vci_cc_vcache_wrapper', - iss_t = 'common:gdb_iss', - gdb_iss_t = 'common:mips32el'), - Uses('caba:vci_mem_cache'), - Uses('caba:vci_simple_ram'), + classname = 'soclib::caba::TsarXbarCluster', + tmpl_parameters = [ + parameter.Module('iss_t'), + parameter.Int('cmd_width'), + parameter.Int('rsp_width'), + ], + header_files = [ '../source/include/tsar_xbar_cluster.h', ], + implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + Uses('caba:vci_cc_vcache_wrapper', + vci_param = 'caba:vci_param', + dspin_in_width = parameter.Reference('cmd_width'), + dspin_out_width = parameter.Reference('rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el' + ), + Uses('caba:vci_mem_cache', + vci_param_int = 'caba:vci_param', + vci_param_ext = 'caba:vci_param_bis', + dspin_in_width = parameter.Reference('rsp_width'), + dspin_out_width = parameter.Reference('cmd_width') + ), + Uses('caba:vci_simple_ram', + vci_param = 'caba:vci_param_bis' + ), + Uses('caba:vci_simple_ram', + vci_param = 'caba:vci_param' + ), Uses('caba:vci_xicu'), Uses('caba:dspin_local_crossbar', - flit_width = parameter.Reference('cmd_width')), + flit_width = parameter.Reference('cmd_width') + ), Uses('caba:dspin_local_crossbar', - flit_width = parameter.Reference('rsp_width')), + flit_width = parameter.Reference('rsp_width') + ), Uses('caba:vci_dspin_initiator_wrapper', dspin_cmd_width = parameter.Reference('cmd_width'), - dspin_rsp_width = parameter.Reference('rsp_width')), + dspin_rsp_width = parameter.Reference('rsp_width') + ), Uses('caba:vci_dspin_target_wrapper', dspin_cmd_width = parameter.Reference('cmd_width'), - dspin_rsp_width = parameter.Reference('rsp_width')), + dspin_rsp_width = parameter.Reference('rsp_width') + ), Uses('caba:virtual_dspin_router', - flit_width = parameter.Reference('cmd_width')), + flit_width = parameter.Reference('cmd_width') + ), Uses('caba:virtual_dspin_router', - flit_width = parameter.Reference('rsp_width')), - Uses('caba:vci_multi_tty'), - Uses('caba:vci_framebuffer'), - Uses('caba:vci_multi_nic'), - Uses('caba:vci_block_device_tsar'), - Uses('caba:vci_multi_dma'), - Uses('common:elf_file_loader'), - ], - ports = [ - Port('caba:bit_in', 'p_resetn', auto = 'resetn'), - Port('caba:clock_in', 'p_clk', auto = 'clock'), - Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), - Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), - Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), - Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), - ], + flit_width = parameter.Reference('rsp_width') + ), + Uses('caba:vci_multi_tty'), + Uses('caba:vci_framebuffer'), + Uses('caba:vci_multi_nic'), + Uses('caba:vci_block_device_tsar'), + Uses('caba:vci_multi_dma'), + Uses('common:elf_file_loader'), + ], + ports = [ + Port('caba:bit_in' , 'p_resetn' , auto = 'resetn'), + Port('caba:clock_in' , 'p_clk' , auto = 'clock'), + Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), + Port('caba:dspin_input' , 'p_cmd_in' , [2, 4], dspin_data_size = parameter.Reference('cmd_width')), + Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), + Port('caba:dspin_input' , 'p_rsp_in' , [2, 4], dspin_data_size = parameter.Reference('rsp_width')), + ], ) Index: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h =================================================================== --- trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 379) +++ trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 389) @@ -34,133 +34,184 @@ #include "vci_cc_vcache_wrapper.h" -namespace soclib { namespace caba { +/////////////////////////////////////////////////////////// +// VCI parameters for DIRECT network +/////////////////////////////////////////////////////////// +#define cell_width 4 +#define address_width 32 +#define plen_width 8 +#define error_width 2 +#define clen_width 1 +#define rflag_width 1 +#define srcid_width 14 +#define pktid_width 4 +#define trdid_width 4 +#define wrplen_width 1 + +/////////////////////////////////////////////////////////// +// VCI parameters for EXTERNAL network +/////////////////////////////////////////////////////////// +#define cell_width_ext 8 +#define address_width_ext address_width +#define plen_width_ext plen_width +#define error_width_ext error_width +#define clen_width_ext clen_width +#define rflag_width_ext rflag_width +#define srcid_width_ext srcid_width +#define pktid_width_ext pktid_width +#define trdid_width_ext trdid_width +#define wrplen_width_ext wrplen_width + +namespace soclib { namespace caba { /////////////////////////////////////////////////////////////////////////// -template +template< + typename iss_t, int cmd_width, int rsp_width + > class TsarXbarCluster /////////////////////////////////////////////////////////////////////////// : public soclib::caba::BaseModule { + // Define VCI parameters + typedef soclib::caba::VciParams vci_param_d; + + typedef soclib::caba::VciParamsBis vci_param_x; public: - // Ports - sc_in p_clk; - sc_in p_resetn; - soclib::caba::DspinOutput **p_cmd_out; - soclib::caba::DspinInput **p_cmd_in; - soclib::caba::DspinOutput **p_rsp_out; - soclib::caba::DspinInput **p_rsp_in; + // Ports + sc_in p_clk; + sc_in p_resetn; + soclib::caba::DspinOutput **p_cmd_out; + soclib::caba::DspinInput **p_cmd_in; + soclib::caba::DspinOutput **p_rsp_out; + soclib::caba::DspinInput **p_rsp_in; // interrupt signals - sc_signal signal_false; - sc_signal signal_proc_it[8]; - sc_signal signal_irq_mdma[8]; - sc_signal signal_irq_mtty[23]; - sc_signal signal_irq_mnic_rx[8]; // unused - sc_signal signal_irq_mnic_tx[8]; // unused - sc_signal signal_irq_bdev; - - // DSPIN signals between DSPIN routers and local_crossbars - DspinSignals signal_dspin_cmd_l2g_d; - DspinSignals signal_dspin_cmd_g2l_d; - DspinSignals signal_dspin_m2p_l2g_c; - DspinSignals signal_dspin_m2p_g2l_c; - DspinSignals signal_dspin_rsp_l2g_d; - DspinSignals signal_dspin_rsp_g2l_d; - DspinSignals signal_dspin_p2m_l2g_c; - DspinSignals signal_dspin_p2m_g2l_c; - - // Direct VCI signals to VCI/DSPIN wrappers - VciSignals signal_vci_ini_proc[8]; - VciSignals signal_vci_ini_mdma; - VciSignals signal_vci_ini_bdev; - - VciSignals signal_vci_tgt_memc; - VciSignals signal_vci_tgt_xicu; - VciSignals signal_vci_tgt_mdma; - VciSignals signal_vci_tgt_mtty; - VciSignals signal_vci_tgt_bdev; - VciSignals signal_vci_tgt_brom; - VciSignals signal_vci_tgt_fbuf; - VciSignals signal_vci_tgt_mnic; - - // Direct DSPIN signals to local crossbars - DspinSignals signal_dspin_cmd_proc_i[8]; - DspinSignals signal_dspin_rsp_proc_i[8]; - DspinSignals signal_dspin_cmd_mdma_i; - DspinSignals signal_dspin_rsp_mdma_i; - DspinSignals signal_dspin_cmd_bdev_i; - DspinSignals signal_dspin_rsp_bdev_i; - - DspinSignals signal_dspin_cmd_memc_t; - DspinSignals signal_dspin_rsp_memc_t; - DspinSignals signal_dspin_cmd_xicu_t; - DspinSignals signal_dspin_rsp_xicu_t; - DspinSignals signal_dspin_cmd_mdma_t; - DspinSignals signal_dspin_rsp_mdma_t; - DspinSignals signal_dspin_cmd_mtty_t; - DspinSignals signal_dspin_rsp_mtty_t; - DspinSignals signal_dspin_cmd_bdev_t; - DspinSignals signal_dspin_rsp_bdev_t; - DspinSignals signal_dspin_cmd_brom_t; - DspinSignals signal_dspin_rsp_brom_t; - DspinSignals signal_dspin_cmd_fbuf_t; - DspinSignals signal_dspin_rsp_fbuf_t; - DspinSignals signal_dspin_cmd_mnic_t; - DspinSignals signal_dspin_rsp_mnic_t; - - // Coherence DSPIN signals to local crossbar - DspinSignals signal_dspin_m2p_memc; - DspinSignals signal_dspin_p2m_memc; - DspinSignals signal_dspin_m2p_proc[8]; - DspinSignals signal_dspin_p2m_proc[8]; - - // external RAM VCI signal - VciSignals signal_vci_xram; - + sc_signal signal_false; + sc_signal signal_proc_it[8]; + sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_mtty[23]; + sc_signal signal_irq_mnic_rx[8]; // unused + sc_signal signal_irq_mnic_tx[8]; // unused + sc_signal signal_irq_bdev; + + // DSPIN signals between DSPIN routers and local_crossbars + DspinSignals signal_dspin_cmd_l2g_d; + DspinSignals signal_dspin_cmd_g2l_d; + DspinSignals signal_dspin_m2p_l2g_c; + DspinSignals signal_dspin_m2p_g2l_c; + DspinSignals signal_dspin_rsp_l2g_d; + DspinSignals signal_dspin_rsp_g2l_d; + DspinSignals signal_dspin_p2m_l2g_c; + DspinSignals signal_dspin_p2m_g2l_c; + + // Direct VCI signals to VCI/DSPIN wrappers + VciSignals signal_vci_ini_proc[8]; + VciSignals signal_vci_ini_mdma; + VciSignals signal_vci_ini_bdev; + + VciSignals signal_vci_tgt_memc; + VciSignals signal_vci_tgt_xicu; + VciSignals signal_vci_tgt_mdma; + VciSignals signal_vci_tgt_mtty; + VciSignals signal_vci_tgt_bdev; + VciSignals signal_vci_tgt_brom; + VciSignals signal_vci_tgt_fbuf; + VciSignals signal_vci_tgt_mnic; + + // Direct DSPIN signals to local crossbars + DspinSignals signal_dspin_cmd_proc_i[8]; + DspinSignals signal_dspin_rsp_proc_i[8]; + DspinSignals signal_dspin_cmd_mdma_i; + DspinSignals signal_dspin_rsp_mdma_i; + DspinSignals signal_dspin_cmd_bdev_i; + DspinSignals signal_dspin_rsp_bdev_i; + + DspinSignals signal_dspin_cmd_memc_t; + DspinSignals signal_dspin_rsp_memc_t; + DspinSignals signal_dspin_cmd_xicu_t; + DspinSignals signal_dspin_rsp_xicu_t; + DspinSignals signal_dspin_cmd_mdma_t; + DspinSignals signal_dspin_rsp_mdma_t; + DspinSignals signal_dspin_cmd_mtty_t; + DspinSignals signal_dspin_rsp_mtty_t; + DspinSignals signal_dspin_cmd_bdev_t; + DspinSignals signal_dspin_rsp_bdev_t; + DspinSignals signal_dspin_cmd_brom_t; + DspinSignals signal_dspin_rsp_brom_t; + DspinSignals signal_dspin_cmd_fbuf_t; + DspinSignals signal_dspin_rsp_fbuf_t; + DspinSignals signal_dspin_cmd_mnic_t; + DspinSignals signal_dspin_rsp_mnic_t; + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[8]; + DspinSignals signal_dspin_p2m_proc[8]; + + // external RAM VCI signal + VciSignals signal_vci_xram; + // Components - VciCcVCacheWrapper* proc[8]; - VciDspinInitiatorWrapper* wi_proc[4]; - - VciMemCache* memc; - VciDspinTargetWrapper* wt_memc; - - VciXicu* xicu; - VciDspinTargetWrapper* wt_xicu; - - VciMultiDma* mdma; - VciDspinInitiatorWrapper* wi_mdma; - VciDspinTargetWrapper* wt_mdma; - - VciSimpleRam* xram; - VciDspinTargetWrapper* wt_xram; - - VciSimpleRam* brom; - VciDspinTargetWrapper* wt_brom; - - VciMultiTty* mtty; - VciDspinTargetWrapper* wt_mtty; - - VciFrameBuffer* fbuf; - VciDspinTargetWrapper* wt_fbuf; - - VciMultiNic* mnic; - VciDspinTargetWrapper* wt_mnic; - - VciBlockDeviceTsar* bdev; - VciDspinInitiatorWrapper* wi_bdev; - VciDspinTargetWrapper* wt_bdev; - - DspinLocalCrossbar* xbar_cmd_d; - DspinLocalCrossbar* xbar_rsp_d; - DspinLocalCrossbar* xbar_m2p_c; - DspinLocalCrossbar* xbar_p2m_c; - - VirtualDspinRouter* router_cmd; - VirtualDspinRouter* router_rsp; - - TsarXbarCluster( sc_module_name insname, + VciCcVCacheWrapper* proc[8]; + VciDspinInitiatorWrapper* wi_proc[4]; + + VciMemCache * memc; + VciDspinTargetWrapper* wt_memc; + + VciXicu* xicu; + VciDspinTargetWrapper* wt_xicu; + + VciMultiDma* mdma; + VciDspinInitiatorWrapper* wi_mdma; + VciDspinTargetWrapper* wt_mdma; + + VciSimpleRam* xram; + + VciSimpleRam* brom; + VciDspinTargetWrapper* wt_brom; + + VciMultiTty* mtty; + VciDspinTargetWrapper* wt_mtty; + + VciFrameBuffer* fbuf; + VciDspinTargetWrapper* wt_fbuf; + + VciMultiNic* mnic; + VciDspinTargetWrapper* wt_mnic; + + VciBlockDeviceTsar* bdev; + VciDspinInitiatorWrapper* wi_bdev; + VciDspinTargetWrapper* wt_bdev; + + DspinLocalCrossbar* xbar_cmd_d; + DspinLocalCrossbar* xbar_rsp_d; + DspinLocalCrossbar* xbar_m2p_c; + DspinLocalCrossbar* xbar_p2m_c; + + VirtualDspinRouter* router_cmd; + VirtualDspinRouter* router_rsp; + + TsarXbarCluster( sc_module_name insname, size_t nb_procs, // number of processors size_t nb_ttys, // number of TTY terminals @@ -171,11 +222,11 @@ const soclib::common::MappingTable &mtd, // direct mapping table const soclib::common::MappingTable &mtx, // xram mapping table - size_t x_width, // x field number of bits - size_t y_width, // y field number of bits - size_t l_width, // l field number of bits - size_t tgtid_memc, - size_t tgtid_xicu, + size_t x_width, // x field number of bits + size_t y_width, // y field number of bits + size_t l_width, // l field number of bits + size_t tgtid_memc, + size_t tgtid_xicu, size_t tgtid_mdma, - size_t tgtid_fbuf, + size_t tgtid_fbuf, size_t tgtid_mtty, size_t tgtid_brom, @@ -187,7 +238,7 @@ size_t l1_i_sets, size_t l1_d_ways, - size_t l1_d_sets, + size_t l1_d_sets, size_t xram_latency, // external ram latency - bool io, // I/O cluster if true + bool io, // I/O cluster if true size_t xfb, // frame buffer pixels size_t yfb, // frame buffer lines @@ -197,6 +248,6 @@ char* nic_rx_name, // file name rx packets char* nic_tx_name, // file name tx packets - uint32_t nic_timeout, // number of cycles - const Loader &loader, // loader for BROM + uint32_t nic_timeout, // number of cycles + const Loader &loader, // loader for BROM uint32_t frozen_cycles, // max frozen cycles uint32_t start_debug_cycle, @@ -204,5 +255,5 @@ bool proc_debug_ok); - ~TsarXbarCluster(); + ~TsarXbarCluster(); }; }} Index: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp =================================================================== --- trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 379) +++ trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 389) @@ -26,4 +26,10 @@ #include "../include/tsar_xbar_cluster.h" +#define tmpl(x) template<\ + typename iss_t,int cmd_width, int rsp_width> \ + x TsarXbarCluster<\ + iss_t, cmd_width, rsp_width\ + > + namespace soclib { namespace caba { @@ -32,6 +38,5 @@ // Constructor ////////////////////////////////////////////////////////////////////////// -template -TsarXbarCluster::TsarXbarCluster( +tmpl(/**/)::TsarXbarCluster( sc_module_name insname, size_t nb_procs, @@ -103,5 +108,5 @@ std::ostringstream sproc; sproc << "proc_" << p; - proc[p] = new VciCcVCacheWrapper( + proc[p] = new VciCcVCacheWrapper( sproc.str().c_str(), cluster_id*nb_procs + p, // GLOBAL PROC_ID @@ -125,5 +130,5 @@ std::ostringstream swip; swip << "wi_proc_" << x_id << "_" << y_id << p; - wi_proc[p] = new VciDspinInitiatorWrapper( + wi_proc[p] = new VciDspinInitiatorWrapper( swip.str().c_str(), x_width + y_width + l_width); @@ -133,5 +138,5 @@ std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; - memc = new VciMemCache( + memc = new VciMemCache( "memc", mtd, // Mapping Table direct space @@ -148,5 +153,5 @@ memc_debug_ok ); - wt_memc = new VciDspinTargetWrapper( + wt_memc = new VciDspinTargetWrapper( "wt_memc", x_width + y_width + l_width); @@ -155,5 +160,5 @@ std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; - xram = new VciSimpleRam( + xram = new VciSimpleRam( "xram", IntTab(cluster_id), @@ -165,5 +170,5 @@ std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; - xicu = new VciXicu( + xicu = new VciXicu( "xicu", mtd, // mapping table @@ -171,8 +176,8 @@ nb_procs, // number of timer IRQs 32, // number of hard IRQs - 0, // number of soft IRQs + 32, // number of soft IRQs nb_procs); // number of output IRQs - wt_xicu = new VciDspinTargetWrapper( + wt_xicu = new VciDspinTargetWrapper( "wt_xicu", x_width + y_width + l_width); @@ -181,5 +186,5 @@ std::cout << " - building mdma_" << x_id << "_" << y_id << std::endl; - mdma = new VciMultiDma( + mdma = new VciMultiDma( "mdma", mtd, @@ -189,9 +194,9 @@ nb_dmas); // number of IRQs - wt_mdma = new VciDspinTargetWrapper( + wt_mdma = new VciDspinTargetWrapper( "wt_mdma", x_width + y_width + l_width); - wi_mdma = new VciDspinInitiatorWrapper( + wi_mdma = new VciDspinInitiatorWrapper( "wi_mdma", x_width + y_width + l_width); @@ -285,5 +290,5 @@ std::cout << " - building brom" << std::endl; - brom = new VciSimpleRam( + brom = new VciSimpleRam( "brom", IntTab(cluster_id, tgtid_brom), @@ -291,5 +296,5 @@ loader); - wt_brom = new VciDspinTargetWrapper("wt_brom", + wt_brom = new VciDspinTargetWrapper("wt_brom", x_width + y_width + l_width); @@ -297,5 +302,5 @@ std::cout << " - building fbuf" << std::endl; - fbuf = new VciFrameBuffer( + fbuf = new VciFrameBuffer( "fbuf", IntTab(cluster_id, tgtid_fbuf), @@ -303,5 +308,5 @@ xfb, yfb); - wt_fbuf = new VciDspinTargetWrapper("wt_fbuf", + wt_fbuf = new VciDspinTargetWrapper("wt_fbuf", x_width + y_width + l_width); @@ -309,5 +314,5 @@ std::cout << " - building bdev" << std::endl; - bdev = new VciBlockDeviceTsar( + bdev = new VciBlockDeviceTsar( "bdev", mtd, @@ -318,7 +323,7 @@ 64); // burst size - wt_bdev = new VciDspinTargetWrapper("wt_bdev", - x_width + y_width + l_width); - wi_bdev = new VciDspinInitiatorWrapper("wi_bdev", + wt_bdev = new VciDspinTargetWrapper("wt_bdev", + x_width + y_width + l_width); + wi_bdev = new VciDspinInitiatorWrapper("wi_bdev", x_width + y_width + l_width); @@ -326,5 +331,5 @@ std::cout << " - building mnic" << std::endl; - mnic = new VciMultiNic( + mnic = new VciMultiNic( "mnic", IntTab(cluster_id, tgtid_mnic), @@ -336,5 +341,5 @@ 0 ); // mac_2 address - wt_mnic = new VciDspinTargetWrapper("wt_mnic", + wt_mnic = new VciDspinTargetWrapper("wt_mnic", x_width + y_width + l_width); @@ -349,5 +354,5 @@ vect_names.push_back(term_name.str().c_str()); } - mtty = new VciMultiTty( + mtty = new VciMultiTty( "mtty", IntTab(cluster_id, tgtid_mtty), @@ -355,5 +360,5 @@ vect_names); - wt_mtty = new VciDspinTargetWrapper("wt_mtty", + wt_mtty = new VciDspinTargetWrapper("wt_mtty", x_width + y_width + l_width); @@ -677,7 +682,5 @@ // destructor /////////////////////////////////////////////////////////////////////////// -template -TsarXbarCluster::~TsarXbarCluster() {} - +tmpl(/**/)::~TsarXbarCluster() {} } }