Changeset 392
- Timestamp:
- May 28, 2013, 12:35:01 AM (12 years ago)
- Location:
- trunk/modules/vci_block_device_tsar
- Files:
-
- 3 edited
-
caba/source/include/vci_block_device_tsar.h (modified) (4 diffs)
-
caba/source/src/vci_block_device_tsar.cpp (modified) (13 diffs)
-
include/soclib/block_device_tsar.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h
r391 r392 40 40 // asserted when the transfer is completed. 41 41 // 42 // As a target this block device controler contains 8memory mapped registers,43 // taking 3 2bytes in the address space.44 // - BLOCK_DEVICE_BUFFER 0x00 (read/write) Memory buffer base address .42 // As a target this block device controler contains 9 memory mapped registers, 43 // taking 36 bytes in the address space. 44 // - BLOCK_DEVICE_BUFFER 0x00 (read/write) Memory buffer base address (32 LSB bits) 45 45 // - BLOCK_DEVICE_COUNT 0x04 (read/write) Number of blocks to be transfered. 46 46 // - BLOCK_DEVICE_LBA 0x08 (read/write) Index of first block in the file. … … 50 50 // - BLOCK_DEVICE_SIZE 0x18 (read-only) Number of addressable blocks. 51 51 // - BLOCK_DEVICE_BLOCK_SIZE 0x1C (read_only) Block size in bytes. 52 // - BLOCK_DEVICE_BUFFER_EXT 0x20 (read_only) Memory buffer base address (32 MSB bits) 52 53 // 53 54 // The following operations codes are supported: … … 96 97 97 98 // Registers 98 sc_signal<int> r_target_fsm;// target fsm state register99 sc_signal<int> r_initiator_fsm; // initiator fsm state register100 sc_signal<bool> r_irq_enable;// default value is true101 sc_signal<uint32_t> r_nblocks;// number of blocks in transfer102 sc_signal<uint 32_t> r_buf_address; // memory buffer address103 sc_signal<uint32_t> r_lba;// first block index104 sc_signal<bool> r_read;// requested operation105 sc_signal<uint32_t> r_index;// flit index in local buffer106 sc_signal<uint32_t> r_latency_count; // latency counter107 sc_signal<uint32_t> r_flit_count;// flit counter (in a burst)108 sc_signal<uint32_t> r_burst_count;// burst counter (in a block)109 sc_signal<uint32_t> r_block_count;// block counter (in a transfer)110 sc_signal<uint32_t> r_burst_offset; // number of non aligned flits111 sc_signal<uint32_t> r_burst_nflits; // number of flits in a burst112 sc_signal<bool> r_go;// command from T_FSM to M_FSM113 114 sc_signal<sc_dt::sc_uint<vci_param::S> > r_srcid; 115 sc_signal<sc_dt::sc_uint<vci_param::T> > r_trdid; 116 sc_signal<sc_dt::sc_uint<vci_param::P> > r_pktid; 117 118 uint32_t* r_local_buffer;// capacity is one block99 sc_signal<int> r_target_fsm; // target fsm state register 100 sc_signal<int> r_initiator_fsm; // initiator fsm state register 101 sc_signal<bool> r_irq_enable; // default value is true 102 sc_signal<uint32_t> r_nblocks; // number of blocks in transfer 103 sc_signal<uint64_t> r_buf_address; // memory buffer address 104 sc_signal<uint32_t> r_lba; // first block index 105 sc_signal<bool> r_read; // requested operation 106 sc_signal<uint32_t> r_index; // flit index in local buffer 107 sc_signal<uint32_t> r_latency_count; // latency counter 108 sc_signal<uint32_t> r_flit_count; // flit counter (in a burst) 109 sc_signal<uint32_t> r_burst_count; // burst counter (in a block) 110 sc_signal<uint32_t> r_block_count; // block counter (in a transfer) 111 sc_signal<uint32_t> r_burst_offset; // number of non aligned flits 112 sc_signal<uint32_t> r_burst_nflits; // number of flits in a burst 113 sc_signal<bool> r_go; // command from T_FSM to M_FSM 114 115 sc_signal<sc_dt::sc_uint<vci_param::S> > r_srcid; // save srcid 116 sc_signal<sc_dt::sc_uint<vci_param::T> > r_trdid; // save trdid 117 sc_signal<sc_dt::sc_uint<vci_param::P> > r_pktid; // save pktid 118 119 uint32_t* r_local_buffer; // capacity is one block 119 120 120 121 // structural parameters 121 soclib::common::Segment m_segment;// segment associated to target122 uint32_t m_srcid;// initiator index123 int m_fd;// File descriptor124 uint64_t m_device_size;// Total number of blocks125 const uint32_t m_flits_per_block;// number of flits in a block126 const uint32_t m_flits_per_burst;// number of flits in a burst127 const uint32_t m_bursts_per_block; // number of bursts in a block128 const uint32_t m_latency;// device latency122 soclib::common::Segment m_segment; // segment associated to target 123 uint32_t m_srcid; // initiator index 124 int m_fd; // File descriptor 125 uint64_t m_device_size; // Total number of blocks 126 const uint32_t m_flits_per_block; // number of flits in a block 127 const uint32_t m_flits_per_burst; // number of flits in a burst 128 const uint32_t m_bursts_per_block; // number of bursts in a block 129 const uint32_t m_latency; // device latency 129 130 130 131 // methods … … 156 157 T_WRITE_BUFFER = 1, 157 158 T_READ_BUFFER = 2, 158 T_WRITE_COUNT = 3, 159 T_READ_COUNT = 4, 160 T_WRITE_LBA = 5, 161 T_READ_LBA = 6, 162 T_WRITE_OP = 7, 163 T_READ_STATUS = 8, 164 T_WRITE_IRQEN = 9, 165 T_READ_IRQEN = 10, 166 T_READ_SIZE = 11, 167 T_READ_BLOCK = 12, 168 T_READ_ERROR = 13, 169 T_WRITE_ERROR = 14, 159 T_WRITE_BUFFER_EXT = 3, 160 T_READ_BUFFER_EXT = 4, 161 T_WRITE_COUNT = 5, 162 T_READ_COUNT = 6, 163 T_WRITE_LBA = 7, 164 T_READ_LBA = 8, 165 T_WRITE_OP = 9, 166 T_READ_STATUS = 10, 167 T_WRITE_IRQEN = 11, 168 T_READ_IRQEN = 12, 169 T_READ_SIZE = 13, 170 T_READ_BLOCK = 14, 171 T_READ_ERROR = 15, 172 T_WRITE_ERROR = 16, 170 173 }; 171 174 -
trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp
r381 r392 44 44 if(p_resetn.read() == false) 45 45 { 46 r_initiator_fsm = M_IDLE;47 r_target_fsm = T_IDLE;48 r_irq_enable = true;49 r_go = false;46 r_initiator_fsm = M_IDLE; 47 r_target_fsm = T_IDLE; 48 r_irq_enable = true; 49 r_go = false; 50 50 return; 51 51 } … … 67 67 sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); 68 68 bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); 69 uint32_t cell = (uint32_t)((address & 0x 1F)>>2);69 uint32_t cell = (uint32_t)((address & 0x3F)>>2); 70 70 71 71 if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; … … 75 75 else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; 76 76 else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; 77 else if( !read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_WRITE_BUFFER_EXT; 78 else if( read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_READ_BUFFER_EXT; 77 79 else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; 78 80 else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; … … 91 93 case T_WRITE_BUFFER: 92 94 { 93 if ( r_initiator_fsm == M_IDLE ) r_buf_address = (uint32_t)p_vci_target.wdata.read(); 94 if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; 95 if ( (r_initiator_fsm.read() == M_IDLE) and p_vci_target.rspack.read() ) 96 { 97 r_buf_address = (uint64_t)p_vci_target.wdata.read(); 98 r_target_fsm = T_IDLE; 99 } 100 break; 101 } 102 //////////////////////// 103 case T_WRITE_BUFFER_EXT: 104 { 105 if ( (r_initiator_fsm.read() == M_IDLE) and p_vci_target.rspack.read() ) 106 { 107 r_buf_address = r_buf_address.read() + 108 (((uint64_t)p_vci_target.wdata.read())<<32); 109 r_target_fsm = T_IDLE; 110 } 95 111 break; 96 112 } … … 98 114 case T_WRITE_COUNT: 99 115 { 100 if ( r_initiator_fsm == M_IDLE ) r_nblocks = (uint32_t)p_vci_target.wdata.read(); 101 if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; 116 if ( (r_initiator_fsm.read() == M_IDLE) and p_vci_target.rspack.read() ) 117 { 118 r_nblocks = (uint32_t)p_vci_target.wdata.read(); 119 r_target_fsm = T_IDLE; 120 } 102 121 break; 103 122 } … … 105 124 case T_WRITE_LBA: 106 125 { 107 if ( r_initiator_fsm == M_IDLE ) r_lba = (uint32_t)p_vci_target.wdata.read(); 108 if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; 126 if ( (r_initiator_fsm.read() == M_IDLE) and p_vci_target.rspack.read() ) 127 { 128 r_lba = (uint32_t)p_vci_target.wdata.read(); 129 r_target_fsm = T_IDLE; 130 } 109 131 break; 110 132 } … … 112 134 case T_WRITE_OP: 113 135 { 114 if ( r_initiator_fsm == M_IDLE ) 115 { 116 if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ ) 136 if ( p_vci_target.rspack.read() ) 137 { 138 if ( ((uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ) and 139 (r_initiator_fsm.read() == M_IDLE) ) 117 140 { 118 141 r_read = true; 119 r_go = true; 120 } 121 else if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE) 142 r_go = true; 143 } 144 else if ( ((uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE) and 145 (r_initiator_fsm.read() == M_IDLE) ) 122 146 { 123 147 r_read = false; 124 r_go = true; 125 } 126 } 127 if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; 148 r_go = true; 149 } 150 else 151 { 152 r_go = false; 153 } 154 r_target_fsm = T_IDLE; 155 } 128 156 break; 129 157 } … … 131 159 case T_WRITE_IRQEN: 132 160 { 133 r_irq_enable = (p_vci_target.wdata.read() != 0); 134 if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; 161 if ( p_vci_target.rspack.read() ) 162 { 163 r_target_fsm = T_IDLE; 164 r_irq_enable = (p_vci_target.wdata.read() != 0); 165 } 135 166 break; 136 167 } 137 168 /////////////////// 138 169 case T_READ_BUFFER: 170 case T_READ_BUFFER_EXT: 139 171 case T_READ_COUNT: 140 172 case T_READ_LBA: … … 190 222 191 223 // compute r_burst_offset (zero when buffer aligned) 192 r_burst_offset = ( r_buf_address.read()>>2) % m_flits_per_burst;224 r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_flits_per_burst); 193 225 194 226 // start tranfer … … 338 370 if ( p_vci_initiator.reop.read() ) // last flit of the burst 339 371 { 340 r_flit_count = 0;372 r_flit_count = 0; 341 373 r_buf_address = r_buf_address.read() + (r_burst_nflits.read()<<2); 342 374 343 if( (p_vci_initiator.rerror.read()&0x1) != 0 )375 if( (p_vci_initiator.rerror.read()&0x1) != 0 ) 344 376 { 345 377 r_initiator_fsm = M_WRITE_ERROR; … … 431 463 p_vci_target.rspval = true; 432 464 p_vci_target.rdata = (uint32_t)r_buf_address.read(); 465 p_vci_target.rerror = VCI_READ_OK; 466 break; 467 case T_READ_BUFFER_EXT: 468 p_vci_target.cmdack = false; 469 p_vci_target.rspval = true; 470 p_vci_target.rdata = (uint32_t)(r_buf_address.read()>>32); 433 471 p_vci_target.rerror = VCI_READ_OK; 434 472 break; … … 649 687 }; 650 688 const char* target_str[] = { 651 "IDLE 689 "IDLE", 652 690 "WRITE_BUFFER", 653 "READ_BUFFER ", 654 "WRITE_COUNT ", 655 "READ_COUNT ", 656 "WRITE_LBA ", 657 "READ_LBA ", 658 "WRITE_OP ", 659 "READ_STATUS ", 660 "WRITE_IRQEN ", 661 "READ_IRQEN ", 662 "READ_SIZE ", 663 "READ_BLOCK ", 664 "READ_ERROR ", 691 "READ_BUFFER", 692 "WRITE_BUFFER_EXT", 693 "READ_BUFFER_EXT", 694 "WRITE_COUNT", 695 "READ_COUNT", 696 "WRITE_LBA", 697 "READ_LBA", 698 "WRITE_OP", 699 "READ_STATUS", 700 "WRITE_IRQEN", 701 "READ_IRQEN", 702 "READ_SIZE", 703 "READ_BLOCK", 704 "READ_ERROR", 665 705 "WRITE_ERROR ", 666 706 }; … … 668 708 std::cout << "BDEV_TGT : " << target_str[r_target_fsm.read()] 669 709 << " BDEV_INI : " << initiator_str[r_initiator_fsm.read()] 670 << " block = " << r_block_count.read() 710 << " buf = " << std::hex << r_buf_address.read() 711 << " block = " << std::dec << r_block_count.read() 671 712 << " burst = " << r_burst_count.read() 672 713 << " flit = " << r_flit_count.read() <<std::endl; -
trunk/modules/vci_block_device_tsar/include/soclib/block_device_tsar.h
r374 r392 37 37 BLOCK_DEVICE_SIZE, 38 38 BLOCK_DEVICE_BLOCK_SIZE, 39 BLOCK_DEVICE_BUFFER_EXT, 39 40 }; 40 41
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