Index: /trunk/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h =================================================================== --- /trunk/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h (revision 391) +++ /trunk/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h (revision 392) @@ -40,7 +40,7 @@ // asserted when the transfer is completed. // -// As a target this block device controler contains 8 memory mapped registers, -// taking 32 bytes in the address space. -// - BLOCK_DEVICE_BUFFER 0x00 (read/write) Memory buffer base address. +// As a target this block device controler contains 9 memory mapped registers, +// taking 36 bytes in the address space. +// - BLOCK_DEVICE_BUFFER 0x00 (read/write) Memory buffer base address (32 LSB bits) // - BLOCK_DEVICE_COUNT 0x04 (read/write) Number of blocks to be transfered. // - BLOCK_DEVICE_LBA 0x08 (read/write) Index of first block in the file. @@ -50,4 +50,5 @@ // - BLOCK_DEVICE_SIZE 0x18 (read-only) Number of addressable blocks. // - BLOCK_DEVICE_BLOCK_SIZE 0x1C (read_only) Block size in bytes. +// - BLOCK_DEVICE_BUFFER_EXT 0x20 (read_only) Memory buffer base address (32 MSB bits) // // The following operations codes are supported: @@ -96,35 +97,35 @@ // Registers - sc_signal r_target_fsm; // target fsm state register - sc_signal r_initiator_fsm; // initiator fsm state register - sc_signal r_irq_enable; // default value is true - sc_signal r_nblocks; // number of blocks in transfer - sc_signal r_buf_address; // memory buffer address - sc_signal r_lba; // first block index - sc_signal r_read; // requested operation - sc_signal r_index; // flit index in local buffer - sc_signal r_latency_count; // latency counter - sc_signal r_flit_count; // flit counter (in a burst) - sc_signal r_burst_count; // burst counter (in a block) - sc_signal r_block_count; // block counter (in a transfer) - sc_signal r_burst_offset; // number of non aligned flits - sc_signal r_burst_nflits; // number of flits in a burst - sc_signal r_go; // command from T_FSM to M_FSM - - sc_signal > r_srcid; // save srcid - sc_signal > r_trdid; // save trdid - sc_signal > r_pktid; // save pktid - - uint32_t* r_local_buffer; // capacity is one block + sc_signal r_target_fsm; // target fsm state register + sc_signal r_initiator_fsm; // initiator fsm state register + sc_signal r_irq_enable; // default value is true + sc_signal r_nblocks; // number of blocks in transfer + sc_signal r_buf_address; // memory buffer address + sc_signal r_lba; // first block index + sc_signal r_read; // requested operation + sc_signal r_index; // flit index in local buffer + sc_signal r_latency_count; // latency counter + sc_signal r_flit_count; // flit counter (in a burst) + sc_signal r_burst_count; // burst counter (in a block) + sc_signal r_block_count; // block counter (in a transfer) + sc_signal r_burst_offset; // number of non aligned flits + sc_signal r_burst_nflits; // number of flits in a burst + sc_signal r_go; // command from T_FSM to M_FSM + + sc_signal > r_srcid; // save srcid + sc_signal > r_trdid; // save trdid + sc_signal > r_pktid; // save pktid + + uint32_t* r_local_buffer; // capacity is one block // structural parameters - soclib::common::Segment m_segment; // segment associated to target - uint32_t m_srcid; // initiator index - int m_fd; // File descriptor - uint64_t m_device_size; // Total number of blocks - const uint32_t m_flits_per_block; // number of flits in a block - const uint32_t m_flits_per_burst; // number of flits in a burst - const uint32_t m_bursts_per_block; // number of bursts in a block - const uint32_t m_latency; // device latency + soclib::common::Segment m_segment; // segment associated to target + uint32_t m_srcid; // initiator index + int m_fd; // File descriptor + uint64_t m_device_size; // Total number of blocks + const uint32_t m_flits_per_block; // number of flits in a block + const uint32_t m_flits_per_burst; // number of flits in a burst + const uint32_t m_bursts_per_block; // number of bursts in a block + const uint32_t m_latency; // device latency // methods @@ -156,16 +157,18 @@ T_WRITE_BUFFER = 1, T_READ_BUFFER = 2, - T_WRITE_COUNT = 3, - T_READ_COUNT = 4, - T_WRITE_LBA = 5, - T_READ_LBA = 6, - T_WRITE_OP = 7, - T_READ_STATUS = 8, - T_WRITE_IRQEN = 9, - T_READ_IRQEN = 10, - T_READ_SIZE = 11, - T_READ_BLOCK = 12, - T_READ_ERROR = 13, - T_WRITE_ERROR = 14, + T_WRITE_BUFFER_EXT = 3, + T_READ_BUFFER_EXT = 4, + T_WRITE_COUNT = 5, + T_READ_COUNT = 6, + T_WRITE_LBA = 7, + T_READ_LBA = 8, + T_WRITE_OP = 9, + T_READ_STATUS = 10, + T_WRITE_IRQEN = 11, + T_READ_IRQEN = 12, + T_READ_SIZE = 13, + T_READ_BLOCK = 14, + T_READ_ERROR = 15, + T_WRITE_ERROR = 16, }; Index: /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp =================================================================== --- /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp (revision 391) +++ /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp (revision 392) @@ -44,8 +44,8 @@ if(p_resetn.read() == false) { - r_initiator_fsm = M_IDLE; - r_target_fsm = T_IDLE; - r_irq_enable = true; - r_go = false; + r_initiator_fsm = M_IDLE; + r_target_fsm = T_IDLE; + r_irq_enable = true; + r_go = false; return; } @@ -67,5 +67,5 @@ sc_dt::sc_uint address = p_vci_target.address.read(); bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); - uint32_t cell = (uint32_t)((address & 0x1F)>>2); + uint32_t cell = (uint32_t)((address & 0x3F)>>2); if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; @@ -75,4 +75,6 @@ else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; + else if( !read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_WRITE_BUFFER_EXT; + else if( read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_READ_BUFFER_EXT; else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; @@ -91,6 +93,20 @@ case T_WRITE_BUFFER: { - if ( r_initiator_fsm == M_IDLE ) r_buf_address = (uint32_t)p_vci_target.wdata.read(); - if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; + if ( (r_initiator_fsm.read() == M_IDLE) and p_vci_target.rspack.read() ) + { + r_buf_address = (uint64_t)p_vci_target.wdata.read(); + r_target_fsm = T_IDLE; + } + break; + } + //////////////////////// + case T_WRITE_BUFFER_EXT: + { + if ( (r_initiator_fsm.read() == M_IDLE) and p_vci_target.rspack.read() ) + { + r_buf_address = r_buf_address.read() + + (((uint64_t)p_vci_target.wdata.read())<<32); + r_target_fsm = T_IDLE; + } break; } @@ -98,6 +114,9 @@ case T_WRITE_COUNT: { - if ( r_initiator_fsm == M_IDLE ) r_nblocks = (uint32_t)p_vci_target.wdata.read(); - if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; + if ( (r_initiator_fsm.read() == M_IDLE) and p_vci_target.rspack.read() ) + { + r_nblocks = (uint32_t)p_vci_target.wdata.read(); + r_target_fsm = T_IDLE; + } break; } @@ -105,6 +124,9 @@ case T_WRITE_LBA: { - if ( r_initiator_fsm == M_IDLE ) r_lba = (uint32_t)p_vci_target.wdata.read(); - if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; + if ( (r_initiator_fsm.read() == M_IDLE) and p_vci_target.rspack.read() ) + { + r_lba = (uint32_t)p_vci_target.wdata.read(); + r_target_fsm = T_IDLE; + } break; } @@ -112,18 +134,24 @@ case T_WRITE_OP: { - if ( r_initiator_fsm == M_IDLE ) - { - if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ ) + if ( p_vci_target.rspack.read() ) + { + if ( ((uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ) and + (r_initiator_fsm.read() == M_IDLE) ) { r_read = true; - r_go = true; - } - else if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE) + r_go = true; + } + else if ( ((uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE) and + (r_initiator_fsm.read() == M_IDLE) ) { r_read = false; - r_go = true; - } - } - if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; + r_go = true; + } + else + { + r_go = false; + } + r_target_fsm = T_IDLE; + } break; } @@ -131,10 +159,14 @@ case T_WRITE_IRQEN: { - r_irq_enable = (p_vci_target.wdata.read() != 0); - if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; + if ( p_vci_target.rspack.read() ) + { + r_target_fsm = T_IDLE; + r_irq_enable = (p_vci_target.wdata.read() != 0); + } break; } /////////////////// case T_READ_BUFFER: + case T_READ_BUFFER_EXT: case T_READ_COUNT: case T_READ_LBA: @@ -190,5 +222,5 @@ // compute r_burst_offset (zero when buffer aligned) - r_burst_offset = (r_buf_address.read()>>2) % m_flits_per_burst; + r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_flits_per_burst); // start tranfer @@ -338,8 +370,8 @@ if ( p_vci_initiator.reop.read() ) // last flit of the burst { - r_flit_count = 0; + r_flit_count = 0; r_buf_address = r_buf_address.read() + (r_burst_nflits.read()<<2); - if( (p_vci_initiator.rerror.read()&0x1) != 0 ) + if( (p_vci_initiator.rerror.read()&0x1) != 0 ) { r_initiator_fsm = M_WRITE_ERROR; @@ -431,4 +463,10 @@ p_vci_target.rspval = true; p_vci_target.rdata = (uint32_t)r_buf_address.read(); + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_BUFFER_EXT: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = (uint32_t)(r_buf_address.read()>>32); p_vci_target.rerror = VCI_READ_OK; break; @@ -649,18 +687,20 @@ }; const char* target_str[] = { - "IDLE ", + "IDLE", "WRITE_BUFFER", - "READ_BUFFER ", - "WRITE_COUNT ", - "READ_COUNT ", - "WRITE_LBA ", - "READ_LBA ", - "WRITE_OP ", - "READ_STATUS ", - "WRITE_IRQEN ", - "READ_IRQEN ", - "READ_SIZE ", - "READ_BLOCK ", - "READ_ERROR ", + "READ_BUFFER", + "WRITE_BUFFER_EXT", + "READ_BUFFER_EXT", + "WRITE_COUNT", + "READ_COUNT", + "WRITE_LBA", + "READ_LBA", + "WRITE_OP", + "READ_STATUS", + "WRITE_IRQEN", + "READ_IRQEN", + "READ_SIZE", + "READ_BLOCK", + "READ_ERROR", "WRITE_ERROR ", }; @@ -668,5 +708,6 @@ std::cout << "BDEV_TGT : " << target_str[r_target_fsm.read()] << " BDEV_INI : " << initiator_str[r_initiator_fsm.read()] - << " block = " << r_block_count.read() + << " buf = " << std::hex << r_buf_address.read() + << " block = " << std::dec << r_block_count.read() << " burst = " << r_burst_count.read() << " flit = " << r_flit_count.read() <