Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 386)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 394)
@@ -63,18 +63,9 @@
     : public soclib::caba::BaseModule
 {
-    typedef uint32_t vaddr_t;
-    typedef uint32_t tag_t;
-    typedef uint32_t type_t;
-    typedef typename iss_t::DataOperationType data_op_t;
-
-    typedef typename vci_param::addr_t  paddr_t;
-    typedef typename vci_param::data_t  vci_data_t;
-    typedef typename vci_param::be_t    vci_be_t;
-    typedef typename vci_param::srcid_t vci_srcid_t;
-    typedef typename vci_param::trdid_t vci_trdid_t;
-    typedef typename vci_param::pktid_t vci_pktid_t;
-    typedef typename vci_param::plen_t  vci_plen_t;
-
-    enum icache_fsm_state_e {
+
+    typedef typename vci_param::fast_addr_t  paddr_t;
+
+    enum icache_fsm_state_e 
+    {
         ICACHE_IDLE,
         // handling XTN processor requests
@@ -104,5 +95,6 @@
     };
 
-    enum dcache_fsm_state_e {
+    enum dcache_fsm_state_e 
+    {
         DCACHE_IDLE,
         // handling itlb & dtlb miss
@@ -154,5 +146,6 @@
     };
 
-    enum cmd_fsm_state_e {
+    enum cmd_fsm_state_e 
+    {
         CMD_IDLE,
         CMD_INS_MISS,
@@ -166,5 +159,6 @@
     };
 
-    enum rsp_fsm_state_e {
+    enum rsp_fsm_state_e 
+    {
         RSP_IDLE,
         RSP_INS_MISS,
@@ -176,5 +170,6 @@
     };
 
-    enum cc_receive_fsm_state_e {
+    enum cc_receive_fsm_state_e 
+    {
         CC_RECEIVE_IDLE,
         CC_RECEIVE_CLACK,
@@ -188,5 +183,6 @@
     };
 
-    enum cc_send_fsm_state_e {
+    enum cc_send_fsm_state_e 
+    {
         CC_SEND_IDLE,
         CC_SEND_CLEANUP_1,
@@ -224,5 +220,6 @@
 
     // cc_send_type
-    typedef enum {
+    typedef enum 
+    {
         CC_TYPE_CLEANUP,
         CC_TYPE_MULTI_ACK,
@@ -230,5 +227,6 @@
 
     // cc_receive_type
-    typedef enum {
+    typedef enum 
+    {
         CC_TYPE_CLACK,
         CC_TYPE_BRDCAST,
@@ -238,5 +236,6 @@
 
     // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
-    enum {
+    enum 
+    {
         INS_TLB_MASK    = 0x8,
         DATA_TLB_MASK   = 0x4,
@@ -298,5 +297,5 @@
     soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table;
 
-    const vci_srcid_t                   m_srcid;
+    const size_t                        m_srcid;
     const size_t                        m_cc_global_id;
     const size_t                        m_nline_width;
@@ -330,12 +329,9 @@
 
     /////////////////////////////////////////////
-    // debug variables (for each FSM)
+    // debug variables 
     /////////////////////////////////////////////
-    bool                                m_debug_previous_hit;
-    bool                                m_idebug_previous_hit;
-    bool                                m_debug_dcache_fsm;
-    bool                                m_debug_icache_fsm;
-    bool                                m_debug_inval_itlb_fsm;
-    bool                                m_debug_inval_dtlb_fsm;
+    bool                                m_debug_previous_i_hit;
+    bool                                m_debug_previous_d_hit;
+    bool                                m_debug_activated;
 
     ///////////////////////////////
@@ -404,5 +400,5 @@
     sc_signal<uint32_t>     r_dcache_save_vaddr;        // virtual address (from proc)
     sc_signal<uint32_t>     r_dcache_save_wdata;        // write data (from proc)
-    sc_signal<vci_be_t>     r_dcache_save_be;           // byte enable (from proc)
+    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
     sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
     sc_signal<bool>         r_dcache_save_cacheable;	// address cacheable
@@ -425,5 +421,5 @@
     sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
     sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
-    sc_signal<vci_data_t>   r_dcache_vci_sc_data;       // SC data (command)
+    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
 
     // register used for XTN inval
@@ -482,6 +478,9 @@
 
     // dcache directory extension
-    bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
-    bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
+    bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
+    bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
+
+    // Physical address extension for data access
+    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
 
     ///////////////////////////////////
@@ -489,8 +488,8 @@
     ///////////////////////////////////
     sc_signal<int>          r_vci_cmd_fsm;
-    sc_signal<size_t>       r_vci_cmd_min;      	    // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_max;      	    // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_cpt;    		    // used for write bursts
-    sc_signal<bool>         r_vci_cmd_imiss_prio;	    // round-robin between imiss & dmiss
+    sc_signal<size_t>       r_vci_cmd_min;      	        // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_max;      	        // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_cpt;    		        // used for write bursts
+    sc_signal<bool>         r_vci_cmd_imiss_prio;	        // round-robin between imiss & dmiss
 
     ///////////////////////////////////
@@ -501,21 +500,21 @@
     sc_signal<bool>         r_vci_rsp_ins_error;
     sc_signal<bool>         r_vci_rsp_data_error;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	    // response FIFO to ICACHE FSM
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	    // response FIFO to DCACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	        // response FIFO to ICACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	        // response FIFO to DCACHE FSM
 
     ///////////////////////////////////
     //  CC_SEND FSM REGISTER
     ///////////////////////////////////
-    sc_signal<int>          r_cc_send_fsm;          // state register
-    sc_signal<bool>         r_cc_send_last_client;  // round robin flip-flop : 0 dcache / 1 icache
+    sc_signal<int>          r_cc_send_fsm;                  // state register
+    sc_signal<bool>         r_cc_send_last_client;          // 0 dcache / 1 icache
 
     ///////////////////////////////////
     //  CC_RECEIVE FSM REGISTER
     ///////////////////////////////////
-    sc_signal<int>          r_cc_receive_fsm;          // state register
-    sc_signal<bool>         r_cc_receive_data_ins;     // request concerning : 0 dcache / 1 icache
-
-    // communication cc updt FIFO between CC_RECEIVE FSM and ICACHE/DCACHE FSM
-    sc_signal<size_t>       r_cc_receive_word_idx;  // word index
+    sc_signal<int>          r_cc_receive_fsm;               // state register
+    sc_signal<bool>         r_cc_receive_data_ins;          // request to : 0 dcache / 1 icache
+
+    // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM
+    sc_signal<size_t>       r_cc_receive_word_idx;          // word index
     GenericFifo<uint32_t>   r_cc_receive_updt_fifo_be;
     GenericFifo<uint32_t>   r_cc_receive_updt_fifo_data;
@@ -523,18 +522,18 @@
 
     // communication between CC_RECEIVE FSM and ICACHE FSM
-    sc_signal<bool>         r_cc_receive_icache_req;       // cc_receive to icache request
-    sc_signal<cc_receive_t> r_cc_receive_icache_type;      // cc_receive type of coherence request
-    sc_signal<size_t>       r_cc_receive_icache_way;       // cc_receive to icache way
-    sc_signal<size_t>       r_cc_receive_icache_set;       // cc_receive to icache set
+    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
+    sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
+    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
+    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
     sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_icache_nline;	   // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_icache_nline;	    // cache line physical address
 
     // communication between CC_RECEIVE FSM and DCACHE FSM
-    sc_signal<bool>         r_cc_receive_dcache_req;       // cc_receive to dcache request
-    sc_signal<cc_receive_t> r_cc_receive_dcache_type;      // cc_receive type of coherence request
-    sc_signal<size_t>       r_cc_receive_dcache_way;       // cc_receive to dcache way
-    sc_signal<size_t>       r_cc_receive_dcache_set;       // cc_receive to dcache set
+    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
+    sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
+    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
+    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
     sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_dcache_nline;	   // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_dcache_nline;	    // cache line physical address
 
     //////////////////////////////////////////////////////////////////
@@ -714,6 +713,7 @@
     void print_trace(size_t mode = 0);
     void cache_monitor(paddr_t addr);
-    inline void iss_set_debug_mask(uint v) {
-	r_iss.set_debug_mask(v);
+    inline void iss_set_debug_mask(uint v) 
+    {
+	    r_iss.set_debug_mask(v);
     }
 
