Index: /trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- /trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 393) +++ /trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 394) @@ -63,18 +63,9 @@ : public soclib::caba::BaseModule { - typedef uint32_t vaddr_t; - typedef uint32_t tag_t; - typedef uint32_t type_t; - typedef typename iss_t::DataOperationType data_op_t; - - typedef typename vci_param::addr_t paddr_t; - typedef typename vci_param::data_t vci_data_t; - typedef typename vci_param::be_t vci_be_t; - typedef typename vci_param::srcid_t vci_srcid_t; - typedef typename vci_param::trdid_t vci_trdid_t; - typedef typename vci_param::pktid_t vci_pktid_t; - typedef typename vci_param::plen_t vci_plen_t; - - enum icache_fsm_state_e { + + typedef typename vci_param::fast_addr_t paddr_t; + + enum icache_fsm_state_e + { ICACHE_IDLE, // handling XTN processor requests @@ -104,5 +95,6 @@ }; - enum dcache_fsm_state_e { + enum dcache_fsm_state_e + { DCACHE_IDLE, // handling itlb & dtlb miss @@ -154,5 +146,6 @@ }; - enum cmd_fsm_state_e { + enum cmd_fsm_state_e + { CMD_IDLE, CMD_INS_MISS, @@ -166,5 +159,6 @@ }; - enum rsp_fsm_state_e { + enum rsp_fsm_state_e + { RSP_IDLE, RSP_INS_MISS, @@ -176,5 +170,6 @@ }; - enum cc_receive_fsm_state_e { + enum cc_receive_fsm_state_e + { CC_RECEIVE_IDLE, CC_RECEIVE_CLACK, @@ -188,5 +183,6 @@ }; - enum cc_send_fsm_state_e { + enum cc_send_fsm_state_e + { CC_SEND_IDLE, CC_SEND_CLEANUP_1, @@ -224,5 +220,6 @@ // cc_send_type - typedef enum { + typedef enum + { CC_TYPE_CLEANUP, CC_TYPE_MULTI_ACK, @@ -230,5 +227,6 @@ // cc_receive_type - typedef enum { + typedef enum + { CC_TYPE_CLACK, CC_TYPE_BRDCAST, @@ -238,5 +236,6 @@ // TLB Mode : ITLB / DTLB / ICACHE / DCACHE - enum { + enum + { INS_TLB_MASK = 0x8, DATA_TLB_MASK = 0x4, @@ -298,5 +297,5 @@ soclib::common::AddressDecodingTable m_cacheability_table; - const vci_srcid_t m_srcid; + const size_t m_srcid; const size_t m_cc_global_id; const size_t m_nline_width; @@ -330,12 +329,9 @@ ///////////////////////////////////////////// - // debug variables (for each FSM) + // debug variables ///////////////////////////////////////////// - bool m_debug_previous_hit; - bool m_idebug_previous_hit; - bool m_debug_dcache_fsm; - bool m_debug_icache_fsm; - bool m_debug_inval_itlb_fsm; - bool m_debug_inval_dtlb_fsm; + bool m_debug_previous_i_hit; + bool m_debug_previous_d_hit; + bool m_debug_activated; /////////////////////////////// @@ -404,5 +400,5 @@ sc_signal r_dcache_save_vaddr; // virtual address (from proc) sc_signal r_dcache_save_wdata; // write data (from proc) - sc_signal r_dcache_save_be; // byte enable (from proc) + sc_signal r_dcache_save_be; // byte enable (from proc) sc_signal r_dcache_save_paddr; // physical address sc_signal r_dcache_save_cacheable; // address cacheable @@ -425,5 +421,5 @@ sc_signal r_dcache_vci_ll_req; // atomic read request LL sc_signal r_dcache_vci_sc_req; // atomic write request SC - sc_signal r_dcache_vci_sc_data; // SC data (command) + sc_signal r_dcache_vci_sc_data; // SC data (command) // register used for XTN inval @@ -482,6 +478,9 @@ // dcache directory extension - bool *r_dcache_in_tlb; // copy exist in dtlb or itlb - bool *r_dcache_contains_ptd; // cache line contains a PTD + bool *r_dcache_in_tlb; // copy exist in dtlb or itlb + bool *r_dcache_contains_ptd; // cache line contains a PTD + + // Physical address extension for data access + sc_signal r_dcache_paddr_ext; // CP2 register (if vci_address > 32) /////////////////////////////////// @@ -489,8 +488,8 @@ /////////////////////////////////// sc_signal r_vci_cmd_fsm; - sc_signal r_vci_cmd_min; // used for write bursts - sc_signal r_vci_cmd_max; // used for write bursts - sc_signal r_vci_cmd_cpt; // used for write bursts - sc_signal r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss + sc_signal r_vci_cmd_min; // used for write bursts + sc_signal r_vci_cmd_max; // used for write bursts + sc_signal r_vci_cmd_cpt; // used for write bursts + sc_signal r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss /////////////////////////////////// @@ -501,21 +500,21 @@ sc_signal r_vci_rsp_ins_error; sc_signal r_vci_rsp_data_error; - GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM - GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM + GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM + GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM /////////////////////////////////// // CC_SEND FSM REGISTER /////////////////////////////////// - sc_signal r_cc_send_fsm; // state register - sc_signal r_cc_send_last_client; // round robin flip-flop : 0 dcache / 1 icache + sc_signal r_cc_send_fsm; // state register + sc_signal r_cc_send_last_client; // 0 dcache / 1 icache /////////////////////////////////// // CC_RECEIVE FSM REGISTER /////////////////////////////////// - sc_signal r_cc_receive_fsm; // state register - sc_signal r_cc_receive_data_ins; // request concerning : 0 dcache / 1 icache - - // communication cc updt FIFO between CC_RECEIVE FSM and ICACHE/DCACHE FSM - sc_signal r_cc_receive_word_idx; // word index + sc_signal r_cc_receive_fsm; // state register + sc_signal r_cc_receive_data_ins; // request to : 0 dcache / 1 icache + + // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM + sc_signal r_cc_receive_word_idx; // word index GenericFifo r_cc_receive_updt_fifo_be; GenericFifo r_cc_receive_updt_fifo_data; @@ -523,18 +522,18 @@ // communication between CC_RECEIVE FSM and ICACHE FSM - sc_signal r_cc_receive_icache_req; // cc_receive to icache request - sc_signal r_cc_receive_icache_type; // cc_receive type of coherence request - sc_signal r_cc_receive_icache_way; // cc_receive to icache way - sc_signal r_cc_receive_icache_set; // cc_receive to icache set + sc_signal r_cc_receive_icache_req; // cc_receive to icache request + sc_signal r_cc_receive_icache_type; // cc_receive type of request + sc_signal r_cc_receive_icache_way; // cc_receive to icache way + sc_signal r_cc_receive_icache_set; // cc_receive to icache set sc_signal r_cc_receive_icache_updt_tab_idx; // cc_receive update table index - sc_signal r_cc_receive_icache_nline; // cache line physical address + sc_signal r_cc_receive_icache_nline; // cache line physical address // communication between CC_RECEIVE FSM and DCACHE FSM - sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request - sc_signal r_cc_receive_dcache_type; // cc_receive type of coherence request - sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way - sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set + sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request + sc_signal r_cc_receive_dcache_type; // cc_receive type of request + sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way + sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set sc_signal r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index - sc_signal r_cc_receive_dcache_nline; // cache line physical address + sc_signal r_cc_receive_dcache_nline; // cache line physical address ////////////////////////////////////////////////////////////////// @@ -714,6 +713,7 @@ void print_trace(size_t mode = 0); void cache_monitor(paddr_t addr); - inline void iss_set_debug_mask(uint v) { - r_iss.set_debug_mask(v); + inline void iss_set_debug_mask(uint v) + { + r_iss.set_debug_mask(v); } Index: /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 393) +++ /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 394) @@ -34,5 +34,5 @@ #define DEBUG_DCACHE 1 #define DEBUG_ICACHE 1 -#define DEBUG_CLEANUP 1 +#define DEBUG_CMD 0 namespace soclib { @@ -464,5 +464,6 @@ << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()] - << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()]; + << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] + << " | MMU = " << r_mmu_mode.read(); if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT"; if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; @@ -499,33 +500,42 @@ ////////////////////////////////////////// { - size_t cache_way; - size_t cache_set; - size_t cache_word; - uint32_t cache_rdata; - bool cache_hit = r_dcache.read_neutral( addr, - &cache_rdata, - &cache_way, - &cache_set, - &cache_word ); - bool icache_hit = r_icache.read_neutral( addr, - &cache_rdata, - &cache_way, - &cache_set, - &cache_word ); - if ( cache_hit != m_debug_previous_hit ) - { - std::cout << "PROC " << name() - << " dcache change at cycle " << std::dec << m_cpt_total_cycles - << " for adresse " << std::hex << addr - << " / HIT = " << std::dec << cache_hit << std::endl; - m_debug_previous_hit = cache_hit; - } - if ( icache_hit != m_idebug_previous_hit ) - { - std::cout << "PROC " << name() - << " icache change at cycle " << std::dec << m_cpt_total_cycles - << " for adresse " << std::hex << addr - << " / HIT = " << icache_hit << std::endl; - m_idebug_previous_hit = icache_hit; + bool cache_hit; + size_t cache_way = 0; + size_t cache_set = 0; + size_t cache_word = 0; + uint32_t cache_rdata = 0; + + cache_hit = r_dcache.read_neutral( addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word ); + + if ( cache_hit != m_debug_previous_d_hit ) + { + std::cout << "Monitor PROC " << name() + << " DCACHE at cycle " << std::dec << m_cpt_total_cycles + << " / HIT = " << cache_hit + << " / PADDR = " << std::hex << addr + << " / DATA = " << cache_rdata + << " / WAY = " << cache_way << std::endl; + m_debug_previous_d_hit = cache_hit; + } + + cache_hit = r_icache.read_neutral( addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word ); + + if ( cache_hit != m_debug_previous_i_hit ) + { + std::cout << "Monitor PROC " << name() + << " ICACHE at cycle " << std::dec << m_cpt_total_cycles + << " / HIT = " << cache_hit + << " / PADDR = " << std::hex << addr + << " / DATA = " << cache_rdata + << " / WAY = " << cache_way << std::endl; + m_debug_previous_i_hit = cache_hit; } } @@ -681,5 +691,4 @@ ///////////////////////// { - #define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t> if ( not p_resetn.read() ) { @@ -698,4 +707,7 @@ r_cc_send_fsm = CC_SEND_IDLE; + // reset data physical address extension + r_dcache_paddr_ext = 0; + // reset dcache directory extension for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) @@ -710,4 +722,5 @@ // ICACHE & DCACHE activated + // ITLB & DTLB desactivated r_mmu_mode = 0x3; @@ -762,8 +775,7 @@ // Debug variables - m_debug_previous_hit = false; - m_idebug_previous_hit = false; - m_debug_dcache_fsm = false; - m_debug_icache_fsm = false; + m_debug_previous_i_hit = false; + m_debug_previous_d_hit = false; + m_debug_activated = false; // activity counters @@ -905,6 +917,5 @@ m_cpt_total_cycles++; - m_debug_icache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_dcache_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; ///////////////////////////////////////////////////////////////////// @@ -1157,10 +1168,7 @@ r_icache_fsm = ICACHE_MISS_SELECT; #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " READ MISS in icache" - << " : PADDR = " << std::hex << paddr << std::endl; -} +if ( m_debug_activated ) +std::cout << " READ MISS in icache" + << " : PADDR = " << std::hex << paddr << std::endl; #endif r_icache_miss_req = true; @@ -1182,10 +1190,7 @@ r_icache_fsm = ICACHE_IDLE; #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " READ HIT in icache" - << " : PADDR = " << std::hex << paddr << std::endl; -} +if ( m_debug_activated ) +std::cout << " READ HIT in icache" + << " : PADDR = " << std::hex << paddr << std::endl; #endif } @@ -1197,5 +1202,5 @@ #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) +if ( m_debug_activated ) { std::cout << " 32) + paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); } } // end physical address computation @@ -2227,14 +2235,12 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Cache update in P1 stage" << std::dec - << " / WAY = " << r_dcache_save_cache_way.read() - << " / SET = " << r_dcache_save_cache_set.read() - << " / WORD = " << r_dcache_save_cache_word.read() << std::hex - << " / DATA = " << r_dcache_save_wdata.read() - << " / BE = " << r_dcache_save_be.read() << std::endl; -} +if ( m_debug_activated ) +std::cout << " " + << " Cache update in P1 stage" << std::dec + << " / WAY = " << r_dcache_save_cache_way.read() + << " / SET = " << r_dcache_save_cache_set.read() + << " / WORD = " << r_dcache_save_cache_word.read() << std::hex + << " / WDATA = " << r_dcache_save_wdata.read() + << " / BE = " << r_dcache_save_be.read() << std::endl; #endif } // end test TLB inval @@ -2379,4 +2385,10 @@ case iss_t::XTN_MMU_WORD_HI: m_drsp.rdata = r_mmu_word_hi.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_DATA_PADDR_EXT: + m_drsp.rdata = r_dcache_paddr_ext.read(); m_drsp.valid = true; m_drsp.error = false; @@ -2503,4 +2515,10 @@ m_drsp.valid = true; r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access + r_dcache_paddr_ext = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; @@ -2568,9 +2586,7 @@ m_drsp.rdata = 0; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " HIT in dtlb, but privilege violation" << std::endl; -} +if ( m_debug_activated ) +std::cout << " " + << " HIT in dtlb, but privilege violation" << std::endl; #endif } @@ -2586,9 +2602,7 @@ m_drsp.rdata = 0; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " HIT in dtlb, but writable violation" << std::endl; -} +if ( m_debug_activated ) +std::cout << " " + << " HIT in dtlb, but writable violation" << std::endl; #endif } @@ -2607,5 +2621,5 @@ } // end DTLB activated - if ( valid_req ) // processor request is valid after TLB check + if ( valid_req ) // processor request is valid (after MMU check) { r_dcache_save_cacheable = cacheable; @@ -2631,10 +2645,8 @@ r_dcache_fsm = DCACHE_MISS_SELECT; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " READ MISS in dcache" - << " : PADDR = " << std::hex << paddr << std::endl; -} +if ( m_debug_activated ) +std::cout << " " + << " READ MISS in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; #endif } @@ -2643,4 +2655,10 @@ // stalled until cleanup is acknowledged r_dcache_fsm = DCACHE_IDLE; +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " " + << " Pending cleanup, stalled until cleanup acknowledge" + << " / PADDR = " << std::hex << paddr << std::endl; +#endif } else // cache hit @@ -2654,10 +2672,8 @@ m_drsp.rdata = cache_rdata; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " READ HIT in dcache" - << " : PADDR = " << std::hex << paddr << std::endl; -} +if ( m_debug_activated ) +std::cout << " " + << " READ HIT in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; #endif } @@ -2670,10 +2686,8 @@ r_dcache_fsm = DCACHE_UNC_WAIT; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " READ UNCACHEABLE in dcache" - << " : PADDR = " << std::hex << paddr << std::endl; -} +if ( m_debug_activated ) +std::cout << " " + << " READ UNCACHEABLE in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; #endif } @@ -2845,6 +2859,6 @@ if ( not bypass ) // Try to read PTE1/PTD1 in dcache { - pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) | - (paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2); + pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) | + ((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2); r_dcache_tlb_paddr = pte_paddr; r_dcache_fsm = DCACHE_TLB_PTE1_GET; @@ -2859,15 +2873,12 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { if ( r_dcache_tlb_ins.read() ) - { - std::cout << " ITLB miss"; - } + std::cout << " ITLB miss"; else - { - std::cout << " DTLB miss"; - } + std::cout << " DTLB miss"; std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() + << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) << " / BYPASS = " << bypass << " / PTE_ADR = " << pte_paddr << std::endl; @@ -2924,7 +2935,8 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { - std::cout << " HIT in dcache, but unmapped" + std::cout << " HIT in dcache, but unmapped" << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() << std::dec << " / way = " << way @@ -2960,7 +2972,8 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { - std::cout << " HIT in dcache" + std::cout << " HIT in dcache" << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() << std::dec << " / way = " << way @@ -2981,7 +2994,8 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { - std::cout << " HIT in dcache" + std::cout << " HIT in dcache" << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() << std::dec << " / way = " << way @@ -3007,7 +3021,8 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { - std::cout << " MISS in dcache:" + std::cout << " MISS in dcache:" << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; } @@ -3047,10 +3062,12 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { if ( r_dcache_tlb_ins.read() ) - std::cout << " Select a slot in ITLB:"; + std::cout << " Select a slot in ITLB:"; else - std::cout << " Select a slot in DTLB:"; + std::cout << " Select a slot in DTLB:"; std::cout << " way = " << std::dec << way << " / set = " << set << std::endl; @@ -3117,8 +3134,9 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { - std::cout << " write PTE1 in ITLB"; - std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() + std::cout << " write PTE1 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() << " / way = " << r_dcache_tlb_way.read() << std::endl; r_itlb.printTrace(); @@ -3140,8 +3158,9 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { - std::cout << " write PTE1 in DTLB"; - std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() + std::cout << " write PTE1 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() << " / way = " << r_dcache_tlb_way.read() << std::endl; r_dtlb.printTrace(); @@ -3156,7 +3175,8 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { - std::cout << " L/R bit update required" + std::cout << " L/R bit update required" << std::endl; } @@ -3215,5 +3235,5 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { std::cout << " Switch slot to ZOMBI state" - << " PADDR = " << std::hex << r_dcache_save_paddr.read() - << " / WAY = " << std::dec << r_dcache_miss_way.read() - << " / SET = " << r_dcache_miss_set.read() << std::endl; -} +if ( m_debug_activated ) +std::cout << " Switch slot to ZOMBI state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; #endif } @@ -4139,16 +4156,10 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Switch slot to VALID state" - << " PADDR = " << std::hex << r_dcache_save_paddr.read() - << " / WAY = " << std::dec << r_dcache_miss_way.read() - << " / SET = " << r_dcache_miss_set.read() << std::endl; - -// r_dcache.printTrace(); - - -} +if ( m_debug_activated ) +std::cout << " Switch slot to VALID state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; #endif // reset directory extension @@ -4322,5 +4333,5 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) +if ( m_debug_activated ) { std::cout << " Invalidate DTLB entry:" << std::hex - << " line = " << line << std::dec - << " / set = " << set - << " / way = " << way << std::endl; -} +if ( m_debug_activated and ok ) +std::cout << " " + << " Invalidate DTLB entry" << std::hex + << " / line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; #endif } @@ -4911,5 +4923,5 @@ case CMD_IDLE: { - // DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and + // DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and // ICACHE read requests (r_icache_miss_req) require both a write_buffer access // to check a possible pending write on the same cache line. @@ -4936,5 +4948,4 @@ or r_vci_cmd_imiss_prio.read() ); - // 1 - Data Read Miss if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) @@ -4970,6 +4981,6 @@ else if ( r_icache_unc_req.read() ) { - r_vci_cmd_fsm = CMD_INS_UNC; - r_icache_unc_req = false; + r_vci_cmd_fsm = CMD_INS_UNC; + r_icache_unc_req = false; // m_cpt_iunc_transaction++; } @@ -5000,4 +5011,14 @@ // m_cpt_cas_transaction++; } + +#if DEBUG_CMD +if ( m_debug_activated ) +{ +std::cout << " " + << " / dmiss_req = " << dcache_miss_req + << " / imiss_req = " << icache_miss_req + << std::endl; +} +#endif break; } @@ -5820,5 +5841,5 @@ - // Send coherence packets on DSPIN L2M + // Send coherence packets on DSPIN P2M // it depends on the CC_SEND FSM @@ -5857,5 +5878,5 @@ DspinDhccpParam::dspin_set(dspin_send_data, - r_dcache_cc_send_nline.read() & 0x300000000ULL, + (r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32, DspinDhccpParam::CLEANUP_NLINE_MSB); @@ -5879,5 +5900,5 @@ DspinDhccpParam::dspin_set(dspin_send_data, - r_icache_cc_send_nline.read() & 0x300000000ULL, + (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32, DspinDhccpParam::CLEANUP_NLINE_MSB);