Changeset 396
- Timestamp:
- May 28, 2013, 11:02:08 AM (12 years ago)
- Location:
- trunk/platforms/tsar_generic_xbar
- Files:
-
- 5 edited
-
top.cpp (modified) (25 diffs)
-
top.desc (modified) (1 diff)
-
tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (modified) (1 diff)
-
tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (modified) (3 diffs)
-
tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (modified) (24 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_xbar/top.cpp
r389 r396 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 // Date : august 20125 // Date : may 2013 6 6 // This program is released under the GNU public license 7 7 ///////////////////////////////////////////////////////////////////////// 8 // This file define a generic TSAR architecture with virtual memory. 9 // The physical address space is 32 bits. 8 // This file define a generic TSAR architecture. 9 // The physical address space is 40 bits. 10 // 10 11 // The number of clusters cannot be larger than 256. 11 12 // The number of processors per cluster cannot be larger than 8. … … 15 16 // - It uses the vci_cc_vcache_wrapper 16 17 // - It uses the vci_mem_cache 17 // - It contains one vci_xicu and one vci_multi_dma per cluster. 18 // - It contains one vci_simple ram per cluster to model the L3 cache. 18 // - It contains one vci_xicu per cluster. 19 // - It contains one vci_multi_dma per cluster. 20 // - It contains one vci_simple_ram per cluster to model the L3 cache. 19 21 // 20 // All clusters are identical, but the cluster containing address 21 // 0xBFC00000 (called io_cluster), contains 5 extra components: 22 // The communication between the MemCache and the Xram is 64 bits. 23 // 24 // All clusters are identical, but the cluster 0 (called io_cluster), 25 // contains 5 extra components: 22 26 // - the boot rom (BROM) 23 27 // - the disk controller (BDEV) … … 26 30 // - the frame buffer controller (FBUF) 27 31 // 28 // It is build with one single component implementing a cluster: 29 // The Tsarv4ClusterMmu component is defined in files 30 // tsar_xbar_cluster.* (with * = cpp, h, sd) 32 // It is build with one single component implementing a cluster, 33 // defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) 31 34 // 32 35 // The IRQs are connected to XICUs as follow: … … 36 39 // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. 37 40 // 38 // The main hardware parameters must be defined in the hard_config.h file : 41 // Some hardware parameters are used when compiling the OS, and are used 42 // by this top.cpp file. They must be defined in the hard_config.h file : 39 43 // - CLUSTER_X : number of clusters in a row (power of 2) 40 44 // - CLUSTER_Y : number of clusters in a column (power of 2) 41 45 // - CLUSTER_SIZE : size of the segment allocated to a cluster 42 46 // - NB_PROCS_MAX : number of processors per cluster (power of 2) 43 // - NB_DMA S_MAX: number of DMA channels per cluster (< 9)44 // - NB_TTY S : number of TTY channels in I/O cluster (< 16)45 // - NB_NIC S : number of NIC channels in I/O cluster (< 9)47 // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) 48 // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) 49 // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) 46 50 // 47 // Some secondary hardware parameters must be defined in this top.cpp file: 51 // Some other hardware parameters are not used when compiling the OS, 52 // and can be directly defined in this top.cpp file: 48 53 // - XRAM_LATENCY : external ram latency 49 54 // - MEMC_WAYS : L2 cache number of ways … … 60 65 // - NIC_TX_NAME : file pathname for NIC transmited packets 61 66 // - NIC_TIMEOUT : max number of cycles before closing a container 62 // 63 // General policy for 32bits physical address decoding:64 // All segments base addresses are multiple of 64 Kbytes65 // Therefore the 16 address MSB bits completely define the target:67 ///////////////////////////////////////////////////////////////////////// 68 // General policy for 40 bits physical address decoding: 69 // All physical segments base addresses are multiple of 1 Mbytes 70 // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) 66 71 // The (x_width + y_width) MSB bits (left aligned) define 67 // the cluster index, and the 8 LSBbits define the local index:72 // the cluster index, and the LADR bits define the local index: 68 73 // | X_ID | Y_ID |---| LADR | OFFSET | 69 // |x_width|y_width|---| 8 | 16|70 // 71 // General policy for hardware component indexing:72 // Each component is identified by (x_id, y_id,l_id) tuple.73 // | X_ID | Y_ID | L_ID |74 // |x_width|y_width| 4|74 // |x_width|y_width|---| 8 | 24 | 75 ///////////////////////////////////////////////////////////////////////// 76 // General policy for 14 bits SRCID decoding: 77 // Each component is identified by (x_id, y_id, l_id) tuple. 78 // | X_ID | Y_ID |---| L_ID | 79 // |x_width|y_width|---| 6 | 75 80 ///////////////////////////////////////////////////////////////////////// 76 81 … … 113 118 /////////////////////////////////////////////////////////// 114 119 115 #define cmd_width 40 116 #define rsp_width 33 120 #define dspin_cmd_width 40 121 #define dspin_rsp_width 33 122 123 /////////////////////////////////////////////////////////// 124 // VCI parameters 125 /////////////////////////////////////////////////////////// 126 127 #define int_vci_cell_width 4 128 #define int_vci_plen_width 8 129 #define int_vci_address_width 40 130 #define int_vci_rerror_width 1 131 #define int_vci_clen_width 1 132 #define int_vci_rflag_width 1 133 #define int_vci_srcid_width 14 134 #define int_vci_pktid_width 4 135 #define int_vci_trdid_width 4 136 #define int_vci_wrplen_width 1 137 138 #define ext_vci_cell_width 8 139 #define ext_vci_plen_width 8 140 #define ext_vci_address_width 40 141 #define ext_vci_rerror_width 1 142 #define ext_vci_clen_width 1 143 #define ext_vci_rflag_width 1 144 #define ext_vci_srcid_width 14 145 #define ext_vci_pktid_width 4 146 #define ext_vci_trdid_width 4 147 #define ext_vci_wrplen_width 1 117 148 118 149 //////////////////////////////////////////////////////////// … … 123 154 124 155 //////////////////////////////////////////////////////////// 125 // Secondary Hardware Parameters values156 // Secondary Hardware Parameters 126 157 //////////////////////i///////////////////////////////////// 127 158 … … 151 182 //////////////////////i///////////////////////////////////// 152 183 153 #define BOOT_SOFT_NAME "giet_vm/soft.elf"184 #define SOFT_NAME "giet_vm/soft.elf" 154 185 155 186 //////////////////////////////////////////////////////////// … … 159 190 #define MAX_FROZEN_CYCLES 10000 160 191 161 #define TRACE_MEMC_ID 0162 #define TRACE_PROC_ID 0192 #define TRACE_MEMC_ID 1000000 193 #define TRACE_PROC_ID 1000000 163 194 164 195 ///////////////////////////////////////////////////////// … … 172 203 // specific segments in "IO" cluster : absolute physical address 173 204 174 #define BROM_BASE 0xBFC00000175 #define BROM_SIZE 0x00100000 // 1 Mbytes176 177 #define FBUF_BASE 0xBFD00000178 #define FBUF_SIZE 0x00200000 // 2 Mbytes179 180 #define BDEV_BASE 0xBFF10000181 #define BDEV_SIZE 0x00001000 // 4 Kbytes182 183 #define MTTY_BASE 0xBFF20000184 #define MTTY_SIZE 0x00001000 // 4 Kbytes185 186 #define MNIC_BASE 0xBFF80000187 #define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes205 #define BROM_BASE 0x00BFC00000 206 #define BROM_SIZE 0x0000100000 // 1 Mbytes 207 208 #define FBUF_BASE 0x00B2000000 209 #define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE 210 211 #define BDEV_BASE 0x00B3000000 212 #define BDEV_SIZE 0x0000001000 // 4 Kbytes 213 214 #define MTTY_BASE 0x00B4000000 215 #define MTTY_SIZE 0x0000001000 // 4 Kbytes 216 217 #define MNIC_BASE 0x00B5000000 218 #define MNIC_SIZE 0x0000002000 * (NB_NIC_CHANNELS + 1) // 8 Kbytes per channel + 8 Kbytes 188 219 189 220 // replicated segments : address is incremented by a cluster offset 190 221 // offset = cluster(x,y) << (address_width-x_width-y_width); 191 222 192 #define MEMC_BASE 0x00000000193 #define MEMC_SIZE 0x00C00000 // 12 Mbytes194 195 #define XICU_BASE 0x00F00000196 #define XICU_SIZE 0x00001000 // 4 Kbytes197 198 #define CDMA_BASE 0x00F30000199 #define CDMA_SIZE 0x00001000 * NB_DMAS_MAX// 4 Kbytes per channel223 #define MEMC_BASE 0x0000000000 224 #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster 225 226 #define XICU_BASE 0x00B0000000 227 #define XICU_SIZE 0x0000001000 // 4 Kbytes 228 229 #define MDMA_BASE 0x00B1000000 230 #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel 200 231 201 232 //////////////////////////////////////////////////////////////////// … … 204 235 //////////////////////////////////////////////////////////////////// 205 236 206 #define MEMC_TGTID 207 #define XICU_TGTID 208 #define CDMA_TGTID2209 #define MTTY_TGTID 210 #define FBUF_TGTID 211 #define B ROM_TGTID5212 #define BDEV_TGTID6213 #define MNIC_TGTID7237 #define MEMC_TGTID 0 238 #define XICU_TGTID 1 239 #define MDMA_TGTID 2 240 #define MTTY_TGTID 3 241 #define FBUF_TGTID 4 242 #define BDEV_TGTID 5 243 #define MNIC_TGTID 6 244 #define BROM_TGTID 7 214 245 215 246 ///////////////////////////////// … … 221 252 222 253 223 char soft_name[256] = BOOT_SOFT_NAME;// pathname to binary code254 char soft_name[256] = SOFT_NAME; // pathname to binary code 224 255 size_t ncycles = 1000000000; // simulated cycles 225 256 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image … … 229 260 bool debug_ok = false; // trace activated 230 261 size_t debug_period = 1; // trace period 231 size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id)262 size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced 232 263 size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced 233 264 uint32_t debug_from = 0; // trace start cycle 234 265 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 266 size_t cluster_io_id = 0; // index of cluster containing IOs 235 267 236 268 ////////////// command line arguments ////////////////////// … … 300 332 } 301 333 302 // checking hardware parameters 303 assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or 304 (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and 305 "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" ); 306 307 assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or 308 (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and 309 "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" ); 310 311 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or 312 (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and 313 "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); 314 315 assert( (NB_DMAS_MAX < 9) and 316 "The NB_DMAS_MAX parameter must be smaller than 9" ); 317 318 assert( (NB_TTYS < 15) and 319 "The NB_TTYS parameter must be smaller than 15" ); 320 321 assert( (NB_NICS < 9) and 322 "The NB_NICS parameter must be smaller than 9" ); 323 324 std::cout << std::endl; 325 std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl; 326 std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl; 327 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 328 std::cout << " - NB_DMAS_MAX = " << NB_DMAS_MAX << std::endl; 329 std::cout << " - NB_TTYS = " << NB_TTYS << std::endl; 330 std::cout << " - NB_NICS = " << NB_NICS << std::endl; 331 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 332 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; 333 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 334 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 335 336 std::cout << std::endl; 334 // checking hardware parameters 335 assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or 336 (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and 337 "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" ); 338 339 assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or 340 (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and 341 "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" ); 342 343 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or 344 (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and 345 "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); 346 347 assert( (NB_DMA_CHANNELS < 9) and 348 "The NB_DMA_CHANNELS parameter must be smaller than 9" ); 349 350 assert( (NB_TTY_CHANNELS < 15) and 351 "The NB_TTY_CHANNELS parameter must be smaller than 15" ); 352 353 assert( (NB_NIC_CHANNELS < 9) and 354 "The NB_NIC_CHANNELS parameter must be smaller than 9" ); 355 356 assert( (int_vci_address_width == ext_vci_address_width) and 357 "address widths must be equal on internal & external networks" ); 358 359 assert( (int_vci_address_width == 40) and 360 "VCI address width must be 40 bits" ); 361 362 std::cout << std::endl; 363 std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl; 364 std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl; 365 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 366 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; 367 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; 368 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; 369 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 370 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; 371 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 372 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 373 374 std::cout << std::endl; 375 376 // Internal and External VCI parameters definition 377 typedef soclib::caba::VciParams<int_vci_cell_width, 378 int_vci_plen_width, 379 int_vci_address_width, 380 int_vci_rerror_width, 381 int_vci_clen_width, 382 int_vci_rflag_width, 383 int_vci_srcid_width, 384 int_vci_pktid_width, 385 int_vci_trdid_width, 386 int_vci_wrplen_width> vci_param_int; 387 388 typedef soclib::caba::VciParamsBis<ext_vci_cell_width, 389 ext_vci_plen_width, 390 ext_vci_address_width, 391 ext_vci_rerror_width, 392 ext_vci_clen_width, 393 ext_vci_rflag_width, 394 ext_vci_srcid_width, 395 ext_vci_pktid_width, 396 ext_vci_trdid_width, 397 ext_vci_wrplen_width> vci_param_ext; 337 398 338 399 #if USE_OPENMP … … 343 404 344 405 // Define parameters depending on mesh size 345 size_t cluster_io_id;346 406 size_t x_width; 347 407 size_t y_width; … … 359 419 else y_width = 4; 360 420 361 cluster_io_id = 0xBF >> (8 - x_width - y_width);362 363 421 ///////////////////// 364 422 // Mapping Tables 365 423 ///////////////////// 366 424 367 // directnetwork368 MappingTable maptabd( address_width,369 IntTab(x_width + y_width, 16 - x_width - y_width),370 IntTab(x_width + y_width,srcid_width - x_width - y_width),371 0x00FF0000);425 // internal network 426 MappingTable maptabd(int_vci_address_width, 427 IntTab(x_width + y_width, 16 - x_width - y_width), 428 IntTab(x_width + y_width, int_vci_srcid_width - x_width - y_width), 429 0x00FF000000); 372 430 373 431 for (size_t x = 0; x < CLUSTER_X; x++) … … 375 433 for (size_t y = 0; y < CLUSTER_Y; y++) 376 434 { 377 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 435 sc_uint<int_vci_address_width> offset; 436 offset = (sc_uint<int_vci_address_width>)cluster(x,y) 437 << (int_vci_address_width-x_width-y_width); 378 438 379 439 std::ostringstream sh; 380 sh << "d_seg_memc_" << x << "_" << y; 381 maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); 440 sh << "seg_memc_" << x << "_" << y; 441 maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, 442 IntTab(cluster(x,y),MEMC_TGTID), true)); 382 443 383 444 std::ostringstream si; 384 si << "d_seg_xicu_" << x << "_" << y; 385 maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); 445 si << "seg_xicu_" << x << "_" << y; 446 maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, 447 IntTab(cluster(x,y),XICU_TGTID), false)); 386 448 387 449 std::ostringstream sd; 388 sd << "d_seg_mdma_" << x << "_" << y; 389 maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); 450 sd << "seg_mdma_" << x << "_" << y; 451 maptabd.add(Segment(sd.str(), MDMA_BASE+offset, MDMA_SIZE, 452 IntTab(cluster(x,y),MDMA_TGTID), false)); 390 453 391 454 if ( cluster(x,y) == cluster_io_id ) 392 455 { 393 maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); 394 maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); 395 maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); 396 maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false)); 397 maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); 456 maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, 457 IntTab(cluster(x,y),MTTY_TGTID), false)); 458 maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, 459 IntTab(cluster(x,y),FBUF_TGTID), false)); 460 maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, 461 IntTab(cluster(x,y),BDEV_TGTID), false)); 462 maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, 463 IntTab(cluster(x,y),MNIC_TGTID), false)); 464 maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, 465 IntTab(cluster(x,y),BROM_TGTID), true)); 398 466 } 399 467 } … … 402 470 403 471 // external network 404 MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); 472 MappingTable maptabx(ext_vci_address_width, 473 IntTab(x_width+y_width), 474 IntTab(x_width+y_width), 475 0xFFFF000000ULL); 405 476 406 477 for (size_t x = 0; x < CLUSTER_X; x++) … … 408 479 for (size_t y = 0; y < CLUSTER_Y ; y++) 409 480 { 410 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 481 482 sc_uint<ext_vci_address_width> offset; 483 offset = (sc_uint<ext_vci_address_width>)cluster(x,y) 484 << (ext_vci_address_width-x_width-y_width); 485 411 486 std::ostringstream sh; 412 487 sh << "x_seg_memc_" << x << "_" << y; 488 413 489 maptabx.add(Segment(sh.str(), MEMC_BASE+offset, 414 490 MEMC_SIZE, IntTab(cluster(x,y)), false)); … … 425 501 426 502 // Horizontal inter-clusters DSPIN signals 427 DspinSignals< cmd_width>*** signal_dspin_h_cmd_inc =428 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2);429 DspinSignals< cmd_width>*** signal_dspin_h_cmd_dec =430 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2);431 DspinSignals< rsp_width>*** signal_dspin_h_rsp_inc =432 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2);433 DspinSignals< rsp_width>*** signal_dspin_h_rsp_dec =434 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2);503 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc = 504 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2); 505 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec = 506 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2); 507 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc = 508 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2); 509 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec = 510 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2); 435 511 436 512 // Vertical inter-clusters DSPIN signals 437 DspinSignals< cmd_width>*** signal_dspin_v_cmd_inc =438 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2);439 DspinSignals< cmd_width>*** signal_dspin_v_cmd_dec =440 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2);441 DspinSignals< rsp_width>*** signal_dspin_v_rsp_inc =442 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2);443 DspinSignals< rsp_width>*** signal_dspin_v_rsp_dec =444 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2);513 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc = 514 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2); 515 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec = 516 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2); 517 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc = 518 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2); 519 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec = 520 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2); 445 521 446 522 // Mesh boundaries DSPIN signals 447 DspinSignals< cmd_width>**** signal_dspin_false_cmd_in =448 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4);449 DspinSignals< cmd_width>**** signal_dspin_false_cmd_out =450 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4);451 DspinSignals< rsp_width>**** signal_dspin_false_rsp_in =452 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4);453 DspinSignals< rsp_width>**** signal_dspin_false_rsp_out =454 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4);523 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in = 524 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4); 525 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out = 526 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4); 527 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in = 528 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4); 529 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out = 530 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4); 455 531 456 532 … … 474 550 //////////////////////////// 475 551 476 TsarXbarCluster< 477 proc_iss, cmd_width, rsp_width 478 > * clusters[CLUSTER_X][CLUSTER_Y]; 552 TsarXbarCluster<dspin_cmd_width, 553 dspin_rsp_width, 554 vci_param_int, 555 vci_param_ext>* clusters[CLUSTER_X][CLUSTER_Y]; 479 556 480 557 #if USE_OPENMP … … 496 573 std::ostringstream sc; 497 574 sc << "cluster_" << x << "_" << y; 498 clusters[x][y] = new TsarXbarCluster< 499 proc_iss, cmd_width, rsp_width 500 > 575 clusters[x][y] = new TsarXbarCluster<dspin_cmd_width, 576 dspin_rsp_width, 577 vci_param_int, 578 vci_param_ext> 501 579 ( 502 580 sc.str().c_str(), 503 NB_PROCS_MAX , NB_TTYS , NB_DMAS_MAX , // cluster params 504 x , y , cluster(x,y), // mesh coordinates 505 maptabd , maptabx , // mapping tables 506 x_width , y_width , srcid_width - x_width - y_width, // srcid width, 507 MEMC_TGTID , XICU_TGTID , CDMA_TGTID , // 508 FBUF_TGTID , MTTY_TGTID , BROM_TGTID , // targets ids 509 MNIC_TGTID , BDEV_TGTID, // 510 MEMC_WAYS , MEMC_SETS , // MC params 511 L1_IWAYS , L1_ISETS , L1_DWAYS , L1_DSETS, // L1 params 512 XRAM_LATENCY , // 513 is_io_cluster, // is IO cluster ? 514 FBUF_X_SIZE , FBUF_Y_SIZE , // FB params 515 disk_name , BDEV_SECTOR_SIZE, // IOC params 516 NB_NICS , nic_rx_name , nic_tx_name , NIC_TIMEOUT, // NIC params 517 loader , 581 <<<<<<< .mine 582 NB_PROCS_MAX, 583 NB_TTY_CHANNELS, 584 NB_DMA_CHANNELS, 585 x, 586 y, 587 cluster(x,y), 588 maptabd, 589 maptabx, 590 x_width, 591 y_width, 592 int_vci_srcid_width - x_width - y_width, // l_id width, 593 MEMC_TGTID, 594 XICU_TGTID, 595 MDMA_TGTID, 596 FBUF_TGTID, 597 MTTY_TGTID, 598 BROM_TGTID, 599 MNIC_TGTID, 600 BDEV_TGTID, 601 MEMC_WAYS, 602 MEMC_SETS, 603 L1_IWAYS, 604 L1_ISETS, 605 L1_DWAYS, 606 L1_DSETS, 607 XRAM_LATENCY, 608 (cluster(x,y) == cluster_io_id), 609 FBUF_X_SIZE, 610 FBUF_Y_SIZE, 611 disk_name, 612 BDEV_SECTOR_SIZE, 613 NB_NIC_CHANNELS, 614 nic_rx_name, 615 nic_tx_name, 616 NIC_TIMEOUT, 617 loader, 518 618 frozen_cycles, 519 619 debug_from , … … 617 717 } 618 718 } 719 std::cout << "North, South, West, East connections established" << std::endl; 720 std::cout << std::endl; 619 721 620 722 … … 650 752 for (size_t n = 1; n < ncycles; n++) 651 753 { 754 // Monitor a specific address for L1 & L2 caches 755 //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); 756 //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); 757 652 758 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 653 759 { 654 760 std::cout << "****************** cycle " << std::dec << n ; 655 761 std::cout << " ************************************************" << std::endl; 656 /* 657 clusters[0][0]->proc[0]->print_trace(); 658 clusters[0][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_0_0 vci_ini"); 659 clusters[0][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_0_0"); 660 clusters[0][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_0_0"); 661 clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_0_0"); 662 clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_0_0"); 663 clusters[0][0]->memc->print_trace(); 664 clusters[0][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_0_vci_tgt"); 665 clusters[0][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_0"); 666 clusters[0][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_0"); 667 clusters[0][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_0"); 668 clusters[0][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_0"); 669 clusters[0][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_0"); 670 clusters[0][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_0"); 671 clusters[0][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_0"); 672 673 clusters[0][1]->proc[0]->print_trace(); 674 clusters[0][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_1_0 vci_ini"); 675 clusters[0][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_1_0"); 676 clusters[0][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_1_0"); 677 clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_1_0"); 678 clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_1_0"); 679 clusters[0][1]->memc->print_trace(); 680 clusters[0][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_1_vci_tgt"); 681 clusters[0][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_1"); 682 clusters[0][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_1"); 683 clusters[0][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_1"); 684 clusters[0][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_1"); 685 clusters[0][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_1"); 686 clusters[0][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_1"); 687 clusters[0][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_1"); 688 689 clusters[1][0]->proc[0]->print_trace(); 690 clusters[1][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_0_0 vci_ini"); 691 clusters[1][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_0_0"); 692 clusters[1][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_0_0"); 693 clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_0_0"); 694 clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_0_0"); 695 clusters[1][0]->memc->print_trace(); 696 clusters[1][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_0_vci_tgt"); 697 clusters[1][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_0"); 698 clusters[1][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_0"); 699 clusters[1][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_0"); 700 clusters[1][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_0"); 701 clusters[1][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_0"); 702 clusters[1][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_0"); 703 clusters[1][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_0"); 704 705 clusters[1][1]->proc[0]->print_trace(); 706 clusters[1][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_1_0 vci_ini"); 707 clusters[1][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_1_0"); 708 clusters[1][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_1_0"); 709 clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_1_0"); 710 clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_1_0"); 711 clusters[1][1]->memc->print_trace(); 712 clusters[1][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_1_vci_tgt"); 713 clusters[1][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_1"); 714 clusters[1][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_1"); 715 clusters[1][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_1"); 716 clusters[1][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_1"); 717 clusters[1][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_1"); 718 clusters[1][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_1"); 719 clusters[1][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_1"); 720 */ 762 721 763 // trace proc[debug_proc_id] 722 764 if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) 723 765 { 724 size_t l = debug_proc_id % (CLUSTER_X * CLUSTER_Y);766 size_t l = debug_proc_id % NB_PROCS_MAX ; 725 767 size_t y = (debug_proc_id / NB_PROCS_MAX) % CLUSTER_Y ; 726 768 size_t x = debug_proc_id / (CLUSTER_Y * NB_PROCS_MAX) ; 727 769 728 std::ostringstream signame; 729 signame << "VCI signal PROC_" << x << "_" << y << "_" << l; 770 std::ostringstream vci_signame; 771 vci_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 772 std::ostringstream p2m_signame; 773 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 774 std::ostringstream m2p_signame; 775 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 730 776 731 777 clusters[x][y]->proc[l]->print_trace(); 732 clusters[x][y]->signal_vci_ini_proc[l].print_trace("signame"); 778 clusters[x][y]->signal_vci_ini_proc[l].print_trace(vci_signame.str()); 779 clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 780 clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 733 781 } 734 /*735 782 // trace memc[debug_memc_id] 736 783 if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) … … 739 786 size_t y = debug_memc_id % CLUSTER_Y; 740 787 741 std::ostringstream signame; 742 signame << "VCI signal MEMC_" << x << "_" << y; 743 744 clusters[memc_x][memc_y]->memc->print_trace(); 745 clusters[memc_x][memc_y]->signal_vci_tgt_memc.print_trace("signame"); 788 std::ostringstream smemc; 789 smemc << "[SIG]MEMC_" << x << "_" << y; 790 std::ostringstream sxram; 791 sxram << "[SIG]XRAM_" << x << "_" << y; 792 std::ostringstream sm2p; 793 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; 794 std::ostringstream sp2m; 795 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; 796 797 clusters[x][y]->memc->print_trace(); 798 clusters[x][y]->xram->print_trace(); 799 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 800 clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 801 clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); 802 clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); 746 803 } 747 */ 804 805 // trace replicated peripherals 806 clusters[1][1]->mdma->print_trace(); 807 clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); 808 clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); 809 810 748 811 // trace external peripherals 749 812 size_t io_x = cluster_io_id / CLUSTER_Y; 750 813 size_t io_y = cluster_io_id % CLUSTER_Y; 751 814 752 clusters[io_x][io_y]->signal_vci_tgt_mtty.print_trace("VCI signal TTY"); 753 /* 815 // clusters[io_x][io_y]->brom->print_trace(); 816 // clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("/SIG/BROM"); 817 // clusters[io_x][io_y]->signal_vci_tgt_mtty.print_trace("VCI signal TTY"); 818 754 819 clusters[io_x][io_y]->bdev->print_trace(); 755 clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("VCI signal BDEV_TGT"); 756 clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("VCI signal BDEV_INI"); 757 */ 820 clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 821 clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 758 822 } 759 823 -
trunk/platforms/tsar_generic_xbar/top.desc
r389 r396 2 2 # -*- python -*- 3 3 4 # internal VCI parameters values 5 int_vci_cell_size = 4 6 int_vci_plen_size = 8 7 int_vci_addr_size = 40 8 int_vci_rerror_size = 1 9 int_vci_clen_size = 1 10 int_vci_rflag_size = 1 11 int_vci_srcid_size = 14 12 int_vci_pktid_size = 4 13 int_vci_trdid_size = 4 14 int_vci_wrplen_size = 1 15 16 # external VCI parameters values 17 ext_vci_cell_size = 8 18 ext_vci_plen_size = 8 19 ext_vci_addr_size = 40 20 ext_vci_rerror_size = 1 21 ext_vci_clen_size = 1 22 ext_vci_rflag_size = 1 23 ext_vci_srcid_size = 14 24 ext_vci_pktid_size = 4 25 ext_vci_trdid_size = 4 26 ext_vci_wrplen_size = 1 27 28 # DSPIN network parameters values 29 dspin_cmd_flit_size = 40 30 dspin_rsp_flit_size = 33 31 4 32 todo = Platform('caba', 'top.cpp', 5 uses = [ 33 34 uses = [ 6 35 Uses('caba:tsar_xbar_cluster', 7 iss_t = 'common:gdb_iss', 8 gdb_iss_t = 'common:mips32el', 9 cmd_width = 40, 10 rsp_width = 33 11 ), 12 Uses('common:elf_file_loader'), 36 dspin_cmd_width = dspin_cmd_flit_size, 37 dspin_rsp_width = dspin_rsp_flit_size, 38 39 vci_param_int = 'caba:vci_param', 40 41 cell_size = int_vci_cell_size, 42 plen_size = int_vci_plen_size, 43 addr_size = int_vci_addr_size, 44 rerror_size = int_vci_rerror_size, 45 clen_size = int_vci_clen_size, 46 rflag_size = int_vci_rflag_size, 47 srcid_size = int_vci_srcid_size, 48 pktid_size = int_vci_pktid_size, 49 trdid_size = int_vci_trdid_size, 50 wrplen_size = int_vci_wrplen_size, 51 52 vci_param_ext = 'caba:vci_param_bis', 53 54 cell_size_bis = ext_vci_cell_size, 55 plen_size_bis = ext_vci_plen_size, 56 addr_size_bis = ext_vci_addr_size, 57 rerror_size_bis = ext_vci_rerror_size, 58 clen_size_bis = ext_vci_clen_size, 59 rflag_size_bis = ext_vci_rflag_size, 60 srcid_size_bis = ext_vci_srcid_size, 61 pktid_size_bis = ext_vci_pktid_size, 62 trdid_size_bis = ext_vci_trdid_size, 63 wrplen_size_bis = ext_vci_wrplen_size), 64 65 Uses('common:elf_file_loader'), 13 66 Uses('common:plain_file_loader'), 14 ], 15 cell_size_bis = 8, 16 plen_size_bis = 8, 17 addr_size_bis = 32, 18 rerror_size_bis = 2, 19 clen_size_bis = 1, 20 rflag_size_bis = 1, 21 srcid_size_bis = 14, 22 pktid_size_bis = 4, 23 trdid_size_bis = 4, 24 wrplen_size_bis = 1, 25 26 cell_size = 4, 27 plen_size = 8, 28 addr_size = 32, 29 rerror_size = 2, 30 clen_size = 1, 31 rflag_size = 1, 32 srcid_size = 14, 33 pktid_size = 4, 34 trdid_size = 4, 35 wrplen_size = 1, 67 ], 36 68 ) -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd
r389 r396 2 2 # -*- python -*- 3 3 4 Module('caba:tsar_xbar_cluster', 4 Module('caba:tsar_xbar_cluster', 5 5 classname = 'soclib::caba::TsarXbarCluster', 6 tmpl_parameters = [ 7 parameter.Module('iss_t'), 8 parameter.Int('cmd_width'), 9 parameter.Int('rsp_width'), 6 tmpl_parameters = [ 7 parameter.Int('dspin_cmd_width'), 8 parameter.Int('dspin_rsp_width'), 9 parameter.Module('vci_param_int'), 10 parameter.Module('vci_param_ext'), 10 11 ], 11 header_files = [ '../source/include/tsar_xbar_cluster.h', ], 12 implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], 13 uses = [ 14 Uses('caba:base_module'), 15 Uses('common:mapping_table'), 16 Uses('common:iss2'), 17 Uses('caba:vci_cc_vcache_wrapper', 18 vci_param = 'caba:vci_param', 19 dspin_in_width = parameter.Reference('cmd_width'), 20 dspin_out_width = parameter.Reference('rsp_width'), 12 13 header_files = [ '../source/include/tsar_xbar_cluster.h', ], 14 implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], 15 16 uses = [ 17 Uses('caba:base_module'), 18 Uses('common:mapping_table'), 19 Uses('common:iss2'), 20 21 Uses('caba:vci_cc_vcache_wrapper', 22 vci_param = parameter.Reference('vci_param_int'), 23 dspin_in_width = parameter.Reference('dspin_cmd_width'), 24 dspin_out_width = parameter.Reference('dspin_rsp_width'), 21 25 iss_t = 'common:gdb_iss', 22 gdb_iss_t = 'common:mips32el' 23 ), 24 Uses('caba:vci_mem_cache', 26 gdb_iss_t = 'common:mips32el'), 27 28 Uses('caba:vci_simple_ram', 29 vci_param = parameter.Reference('vci_param_int')), 30 31 Uses('caba:vci_simple_ram', 32 vci_param = parameter.Reference('vci_param_ext')), 33 34 Uses('caba:vci_xicu', 35 vci_param = parameter.Reference('vci_param_int')), 36 37 Uses('caba:dspin_local_crossbar', 38 flit_width = parameter.Reference('dspin_cmd_width')), 39 40 Uses('caba:dspin_local_crossbar', 41 flit_width = parameter.Reference('dspin_rsp_width')), 42 43 Uses('caba:virtual_dspin_router', 44 flit_width = parameter.Reference('dspin_cmd_width')), 45 46 Uses('caba:virtual_dspin_router', 47 flit_width = parameter.Reference('dspin_rsp_width')), 48 49 Uses('caba:vci_multi_tty', 50 vci_param = parameter.Reference('vci_param_int')), 51 52 Uses('caba:vci_framebuffer', 53 vci_param = parameter.Reference('vci_param_int')), 54 55 Uses('caba:vci_multi_nic', 56 vci_param = parameter.Reference('vci_param_int')), 57 58 Uses('caba:vci_block_device_tsar', 59 vci_param = parameter.Reference('vci_param_int')), 60 61 Uses('caba:vci_multi_dma', 62 vci_param = parameter.Reference('vci_param_int')), 63 64 Uses('caba:vci_dspin_target_wrapper', 65 vci_param = parameter.Reference('vci_param_int')), 66 67 Uses('caba:vci_dspin_initiator_wrapper', 68 vci_param = parameter.Reference('vci_param_int')), 69 70 Uses('caba:vci_mem_cache', 25 71 vci_param_int = 'caba:vci_param', 26 72 vci_param_ext = 'caba:vci_param_bis', 27 dspin_in_width = parameter.Reference('rsp_width'), 28 dspin_out_width = parameter.Reference('cmd_width') 29 ), 30 Uses('caba:vci_simple_ram', 31 vci_param = 'caba:vci_param_bis' 32 ), 33 Uses('caba:vci_simple_ram', 34 vci_param = 'caba:vci_param' 35 ), 36 Uses('caba:vci_xicu'), 37 Uses('caba:dspin_local_crossbar', 38 flit_width = parameter.Reference('cmd_width') 39 ), 40 Uses('caba:dspin_local_crossbar', 41 flit_width = parameter.Reference('rsp_width') 42 ), 43 Uses('caba:vci_dspin_initiator_wrapper', 44 dspin_cmd_width = parameter.Reference('cmd_width'), 45 dspin_rsp_width = parameter.Reference('rsp_width') 46 ), 47 Uses('caba:vci_dspin_target_wrapper', 48 dspin_cmd_width = parameter.Reference('cmd_width'), 49 dspin_rsp_width = parameter.Reference('rsp_width') 50 ), 51 Uses('caba:virtual_dspin_router', 52 flit_width = parameter.Reference('cmd_width') 53 ), 54 Uses('caba:virtual_dspin_router', 55 flit_width = parameter.Reference('rsp_width') 56 ), 57 Uses('caba:vci_multi_tty'), 58 Uses('caba:vci_framebuffer'), 59 Uses('caba:vci_multi_nic'), 60 Uses('caba:vci_block_device_tsar'), 61 Uses('caba:vci_multi_dma'), 62 Uses('common:elf_file_loader'), 63 ], 64 ports = [ 65 Port('caba:bit_in' , 'p_resetn' , auto = 'resetn'), 66 Port('caba:clock_in' , 'p_clk' , auto = 'clock'), 67 Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 68 Port('caba:dspin_input' , 'p_cmd_in' , [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 69 Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 70 Port('caba:dspin_input' , 'p_rsp_in' , [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 71 ], 73 dspin_in_width = parameter.Reference('dspin_rsp_width'), 74 dspin_out_width = parameter.Reference('dspin_cmd_width')), 75 76 Uses('common:elf_file_loader'), 77 ], 78 79 ports = [ 80 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), 81 Port('caba:clock_in', 'p_clk', auto = 'clock'), 82 Port('caba:dspin_output', 'p_cmd_out', [2, 4], 83 dspin_data_size = parameter.Reference('dspin_cmd_width')), 84 Port('caba:dspin_input', 'p_cmd_in', [2, 4], 85 dspin_data_size = parameter.Reference('dspin_cmd_width')), 86 Port('caba:dspin_output', 'p_rsp_out', [2, 4], 87 dspin_data_size = parameter.Reference('dspin_rsp_width')), 88 Port('caba:dspin_input', 'p_rsp_in', [2, 4], 89 dspin_data_size = parameter.Reference('dspin_rsp_width')), 90 ], 72 91 ) 73 92 -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
r389 r396 1 1 ////////////////////////////////////////////////////////////////////////////// 2 // File: tsar_xbar_cluster _mmu.h2 // File: tsar_xbar_cluster.h 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 // Date : march 201 15 // Date : march 2013 6 6 // This program is released under the GNU public license 7 7 ////////////////////////////////////////////////////////////////////////////// … … 34 34 #include "vci_cc_vcache_wrapper.h" 35 35 36 ///////////////////////////////////////////////////////////37 // VCI parameters for DIRECT network38 ///////////////////////////////////////////////////////////39 #define cell_width 440 #define address_width 3241 #define plen_width 842 #define error_width 243 #define clen_width 144 #define rflag_width 145 #define srcid_width 1446 #define pktid_width 447 #define trdid_width 448 #define wrplen_width 149 50 ///////////////////////////////////////////////////////////51 // VCI parameters for EXTERNAL network52 ///////////////////////////////////////////////////////////53 #define cell_width_ext 854 #define address_width_ext address_width55 #define plen_width_ext plen_width56 #define error_width_ext error_width57 #define clen_width_ext clen_width58 #define rflag_width_ext rflag_width59 #define srcid_width_ext srcid_width60 #define pktid_width_ext pktid_width61 #define trdid_width_ext trdid_width62 #define wrplen_width_ext wrplen_width63 64 36 namespace soclib { namespace caba { 65 37 66 38 /////////////////////////////////////////////////////////////////////////// 67 template< 68 typename iss_t, int cmd_width, int rsp_width69 >70 class TsarXbarCluster39 template<size_t dspin_cmd_width, 40 size_t dspin_rsp_width, 41 typename vci_param_int, 42 typename vci_param_ext> class TsarXbarCluster 71 43 /////////////////////////////////////////////////////////////////////////// 72 44 : public soclib::caba::BaseModule 73 45 { 74 // Define VCI parameters 75 typedef soclib::caba::VciParams<cell_width, 76 plen_width, 77 address_width, 78 error_width, 79 clen_width, 80 rflag_width, 81 srcid_width, 82 pktid_width, 83 trdid_width, 84 wrplen_width> vci_param_d; 85 86 typedef soclib::caba::VciParamsBis<cell_width_ext, 87 plen_width_ext, 88 address_width_ext, 89 error_width_ext, 90 clen_width_ext, 91 rflag_width_ext, 92 srcid_width_ext, 93 pktid_width_ext, 94 trdid_width_ext, 95 wrplen_width_ext> vci_param_x; 96 97 public: 98 99 // Ports 100 sc_in<bool> p_clk; 101 sc_in<bool> p_resetn; 102 soclib::caba::DspinOutput<cmd_width> **p_cmd_out; 103 soclib::caba::DspinInput<cmd_width> **p_cmd_in; 104 soclib::caba::DspinOutput<rsp_width> **p_rsp_out; 105 soclib::caba::DspinInput<rsp_width> **p_rsp_in; 46 public: 47 48 // Ports 49 sc_in<bool> p_clk; 50 sc_in<bool> p_resetn; 51 soclib::caba::DspinOutput<dspin_cmd_width> **p_cmd_out; 52 soclib::caba::DspinInput<dspin_cmd_width> **p_cmd_in; 53 soclib::caba::DspinOutput<dspin_rsp_width> **p_rsp_out; 54 soclib::caba::DspinInput<dspin_rsp_width> **p_rsp_in; 106 55 107 56 // interrupt signals 108 sc_signal<bool>signal_false;109 sc_signal<bool>signal_proc_it[8];110 sc_signal<bool>signal_irq_mdma[8];111 sc_signal<bool>signal_irq_mtty[23];112 sc_signal<bool> signal_irq_mnic_rx[8];// unused113 sc_signal<bool> signal_irq_mnic_tx[8];// unused114 sc_signal<bool>signal_irq_bdev;115 116 117 DspinSignals<cmd_width>signal_dspin_cmd_l2g_d;118 DspinSignals<cmd_width>signal_dspin_cmd_g2l_d;119 DspinSignals<cmd_width>signal_dspin_m2p_l2g_c;120 DspinSignals<cmd_width>signal_dspin_m2p_g2l_c;121 DspinSignals<rsp_width>signal_dspin_rsp_l2g_d;122 DspinSignals<rsp_width>signal_dspin_rsp_g2l_d;123 DspinSignals<rsp_width>signal_dspin_p2m_l2g_c;124 DspinSignals<rsp_width>signal_dspin_p2m_g2l_c;125 126 127 VciSignals<vci_param_d>signal_vci_ini_proc[8];128 VciSignals<vci_param_d>signal_vci_ini_mdma;129 VciSignals<vci_param_d>signal_vci_ini_bdev;130 131 VciSignals<vci_param_d>signal_vci_tgt_memc;132 VciSignals<vci_param_d>signal_vci_tgt_xicu;133 VciSignals<vci_param_d>signal_vci_tgt_mdma;134 VciSignals<vci_param_d>signal_vci_tgt_mtty;135 VciSignals<vci_param_d>signal_vci_tgt_bdev;136 VciSignals<vci_param_d>signal_vci_tgt_brom;137 VciSignals<vci_param_d>signal_vci_tgt_fbuf;138 VciSignals<vci_param_d>signal_vci_tgt_mnic;139 140 141 DspinSignals<cmd_width> signal_dspin_cmd_proc_i[8];142 DspinSignals<rsp_width> signal_dspin_rsp_proc_i[8];143 DspinSignals<cmd_width> signal_dspin_cmd_mdma_i;144 DspinSignals<rsp_width> signal_dspin_rsp_mdma_i;145 DspinSignals<cmd_width> signal_dspin_cmd_bdev_i;146 DspinSignals<rsp_width> signal_dspin_rsp_bdev_i;147 148 DspinSignals<cmd_width> signal_dspin_cmd_memc_t;149 DspinSignals<rsp_width> signal_dspin_rsp_memc_t;150 DspinSignals<cmd_width> signal_dspin_cmd_xicu_t;151 DspinSignals<rsp_width> signal_dspin_rsp_xicu_t;152 DspinSignals<cmd_width> signal_dspin_cmd_mdma_t;153 DspinSignals<rsp_width> signal_dspin_rsp_mdma_t;154 DspinSignals<cmd_width> signal_dspin_cmd_mtty_t;155 DspinSignals<rsp_width> signal_dspin_rsp_mtty_t;156 DspinSignals<cmd_width> signal_dspin_cmd_bdev_t;157 DspinSignals<rsp_width> signal_dspin_rsp_bdev_t;158 DspinSignals<cmd_width> signal_dspin_cmd_brom_t;159 DspinSignals<rsp_width> signal_dspin_rsp_brom_t;160 DspinSignals<cmd_width> signal_dspin_cmd_fbuf_t;161 DspinSignals<rsp_width> signal_dspin_rsp_fbuf_t;162 DspinSignals<cmd_width> signal_dspin_cmd_mnic_t;163 DspinSignals<rsp_width> signal_dspin_rsp_mnic_t;164 165 166 DspinSignals<cmd_width> signal_dspin_m2p_memc;167 DspinSignals<rsp_width> signal_dspin_p2m_memc;168 DspinSignals<cmd_width> signal_dspin_m2p_proc[8];169 DspinSignals<rsp_width> signal_dspin_p2m_proc[8];170 171 // external RAMVCI signal172 VciSignals<vci_param_x>signal_vci_xram;173 57 sc_signal<bool> signal_false; 58 sc_signal<bool> signal_proc_it[8]; 59 sc_signal<bool> signal_irq_mdma[8]; 60 sc_signal<bool> signal_irq_mtty[23]; 61 sc_signal<bool> signal_irq_mnic_rx[8]; // unused 62 sc_signal<bool> signal_irq_mnic_tx[8]; // unused 63 sc_signal<bool> signal_irq_bdev; 64 65 // DSPIN signals between DSPIN routers and local_crossbars 66 DspinSignals<dspin_cmd_width> signal_dspin_cmd_l2g_d; 67 DspinSignals<dspin_cmd_width> signal_dspin_cmd_g2l_d; 68 DspinSignals<dspin_cmd_width> signal_dspin_m2p_l2g_c; 69 DspinSignals<dspin_cmd_width> signal_dspin_m2p_g2l_c; 70 DspinSignals<dspin_rsp_width> signal_dspin_rsp_l2g_d; 71 DspinSignals<dspin_rsp_width> signal_dspin_rsp_g2l_d; 72 DspinSignals<dspin_rsp_width> signal_dspin_p2m_l2g_c; 73 DspinSignals<dspin_rsp_width> signal_dspin_p2m_g2l_c; 74 75 // Direct VCI signals to VCI/DSPIN wrappers 76 VciSignals<vci_param_int> signal_vci_ini_proc[8]; 77 VciSignals<vci_param_int> signal_vci_ini_mdma; 78 VciSignals<vci_param_int> signal_vci_ini_bdev; 79 80 VciSignals<vci_param_int> signal_vci_tgt_memc; 81 VciSignals<vci_param_int> signal_vci_tgt_xicu; 82 VciSignals<vci_param_int> signal_vci_tgt_mdma; 83 VciSignals<vci_param_int> signal_vci_tgt_mtty; 84 VciSignals<vci_param_int> signal_vci_tgt_bdev; 85 VciSignals<vci_param_int> signal_vci_tgt_brom; 86 VciSignals<vci_param_int> signal_vci_tgt_fbuf; 87 VciSignals<vci_param_int> signal_vci_tgt_mnic; 88 89 // Direct DSPIN signals to local crossbars 90 DspinSignals<dspin_cmd_width> signal_dspin_cmd_proc_i[8]; 91 DspinSignals<dspin_rsp_width> signal_dspin_rsp_proc_i[8]; 92 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_i; 93 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_i; 94 DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_i; 95 DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_i; 96 97 DspinSignals<dspin_cmd_width> signal_dspin_cmd_memc_t; 98 DspinSignals<dspin_rsp_width> signal_dspin_rsp_memc_t; 99 DspinSignals<dspin_cmd_width> signal_dspin_cmd_xicu_t; 100 DspinSignals<dspin_rsp_width> signal_dspin_rsp_xicu_t; 101 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_t; 102 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_t; 103 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mtty_t; 104 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mtty_t; 105 DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_t; 106 DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_t; 107 DspinSignals<dspin_cmd_width> signal_dspin_cmd_brom_t; 108 DspinSignals<dspin_rsp_width> signal_dspin_rsp_brom_t; 109 DspinSignals<dspin_cmd_width> signal_dspin_cmd_fbuf_t; 110 DspinSignals<dspin_rsp_width> signal_dspin_rsp_fbuf_t; 111 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mnic_t; 112 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mnic_t; 113 114 // Coherence DSPIN signals to local crossbar 115 DspinSignals<dspin_cmd_width> signal_dspin_m2p_memc; 116 DspinSignals<dspin_rsp_width> signal_dspin_p2m_memc; 117 DspinSignals<dspin_cmd_width> signal_dspin_m2p_proc[8]; 118 DspinSignals<dspin_rsp_width> signal_dspin_p2m_proc[8]; 119 120 // external RAM to MEMC VCI signal 121 VciSignals<vci_param_ext> signal_vci_xram; 122 174 123 // Components 175 124 176 VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>* proc[8]; 177 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_proc[4]; 178 179 VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width> * memc; 180 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_memc; 181 182 VciXicu<vci_param_d>* xicu; 183 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_xicu; 184 185 VciMultiDma<vci_param_d>* mdma; 186 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_mdma; 187 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mdma; 188 189 VciSimpleRam<vci_param_x>* xram; 190 191 VciSimpleRam<vci_param_d>* brom; 192 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_brom; 193 194 VciMultiTty<vci_param_d>* mtty; 195 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mtty; 196 197 VciFrameBuffer<vci_param_d>* fbuf; 198 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_fbuf; 199 200 VciMultiNic<vci_param_d>* mnic; 201 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mnic; 202 203 VciBlockDeviceTsar<vci_param_d>* bdev; 204 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_bdev; 205 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_bdev; 206 207 DspinLocalCrossbar<cmd_width>* xbar_cmd_d; 208 DspinLocalCrossbar<rsp_width>* xbar_rsp_d; 209 DspinLocalCrossbar<cmd_width>* xbar_m2p_c; 210 DspinLocalCrossbar<rsp_width>* xbar_p2m_c; 211 212 VirtualDspinRouter<cmd_width>* router_cmd; 213 VirtualDspinRouter<rsp_width>* router_rsp; 214 215 TsarXbarCluster( sc_module_name insname, 216 size_t nb_procs, // number of processors 217 size_t nb_ttys, // number of TTY terminals 218 size_t nb_dmas, // number of DMA channels 125 VciCcVCacheWrapper<vci_param_int, 126 dspin_cmd_width, 127 dspin_rsp_width, 128 GdbServer<Mips32ElIss> >* proc[8]; 129 130 VciDspinInitiatorWrapper<vci_param_int, 131 dspin_cmd_width, 132 dspin_rsp_width>* wi_proc[8]; 133 134 VciMemCache<vci_param_int, 135 vci_param_ext, 136 dspin_rsp_width, 137 dspin_cmd_width>* memc; 138 139 VciDspinTargetWrapper<vci_param_int, 140 dspin_cmd_width, 141 dspin_rsp_width>* wt_memc; 142 143 VciXicu<vci_param_int>* xicu; 144 145 VciDspinTargetWrapper<vci_param_int, 146 dspin_cmd_width, 147 dspin_rsp_width>* wt_xicu; 148 149 VciMultiDma<vci_param_int>* mdma; 150 151 VciDspinInitiatorWrapper<vci_param_int, 152 dspin_cmd_width, 153 dspin_rsp_width>* wi_mdma; 154 155 VciDspinTargetWrapper<vci_param_int, 156 dspin_cmd_width, 157 dspin_rsp_width>* wt_mdma; 158 159 VciSimpleRam<vci_param_ext>* xram; 160 161 VciSimpleRam<vci_param_int>* brom; 162 163 VciDspinTargetWrapper<vci_param_int, 164 dspin_cmd_width, 165 dspin_rsp_width>* wt_brom; 166 167 VciMultiTty<vci_param_int>* mtty; 168 169 VciDspinTargetWrapper<vci_param_int, 170 dspin_cmd_width, 171 dspin_rsp_width>* wt_mtty; 172 173 VciFrameBuffer<vci_param_int>* fbuf; 174 175 VciDspinTargetWrapper<vci_param_int, 176 dspin_cmd_width, 177 dspin_rsp_width>* wt_fbuf; 178 179 VciMultiNic<vci_param_int>* mnic; 180 181 VciDspinTargetWrapper<vci_param_int, 182 dspin_cmd_width, 183 dspin_rsp_width>* wt_mnic; 184 185 VciBlockDeviceTsar<vci_param_int>* bdev; 186 187 VciDspinInitiatorWrapper<vci_param_int, 188 dspin_cmd_width, 189 dspin_rsp_width>* wi_bdev; 190 191 VciDspinTargetWrapper<vci_param_int, 192 dspin_cmd_width, 193 dspin_rsp_width>* wt_bdev; 194 195 DspinLocalCrossbar<dspin_cmd_width>* xbar_cmd_d; 196 DspinLocalCrossbar<dspin_rsp_width>* xbar_rsp_d; 197 DspinLocalCrossbar<dspin_cmd_width>* xbar_m2p_c; 198 DspinLocalCrossbar<dspin_rsp_width>* xbar_p2m_c; 199 200 VirtualDspinRouter<dspin_cmd_width>* router_cmd; 201 VirtualDspinRouter<dspin_rsp_width>* router_rsp; 202 203 TsarXbarCluster( sc_module_name insname, 204 size_t nb_procs, // processors 205 size_t nb_ttys, // TTY terminals 206 size_t nb_dmas, // DMA channels 219 207 size_t x, // x coordinate 220 208 size_t y, // y coordinate 221 209 size_t cluster, // y + ymax*x 222 const soclib::common::MappingTable &mtd, // direct mapping table223 const soclib::common::MappingTable &mtx, // xram mapping table224 size_t x_width, // x field number ofbits225 size_t y_width, // y field number ofbits226 size_t l_width, // l field number ofbits227 size_t 228 size_t 210 const soclib::common::MappingTable &mtd, // internal 211 const soclib::common::MappingTable &mtx, // external 212 size_t x_width, // x field bits 213 size_t y_width, // y field bits 214 size_t l_width, // l field bits 215 size_t tgtid_memc, 216 size_t tgtid_xicu, 229 217 size_t tgtid_mdma, 230 218 size_t tgtid_fbuf, … … 239 227 size_t l1_d_ways, 240 228 size_t l1_d_sets, 241 size_t xram_latency, // external ram latency242 bool io, // I/O cluster if true243 size_t xfb, // f rame bufferpixels244 size_t yfb, // f rame bufferlines245 char* disk_name, // virtual disk for BDEV246 size_t block_size, // block size for BDEV247 size_t nic_channels, // number ofchannels248 char* nic_rx_name, // file name rx packets249 char* nic_tx_name, // file name tx packets250 uint32_t nic_timeout, // number ofcycles251 const Loader &loader, // loader for BROM 252 uint32_t frozen_cycles, // max frozen cycles229 size_t xram_latency, // external ram 230 bool io, // I/O cluster 231 size_t xfb, // fbf pixels 232 size_t yfb, // fbf lines 233 char* disk_name, // virtual disk 234 size_t block_size, // block size 235 size_t nic_channels, // number channels 236 char* nic_rx_name, // filename rx 237 char* nic_tx_name, // filename tx 238 uint32_t nic_timeout, // cycles 239 const Loader &loader, 240 uint32_t frozen_cycles, 253 241 uint32_t start_debug_cycle, 254 242 bool memc_debug_ok, 255 243 bool proc_debug_ok); 256 244 257 ~TsarXbarCluster();258 245 }; 259 246 }} -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp
r389 r396 15 15 // - Each processor has a private dma channel (vci_multi_dma) 16 16 // - It uses the vci_xicu interrupt controller 17 // - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in the cluster 18 // containing address 0xBFC00000. 17 // - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0) 19 18 // - The Multi-TTY component controls up to 15 terminals. 20 19 // - Each Multi-DMA component controls up to 8 DMA channels. … … 26 25 #include "../include/tsar_xbar_cluster.h" 27 26 28 #define tmpl(x) template<\29 typename iss_t,int cmd_width, int rsp_width> \30 x TsarXbarCluster<\31 iss_t, cmd_width, rsp_width\32 >33 27 34 28 namespace soclib { 35 29 namespace caba { 36 30 37 ////////////////////////////////////////////////////////////////////////// 38 // Constructor 39 ////////////////////////////////////////////////////////////////////////// 40 tmpl(/**/)::TsarXbarCluster( 31 //////////////////////////////////////////////////////////////////////////////////// 32 template<size_t dspin_cmd_width, 33 size_t dspin_rsp_width, 34 typename vci_param_int, 35 typename vci_param_ext> TsarXbarCluster<dspin_cmd_width, 36 dspin_rsp_width, 37 vci_param_int, 38 vci_param_ext>::TsarXbarCluster( 39 //////////////////////////////////////////////////////////////////////////////////// 41 40 sc_module_name insname, 42 41 size_t nb_procs, … … 86 85 { 87 86 // Vectors of ports definition 88 89 p_cmd_ in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);90 p_ cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);91 p_rsp_ in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);92 p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); 93 87 p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 2, 4); 88 p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 2, 4); 89 p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 2, 4); 90 p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 2, 4); 91 92 ///////////////////////////////////////////////////////////////////////////// 94 93 // Components definition 95 96 // on direct network : local srcid[proc] in [0..nb_procs-1]97 // on direct network : local srcid[mdma] = nb_procs98 // on direct network : local srcid[bdev] = nb_procs + 199 100 // on coherence network : local srcid[proc] in [0...nb_procs-1]101 // on coherence network : local srcid[memc] = nb_procs102 103 94 ///////////////////////////////////////////////////////////////////////////// 104 95 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; … … 107 98 { 108 99 std::ostringstream sproc; 109 sproc << "proc_" << p; 110 proc[p] = new VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>( 100 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 101 proc[p] = new VciCcVCacheWrapper<vci_param_int, 102 dspin_cmd_width, 103 dspin_rsp_width, 104 GdbServer<Mips32ElIss> >( 111 105 sproc.str().c_str(), 112 106 cluster_id*nb_procs + p, // GLOBAL PROC_ID … … 130 124 std::ostringstream swip; 131 125 swip << "wi_proc_" << x_id << "_" << y_id << p; 132 wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>( 126 wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int, 127 dspin_cmd_width, 128 dspin_rsp_width>( 133 129 swip.str().c_str(), 134 130 x_width + y_width + l_width); … … 138 134 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 139 135 140 memc = new VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width>( 141 "memc", 136 std::ostringstream smemc; 137 smemc << "memc_" << x_id << "_" << y_id; 138 memc = new VciMemCache<vci_param_int, 139 vci_param_ext, 140 dspin_rsp_width, 141 dspin_cmd_width>( 142 smemc.str().c_str(), 142 143 mtd, // Mapping Table direct space 143 144 mtx, // Mapping Table external space … … 153 154 memc_debug_ok ); 154 155 155 wt_memc = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 156 wt_memc = new VciDspinTargetWrapper<vci_param_int, 157 dspin_cmd_width, 158 dspin_rsp_width>( 156 159 "wt_memc", 157 160 x_width + y_width + l_width); … … 160 163 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 161 164 162 xram = new VciSimpleRam<vci_param_x>( 163 "xram", 165 std::ostringstream sxram; 166 sxram << "xram_" << x_id << "_" << y_id; 167 xram = new VciSimpleRam<vci_param_ext>( 168 sxram.str().c_str(), 164 169 IntTab(cluster_id), 165 170 mtx, … … 170 175 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 171 176 172 xicu = new VciXicu<vci_param_d>( 173 "xicu", 177 std::ostringstream sxicu; 178 sxicu << "xicu_" << x_id << "_" << y_id; 179 xicu = new VciXicu<vci_param_int>( 180 sxicu.str().c_str(), 174 181 mtd, // mapping table 175 182 IntTab(cluster_id, tgtid_xicu), // TGTID_D … … 179 186 nb_procs); // number of output IRQs 180 187 181 wt_xicu = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 188 wt_xicu = new VciDspinTargetWrapper<vci_param_int, 189 dspin_cmd_width, 190 dspin_rsp_width>( 182 191 "wt_xicu", 183 192 x_width + y_width + l_width); … … 186 195 std::cout << " - building mdma_" << x_id << "_" << y_id << std::endl; 187 196 188 mdma = new VciMultiDma<vci_param_d>( 189 "mdma", 197 std::ostringstream smdma; 198 smdma << "mdma_" << x_id << "_" << y_id; 199 mdma = new VciMultiDma<vci_param_int>( 200 smdma.str().c_str(), 190 201 mtd, 191 202 IntTab(cluster_id, nb_procs), // SRCID … … 194 205 nb_dmas); // number of IRQs 195 206 196 wt_mdma = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 207 wt_mdma = new VciDspinTargetWrapper<vci_param_int, 208 dspin_cmd_width, 209 dspin_rsp_width>( 197 210 "wt_mdma", 198 211 x_width + y_width + l_width); 199 212 200 wi_mdma = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>( 213 wi_mdma = new VciDspinInitiatorWrapper<vci_param_int, 214 dspin_cmd_width, 215 dspin_rsp_width>( 201 216 "wi_mdma", 202 217 x_width + y_width + l_width); … … 213 228 } 214 229 215 xbar_cmd_d = new DspinLocalCrossbar< cmd_width>(230 xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>( 216 231 "xbar_cmd_d", 217 232 mtd, // mapping table … … 227 242 std::cout << " - building xbar_rsp_d_" << x_id << "_" << y_id << std::endl; 228 243 229 xbar_rsp_d = new DspinLocalCrossbar< rsp_width>(244 xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>( 230 245 "xbar_rsp_d", 231 246 mtd, // mapping table … … 241 256 std::cout << " - building xbar_m2p_c" << x_id << "_" << y_id << std::endl; 242 257 243 xbar_m2p_c = new DspinLocalCrossbar< cmd_width>(258 xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>( 244 259 "xbar_m2p_c", 245 260 mtd, // mapping table … … 255 270 std::cout << " - building xbar_p2m_c_" << x_id << "_" << y_id << std::endl; 256 271 257 xbar_p2m_c = new DspinLocalCrossbar< rsp_width>(272 xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>( 258 273 "xbar_p2m_c", 259 274 mtd, // mapping table … … 269 284 std::cout << " - building router_cmd_" << x_id << "_" << y_id << std::endl; 270 285 271 router_cmd = new VirtualDspinRouter< cmd_width>(286 router_cmd = new VirtualDspinRouter<dspin_cmd_width>( 272 287 "router_cmd", 273 288 x_id,y_id, // coordinate in the mesh … … 278 293 std::cout << " - building router_rsp_" << x_id << "_" << y_id << std::endl; 279 294 280 router_rsp = new VirtualDspinRouter< rsp_width>(295 router_rsp = new VirtualDspinRouter<dspin_rsp_width>( 281 296 "router_rsp", 282 297 x_id,y_id, // coordinates in mesh … … 290 305 std::cout << " - building brom" << std::endl; 291 306 292 brom = new VciSimpleRam<vci_param_d>( 293 "brom", 294 IntTab(cluster_id, tgtid_brom), 295 mtd, 296 loader); 297 298 wt_brom = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_brom", 307 brom = new VciSimpleRam<vci_param_int>( 308 "brom", 309 IntTab(cluster_id, tgtid_brom), 310 mtd, 311 loader); 312 313 wt_brom = new VciDspinTargetWrapper<vci_param_int, 314 dspin_cmd_width, 315 dspin_rsp_width>( 316 "wt_brom", 299 317 x_width + y_width + l_width); 300 318 … … 302 320 std::cout << " - building fbuf" << std::endl; 303 321 304 fbuf = new VciFrameBuffer<vci_param_d>( 305 "fbuf", 306 IntTab(cluster_id, tgtid_fbuf), 307 mtd, 308 xfb, yfb); 309 310 wt_fbuf = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_fbuf", 322 fbuf = new VciFrameBuffer<vci_param_int>( 323 "fbuf", 324 IntTab(cluster_id, tgtid_fbuf), 325 mtd, 326 xfb, yfb); 327 328 wt_fbuf = new VciDspinTargetWrapper<vci_param_int, 329 dspin_cmd_width, 330 dspin_rsp_width>( 331 "wt_fbuf", 311 332 x_width + y_width + l_width); 312 333 … … 314 335 std::cout << " - building bdev" << std::endl; 315 336 316 bdev = new VciBlockDeviceTsar<vci_param_d>( 317 "bdev", 318 mtd, 319 IntTab(cluster_id, nb_procs+1), 320 IntTab(cluster_id, tgtid_bdev), 321 disk_name, 322 block_size, 323 64); // burst size 324 325 wt_bdev = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_bdev", 326 x_width + y_width + l_width); 327 wi_bdev = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>("wi_bdev", 337 bdev = new VciBlockDeviceTsar<vci_param_int>( 338 "bdev", 339 mtd, 340 IntTab(cluster_id, nb_procs+1), 341 IntTab(cluster_id, tgtid_bdev), 342 disk_name, 343 block_size, 344 64); // burst size 345 346 wt_bdev = new VciDspinTargetWrapper<vci_param_int, 347 dspin_cmd_width, 348 dspin_rsp_width>( 349 "wt_bdev", 350 x_width + y_width + l_width); 351 352 wi_bdev = new VciDspinInitiatorWrapper<vci_param_int, 353 dspin_cmd_width, 354 dspin_rsp_width>( 355 "wi_bdev", 328 356 x_width + y_width + l_width); 329 357 … … 331 359 std::cout << " - building mnic" << std::endl; 332 360 333 mnic = new VciMultiNic<vci_param_d>( 334 "mnic", 335 IntTab(cluster_id, tgtid_mnic), 336 mtd, 337 nic_channels, 338 nic_rx_name, 339 nic_tx_name, 340 0, // mac_4 address 341 0 ); // mac_2 address 342 343 wt_mnic = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_mnic", 361 mnic = new VciMultiNic<vci_param_int>( 362 "mnic", 363 IntTab(cluster_id, tgtid_mnic), 364 mtd, 365 nic_channels, 366 nic_rx_name, 367 nic_tx_name, 368 0, // mac_4 address 369 0 ); // mac_2 address 370 371 wt_mnic = new VciDspinTargetWrapper<vci_param_int, 372 dspin_cmd_width, 373 dspin_rsp_width>( 374 "wt_mnic", 344 375 x_width + y_width + l_width); 345 376 … … 354 385 vect_names.push_back(term_name.str().c_str()); 355 386 } 356 mtty = new VciMultiTty<vci_param_d>( 357 "mtty", 358 IntTab(cluster_id, tgtid_mtty), 359 mtd, 360 vect_names); 361 362 wt_mtty = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_mtty", 363 x_width + y_width + l_width); 364 387 mtty = new VciMultiTty<vci_param_int>( 388 "mtty", 389 IntTab(cluster_id, tgtid_mtty), 390 mtd, 391 vect_names); 392 393 wt_mtty = new VciDspinTargetWrapper<vci_param_int, 394 dspin_cmd_width, 395 dspin_rsp_width>( 396 "wt_mtty", 397 x_width + y_width + l_width); 365 398 } 366 399 … … 679 712 } // end constructor 680 713 681 /////////////////////////////////////////////////////////////////////////// 682 // destructor 683 /////////////////////////////////////////////////////////////////////////// 684 tmpl(/**/)::~TsarXbarCluster() {} 685 } 686 } 687 714 }} 688 715 689 716 // Local Variables:
Note: See TracChangeset
for help on using the changeset viewer.
