Index: trunk/platforms/tsar_generic_xbar/top.cpp =================================================================== --- trunk/platforms/tsar_generic_xbar/top.cpp (revision 395) +++ trunk/platforms/tsar_generic_xbar/top.cpp (revision 396) @@ -3,9 +3,10 @@ // Author: Alain Greiner // Copyright: UPMC/LIP6 -// Date : august 2012 +// Date : may 2013 // This program is released under the GNU public license ///////////////////////////////////////////////////////////////////////// -// This file define a generic TSAR architecture with virtual memory. -// The physical address space is 32 bits. +// This file define a generic TSAR architecture. +// The physical address space is 40 bits. +// // The number of clusters cannot be larger than 256. // The number of processors per cluster cannot be larger than 8. @@ -15,9 +16,12 @@ // - It uses the vci_cc_vcache_wrapper // - It uses the vci_mem_cache -// - It contains one vci_xicu and one vci_multi_dma per cluster. -// - It contains one vci_simple ram per cluster to model the L3 cache. +// - It contains one vci_xicu per cluster. +// - It contains one vci_multi_dma per cluster. +// - It contains one vci_simple_ram per cluster to model the L3 cache. // -// All clusters are identical, but the cluster containing address -// 0xBFC00000 (called io_cluster), contains 5 extra components: +// The communication between the MemCache and the Xram is 64 bits. +// +// All clusters are identical, but the cluster 0 (called io_cluster), +// contains 5 extra components: // - the boot rom (BROM) // - the disk controller (BDEV) @@ -26,7 +30,6 @@ // - the frame buffer controller (FBUF) // -// It is build with one single component implementing a cluster: -// The Tsarv4ClusterMmu component is defined in files -// tsar_xbar_cluster.* (with * = cpp, h, sd) +// It is build with one single component implementing a cluster, +// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) // // The IRQs are connected to XICUs as follow: @@ -36,14 +39,16 @@ // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. // -// The main hardware parameters must be defined in the hard_config.h file : +// Some hardware parameters are used when compiling the OS, and are used +// by this top.cpp file. They must be defined in the hard_config.h file : // - CLUSTER_X : number of clusters in a row (power of 2) // - CLUSTER_Y : number of clusters in a column (power of 2) // - CLUSTER_SIZE : size of the segment allocated to a cluster // - NB_PROCS_MAX : number of processors per cluster (power of 2) -// - NB_DMAS_MAX : number of DMA channels per cluster (< 9) -// - NB_TTYS : number of TTY channels in I/O cluster (< 16) -// - NB_NICS : number of NIC channels in I/O cluster (< 9) +// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) +// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) +// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) // -// Some secondary hardware parameters must be defined in this top.cpp file: +// Some other hardware parameters are not used when compiling the OS, +// and can be directly defined in this top.cpp file: // - XRAM_LATENCY : external ram latency // - MEMC_WAYS : L2 cache number of ways @@ -60,17 +65,17 @@ // - NIC_TX_NAME : file pathname for NIC transmited packets // - NIC_TIMEOUT : max number of cycles before closing a container -// -// General policy for 32 bits physical address decoding: -// All segments base addresses are multiple of 64 Kbytes -// Therefore the 16 address MSB bits completely define the target: +///////////////////////////////////////////////////////////////////////// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) // The (x_width + y_width) MSB bits (left aligned) define -// the cluster index, and the 8 LSB bits define the local index: +// the cluster index, and the LADR bits define the local index: // | X_ID | Y_ID |---| LADR | OFFSET | -// |x_width|y_width|---| 8 | 16 | -// -// General policy for hardware component indexing: -// Each component is identified by (x_id,y_id,l_id) tuple. -// | X_ID | Y_ID | L_ID | -// |x_width|y_width| 4 | +// |x_width|y_width|---| 8 | 24 | +///////////////////////////////////////////////////////////////////////// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// | X_ID | Y_ID |---| L_ID | +// |x_width|y_width|---| 6 | ///////////////////////////////////////////////////////////////////////// @@ -113,6 +118,32 @@ /////////////////////////////////////////////////////////// -#define cmd_width 40 -#define rsp_width 33 +#define dspin_cmd_width 40 +#define dspin_rsp_width 33 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// + +#define int_vci_cell_width 4 +#define int_vci_plen_width 8 +#define int_vci_address_width 40 +#define int_vci_rerror_width 1 +#define int_vci_clen_width 1 +#define int_vci_rflag_width 1 +#define int_vci_srcid_width 14 +#define int_vci_pktid_width 4 +#define int_vci_trdid_width 4 +#define int_vci_wrplen_width 1 + +#define ext_vci_cell_width 8 +#define ext_vci_plen_width 8 +#define ext_vci_address_width 40 +#define ext_vci_rerror_width 1 +#define ext_vci_clen_width 1 +#define ext_vci_rflag_width 1 +#define ext_vci_srcid_width 14 +#define ext_vci_pktid_width 4 +#define ext_vci_trdid_width 4 +#define ext_vci_wrplen_width 1 //////////////////////////////////////////////////////////// @@ -123,5 +154,5 @@ //////////////////////////////////////////////////////////// -// Secondary Hardware Parameters values +// Secondary Hardware Parameters //////////////////////i///////////////////////////////////// @@ -151,5 +182,5 @@ //////////////////////i///////////////////////////////////// -#define BOOT_SOFT_NAME "giet_vm/soft.elf" +#define SOFT_NAME "giet_vm/soft.elf" //////////////////////////////////////////////////////////// @@ -159,6 +190,6 @@ #define MAX_FROZEN_CYCLES 10000 -#define TRACE_MEMC_ID 0 -#define TRACE_PROC_ID 0 +#define TRACE_MEMC_ID 1000000 +#define TRACE_PROC_ID 1000000 ///////////////////////////////////////////////////////// @@ -172,30 +203,30 @@ // specific segments in "IO" cluster : absolute physical address -#define BROM_BASE 0xBFC00000 -#define BROM_SIZE 0x00100000 // 1 Mbytes - -#define FBUF_BASE 0xBFD00000 -#define FBUF_SIZE 0x00200000 // 2 Mbytes - -#define BDEV_BASE 0xBFF10000 -#define BDEV_SIZE 0x00001000 // 4 Kbytes - -#define MTTY_BASE 0xBFF20000 -#define MTTY_SIZE 0x00001000 // 4 Kbytes - -#define MNIC_BASE 0xBFF80000 -#define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes +#define BROM_BASE 0x00BFC00000 +#define BROM_SIZE 0x0000100000 // 1 Mbytes + +#define FBUF_BASE 0x00B2000000 +#define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE + +#define BDEV_BASE 0x00B3000000 +#define BDEV_SIZE 0x0000001000 // 4 Kbytes + +#define MTTY_BASE 0x00B4000000 +#define MTTY_SIZE 0x0000001000 // 4 Kbytes + +#define MNIC_BASE 0x00B5000000 +#define MNIC_SIZE 0x0000002000 * (NB_NIC_CHANNELS + 1) // 8 Kbytes per channel + 8 Kbytes // replicated segments : address is incremented by a cluster offset // offset = cluster(x,y) << (address_width-x_width-y_width); -#define MEMC_BASE 0x00000000 -#define MEMC_SIZE 0x00C00000 // 12 Mbytes - -#define XICU_BASE 0x00F00000 -#define XICU_SIZE 0x00001000 // 4 Kbytes - -#define CDMA_BASE 0x00F30000 -#define CDMA_SIZE 0x00001000 * NB_DMAS_MAX // 4 Kbytes per channel +#define MEMC_BASE 0x0000000000 +#define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster + +#define XICU_BASE 0x00B0000000 +#define XICU_SIZE 0x0000001000 // 4 Kbytes + +#define MDMA_BASE 0x00B1000000 +#define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel //////////////////////////////////////////////////////////////////// @@ -204,12 +235,12 @@ //////////////////////////////////////////////////////////////////// -#define MEMC_TGTID 0 -#define XICU_TGTID 1 -#define CDMA_TGTID 2 -#define MTTY_TGTID 3 -#define FBUF_TGTID 4 -#define BROM_TGTID 5 -#define BDEV_TGTID 6 -#define MNIC_TGTID 7 +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define MDMA_TGTID 2 +#define MTTY_TGTID 3 +#define FBUF_TGTID 4 +#define BDEV_TGTID 5 +#define MNIC_TGTID 6 +#define BROM_TGTID 7 ///////////////////////////////// @@ -221,5 +252,5 @@ - char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code + char soft_name[256] = SOFT_NAME; // pathname to binary code size_t ncycles = 1000000000; // simulated cycles char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image @@ -229,8 +260,9 @@ bool debug_ok = false; // trace activated size_t debug_period = 1; // trace period - size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) + size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced uint32_t debug_from = 0; // trace start cycle uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t cluster_io_id = 0; // index of cluster containing IOs ////////////// command line arguments ////////////////////// @@ -300,39 +332,68 @@ } - // checking hardware parameters - assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or - (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and - "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" ); - - assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or - (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and - "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" ); - - assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or - (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and - "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); - - assert( (NB_DMAS_MAX < 9) and - "The NB_DMAS_MAX parameter must be smaller than 9" ); - - assert( (NB_TTYS < 15) and - "The NB_TTYS parameter must be smaller than 15" ); - - assert( (NB_NICS < 9) and - "The NB_NICS parameter must be smaller than 9" ); - - std::cout << std::endl; - std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl; - std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl; - std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; - std::cout << " - NB_DMAS_MAX = " << NB_DMAS_MAX << std::endl; - std::cout << " - NB_TTYS = " << NB_TTYS << std::endl; - std::cout << " - NB_NICS = " << NB_NICS << std::endl; - std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; - std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; - std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; - std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; - - std::cout << std::endl; + // checking hardware parameters + assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or + (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and + "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" ); + + assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or + (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and + "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" ); + + assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or + (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and + "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); + + assert( (NB_DMA_CHANNELS < 9) and + "The NB_DMA_CHANNELS parameter must be smaller than 9" ); + + assert( (NB_TTY_CHANNELS < 15) and + "The NB_TTY_CHANNELS parameter must be smaller than 15" ); + + assert( (NB_NIC_CHANNELS < 9) and + "The NB_NIC_CHANNELS parameter must be smaller than 9" ); + + assert( (int_vci_address_width == ext_vci_address_width) and + "address widths must be equal on internal & external networks" ); + + assert( (int_vci_address_width == 40) and + "VCI address width must be 40 bits" ); + + std::cout << std::endl; + std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl; + std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl; + std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; + std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; + std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; + std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; + std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; + std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; + std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; + std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; + + std::cout << std::endl; + + // Internal and External VCI parameters definition + typedef soclib::caba::VciParams vci_param_int; + + typedef soclib::caba::VciParamsBis vci_param_ext; #if USE_OPENMP @@ -343,5 +404,4 @@ // Define parameters depending on mesh size - size_t cluster_io_id; size_t x_width; size_t y_width; @@ -359,15 +419,13 @@ else y_width = 4; - cluster_io_id = 0xBF >> (8 - x_width - y_width); - ///////////////////// // Mapping Tables ///////////////////// - // direct network - MappingTable maptabd(address_width, - IntTab(x_width + y_width, 16 - x_width - y_width), - IntTab(x_width + y_width, srcid_width - x_width - y_width), - 0x00FF0000); + // internal network + MappingTable maptabd(int_vci_address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, int_vci_srcid_width - x_width - y_width), + 0x00FF000000); for (size_t x = 0; x < CLUSTER_X; x++) @@ -375,25 +433,35 @@ for (size_t y = 0; y < CLUSTER_Y; y++) { - sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (int_vci_address_width-x_width-y_width); std::ostringstream sh; - sh << "d_seg_memc_" << x << "_" << y; - maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); + sh << "seg_memc_" << x << "_" << y; + maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, + IntTab(cluster(x,y),MEMC_TGTID), true)); std::ostringstream si; - si << "d_seg_xicu_" << x << "_" << y; - maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); + si << "seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, + IntTab(cluster(x,y),XICU_TGTID), false)); std::ostringstream sd; - sd << "d_seg_mdma_" << x << "_" << y; - maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); + sd << "seg_mdma_" << x << "_" << y; + maptabd.add(Segment(sd.str(), MDMA_BASE+offset, MDMA_SIZE, + IntTab(cluster(x,y),MDMA_TGTID), false)); if ( cluster(x,y) == cluster_io_id ) { - maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); - maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); - maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); - maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false)); - maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); + maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, + IntTab(cluster(x,y),MTTY_TGTID), false)); + maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, + IntTab(cluster(x,y),FBUF_TGTID), false)); + maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, + IntTab(cluster(x,y),BDEV_TGTID), false)); + maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, + IntTab(cluster(x,y),MNIC_TGTID), false)); + maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, + IntTab(cluster(x,y),BROM_TGTID), true)); } } @@ -402,5 +470,8 @@ // external network - MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); + MappingTable maptabx(ext_vci_address_width, + IntTab(x_width+y_width), + IntTab(x_width+y_width), + 0xFFFF000000ULL); for (size_t x = 0; x < CLUSTER_X; x++) @@ -408,7 +479,12 @@ for (size_t y = 0; y < CLUSTER_Y ; y++) { - sc_uint offset = cluster(x,y) << (address_width-x_width-y_width); + + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (ext_vci_address_width-x_width-y_width); + std::ostringstream sh; sh << "x_seg_memc_" << x << "_" << y; + maptabx.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y)), false)); @@ -425,32 +501,32 @@ // Horizontal inter-clusters DSPIN signals - DspinSignals*** signal_dspin_h_cmd_inc = - alloc_elems >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2); - DspinSignals*** signal_dspin_h_cmd_dec = - alloc_elems >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2); - DspinSignals*** signal_dspin_h_rsp_inc = - alloc_elems >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2); - DspinSignals*** signal_dspin_h_rsp_dec = - alloc_elems >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2); + DspinSignals*** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2); + DspinSignals*** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2); + DspinSignals*** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2); + DspinSignals*** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2); // Vertical inter-clusters DSPIN signals - DspinSignals*** signal_dspin_v_cmd_inc = - alloc_elems >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2); - DspinSignals*** signal_dspin_v_cmd_dec = - alloc_elems >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2); - DspinSignals*** signal_dspin_v_rsp_inc = - alloc_elems >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2); - DspinSignals*** signal_dspin_v_rsp_dec = - alloc_elems >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2); + DspinSignals*** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2); + DspinSignals*** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2); + DspinSignals*** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2); + DspinSignals*** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2); // Mesh boundaries DSPIN signals - DspinSignals**** signal_dspin_false_cmd_in = - alloc_elems >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4); - DspinSignals**** signal_dspin_false_cmd_out = - alloc_elems >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4); - DspinSignals**** signal_dspin_false_rsp_in = - alloc_elems >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4); - DspinSignals**** signal_dspin_false_rsp_out = - alloc_elems >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4); + DspinSignals**** signal_dspin_false_cmd_in = + alloc_elems >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4); + DspinSignals**** signal_dspin_false_cmd_out = + alloc_elems >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4); + DspinSignals**** signal_dspin_false_rsp_in = + alloc_elems >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4); + DspinSignals**** signal_dspin_false_rsp_out = + alloc_elems >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4); @@ -474,7 +550,8 @@ //////////////////////////// - TsarXbarCluster< - proc_iss, cmd_width, rsp_width - > * clusters[CLUSTER_X][CLUSTER_Y]; + TsarXbarCluster* clusters[CLUSTER_X][CLUSTER_Y]; #if USE_OPENMP @@ -496,24 +573,47 @@ std::ostringstream sc; sc << "cluster_" << x << "_" << y; - clusters[x][y] = new TsarXbarCluster< - proc_iss, cmd_width, rsp_width - > + clusters[x][y] = new TsarXbarCluster ( sc.str().c_str(), - NB_PROCS_MAX , NB_TTYS , NB_DMAS_MAX , // cluster params - x , y , cluster(x,y), // mesh coordinates - maptabd , maptabx , // mapping tables - x_width , y_width , srcid_width - x_width - y_width, // srcid width, - MEMC_TGTID , XICU_TGTID , CDMA_TGTID , // - FBUF_TGTID , MTTY_TGTID , BROM_TGTID , // targets ids - MNIC_TGTID , BDEV_TGTID, // - MEMC_WAYS , MEMC_SETS , // MC params - L1_IWAYS , L1_ISETS , L1_DWAYS , L1_DSETS, // L1 params - XRAM_LATENCY , // - is_io_cluster, // is IO cluster ? - FBUF_X_SIZE , FBUF_Y_SIZE , // FB params - disk_name , BDEV_SECTOR_SIZE, // IOC params - NB_NICS , nic_rx_name , nic_tx_name , NIC_TIMEOUT, // NIC params - loader , +<<<<<<< .mine + NB_PROCS_MAX, + NB_TTY_CHANNELS, + NB_DMA_CHANNELS, + x, + y, + cluster(x,y), + maptabd, + maptabx, + x_width, + y_width, + int_vci_srcid_width - x_width - y_width, // l_id width, + MEMC_TGTID, + XICU_TGTID, + MDMA_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + MNIC_TGTID, + BDEV_TGTID, + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + XRAM_LATENCY, + (cluster(x,y) == cluster_io_id), + FBUF_X_SIZE, + FBUF_Y_SIZE, + disk_name, + BDEV_SECTOR_SIZE, + NB_NIC_CHANNELS, + nic_rx_name, + nic_tx_name, + NIC_TIMEOUT, + loader, frozen_cycles, debug_from , @@ -617,4 +717,6 @@ } } + std::cout << "North, South, West, East connections established" << std::endl; + std::cout << std::endl; @@ -650,87 +752,32 @@ for (size_t n = 1; n < ncycles; n++) { + // Monitor a specific address for L1 & L2 caches + //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); + //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); + if (debug_ok and (n > debug_from) and (n % debug_period == 0)) { std::cout << "****************** cycle " << std::dec << n ; std::cout << " ************************************************" << std::endl; -/* - clusters[0][0]->proc[0]->print_trace(); - clusters[0][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_0_0 vci_ini"); - clusters[0][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_0_0"); - clusters[0][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_0_0"); - clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_0_0"); - clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_0_0"); - clusters[0][0]->memc->print_trace(); - clusters[0][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_0_vci_tgt"); - clusters[0][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_0"); - clusters[0][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_0"); - clusters[0][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_0"); - clusters[0][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_0"); - clusters[0][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_0"); - clusters[0][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_0"); - clusters[0][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_0"); - - clusters[0][1]->proc[0]->print_trace(); - clusters[0][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_1_0 vci_ini"); - clusters[0][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_1_0"); - clusters[0][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_1_0"); - clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_1_0"); - clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_1_0"); - clusters[0][1]->memc->print_trace(); - clusters[0][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_1_vci_tgt"); - clusters[0][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_1"); - clusters[0][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_1"); - clusters[0][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_1"); - clusters[0][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_1"); - clusters[0][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_1"); - clusters[0][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_1"); - clusters[0][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_1"); - - clusters[1][0]->proc[0]->print_trace(); - clusters[1][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_0_0 vci_ini"); - clusters[1][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_0_0"); - clusters[1][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_0_0"); - clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_0_0"); - clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_0_0"); - clusters[1][0]->memc->print_trace(); - clusters[1][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_0_vci_tgt"); - clusters[1][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_0"); - clusters[1][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_0"); - clusters[1][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_0"); - clusters[1][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_0"); - clusters[1][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_0"); - clusters[1][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_0"); - clusters[1][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_0"); - - clusters[1][1]->proc[0]->print_trace(); - clusters[1][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_1_0 vci_ini"); - clusters[1][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_1_0"); - clusters[1][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_1_0"); - clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_1_0"); - clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_1_0"); - clusters[1][1]->memc->print_trace(); - clusters[1][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_1_vci_tgt"); - clusters[1][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_1"); - clusters[1][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_1"); - clusters[1][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_1"); - clusters[1][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_1"); - clusters[1][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_1"); - clusters[1][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_1"); - clusters[1][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_1"); -*/ + // trace proc[debug_proc_id] if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) { - size_t l = debug_proc_id % (CLUSTER_X * CLUSTER_Y) ; + size_t l = debug_proc_id % NB_PROCS_MAX ; size_t y = (debug_proc_id / NB_PROCS_MAX) % CLUSTER_Y ; size_t x = debug_proc_id / (CLUSTER_Y * NB_PROCS_MAX) ; - std::ostringstream signame; - signame << "VCI signal PROC_" << x << "_" << y << "_" << l; + std::ostringstream vci_signame; + vci_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; + std::ostringstream p2m_signame; + p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; + std::ostringstream m2p_signame; + m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; clusters[x][y]->proc[l]->print_trace(); - clusters[x][y]->signal_vci_ini_proc[l].print_trace("signame"); + clusters[x][y]->signal_vci_ini_proc[l].print_trace(vci_signame.str()); + clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); + clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); } -/* // trace memc[debug_memc_id] if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) @@ -739,21 +786,38 @@ size_t y = debug_memc_id % CLUSTER_Y; - std::ostringstream signame; - signame << "VCI signal MEMC_" << x << "_" << y; - - clusters[memc_x][memc_y]->memc->print_trace(); - clusters[memc_x][memc_y]->signal_vci_tgt_memc.print_trace("signame"); + std::ostringstream smemc; + smemc << "[SIG]MEMC_" << x << "_" << y; + std::ostringstream sxram; + sxram << "[SIG]XRAM_" << x << "_" << y; + std::ostringstream sm2p; + sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; + std::ostringstream sp2m; + sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; + + clusters[x][y]->memc->print_trace(); + clusters[x][y]->xram->print_trace(); + clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); + clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); + clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); + clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); } -*/ + + // trace replicated peripherals + clusters[1][1]->mdma->print_trace(); + clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); + clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); + + // trace external peripherals size_t io_x = cluster_io_id / CLUSTER_Y; size_t io_y = cluster_io_id % CLUSTER_Y; - clusters[io_x][io_y]->signal_vci_tgt_mtty.print_trace("VCI signal TTY"); -/* +// clusters[io_x][io_y]->brom->print_trace(); +// clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("/SIG/BROM"); +// clusters[io_x][io_y]->signal_vci_tgt_mtty.print_trace("VCI signal TTY"); + clusters[io_x][io_y]->bdev->print_trace(); - clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("VCI signal BDEV_TGT"); - clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("VCI signal BDEV_INI"); -*/ + clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); + clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); } Index: trunk/platforms/tsar_generic_xbar/top.desc =================================================================== --- trunk/platforms/tsar_generic_xbar/top.desc (revision 395) +++ trunk/platforms/tsar_generic_xbar/top.desc (revision 396) @@ -2,35 +2,67 @@ # -*- python -*- +# internal VCI parameters values +int_vci_cell_size = 4 +int_vci_plen_size = 8 +int_vci_addr_size = 40 +int_vci_rerror_size = 1 +int_vci_clen_size = 1 +int_vci_rflag_size = 1 +int_vci_srcid_size = 14 +int_vci_pktid_size = 4 +int_vci_trdid_size = 4 +int_vci_wrplen_size = 1 + +# external VCI parameters values +ext_vci_cell_size = 8 +ext_vci_plen_size = 8 +ext_vci_addr_size = 40 +ext_vci_rerror_size = 1 +ext_vci_clen_size = 1 +ext_vci_rflag_size = 1 +ext_vci_srcid_size = 14 +ext_vci_pktid_size = 4 +ext_vci_trdid_size = 4 +ext_vci_wrplen_size = 1 + +# DSPIN network parameters values +dspin_cmd_flit_size = 40 +dspin_rsp_flit_size = 33 + todo = Platform('caba', 'top.cpp', - uses = [ + + uses = [ Uses('caba:tsar_xbar_cluster', - iss_t = 'common:gdb_iss', - gdb_iss_t = 'common:mips32el', - cmd_width = 40, - rsp_width = 33 - ), - Uses('common:elf_file_loader'), + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size, + + vci_param_int = 'caba:vci_param', + + cell_size = int_vci_cell_size, + plen_size = int_vci_plen_size, + addr_size = int_vci_addr_size, + rerror_size = int_vci_rerror_size, + clen_size = int_vci_clen_size, + rflag_size = int_vci_rflag_size, + srcid_size = int_vci_srcid_size, + pktid_size = int_vci_pktid_size, + trdid_size = int_vci_trdid_size, + wrplen_size = int_vci_wrplen_size, + + vci_param_ext = 'caba:vci_param_bis', + + cell_size_bis = ext_vci_cell_size, + plen_size_bis = ext_vci_plen_size, + addr_size_bis = ext_vci_addr_size, + rerror_size_bis = ext_vci_rerror_size, + clen_size_bis = ext_vci_clen_size, + rflag_size_bis = ext_vci_rflag_size, + srcid_size_bis = ext_vci_srcid_size, + pktid_size_bis = ext_vci_pktid_size, + trdid_size_bis = ext_vci_trdid_size, + wrplen_size_bis = ext_vci_wrplen_size), + + Uses('common:elf_file_loader'), Uses('common:plain_file_loader'), - ], - cell_size_bis = 8, - plen_size_bis = 8, - addr_size_bis = 32, - rerror_size_bis = 2, - clen_size_bis = 1, - rflag_size_bis = 1, - srcid_size_bis = 14, - pktid_size_bis = 4, - trdid_size_bis = 4, - wrplen_size_bis = 1, - - cell_size = 4, - plen_size = 8, - addr_size = 32, - rerror_size = 2, - clen_size = 1, - rflag_size = 1, - srcid_size = 14, - pktid_size = 4, - trdid_size = 4, - wrplen_size = 1, + ], ) Index: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd =================================================================== --- trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 395) +++ trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 396) @@ -2,72 +2,91 @@ # -*- python -*- -Module('caba:tsar_xbar_cluster', +Module('caba:tsar_xbar_cluster', classname = 'soclib::caba::TsarXbarCluster', - tmpl_parameters = [ - parameter.Module('iss_t'), - parameter.Int('cmd_width'), - parameter.Int('rsp_width'), + tmpl_parameters = [ + parameter.Int('dspin_cmd_width'), + parameter.Int('dspin_rsp_width'), + parameter.Module('vci_param_int'), + parameter.Module('vci_param_ext'), ], - header_files = [ '../source/include/tsar_xbar_cluster.h', ], - implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], - uses = [ - Uses('caba:base_module'), - Uses('common:mapping_table'), - Uses('common:iss2'), - Uses('caba:vci_cc_vcache_wrapper', - vci_param = 'caba:vci_param', - dspin_in_width = parameter.Reference('cmd_width'), - dspin_out_width = parameter.Reference('rsp_width'), + + header_files = [ '../source/include/tsar_xbar_cluster.h', ], + implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + + Uses('caba:vci_cc_vcache_wrapper', + vci_param = parameter.Reference('vci_param_int'), + dspin_in_width = parameter.Reference('dspin_cmd_width'), + dspin_out_width = parameter.Reference('dspin_rsp_width'), iss_t = 'common:gdb_iss', - gdb_iss_t = 'common:mips32el' - ), - Uses('caba:vci_mem_cache', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_simple_ram', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:vci_simple_ram', + vci_param = parameter.Reference('vci_param_ext')), + + Uses('caba:vci_xicu', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:vci_multi_tty', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:vci_framebuffer', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:vci_multi_nic', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:vci_block_device_tsar', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:vci_multi_dma', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:vci_dspin_target_wrapper', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:vci_dspin_initiator_wrapper', + vci_param = parameter.Reference('vci_param_int')), + + Uses('caba:vci_mem_cache', vci_param_int = 'caba:vci_param', vci_param_ext = 'caba:vci_param_bis', - dspin_in_width = parameter.Reference('rsp_width'), - dspin_out_width = parameter.Reference('cmd_width') - ), - Uses('caba:vci_simple_ram', - vci_param = 'caba:vci_param_bis' - ), - Uses('caba:vci_simple_ram', - vci_param = 'caba:vci_param' - ), - Uses('caba:vci_xicu'), - Uses('caba:dspin_local_crossbar', - flit_width = parameter.Reference('cmd_width') - ), - Uses('caba:dspin_local_crossbar', - flit_width = parameter.Reference('rsp_width') - ), - Uses('caba:vci_dspin_initiator_wrapper', - dspin_cmd_width = parameter.Reference('cmd_width'), - dspin_rsp_width = parameter.Reference('rsp_width') - ), - Uses('caba:vci_dspin_target_wrapper', - dspin_cmd_width = parameter.Reference('cmd_width'), - dspin_rsp_width = parameter.Reference('rsp_width') - ), - Uses('caba:virtual_dspin_router', - flit_width = parameter.Reference('cmd_width') - ), - Uses('caba:virtual_dspin_router', - flit_width = parameter.Reference('rsp_width') - ), - Uses('caba:vci_multi_tty'), - Uses('caba:vci_framebuffer'), - Uses('caba:vci_multi_nic'), - Uses('caba:vci_block_device_tsar'), - Uses('caba:vci_multi_dma'), - Uses('common:elf_file_loader'), - ], - ports = [ - Port('caba:bit_in' , 'p_resetn' , auto = 'resetn'), - Port('caba:clock_in' , 'p_clk' , auto = 'clock'), - Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), - Port('caba:dspin_input' , 'p_cmd_in' , [2, 4], dspin_data_size = parameter.Reference('cmd_width')), - Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), - Port('caba:dspin_input' , 'p_rsp_in' , [2, 4], dspin_data_size = parameter.Reference('rsp_width')), - ], + dspin_in_width = parameter.Reference('dspin_rsp_width'), + dspin_out_width = parameter.Reference('dspin_cmd_width')), + + Uses('common:elf_file_loader'), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_cmd_out', [2, 4], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_cmd_in', [2, 4], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_output', 'p_rsp_out', [2, 4], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', [2, 4], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + ], ) Index: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h =================================================================== --- trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 395) +++ trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 396) @@ -1,7 +1,7 @@ ////////////////////////////////////////////////////////////////////////////// -// File: tsar_xbar_cluster_mmu.h +// File: tsar_xbar_cluster.h // Author: Alain Greiner // Copyright: UPMC/LIP6 -// Date : march 2011 +// Date : march 2013 // This program is released under the GNU public license ////////////////////////////////////////////////////////////////////////////// @@ -34,197 +34,185 @@ #include "vci_cc_vcache_wrapper.h" -/////////////////////////////////////////////////////////// -// VCI parameters for DIRECT network -/////////////////////////////////////////////////////////// -#define cell_width 4 -#define address_width 32 -#define plen_width 8 -#define error_width 2 -#define clen_width 1 -#define rflag_width 1 -#define srcid_width 14 -#define pktid_width 4 -#define trdid_width 4 -#define wrplen_width 1 - -/////////////////////////////////////////////////////////// -// VCI parameters for EXTERNAL network -/////////////////////////////////////////////////////////// -#define cell_width_ext 8 -#define address_width_ext address_width -#define plen_width_ext plen_width -#define error_width_ext error_width -#define clen_width_ext clen_width -#define rflag_width_ext rflag_width -#define srcid_width_ext srcid_width -#define pktid_width_ext pktid_width -#define trdid_width_ext trdid_width -#define wrplen_width_ext wrplen_width - namespace soclib { namespace caba { /////////////////////////////////////////////////////////////////////////// -template< - typename iss_t, int cmd_width, int rsp_width - > -class TsarXbarCluster +template class TsarXbarCluster /////////////////////////////////////////////////////////////////////////// : public soclib::caba::BaseModule { - // Define VCI parameters - typedef soclib::caba::VciParams vci_param_d; - - typedef soclib::caba::VciParamsBis vci_param_x; - - public: - - // Ports - sc_in p_clk; - sc_in p_resetn; - soclib::caba::DspinOutput **p_cmd_out; - soclib::caba::DspinInput **p_cmd_in; - soclib::caba::DspinOutput **p_rsp_out; - soclib::caba::DspinInput **p_rsp_in; + public: + + // Ports + sc_in p_clk; + sc_in p_resetn; + soclib::caba::DspinOutput **p_cmd_out; + soclib::caba::DspinInput **p_cmd_in; + soclib::caba::DspinOutput **p_rsp_out; + soclib::caba::DspinInput **p_rsp_in; // interrupt signals - sc_signal signal_false; - sc_signal signal_proc_it[8]; - sc_signal signal_irq_mdma[8]; - sc_signal signal_irq_mtty[23]; - sc_signal signal_irq_mnic_rx[8]; // unused - sc_signal signal_irq_mnic_tx[8]; // unused - sc_signal signal_irq_bdev; - - // DSPIN signals between DSPIN routers and local_crossbars - DspinSignals signal_dspin_cmd_l2g_d; - DspinSignals signal_dspin_cmd_g2l_d; - DspinSignals signal_dspin_m2p_l2g_c; - DspinSignals signal_dspin_m2p_g2l_c; - DspinSignals signal_dspin_rsp_l2g_d; - DspinSignals signal_dspin_rsp_g2l_d; - DspinSignals signal_dspin_p2m_l2g_c; - DspinSignals signal_dspin_p2m_g2l_c; - - // Direct VCI signals to VCI/DSPIN wrappers - VciSignals signal_vci_ini_proc[8]; - VciSignals signal_vci_ini_mdma; - VciSignals signal_vci_ini_bdev; - - VciSignals signal_vci_tgt_memc; - VciSignals signal_vci_tgt_xicu; - VciSignals signal_vci_tgt_mdma; - VciSignals signal_vci_tgt_mtty; - VciSignals signal_vci_tgt_bdev; - VciSignals signal_vci_tgt_brom; - VciSignals signal_vci_tgt_fbuf; - VciSignals signal_vci_tgt_mnic; - - // Direct DSPIN signals to local crossbars - DspinSignals signal_dspin_cmd_proc_i[8]; - DspinSignals signal_dspin_rsp_proc_i[8]; - DspinSignals signal_dspin_cmd_mdma_i; - DspinSignals signal_dspin_rsp_mdma_i; - DspinSignals signal_dspin_cmd_bdev_i; - DspinSignals signal_dspin_rsp_bdev_i; - - DspinSignals signal_dspin_cmd_memc_t; - DspinSignals signal_dspin_rsp_memc_t; - DspinSignals signal_dspin_cmd_xicu_t; - DspinSignals signal_dspin_rsp_xicu_t; - DspinSignals signal_dspin_cmd_mdma_t; - DspinSignals signal_dspin_rsp_mdma_t; - DspinSignals signal_dspin_cmd_mtty_t; - DspinSignals signal_dspin_rsp_mtty_t; - DspinSignals signal_dspin_cmd_bdev_t; - DspinSignals signal_dspin_rsp_bdev_t; - DspinSignals signal_dspin_cmd_brom_t; - DspinSignals signal_dspin_rsp_brom_t; - DspinSignals signal_dspin_cmd_fbuf_t; - DspinSignals signal_dspin_rsp_fbuf_t; - DspinSignals signal_dspin_cmd_mnic_t; - DspinSignals signal_dspin_rsp_mnic_t; - - // Coherence DSPIN signals to local crossbar - DspinSignals signal_dspin_m2p_memc; - DspinSignals signal_dspin_p2m_memc; - DspinSignals signal_dspin_m2p_proc[8]; - DspinSignals signal_dspin_p2m_proc[8]; - - // external RAM VCI signal - VciSignals signal_vci_xram; - + sc_signal signal_false; + sc_signal signal_proc_it[8]; + sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_mtty[23]; + sc_signal signal_irq_mnic_rx[8]; // unused + sc_signal signal_irq_mnic_tx[8]; // unused + sc_signal signal_irq_bdev; + + // DSPIN signals between DSPIN routers and local_crossbars + DspinSignals signal_dspin_cmd_l2g_d; + DspinSignals signal_dspin_cmd_g2l_d; + DspinSignals signal_dspin_m2p_l2g_c; + DspinSignals signal_dspin_m2p_g2l_c; + DspinSignals signal_dspin_rsp_l2g_d; + DspinSignals signal_dspin_rsp_g2l_d; + DspinSignals signal_dspin_p2m_l2g_c; + DspinSignals signal_dspin_p2m_g2l_c; + + // Direct VCI signals to VCI/DSPIN wrappers + VciSignals signal_vci_ini_proc[8]; + VciSignals signal_vci_ini_mdma; + VciSignals signal_vci_ini_bdev; + + VciSignals signal_vci_tgt_memc; + VciSignals signal_vci_tgt_xicu; + VciSignals signal_vci_tgt_mdma; + VciSignals signal_vci_tgt_mtty; + VciSignals signal_vci_tgt_bdev; + VciSignals signal_vci_tgt_brom; + VciSignals signal_vci_tgt_fbuf; + VciSignals signal_vci_tgt_mnic; + + // Direct DSPIN signals to local crossbars + DspinSignals signal_dspin_cmd_proc_i[8]; + DspinSignals signal_dspin_rsp_proc_i[8]; + DspinSignals signal_dspin_cmd_mdma_i; + DspinSignals signal_dspin_rsp_mdma_i; + DspinSignals signal_dspin_cmd_bdev_i; + DspinSignals signal_dspin_rsp_bdev_i; + + DspinSignals signal_dspin_cmd_memc_t; + DspinSignals signal_dspin_rsp_memc_t; + DspinSignals signal_dspin_cmd_xicu_t; + DspinSignals signal_dspin_rsp_xicu_t; + DspinSignals signal_dspin_cmd_mdma_t; + DspinSignals signal_dspin_rsp_mdma_t; + DspinSignals signal_dspin_cmd_mtty_t; + DspinSignals signal_dspin_rsp_mtty_t; + DspinSignals signal_dspin_cmd_bdev_t; + DspinSignals signal_dspin_rsp_bdev_t; + DspinSignals signal_dspin_cmd_brom_t; + DspinSignals signal_dspin_rsp_brom_t; + DspinSignals signal_dspin_cmd_fbuf_t; + DspinSignals signal_dspin_rsp_fbuf_t; + DspinSignals signal_dspin_cmd_mnic_t; + DspinSignals signal_dspin_rsp_mnic_t; + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[8]; + DspinSignals signal_dspin_p2m_proc[8]; + + // external RAM to MEMC VCI signal + VciSignals signal_vci_xram; + // Components - VciCcVCacheWrapper* proc[8]; - VciDspinInitiatorWrapper* wi_proc[4]; - - VciMemCache * memc; - VciDspinTargetWrapper* wt_memc; - - VciXicu* xicu; - VciDspinTargetWrapper* wt_xicu; - - VciMultiDma* mdma; - VciDspinInitiatorWrapper* wi_mdma; - VciDspinTargetWrapper* wt_mdma; - - VciSimpleRam* xram; - - VciSimpleRam* brom; - VciDspinTargetWrapper* wt_brom; - - VciMultiTty* mtty; - VciDspinTargetWrapper* wt_mtty; - - VciFrameBuffer* fbuf; - VciDspinTargetWrapper* wt_fbuf; - - VciMultiNic* mnic; - VciDspinTargetWrapper* wt_mnic; - - VciBlockDeviceTsar* bdev; - VciDspinInitiatorWrapper* wi_bdev; - VciDspinTargetWrapper* wt_bdev; - - DspinLocalCrossbar* xbar_cmd_d; - DspinLocalCrossbar* xbar_rsp_d; - DspinLocalCrossbar* xbar_m2p_c; - DspinLocalCrossbar* xbar_p2m_c; - - VirtualDspinRouter* router_cmd; - VirtualDspinRouter* router_rsp; - - TsarXbarCluster( sc_module_name insname, - size_t nb_procs, // number of processors - size_t nb_ttys, // number of TTY terminals - size_t nb_dmas, // number of DMA channels + VciCcVCacheWrapper >* proc[8]; + + VciDspinInitiatorWrapper* wi_proc[8]; + + VciMemCache* memc; + + VciDspinTargetWrapper* wt_memc; + + VciXicu* xicu; + + VciDspinTargetWrapper* wt_xicu; + + VciMultiDma* mdma; + + VciDspinInitiatorWrapper* wi_mdma; + + VciDspinTargetWrapper* wt_mdma; + + VciSimpleRam* xram; + + VciSimpleRam* brom; + + VciDspinTargetWrapper* wt_brom; + + VciMultiTty* mtty; + + VciDspinTargetWrapper* wt_mtty; + + VciFrameBuffer* fbuf; + + VciDspinTargetWrapper* wt_fbuf; + + VciMultiNic* mnic; + + VciDspinTargetWrapper* wt_mnic; + + VciBlockDeviceTsar* bdev; + + VciDspinInitiatorWrapper* wi_bdev; + + VciDspinTargetWrapper* wt_bdev; + + DspinLocalCrossbar* xbar_cmd_d; + DspinLocalCrossbar* xbar_rsp_d; + DspinLocalCrossbar* xbar_m2p_c; + DspinLocalCrossbar* xbar_p2m_c; + + VirtualDspinRouter* router_cmd; + VirtualDspinRouter* router_rsp; + + TsarXbarCluster( sc_module_name insname, + size_t nb_procs, // processors + size_t nb_ttys, // TTY terminals + size_t nb_dmas, // DMA channels size_t x, // x coordinate size_t y, // y coordinate size_t cluster, // y + ymax*x - const soclib::common::MappingTable &mtd, // direct mapping table - const soclib::common::MappingTable &mtx, // xram mapping table - size_t x_width, // x field number of bits - size_t y_width, // y field number of bits - size_t l_width, // l field number of bits - size_t tgtid_memc, - size_t tgtid_xicu, + const soclib::common::MappingTable &mtd, // internal + const soclib::common::MappingTable &mtx, // external + size_t x_width, // x field bits + size_t y_width, // y field bits + size_t l_width, // l field bits + size_t tgtid_memc, + size_t tgtid_xicu, size_t tgtid_mdma, size_t tgtid_fbuf, @@ -239,21 +227,20 @@ size_t l1_d_ways, size_t l1_d_sets, - size_t xram_latency, // external ram latency - bool io, // I/O cluster if true - size_t xfb, // frame buffer pixels - size_t yfb, // frame buffer lines - char* disk_name, // virtual disk for BDEV - size_t block_size, // block size for BDEV - size_t nic_channels, // number of channels - char* nic_rx_name, // file name rx packets - char* nic_tx_name, // file name tx packets - uint32_t nic_timeout, // number of cycles - const Loader &loader, // loader for BROM - uint32_t frozen_cycles, // max frozen cycles + size_t xram_latency, // external ram + bool io, // I/O cluster + size_t xfb, // fbf pixels + size_t yfb, // fbf lines + char* disk_name, // virtual disk + size_t block_size, // block size + size_t nic_channels, // number channels + char* nic_rx_name, // filename rx + char* nic_tx_name, // filename tx + uint32_t nic_timeout, // cycles + const Loader &loader, + uint32_t frozen_cycles, uint32_t start_debug_cycle, bool memc_debug_ok, bool proc_debug_ok); - ~TsarXbarCluster(); }; }} Index: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp =================================================================== --- trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 395) +++ trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 396) @@ -15,6 +15,5 @@ // - Each processor has a private dma channel (vci_multi_dma) // - It uses the vci_xicu interrupt controller -// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in the cluster -// containing address 0xBFC00000. +// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0) // - The Multi-TTY component controls up to 15 terminals. // - Each Multi-DMA component controls up to 8 DMA channels. @@ -26,17 +25,17 @@ #include "../include/tsar_xbar_cluster.h" -#define tmpl(x) template<\ - typename iss_t,int cmd_width, int rsp_width> \ - x TsarXbarCluster<\ - iss_t, cmd_width, rsp_width\ - > namespace soclib { namespace caba { -////////////////////////////////////////////////////////////////////////// -// Constructor -////////////////////////////////////////////////////////////////////////// -tmpl(/**/)::TsarXbarCluster( +//////////////////////////////////////////////////////////////////////////////////// +template TsarXbarCluster::TsarXbarCluster( +//////////////////////////////////////////////////////////////////////////////////// sc_module_name insname, size_t nb_procs, @@ -86,19 +85,11 @@ { // Vectors of ports definition - - p_cmd_in = alloc_elems >("p_cmd_in", 2, 4); - p_cmd_out = alloc_elems >("p_cmd_out", 2, 4); - p_rsp_in = alloc_elems >("p_rsp_in", 2, 4); - p_rsp_out = alloc_elems >("p_rsp_out", 2, 4); - + p_cmd_in = alloc_elems >("p_cmd_in", 2, 4); + p_cmd_out = alloc_elems >("p_cmd_out", 2, 4); + p_rsp_in = alloc_elems >("p_rsp_in", 2, 4); + p_rsp_out = alloc_elems >("p_rsp_out", 2, 4); + + ///////////////////////////////////////////////////////////////////////////// // Components definition - - // on direct network : local srcid[proc] in [0..nb_procs-1] - // on direct network : local srcid[mdma] = nb_procs - // on direct network : local srcid[bdev] = nb_procs + 1 - - // on coherence network : local srcid[proc] in [0...nb_procs-1] - // on coherence network : local srcid[memc] = nb_procs - ///////////////////////////////////////////////////////////////////////////// std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; @@ -107,6 +98,9 @@ { std::ostringstream sproc; - sproc << "proc_" << p; - proc[p] = new VciCcVCacheWrapper( + sproc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper >( sproc.str().c_str(), cluster_id*nb_procs + p, // GLOBAL PROC_ID @@ -130,5 +124,7 @@ std::ostringstream swip; swip << "wi_proc_" << x_id << "_" << y_id << p; - wi_proc[p] = new VciDspinInitiatorWrapper( + wi_proc[p] = new VciDspinInitiatorWrapper( swip.str().c_str(), x_width + y_width + l_width); @@ -138,6 +134,11 @@ std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; - memc = new VciMemCache( - "memc", + std::ostringstream smemc; + smemc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + smemc.str().c_str(), mtd, // Mapping Table direct space mtx, // Mapping Table external space @@ -153,5 +154,7 @@ memc_debug_ok ); - wt_memc = new VciDspinTargetWrapper( + wt_memc = new VciDspinTargetWrapper( "wt_memc", x_width + y_width + l_width); @@ -160,6 +163,8 @@ std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; - xram = new VciSimpleRam( - "xram", + std::ostringstream sxram; + sxram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + sxram.str().c_str(), IntTab(cluster_id), mtx, @@ -170,6 +175,8 @@ std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; - xicu = new VciXicu( - "xicu", + std::ostringstream sxicu; + sxicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + sxicu.str().c_str(), mtd, // mapping table IntTab(cluster_id, tgtid_xicu), // TGTID_D @@ -179,5 +186,7 @@ nb_procs); // number of output IRQs - wt_xicu = new VciDspinTargetWrapper( + wt_xicu = new VciDspinTargetWrapper( "wt_xicu", x_width + y_width + l_width); @@ -186,6 +195,8 @@ std::cout << " - building mdma_" << x_id << "_" << y_id << std::endl; - mdma = new VciMultiDma( - "mdma", + std::ostringstream smdma; + smdma << "mdma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( + smdma.str().c_str(), mtd, IntTab(cluster_id, nb_procs), // SRCID @@ -194,9 +205,13 @@ nb_dmas); // number of IRQs - wt_mdma = new VciDspinTargetWrapper( + wt_mdma = new VciDspinTargetWrapper( "wt_mdma", x_width + y_width + l_width); - wi_mdma = new VciDspinInitiatorWrapper( + wi_mdma = new VciDspinInitiatorWrapper( "wi_mdma", x_width + y_width + l_width); @@ -213,5 +228,5 @@ } - xbar_cmd_d = new DspinLocalCrossbar( + xbar_cmd_d = new DspinLocalCrossbar( "xbar_cmd_d", mtd, // mapping table @@ -227,5 +242,5 @@ std::cout << " - building xbar_rsp_d_" << x_id << "_" << y_id << std::endl; - xbar_rsp_d = new DspinLocalCrossbar( + xbar_rsp_d = new DspinLocalCrossbar( "xbar_rsp_d", mtd, // mapping table @@ -241,5 +256,5 @@ std::cout << " - building xbar_m2p_c" << x_id << "_" << y_id << std::endl; - xbar_m2p_c = new DspinLocalCrossbar( + xbar_m2p_c = new DspinLocalCrossbar( "xbar_m2p_c", mtd, // mapping table @@ -255,5 +270,5 @@ std::cout << " - building xbar_p2m_c_" << x_id << "_" << y_id << std::endl; - xbar_p2m_c = new DspinLocalCrossbar( + xbar_p2m_c = new DspinLocalCrossbar( "xbar_p2m_c", mtd, // mapping table @@ -269,5 +284,5 @@ std::cout << " - building router_cmd_" << x_id << "_" << y_id << std::endl; - router_cmd = new VirtualDspinRouter( + router_cmd = new VirtualDspinRouter( "router_cmd", x_id,y_id, // coordinate in the mesh @@ -278,5 +293,5 @@ std::cout << " - building router_rsp_" << x_id << "_" << y_id << std::endl; - router_rsp = new VirtualDspinRouter( + router_rsp = new VirtualDspinRouter( "router_rsp", x_id,y_id, // coordinates in mesh @@ -290,11 +305,14 @@ std::cout << " - building brom" << std::endl; - brom = new VciSimpleRam( - "brom", - IntTab(cluster_id, tgtid_brom), - mtd, - loader); - - wt_brom = new VciDspinTargetWrapper("wt_brom", + brom = new VciSimpleRam( + "brom", + IntTab(cluster_id, tgtid_brom), + mtd, + loader); + + wt_brom = new VciDspinTargetWrapper( + "wt_brom", x_width + y_width + l_width); @@ -302,11 +320,14 @@ std::cout << " - building fbuf" << std::endl; - fbuf = new VciFrameBuffer( - "fbuf", - IntTab(cluster_id, tgtid_fbuf), - mtd, - xfb, yfb); - - wt_fbuf = new VciDspinTargetWrapper("wt_fbuf", + fbuf = new VciFrameBuffer( + "fbuf", + IntTab(cluster_id, tgtid_fbuf), + mtd, + xfb, yfb); + + wt_fbuf = new VciDspinTargetWrapper( + "wt_fbuf", x_width + y_width + l_width); @@ -314,16 +335,23 @@ std::cout << " - building bdev" << std::endl; - bdev = new VciBlockDeviceTsar( - "bdev", - mtd, - IntTab(cluster_id, nb_procs+1), - IntTab(cluster_id, tgtid_bdev), - disk_name, - block_size, - 64); // burst size - - wt_bdev = new VciDspinTargetWrapper("wt_bdev", - x_width + y_width + l_width); - wi_bdev = new VciDspinInitiatorWrapper("wi_bdev", + bdev = new VciBlockDeviceTsar( + "bdev", + mtd, + IntTab(cluster_id, nb_procs+1), + IntTab(cluster_id, tgtid_bdev), + disk_name, + block_size, + 64); // burst size + + wt_bdev = new VciDspinTargetWrapper( + "wt_bdev", + x_width + y_width + l_width); + + wi_bdev = new VciDspinInitiatorWrapper( + "wi_bdev", x_width + y_width + l_width); @@ -331,15 +359,18 @@ std::cout << " - building mnic" << std::endl; - mnic = new VciMultiNic( - "mnic", - IntTab(cluster_id, tgtid_mnic), - mtd, - nic_channels, - nic_rx_name, - nic_tx_name, - 0, // mac_4 address - 0 ); // mac_2 address - - wt_mnic = new VciDspinTargetWrapper("wt_mnic", + mnic = new VciMultiNic( + "mnic", + IntTab(cluster_id, tgtid_mnic), + mtd, + nic_channels, + nic_rx_name, + nic_tx_name, + 0, // mac_4 address + 0 ); // mac_2 address + + wt_mnic = new VciDspinTargetWrapper( + "wt_mnic", x_width + y_width + l_width); @@ -354,13 +385,15 @@ vect_names.push_back(term_name.str().c_str()); } - mtty = new VciMultiTty( - "mtty", - IntTab(cluster_id, tgtid_mtty), - mtd, - vect_names); - - wt_mtty = new VciDspinTargetWrapper("wt_mtty", - x_width + y_width + l_width); - + mtty = new VciMultiTty( + "mtty", + IntTab(cluster_id, tgtid_mtty), + mtd, + vect_names); + + wt_mtty = new VciDspinTargetWrapper( + "wt_mtty", + x_width + y_width + l_width); } @@ -679,11 +712,5 @@ } // end constructor -/////////////////////////////////////////////////////////////////////////// -// destructor -/////////////////////////////////////////////////////////////////////////// -tmpl(/**/)::~TsarXbarCluster() {} -} -} - +}} // Local Variables: