Changeset 403 for trunk/modules/vci_cc_vcache_wrapper

Timestamp:

Jun 6, 2013, 9:42:29 PM (11 years ago)

Author:

alain

Message:

Updating vci_cc_vcache_wrapper and vci_mem_cache to comply with the new DSPIN signals (explcit EOP).

File:

• trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (14 diffs)

trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -2128 +2128 @@
         size_t          tlb_way;
         size_t          tlb_set;
-        paddr_t         tlb_nline;
+        paddr_t         tlb_nline = 0;
         size_t          cache_way;
         size_t          cache_set;
@@ -5405 +5405 @@
     //   C_RECEIVE  FSM
     // This FSM receive all coherence packets on a DSPIN40 port.
-    // There is 4 packet types:
+    // There is 7 packet types:
     // - CC_DATA_INVAL : DCACHE invalidate request
     // - CC_DATA_UPDT  : DCACHE update request (multi-words)
@@ -5566 +5566 @@
             uint64_t receive_data = p_dspin_in.data.read();
             // for data INVAL, wait for dcache to take the request
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
+            if ( (r_cc_receive_data_ins.read() == 0) and 
+                 not (r_cc_receive_dcache_req.read()) and 
+                 (p_dspin_in.write.read()) )
             {
                 // request dcache to handle the INVAL
@@ -5588 +5590 @@
             }
             // we should never get there
-            assert ( false && "CC_RECEIVE_INVAL_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req\n");
+            assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_INVAL_NLINE\n");
         }
         ////////////////////////////
@@ -5621 +5623 @@
             // for data INVAL, wait for dcache to take the request and fifo to
             // be empty
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
+            if ( (r_cc_receive_data_ins.read() == 0) and 
+                 not (r_cc_receive_dcache_req.read()) and 
+                 r_cc_receive_updt_fifo_be.empty() and 
+                 (p_dspin_in.write.read()) )
             {
                 r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
@@ -5632 +5637 @@
             // for ins INVAL, wait for icache to take the request and fifo to be
             // empty
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
+            if ( (r_cc_receive_data_ins.read() == 1) and 
+                 not (r_cc_receive_icache_req.read()) and 
+                 r_cc_receive_updt_fifo_be.empty() and 
+                 (p_dspin_in.write.read()))
             {
                 r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
@@ -5642 +5650 @@
             }
             // we should never get there
-            assert ( false && "CC_RECEIVE_UPDT_NLINE : incoherent handling of either r_cc_receive_data_ins or r_cc_receive_*cache_req or r_cc_receive_fifo\n");
+            assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_UPDT_NLINE \n");
             break;
         }
@@ -5653 +5661 @@
                 r_cc_receive_icache_req = true;
 
-            // sample data, be and eop
-            uint64_t receive_data = p_dspin_in.data.read();
             // wait for the fifo
             if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
             {
-                cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
+                uint64_t receive_data = p_dspin_in.data.read();
+                bool     receive_eop  = p_dspin_in.eop.read();
+                cc_receive_updt_fifo_be   = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
                 cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
-                // sample eop to test for state exit
-                bool flit_eop = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_EOP);
-                cc_receive_updt_fifo_eop = flit_eop;
+                cc_receive_updt_fifo_eop  = receive_eop;
                 cc_receive_updt_fifo_put  = true;
-                if(flit_eop)
-                    r_cc_receive_fsm = CC_RECEIVE_IDLE;
+                if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
             }
             break;
@@ -5857 +5862 @@
         {
             // initialize dspin send data
-            DspinDhccpParam::dspin_set(dspin_send_data,
-                                       0,
-                                       DspinDhccpParam::FROM_L1_EOP);
+//            DspinDhccpParam::dspin_set(dspin_send_data,
+//                                       0,
+//                                       DspinDhccpParam::FROM_L1_EOP);
             DspinDhccpParam::dspin_set(dspin_send_data,
                                        m_cc_global_id,
@@ -5914 +5919 @@
             p_dspin_out.data  = dspin_send_data;
             p_dspin_out.write = true;
+            p_dspin_out.eop   = false;
             break;
         }
@@ -5920 +5926 @@
         {
             // initialize dspin send data
-            DspinDhccpParam::dspin_set(dspin_send_data,
-                                       1,
-                                       DspinDhccpParam::FROM_L1_EOP);
+//            DspinDhccpParam::dspin_set(dspin_send_data,
+//                                       1,
+//                                       DspinDhccpParam::FROM_L1_EOP);
 
             if(r_cc_send_last_client.read() == 0) // dcache active request
@@ -5939 +5945 @@
             p_dspin_out.data  = dspin_send_data;
             p_dspin_out.write = true;
+            p_dspin_out.eop   = true;
             break;
         }
@@ -5945 +5952 @@
         {
             // initialize dspin send data
-            DspinDhccpParam::dspin_set(dspin_send_data,
-                                       1,
-                                       DspinDhccpParam::FROM_L1_EOP);
+//            DspinDhccpParam::dspin_set(dspin_send_data,
+//                                       1,
+//                                       DspinDhccpParam::FROM_L1_EOP);
             DspinDhccpParam::dspin_set(dspin_send_data,
                                        0,
@@ -5987 +5994 @@
             p_dspin_out.data  = dspin_send_data;
             p_dspin_out.write = true;
+            p_dspin_out.eop   = true;
 
             break;