Index: /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h
===================================================================
--- /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h	(revision 413)
+++ /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h	(revision 413)
@@ -0,0 +1,14 @@
+#define NB_PROCS        1
+#define NB_CLUSTERS     1
+
+#define IRQ_PER_PROC    1
+
+#define CACHE_COHERENCE 1
+#define CACHE_LINE_SIZE 16 //bytes
+
+#define BOOT_DEBUG      1
+#define BOOT_DEBUG_IOC  0
+
+#define TTY_BASE        0x20000000
+#define ICU_BASE        0x30000000
+#define IOC_BASE        0x40000000
Index: /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript
===================================================================
--- /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript	(revision 413)
+++ /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript	(revision 413)
@@ -0,0 +1,29 @@
+/**********************************************************
+  File   : ldscript 
+  Author : Cesar Fuguet
+  Date   : June 2011
+**********************************************************/
+
+/* Definition of the base address for all segments */ 
+
+seg_stack_base    = 0x10000000 - 0x8000 - 0x4;
+seg_boot_base     = 0xBFC00000;       /* le code de boot */
+
+/* Grouping sections into segments */
+
+ENTRY(boot)
+SECTIONS
+{
+    . = seg_boot_base;
+    .text : {
+        *(.boot)
+        *(.reset)
+    }
+
+    .data ALIGN(0x4) : {
+        *(.reset_data)
+        . = ALIGN(0x4);
+        dtb_addr = .;
+        INCLUDE "build/platform.ld";
+    }
+}
Index: /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/platform_soclib.dts
===================================================================
--- /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/platform_soclib.dts	(revision 413)
+++ /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/platform_soclib.dts	(revision 413)
@@ -0,0 +1,5 @@
+/dts-v1/;
+
+/ {
+};
+