- Timestamp:
- Jun 27, 2013, 10:11:29 PM (11 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba
- Files:
-
- 3 edited
-
metadata/vci_mem_cache.sd (modified) (2 diffs)
-
source/include/xram_transaction.h (modified) (6 diffs)
-
source/src/vci_mem_cache.cpp (modified) (43 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd
r395 r422 9 9 10 10 tmpl_parameters = [ 11 parameter.Module('vci_param_int'), 12 parameter.Module('vci_param_ext'), 11 parameter.Module('vci_param_int', 12 default = 'caba:vci_param', 13 cell_size = parameter.Reference('memc_cell_size_int')), 14 parameter.Module('vci_param_ext', 15 default = 'caba:vci_param', 16 cell_size = parameter.Reference('memc_cell_size_ext')), 13 17 parameter.Int('dspin_in_width'), 14 18 parameter.Int('dspin_out_width'), … … 22 26 ], 23 27 24 implementation_files = [ '../source/src/vci_mem_cache.cpp' ], 28 implementation_files = [ 29 '../source/src/vci_mem_cache.cpp' 30 ], 25 31 26 32 uses = [ -
trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h
r385 r422 13 13 //////////////////////////////////////////////////////////////////////// 14 14 15 class TransactionTabEntry { 15 class TransactionTabEntry 16 { 16 17 typedef sc_dt::sc_uint<64> wide_data_t; 17 18 typedef sc_dt::sc_uint<40> addr_t; … … 84 85 // The print() function prints the entry 85 86 //////////////////////////////////////////////////////////////////// 86 void print(){ 87 void print() 88 { 87 89 std::cout << "valid = " << valid << std::endl; 88 90 std::cout << "xram_read = " << xram_read << std::endl; … … 137 139 // The transaction tab 138 140 //////////////////////////////////////////////////////////////////////// 139 class TransactionTab{ 141 class TransactionTab 142 { 140 143 typedef sc_dt::sc_uint<64> wide_data_t; 141 144 typedef sc_dt::sc_uint<40> addr_t; … … 144 147 145 148 private: 146 size_t size_tab; // The size of the tab 149 const std::string tab_name; // the name for logs 150 size_t size_tab; // the size of the tab 147 151 148 152 data_t be_to_mask(be_t be) … … 176 180 } 177 181 178 TransactionTab(size_t n_entries, size_t n_words) 179 { 180 size_tab = n_entries; 182 TransactionTab(const std::string &name, 183 size_t n_entries, 184 size_t n_words ) 185 : tab_name( name ), 186 size_tab( n_entries ) 187 { 181 188 tab = new TransactionTabEntry[size_tab]; 182 for ( size_t i=0; i<size_tab; i++) { 189 for ( size_t i=0; i<size_tab; i++) 190 { 183 191 tab[i].alloc(n_words); 184 192 } … … 385 393 data_t mask; 386 394 387 assert( (index < size_tab) 388 && "Selected entry out of range in write_rsp() Transaction Tab"); 389 assert( (word <= tab[index].wdata_be.size()) 390 && "Bad word_index in write_rsp() in TransactionTab"); 391 assert( tab[index].valid 392 && "Transaction Tab Entry invalid in write_rsp()"); 393 assert( tab[index].xram_read 394 && "Selected entry is not an XRAM read transaction in write_rsp()"); 395 if ( index >= size_tab ) 396 { 397 std::cout << "VCI_MEM_CACHE ERRROR " << tab_name 398 << " TRT entry out of range in write_rsp()" << std::endl; 399 exit(0); 400 } 401 if ( word > tab[index].wdata_be.size() ) 402 { 403 std::cout << "VCI_MEM_CACHE ERRROR " << tab_name 404 << " Bad word_index in write_rsp() in TRT" << std::endl; 405 exit(0); 406 } 407 if ( not tab[index].valid ) 408 { 409 std::cout << "VCI_MEM_CACHE ERRROR " << tab_name 410 << " TRT Entry invalid in write_rsp()" << std::endl; 411 exit(0); 412 } 413 if ( not tab[index].xram_read ) 414 { 415 std::cout << "VCI_MEM_CACHE ERRROR " << tab_name 416 << " TRT entry is not an XRAM GET in write_rsp()" << std::endl; 417 exit(0); 418 } 395 419 396 420 // first 32 bits word -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r403 r422 322 322 m_debug_ok( debug_ok ), 323 323 m_trt_lines(trt_lines), 324 m_trt(t rt_lines, nwords),324 m_trt(this->name(), trt_lines, nwords), 325 325 m_upt_lines(upt_lines), 326 326 m_upt(upt_lines), … … 414 414 r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") 415 415 { 416 std::cout << " - Building VciMemCache : " << name << std::endl; 417 416 418 assert(IS_POW_OF_2(nsets)); 417 419 assert(IS_POW_OF_2(nwords)); … … 423 425 // check Transaction table size 424 426 assert((uint32_log2(trt_lines) <= vci_param_ext::T) and 425 427 "MEMC ERROR : Need more bits for VCI TRDID field"); 426 428 427 429 // check internal and external data width 428 430 assert( (vci_param_int::B == 4 ) and 429 431 "MEMC ERROR : VCI internal data width must be 32 bits"); 430 432 431 433 assert( (vci_param_ext::B == 8) and 432 434 "MEMC ERROR : VCI external data width must be 64 bits"); 433 435 434 436 // Check coherence between internal & external addresses 435 437 assert( (vci_param_int::N == vci_param_ext::N) and 436 438 "MEMC ERROR : VCI internal & external addresses must have the same width"); 437 439 438 440 // Get the segments associated to the MemCache … … 442 444 for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) 443 445 { 446 std::cout << " => segment " << seg->name() 447 << " / base = " << std::hex << seg->baseAddress() 448 << " / size = " << seg->size() << std::endl; 444 449 m_nseg++; 445 450 } … … 999 1004 1000 1005 #if DEBUG_MEMC_TGT_CMD 1001 if(m_debug_tgt_cmd_fsm) 1002 { 1003 std::cout << " <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:" 1004 << " address = " << std::hex << p_vci_tgt.address.read() 1005 << " srcid = " << std::dec << p_vci_tgt.srcid.read() 1006 << " trdid = " << p_vci_tgt.trdid.read() 1007 << " pktid = " << p_vci_tgt.pktid.read() 1008 << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 1009 } 1006 if(m_debug_tgt_cmd_fsm) 1007 std::cout << " <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:" 1008 << " address = " << std::hex << p_vci_tgt.address.read() 1009 << " / srcid = " << p_vci_tgt.srcid.read() 1010 << " / trdid = " << p_vci_tgt.trdid.read() 1011 << " / pktid = " << p_vci_tgt.pktid.read() 1012 << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 1010 1013 #endif 1011 1014 cmd_read_fifo_put = true; … … 1024 1027 1025 1028 #if DEBUG_MEMC_TGT_CMD 1026 if(m_debug_tgt_cmd_fsm) 1027 { 1028 std::cout << " <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:" 1029 << " address = " << std::hex << p_vci_tgt.address.read() 1030 << " srcid = " << std::dec << p_vci_tgt.srcid.read() 1031 << " trdid = " << p_vci_tgt.trdid.read() 1032 << " pktid = " << p_vci_tgt.pktid.read() 1033 << " wdata = " << std::hex << p_vci_tgt.wdata.read() 1034 << " be = " << p_vci_tgt.be.read() 1035 << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 1036 } 1029 if(m_debug_tgt_cmd_fsm) 1030 std::cout << " <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:" 1031 << " address = " << std::hex << p_vci_tgt.address.read() 1032 << " / srcid = " << p_vci_tgt.srcid.read() 1033 << " / trdid = " << p_vci_tgt.trdid.read() 1034 << " / pktid = " << p_vci_tgt.pktid.read() 1035 << " / wdata = " << p_vci_tgt.wdata.read() 1036 << " / be = " << p_vci_tgt.be.read() 1037 << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 1037 1038 #endif 1038 1039 cmd_write_fifo_put = true; … … 1057 1058 1058 1059 #if DEBUG_MEMC_TGT_CMD 1059 if(m_debug_tgt_cmd_fsm) 1060 { 1061 std::cout << " <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:" 1062 << " address = " << std::hex << p_vci_tgt.address.read() 1063 << " srcid = " << std::dec << p_vci_tgt.srcid.read() 1064 << " trdid = " << p_vci_tgt.trdid.read() 1065 << " pktid = " << p_vci_tgt.pktid.read() 1066 << " wdata = " << std::hex << p_vci_tgt.wdata.read() 1067 << " be = " << p_vci_tgt.be.read() 1068 << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 1069 } 1060 if(m_debug_tgt_cmd_fsm) 1061 std::cout << " <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:" 1062 << " address = " << std::hex << p_vci_tgt.address.read() 1063 << " srcid = " << p_vci_tgt.srcid.read() 1064 << " trdid = " << p_vci_tgt.trdid.read() 1065 << " pktid = " << p_vci_tgt.pktid.read() 1066 << " wdata = " << p_vci_tgt.wdata.read() 1067 << " be = " << p_vci_tgt.be.read() 1068 << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 1070 1069 #endif 1071 1070 cmd_cas_fifo_put = true; … … 1293 1292 #if DEBUG_MEMC_READ 1294 1293 if(m_debug_read_fsm) 1295 std::cout << " <MEMC " << name() << " READ_IDLE> Read request:" 1296 << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1297 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 1298 << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read() 1294 std::cout << " <MEMC " << name() << " READ_IDLE> Read request" 1295 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() 1296 << " / srcid = " << m_cmd_read_srcid_fifo.read() 1297 << " / trdid = " << m_cmd_read_trdid_fifo.read() 1298 << " / pktid = " << m_cmd_read_pktid_fifo.read() 1299 1299 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1300 1300 #endif … … 1462 1462 << " / set = " << std::dec << set 1463 1463 << " / way = " << way 1464 << " / owner_id = " << entry.owner.srcid1465 << " / owner_ins = " << entry.owner.inst1464 << " / owner_id = " << std::hex << entry.owner.srcid 1465 << " / owner_ins = " << std::dec << entry.owner.inst 1466 1466 << " / count = " << entry.count 1467 1467 << " / is_cnt = " << entry.is_cnt << std::endl; … … 1626 1626 if(m_debug_read_fsm) 1627 1627 std::cout << " <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:" 1628 << " owner_id = " << heap_entry.owner.srcid1629 << " owner_ins = " << heap_entry.owner.inst << std::endl;1628 << " owner_id = " << std::hex << heap_entry.owner.srcid 1629 << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl; 1630 1630 #endif 1631 1631 } … … 1714 1714 if(m_debug_read_fsm) 1715 1715 std::cout << " <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:" 1716 << " rsrcid = " << std:: dec<< m_cmd_read_srcid_fifo.read()1716 << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() 1717 1717 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 1718 1718 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; … … 2497 2497 2498 2498 #if DEBUG_MEMC_WRITE 2499 2500 2501 std::cout << " <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid ="2502 << std::dec<< r_write_srcid.read() << std::endl;2503 2504 2505 2506 << " srcid = " << std::dec<< m_cmd_write_srcid_fifo.read()2507 << " / address = " << std::hex<< m_cmd_write_addr_fifo.read()2508 2509 2510 2499 if(m_debug_write_fsm) 2500 { 2501 std::cout << " <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM" 2502 << " : rsrcid = " << std::hex << r_write_srcid.read() << std::endl; 2503 if(m_cmd_write_addr_fifo.rok()) 2504 { 2505 std::cout << " New Write request: " 2506 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() 2507 << " / address = " << m_cmd_write_addr_fifo.read() 2508 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 2509 } 2510 } 2511 2511 #endif 2512 2512 } … … 2521 2521 2522 2522 #if DEBUG_MEMC_WRITE 2523 if(m_debug_write_fsm) 2524 { 2525 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl; 2526 } 2523 if(m_debug_write_fsm) 2524 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl; 2527 2525 #endif 2528 2526 size_t hit_index = 0; … … 2557 2555 case WRITE_WAIT: // release the locks protecting the shared ressources 2558 2556 { 2557 2559 2558 #if DEBUG_MEMC_WRITE 2560 if(m_debug_write_fsm) 2561 { 2562 std::cout << " <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl; 2563 } 2559 if(m_debug_write_fsm) 2560 std::cout << " <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl; 2564 2561 #endif 2565 2562 r_write_fsm = WRITE_DIR_REQ; … … 2595 2592 2596 2593 #if DEBUG_MEMC_WRITE 2597 if(m_debug_write_fsm) 2598 { 2599 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl; 2600 } 2594 if(m_debug_write_fsm) 2595 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl; 2601 2596 #endif 2602 2597 } … … 2624 2619 2625 2620 #if DEBUG_MEMC_WRITE 2626 if(m_debug_write_fsm) 2627 { 2628 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl; 2629 m_trt.print(r_write_trt_index.read()); 2630 } 2621 if(m_debug_write_fsm) 2622 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl; 2631 2623 #endif 2632 2624 } … … 2646 2638 2647 2639 #if DEBUG_MEMC_WRITE 2648 if(m_debug_write_fsm) 2649 { 2650 std::cout << " <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl; 2651 } 2640 if(m_debug_write_fsm) 2641 std::cout << " <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl; 2652 2642 #endif 2653 2643 } … … 2673 2663 2674 2664 #if DEBUG_MEMC_WRITE 2675 if(m_debug_write_fsm) 2676 { 2677 std::cout << " <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT : wok = " 2678 << wok << " / index = " << wok_index << std::endl; 2679 } 2665 if(m_debug_write_fsm) 2666 std::cout << " <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT" 2667 << " : wok = " << wok << " / index = " << wok_index << std::endl; 2680 2668 #endif 2681 2669 } … … 2707 2695 2708 2696 #if DEBUG_MEMC_WRITE 2709 if(m_debug_write_fsm) 2710 { 2711 if(wok) 2712 { 2713 std::cout << " <MEMC " << name() << " WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / " 2714 << " nb_copies = " << r_write_count.read() << std::endl; 2715 } 2716 } 2697 if( m_debug_write_fsm and wok ) 2698 std::cout << " <MEMC " << name() << " WRITE_BC_UPT_LOCK> Register broadcast inval in UPT" 2699 << " / nb_copies = " << r_write_count.read() << std::endl; 2717 2700 #endif 2718 2701 r_write_upt_index = index; … … 2771 2754 2772 2755 #if DEBUG_MEMC_WRITE 2773 if(m_debug_write_fsm) 2774 { 2775 std::cout << " <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = " 2776 << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; 2777 } 2756 if(m_debug_write_fsm) 2757 std::cout << " <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = " 2758 << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; 2778 2759 #endif 2779 2760 r_write_fsm = WRITE_BC_CC_SEND; … … 3428 3409 << " way = " << std::dec << way 3429 3410 << " / set = " << set 3430 << " / owner_id = " << entry.owner.srcid3431 << " / owner_ins = " << entry.owner.inst3411 << " / owner_id = " << std::hex << entry.owner.srcid 3412 << " / owner_ins = " << std::dec << entry.owner.inst 3432 3413 << " / count = " << entry.count 3433 3414 << " / is_cnt = " << entry.is_cnt << std::endl; … … 3505 3486 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_RSP>" 3506 3487 << " Request the TGT_RSP FSM to return data:" 3507 << " rsrcid = " << std:: dec<< r_xram_rsp_trt_buf.srcid3488 << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid 3508 3489 << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 3509 3490 << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; … … 4515 4496 << " CLEANUP_WRITE_RSP> Send a response to a previous" 4516 4497 << " write request waiting for coherence transaction completion: " 4517 << " rsrcid = " << std:: dec<< r_cleanup_write_srcid.read()4518 << " / rtrdid = " << std:: dec<< r_cleanup_write_trdid.read()4498 << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() 4499 << " / rtrdid = " << std::hex << r_cleanup_write_trdid.read() 4519 4500 << std::endl; 4520 4501 } … … 4722 4703 4723 4704 #if DEBUG_MEMC_CAS 4724 if(m_debug_cas_fsm) 4725 { 4726 std::cout 4727 << " <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from " 4728 << " cache and store it in buffer" 4729 << std::endl; 4730 } 4705 if(m_debug_cas_fsm) 4706 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from " 4707 << " cache and store it in buffer" << std::endl; 4731 4708 #endif 4732 4709 break; … … 4759 4736 4760 4737 #if DEBUG_MEMC_CAS 4761 if(m_debug_cas_fsm) 4762 { 4763 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old" 4764 << " and the new data" 4765 << " / expected value = " << r_cas_rdata[0].read() 4766 << " / actual value = " << r_cas_data[word].read() 4767 << " / forced_fail = " << forced_fail << std::endl; 4768 } 4738 if(m_debug_cas_fsm) 4739 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old" 4740 << " and the new data" 4741 << " / expected value = " << r_cas_rdata[0].read() 4742 << " / actual value = " << r_cas_data[word].read() 4743 << " / forced_fail = " << forced_fail << std::endl; 4769 4744 #endif 4770 4745 break; … … 4821 4796 4822 4797 #if DEBUG_MEMC_CAS 4823 if(m_debug_cas_fsm) 4824 { 4825 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:" 4826 << " way = " << std::dec << way 4827 << " / set = " << set 4828 << " / word = " << word 4829 << " / value = " << r_cas_wdata.read() 4830 << " / count = " << r_cas_count.read() << std::endl; 4831 std::cout << " <MEMC " 4832 << name() << " CAS_DIR_HIT_WRITE> global_llsc_table SW access" << std::endl; 4833 } 4798 if(m_debug_cas_fsm) 4799 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:" 4800 << " way = " << std::dec << way 4801 << " / set = " << set 4802 << " / word = " << word 4803 << " / value = " << r_cas_wdata.read() 4804 << " / count = " << r_cas_count.read() 4805 << " / global_llsc_table access" << std::endl; 4834 4806 #endif 4835 4807 } … … 4893 4865 4894 4866 #if DEBUG_MEMC_CAS 4895 if(m_debug_cas_fsm) 4896 { 4897 std::cout << " <MEMC " << name() 4898 << " CAS_UPT_LOCK> Register multi-update transaction in UPT" 4899 << " / wok = " << wok 4900 << " / nline = " << std::hex << nline 4901 << " / count = " << nb_copies << std::endl; 4902 } 4867 if(m_debug_cas_fsm) 4868 std::cout << " <MEMC " << name() 4869 << " CAS_UPT_LOCK> Register multi-update transaction in UPT" 4870 << " / wok = " << wok 4871 << " / nline = " << std::hex << nline 4872 << " / count = " << nb_copies << std::endl; 4903 4873 #endif 4904 4874 } … … 5125 5095 r_cas_upt_index = index; 5126 5096 r_cas_fsm = CAS_BC_DIR_INVAL; 5097 5127 5098 #if DEBUG_MEMC_CAS 5128 if(m_debug_cas_fsm) 5129 { 5130 std::cout << " <MEMC " << name() << " CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT" 5131 << " / nline = " << nline 5132 << " / count = " << nb_copies 5133 << " / upt_index = " << index << std::endl; 5134 } 5099 if(m_debug_cas_fsm) 5100 std::cout << " <MEMC " << name() 5101 << " CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT" 5102 << " / nline = " << std::hex << nline 5103 << " / count = " << std::dec << nb_copies 5104 << " / upt_index = " << index << std::endl; 5135 5105 #endif 5136 5106 } … … 5142 5112 break; 5143 5113 } 5144 ////////////////// 5114 ////////////////////// 5145 5115 case CAS_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry 5146 5116 { … … 5183 5153 5184 5154 #if DEBUG_MEMC_CAS 5185 if(m_debug_cas_fsm) 5186 { 5187 std::cout << " <MEMC " << name() << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry" 5188 << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())] 5189 << " / set = " << std::dec << set << " / way = " << way << std::endl; 5190 } 5155 if(m_debug_cas_fsm) 5156 std::cout << " <MEMC " << name() 5157 << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry" 5158 << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())] 5159 << " / set = " << std::dec << set << " / way = " << way << std::endl; 5191 5160 #endif 5192 5161 } … … 5228 5197 5229 5198 #if DEBUG_MEMC_CAS 5230 if(m_debug_cas_fsm) 5231 { 5232 std::cout << " <MEMC " << name() << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex 5233 << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] 5234 << " / trt_index = " << r_cas_trt_index.read() << std::endl; 5235 } 5199 if(m_debug_cas_fsm) 5200 std::cout << " <MEMC " << name() 5201 << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex 5202 << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] 5203 << " / trt_index = " << r_cas_trt_index.read() << std::endl; 5236 5204 #endif 5237 5205 } 5238 5206 else 5239 5207 { 5240 std::cout << " MEM_CACHE, CAS_BC_XRAM_REQ state : request should not have been previously set"5241 << std::endl;5208 std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state" 5209 << " : request should not have been previously set" << std::endl; 5242 5210 } 5243 5211 break; … … 5258 5226 5259 5227 #if DEBUG_MEMC_CAS 5260 if(m_debug_cas_fsm) 5261 { 5262 std::cout << " <MEMC " << name() << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl; 5263 } 5228 if(m_debug_cas_fsm) 5229 std::cout << " <MEMC " << name() 5230 << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl; 5264 5231 #endif 5265 5232 } … … 5281 5248 5282 5249 #if DEBUG_MEMC_CAS 5283 if(m_debug_cas_fsm) 5284 { 5285 std::cout << " <MEMC " << name() << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl; 5286 } 5250 if(m_debug_cas_fsm) 5251 std::cout << " <MEMC " << name() 5252 << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl; 5287 5253 #endif 5288 5254 } … … 5649 5615 5650 5616 #if DEBUG_MEMC_CC_SEND 5651 if(m_debug_cc_send_fsm) 5652 { 5653 std::cout 5654 << " <MEMC " << name() 5655 << " CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid " 5656 << r_cleanup_to_cc_send_srcid.read() 5657 << std::endl; 5658 } 5617 if(m_debug_cc_send_fsm) 5618 std::cout << " <MEMC " << name() 5619 << " CC_SEND_CLEANUP_ACK> Cleanup Ack for srcid " 5620 << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl; 5659 5621 #endif 5660 5622 break; … … 5692 5654 5693 5655 #if DEBUG_MEMC_CC_SEND 5694 if(m_debug_cc_send_fsm) 5695 { 5696 std::cout 5697 << " <MEMC " << name() 5698 << " CC_SEND_XRAM_RSP_INVAL_NLINE> Broadcast-Inval for line " 5699 << r_xram_rsp_to_cc_send_nline.read() 5700 << std::endl; 5701 } 5656 if(m_debug_cc_send_fsm) 5657 std::cout << " <MEMC " << name() 5658 << " CC_SEND_XRAM_RSP_INVAL_NLINE> BC-Inval for line " 5659 << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; 5702 5660 #endif 5703 5661 break; … … 5724 5682 5725 5683 #if DEBUG_MEMC_CC_SEND 5726 if(m_debug_cc_send_fsm) 5727 { 5728 std::cout 5729 << " <MEMC " << name() 5730 << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> Broadcast-Inval for line " 5731 << r_xram_rsp_to_cc_send_nline.read() 5732 << std::endl; 5733 } 5684 if(m_debug_cc_send_fsm) 5685 std::cout << " <MEMC " << name() 5686 << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> BC-Inval for line " 5687 << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; 5734 5688 #endif 5735 5689 break; … … 5756 5710 5757 5711 #if DEBUG_MEMC_CC_SEND 5758 if(m_debug_cc_send_fsm) 5759 { 5760 std::cout 5761 << " <MEMC " << name() 5762 << " CC_SEND_WRITE_BRDCAST_NLINE> Broadcast-Inval for line " 5763 << r_write_to_cc_send_nline.read() 5764 << std::endl; 5765 } 5712 if(m_debug_cc_send_fsm) 5713 std::cout << " <MEMC " << name() 5714 << " CC_SEND_WRITE_BRDCAST_NLINE> BC-Inval for line " 5715 << std::hex << r_write_to_cc_send_nline.read() << std::endl; 5766 5716 #endif 5767 5717 break; … … 6153 6103 std::cout 6154 6104 << " <MEMC " << name() << " TGT_RSP_READ> Read response" 6155 << " / rsrcid = " << std:: dec<< r_read_to_tgt_rsp_srcid.read()6105 << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read() 6156 6106 << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() 6157 6107 << " / rpktid = " << r_read_to_tgt_rsp_pktid.read() 6158 << " / rdata = " << std::hex <<r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()6108 << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() 6159 6109 << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; 6160 6110 } … … 6193 6143 6194 6144 #if DEBUG_MEMC_TGT_RSP 6195 if(m_debug_tgt_rsp_fsm) 6196 { 6197 std::cout << " <MEMC " << name() << " TGT_RSP_WRITE> Write response" 6198 << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read() 6199 << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() 6200 << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; 6201 } 6145 if(m_debug_tgt_rsp_fsm) 6146 std::cout << " <MEMC " << name() << " TGT_RSP_WRITE> Write response" 6147 << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() 6148 << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() 6149 << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; 6202 6150 #endif 6203 6151 r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE; … … 6213 6161 6214 6162 #if DEBUG_MEMC_TGT_RSP 6215 if(m_debug_tgt_rsp_fsm) 6216 { 6217 std::cout << " <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response" 6218 << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read() 6219 << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() 6220 << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; 6221 } 6163 if(m_debug_tgt_rsp_fsm) 6164 std::cout << " <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response" 6165 << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read() 6166 << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() 6167 << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; 6222 6168 #endif 6223 6169 r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE; … … 6233 6179 6234 6180 #if DEBUG_MEMC_TGT_RSP 6235 if(m_debug_tgt_rsp_fsm) 6236 { 6237 std::cout << " <MEMC " << name() << " TGT_RSP_CAS> CAS response" 6238 << " / rsrcid = " << std::dec << r_cas_to_tgt_rsp_srcid.read() 6239 << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() 6240 << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; 6241 } 6181 if(m_debug_tgt_rsp_fsm) 6182 std::cout << " <MEMC " << name() << " TGT_RSP_CAS> CAS response" 6183 << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() 6184 << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() 6185 << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; 6242 6186 #endif 6243 6187 r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE; … … 6255 6199 #if DEBUG_MEMC_TGT_RSP 6256 6200 if( m_debug_tgt_rsp_fsm ) 6257 { 6258 std::cout 6259 << " <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access" 6260 << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read() 6261 << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() 6262 << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() 6263 << " / rdata = " << std::hex << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() 6264 << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; 6265 } 6201 std::cout << " <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access" 6202 << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() 6203 << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() 6204 << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() 6205 << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() 6206 << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; 6266 6207 #endif 6267 6208 uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1; … … 6299 6240 6300 6241 #if DEBUG_MEMC_TGT_RSP 6301 if(m_debug_tgt_rsp_fsm) 6302 { 6303 std::cout << " <MEMC " << name() << " TGT_RSP_INIT> Write response after coherence transaction" 6304 << " / rsrcid = " << std::dec << r_multi_ack_to_tgt_rsp_srcid.read() 6305 << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read() 6306 << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl; 6307 } 6242 if(m_debug_tgt_rsp_fsm) 6243 std::cout << " <MEMC " << name() << " TGT_RSP_INIT> Write response after coherence transaction" 6244 << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() 6245 << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read() 6246 << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl; 6308 6247 #endif 6309 6248 r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
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