Changeset 422 for trunk/modules


Ignore:
Timestamp:
Jun 27, 2013, 10:11:29 PM (11 years ago)
Author:
alain
Message:

cosmetic

Location:
trunk/modules/vci_mem_cache/caba
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd

    r395 r422  
    99
    1010        tmpl_parameters = [
    11                         parameter.Module('vci_param_int'),
    12             parameter.Module('vci_param_ext'),
     11                        parameter.Module('vci_param_int',
     12                              default = 'caba:vci_param',
     13                              cell_size = parameter.Reference('memc_cell_size_int')),
     14            parameter.Module('vci_param_ext',
     15                              default = 'caba:vci_param',
     16                              cell_size = parameter.Reference('memc_cell_size_ext')),
    1317            parameter.Int('dspin_in_width'),
    1418            parameter.Int('dspin_out_width'),
    … …  
    2226        ],
    2327
    24         implementation_files = [ '../source/src/vci_mem_cache.cpp' ],
     28        implementation_files = [
     29            '../source/src/vci_mem_cache.cpp'
     30        ],
    2531
    2632        uses = [

  • trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h

    r385 r422  
    1313////////////////////////////////////////////////////////////////////////
    1414
    15 class TransactionTabEntry {
     15class TransactionTabEntry
     16{
    1617    typedef sc_dt::sc_uint<64>    wide_data_t;
    1718    typedef sc_dt::sc_uint<40>    addr_t;
    … …  
    8485    // The print() function prints the entry
    8586    ////////////////////////////////////////////////////////////////////
    86     void print(){
     87    void print()
     88    {
    8789        std::cout << "valid       = " << valid        << std::endl;
    8890        std::cout << "xram_read   = " << xram_read    << std::endl;
    … …  
    137139//                  The transaction tab                             
    138140////////////////////////////////////////////////////////////////////////
    139 class TransactionTab{
     141class TransactionTab
     142{
    140143    typedef sc_dt::sc_uint<64>    wide_data_t;
    141144    typedef sc_dt::sc_uint<40>    addr_t;
    … …  
    144147
    145148    private:
    146     size_t size_tab;                // The size of the tab
     149    const std::string tab_name;                // the name for logs
     150    size_t            size_tab;                // the size of the tab
    147151
    148152    data_t be_to_mask(be_t be)
    … …  
    176180    }
    177181
    178     TransactionTab(size_t n_entries, size_t n_words)
    179     {
    180         size_tab = n_entries;
     182    TransactionTab(const std::string &name,
     183                   size_t            n_entries,
     184                   size_t            n_words )
     185    : tab_name( name ),
     186      size_tab( n_entries )
     187    {
    181188        tab = new TransactionTabEntry[size_tab];
    182         for ( size_t i=0; i<size_tab; i++) {
     189        for ( size_t i=0; i<size_tab; i++)
     190        {
    183191            tab[i].alloc(n_words);
    184192        }
    … …  
    385393        data_t  mask;
    386394
    387         assert( (index < size_tab)
    388                 && "Selected entry  out of range in write_rsp() Transaction Tab");
    389         assert( (word <= tab[index].wdata_be.size())
    390                 && "Bad word_index in write_rsp() in TransactionTab");
    391         assert( tab[index].valid
    392                 && "Transaction Tab Entry invalid in write_rsp()");
    393         assert( tab[index].xram_read
    394                 && "Selected entry is not an XRAM read transaction in write_rsp()");
     395        if ( index >= size_tab )
     396        {
     397            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
     398                      <<  " TRT entry  out of range in write_rsp()" << std::endl;
     399            exit(0);
     400        }
     401        if ( word > tab[index].wdata_be.size() )
     402        {
     403            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
     404                      <<  " Bad word_index in write_rsp() in TRT" << std::endl;
     405            exit(0);
     406        }
     407        if ( not tab[index].valid )
     408        {
     409            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
     410                      <<  " TRT Entry invalid in write_rsp()" << std::endl;
     411            exit(0);
     412        }
     413        if ( not tab[index].xram_read )
     414        {
     415            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
     416                      <<  " TRT entry is not an XRAM GET in write_rsp()" << std::endl;
     417            exit(0);
     418        }
    395419
    396420        // first 32 bits word

  • trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

    r403 r422  
    322322    m_debug_ok( debug_ok ),
    323323    m_trt_lines(trt_lines),
    324     m_trt(trt_lines, nwords),
     324    m_trt(this->name(), trt_lines, nwords),
    325325    m_upt_lines(upt_lines),
    326326    m_upt(upt_lines),
    … …  
    414414    r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt")
    415415{
     416    std::cout << "  - Building VciMemCache : " << name << std::endl;
     417
    416418    assert(IS_POW_OF_2(nsets));
    417419    assert(IS_POW_OF_2(nwords));
    … …  
    423425    // check Transaction table size
    424426    assert((uint32_log2(trt_lines) <= vci_param_ext::T) and
    425          "MEMC ERROR : Need more bits for VCI TRDID field");
     427    "MEMC ERROR : Need more bits for VCI TRDID field");
    426428
    427429    // check internal and external data width
    428430    assert( (vci_param_int::B == 4 ) and
    429          "MEMC ERROR : VCI internal data width must be 32 bits");
     431    "MEMC ERROR : VCI internal data width must be 32 bits");
    430432         
    431433    assert( (vci_param_ext::B == 8) and
    432          "MEMC ERROR : VCI external data width must be 64 bits");
     434    "MEMC ERROR : VCI external data width must be 64 bits");
    433435
    434436    // Check coherence between internal & external addresses
    435437    assert( (vci_param_int::N == vci_param_ext::N) and
    436          "MEMC ERROR : VCI internal & external addresses must have the same width");
     438    "MEMC ERROR : VCI internal & external addresses must have the same width");
    437439         
    438440    // Get the segments associated to the MemCache
    … …  
    442444    for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++)
    443445    {
     446        std::cout << "    => segment " << seg->name()
     447                  << " / base = " << std::hex << seg->baseAddress()
     448                  << " / size = " << seg->size() << std::endl;
    444449        m_nseg++;
    445450    }
    … …  
    9991004
    10001005#if DEBUG_MEMC_TGT_CMD
    1001         if(m_debug_tgt_cmd_fsm)
    1002         {
    1003           std::cout << "  <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:"
    1004                     << " address = " << std::hex << p_vci_tgt.address.read()
    1005                     << " srcid = " << std::dec << p_vci_tgt.srcid.read()
    1006                     << " trdid = " << p_vci_tgt.trdid.read()
    1007                     << " pktid = " << p_vci_tgt.pktid.read()
    1008                     << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
    1009         }
     1006if(m_debug_tgt_cmd_fsm)
     1007std::cout << "  <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:"
     1008          << " address = " << std::hex << p_vci_tgt.address.read()
     1009          << " / srcid = " << p_vci_tgt.srcid.read()
     1010          << " / trdid = " << p_vci_tgt.trdid.read()
     1011          << " / pktid = " << p_vci_tgt.pktid.read()
     1012          << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
    10101013#endif
    10111014        cmd_read_fifo_put = true;
    … …  
    10241027
    10251028#if DEBUG_MEMC_TGT_CMD
    1026         if(m_debug_tgt_cmd_fsm)
    1027         {
    1028           std::cout << "  <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:"
    1029                     << " address = " << std::hex << p_vci_tgt.address.read()
    1030                     << " srcid = " << std::dec << p_vci_tgt.srcid.read()
    1031                     << " trdid = " << p_vci_tgt.trdid.read()
    1032                     << " pktid = " << p_vci_tgt.pktid.read()
    1033                     << " wdata = " << std::hex << p_vci_tgt.wdata.read()
    1034                     << " be = " << p_vci_tgt.be.read()
    1035                     << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
    1036         }
     1029if(m_debug_tgt_cmd_fsm)
     1030std::cout << "  <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:"
     1031          << " address = " << std::hex << p_vci_tgt.address.read()
     1032          << " / srcid = " << p_vci_tgt.srcid.read()
     1033          << " / trdid = " << p_vci_tgt.trdid.read()
     1034          << " / pktid = " << p_vci_tgt.pktid.read()
     1035          << " / wdata = " << p_vci_tgt.wdata.read()
     1036          << " / be = " << p_vci_tgt.be.read()
     1037          << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
    10371038#endif
    10381039        cmd_write_fifo_put = true;
    … …  
    10571058
    10581059#if DEBUG_MEMC_TGT_CMD
    1059         if(m_debug_tgt_cmd_fsm)
    1060         {
    1061           std::cout << "  <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
    1062                     << " address = " << std::hex << p_vci_tgt.address.read()
    1063                     << " srcid = " << std::dec << p_vci_tgt.srcid.read()
    1064                     << " trdid = " << p_vci_tgt.trdid.read()
    1065                     << " pktid = " << p_vci_tgt.pktid.read()
    1066                     << " wdata = " << std::hex << p_vci_tgt.wdata.read()
    1067                     << " be = " << p_vci_tgt.be.read()
    1068                     << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
    1069         }
     1060if(m_debug_tgt_cmd_fsm)
     1061std::cout << "  <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
     1062          << " address = " << std::hex << p_vci_tgt.address.read()
     1063          << " srcid = " << p_vci_tgt.srcid.read()
     1064          << " trdid = " << p_vci_tgt.trdid.read()
     1065          << " pktid = " << p_vci_tgt.pktid.read()
     1066          << " wdata = " << p_vci_tgt.wdata.read()
     1067          << " be = " << p_vci_tgt.be.read()
     1068          << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
    10701069#endif
    10711070        cmd_cas_fifo_put = true;
    … …  
    12931292#if DEBUG_MEMC_READ
    12941293if(m_debug_read_fsm)
    1295 std::cout << "  <MEMC " << name() << " READ_IDLE> Read request:"
    1296           << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
    1297           << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
    1298           << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read()
     1294std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
     1295          << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
     1296          << " / srcid = " << m_cmd_read_srcid_fifo.read()
     1297          << " / trdid = " << m_cmd_read_trdid_fifo.read()
     1298          << " / pktid = " << m_cmd_read_pktid_fifo.read()
    12991299          << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
    13001300#endif
    … …  
    14621462          << " / set = " << std::dec << set
    14631463          << " / way = " << way
    1464           << " / owner_id = " << entry.owner.srcid
    1465           << " / owner_ins = " << entry.owner.inst
     1464          << " / owner_id = " << std::hex << entry.owner.srcid
     1465          << " / owner_ins = " << std::dec << entry.owner.inst
    14661466          << " / count = " << entry.count
    14671467          << " / is_cnt = " << entry.is_cnt << std::endl;
    … …  
    16261626if(m_debug_read_fsm)
    16271627std::cout << "  <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:"
    1628           << " owner_id = " << heap_entry.owner.srcid
    1629           << " owner_ins = " << heap_entry.owner.inst << std::endl;
     1628          << " owner_id = " << std::hex << heap_entry.owner.srcid
     1629          << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl;
    16301630#endif
    16311631      }
    … …  
    17141714if(m_debug_read_fsm)
    17151715std::cout << "  <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:"
    1716           << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read()
     1716          << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read()
    17171717          << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
    17181718          << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
    … …  
    24972497
    24982498#if DEBUG_MEMC_WRITE
    2499         if(m_debug_write_fsm)
    2500         {
    2501           std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
    2502                     << std::dec << r_write_srcid.read() << std::endl;
    2503           if(m_cmd_write_addr_fifo.rok())
    2504           {
    2505             std::cout << "                    New Write request: "
    2506                       << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
    2507                       << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
    2508                       << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
    2509           }
    2510         }
     2499if(m_debug_write_fsm)
     2500{
     2501    std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM"
     2502              << " : rsrcid = " << std::hex << r_write_srcid.read() << std::endl;
     2503    if(m_cmd_write_addr_fifo.rok())
     2504    {
     2505        std::cout << "                    New Write request: "
     2506                  << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
     2507                  << " / address = " << m_cmd_write_addr_fifo.read()
     2508                  << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
     2509    }
     2510}
    25112511#endif
    25122512      }
    … …  
    25212521
    25222522#if DEBUG_MEMC_WRITE
    2523         if(m_debug_write_fsm)
    2524         {
    2525           std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
    2526         }
     2523if(m_debug_write_fsm)
     2524std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
    25272525#endif
    25282526        size_t  hit_index = 0;
    … …  
    25572555    case WRITE_WAIT:  // release the locks protecting the shared ressources
    25582556    {
     2557
    25592558#if DEBUG_MEMC_WRITE
    2560       if(m_debug_write_fsm)
    2561       {
    2562         std::cout << "  <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl;
    2563       }
     2559if(m_debug_write_fsm)
     2560std::cout << "  <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl;
    25642561#endif
    25652562      r_write_fsm = WRITE_DIR_REQ;
    … …  
    25952592
    25962593#if DEBUG_MEMC_WRITE
    2597         if(m_debug_write_fsm)
    2598         {
    2599           std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
    2600         }
     2594if(m_debug_write_fsm)
     2595std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
    26012596#endif
    26022597      }
    … …  
    26242619
    26252620#if DEBUG_MEMC_WRITE
    2626         if(m_debug_write_fsm)
    2627         {
    2628           std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
    2629           m_trt.print(r_write_trt_index.read());
    2630         }
     2621if(m_debug_write_fsm)
     2622std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
    26312623#endif
    26322624      }
    … …  
    26462638
    26472639#if DEBUG_MEMC_WRITE
    2648         if(m_debug_write_fsm)
    2649         {
    2650           std::cout << "  <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
    2651         }
     2640if(m_debug_write_fsm)
     2641std::cout << "  <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
    26522642#endif
    26532643      }
    … …  
    26732663
    26742664#if DEBUG_MEMC_WRITE
    2675         if(m_debug_write_fsm)
    2676         {
    2677           std::cout << "  <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT : wok = "
    2678                     << wok << " / index = " << wok_index << std::endl;
    2679         }
     2665if(m_debug_write_fsm)
     2666std::cout << "  <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT"
     2667          << " : wok = " << wok << " / index = " << wok_index << std::endl;
    26802668#endif
    26812669      }
    … …  
    27072695
    27082696#if DEBUG_MEMC_WRITE
    2709         if(m_debug_write_fsm)
    2710         {
    2711           if(wok)
    2712           {
    2713             std::cout << "  <MEMC " << name() << " WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "
    2714                       << " nb_copies = " << r_write_count.read() << std::endl;
    2715           }
    2716         }
     2697if( m_debug_write_fsm and wok )
     2698std::cout << "  <MEMC " << name() << " WRITE_BC_UPT_LOCK> Register broadcast inval in UPT"
     2699          << " / nb_copies = " << r_write_count.read() << std::endl;
    27172700#endif
    27182701        r_write_upt_index = index;
    … …  
    27712754
    27722755#if DEBUG_MEMC_WRITE
    2773       if(m_debug_write_fsm)
    2774       {
    2775         std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
    2776                   << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
    2777       }
     2756if(m_debug_write_fsm)
     2757std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
     2758          << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
    27782759#endif
    27792760      r_write_fsm = WRITE_BC_CC_SEND;
    … …  
    34283409          << " way = " << std::dec << way
    34293410          << " / set = " << set
    3430           << " / owner_id = " << entry.owner.srcid
    3431           << " / owner_ins = " << entry.owner.inst
     3411          << " / owner_id = " << std::hex << entry.owner.srcid
     3412          << " / owner_ins = " << std::dec << entry.owner.inst
    34323413          << " / count = " << entry.count
    34333414          << " / is_cnt = " << entry.is_cnt << std::endl;
    … …  
    35053486std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_RSP>"
    35063487          << " Request the TGT_RSP FSM to return data:"
    3507           << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid
     3488          << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid
    35083489          << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
    35093490          << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
    … …  
    45154496            << " CLEANUP_WRITE_RSP> Send a response to a previous"
    45164497            << " write request waiting for coherence transaction completion: "
    4517             << " rsrcid = "   << std::dec << r_cleanup_write_srcid.read()
    4518             << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read()
     4498            << " rsrcid = "   << std::hex << r_cleanup_write_srcid.read()
     4499            << " / rtrdid = " << std::hex << r_cleanup_write_trdid.read()
    45194500            << std::endl;
    45204501      }
    … …  
    47224703
    47234704#if DEBUG_MEMC_CAS
    4724       if(m_debug_cas_fsm)
    4725       {
    4726         std::cout
    4727           << "  <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from "
    4728           << " cache and store it in buffer"
    4729           << std::endl;
    4730       }
     4705if(m_debug_cas_fsm)
     4706std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from "
     4707          << " cache and store it in buffer" << std::endl;
    47314708#endif
    47324709      break;
    … …  
    47594736
    47604737#if DEBUG_MEMC_CAS
    4761       if(m_debug_cas_fsm)
    4762       {
    4763         std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old"
    4764                   << " and the new data"
    4765                   << " / expected value = " << r_cas_rdata[0].read()
    4766                   << " / actual value = "   << r_cas_data[word].read()
    4767                   << " / forced_fail = "    << forced_fail << std::endl;
    4768       }
     4738if(m_debug_cas_fsm)
     4739std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old"
     4740          << " and the new data"
     4741          << " / expected value = " << r_cas_rdata[0].read()
     4742          << " / actual value = "   << r_cas_data[word].read()
     4743          << " / forced_fail = "    << forced_fail << std::endl;
    47694744#endif
    47704745      break;
    … …  
    48214796
    48224797#if DEBUG_MEMC_CAS
    4823         if(m_debug_cas_fsm)
    4824         {
    4825           std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:"
    4826                     << " way = " << std::dec << way
    4827                     << " / set = " << set
    4828                     << " / word = " << word
    4829                     << " / value = " << r_cas_wdata.read()
    4830                     << " / count = " << r_cas_count.read() << std::endl;
    4831           std::cout << "  <MEMC "
    4832                     << name() << " CAS_DIR_HIT_WRITE> global_llsc_table SW access" << std::endl;
    4833         }
     4798if(m_debug_cas_fsm)
     4799std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:"
     4800          << " way = " << std::dec << way
     4801          << " / set = " << set
     4802          << " / word = " << word
     4803          << " / value = " << r_cas_wdata.read()
     4804          << " / count = " << r_cas_count.read()
     4805          << " / global_llsc_table access" << std::endl;
    48344806#endif
    48354807      }
    … …  
    48934865
    48944866#if DEBUG_MEMC_CAS
    4895         if(m_debug_cas_fsm)
    4896         {
    4897           std::cout << "  <MEMC " << name()
    4898                     << " CAS_UPT_LOCK> Register multi-update transaction in UPT"
    4899                     << " / wok = " << wok
    4900                     << " / nline  = " << std::hex << nline
    4901                     << " / count = " << nb_copies << std::endl;
    4902         }
     4867if(m_debug_cas_fsm)
     4868std::cout << "  <MEMC " << name()
     4869          << " CAS_UPT_LOCK> Register multi-update transaction in UPT"
     4870          << " / wok = " << wok
     4871          << " / nline  = " << std::hex << nline
     4872          << " / count = " << nb_copies << std::endl;
    49034873#endif
    49044874      }
    … …  
    51255095          r_cas_upt_index = index;
    51265096          r_cas_fsm = CAS_BC_DIR_INVAL;
     5097
    51275098#if DEBUG_MEMC_CAS
    5128           if(m_debug_cas_fsm)
    5129           {
    5130             std::cout << "  <MEMC " << name() << " CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
    5131                       << " / nline = " << nline
    5132                       << " / count = " << nb_copies
    5133                       << " / upt_index = " << index << std::endl;
    5134           }
     5099if(m_debug_cas_fsm)
     5100std::cout << "  <MEMC " << name()
     5101          << " CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
     5102          << " / nline = " << std::hex << nline
     5103          << " / count = " << std::dec << nb_copies
     5104          << " / upt_index = " << index << std::endl;
    51355105#endif
    51365106        }
    … …  
    51425112      break;
    51435113    }
    5144     //////////////////
     5114    //////////////////////
    51455115    case CAS_BC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
    51465116    {
    … …  
    51835153
    51845154#if DEBUG_MEMC_CAS
    5185         if(m_debug_cas_fsm)
    5186         {
    5187           std::cout << "  <MEMC " << name() << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
    5188                     << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]
    5189                     << " / set = " << std::dec << set << " / way = " << way << std::endl;
    5190         }
     5155if(m_debug_cas_fsm)
     5156std::cout << "  <MEMC " << name()
     5157          << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
     5158          << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]
     5159          << " / set = " << std::dec << set << " / way = " << way << std::endl;
    51915160#endif
    51925161      }
    … …  
    52285197
    52295198#if DEBUG_MEMC_CAS
    5230         if(m_debug_cas_fsm)
    5231         {
    5232           std::cout << "  <MEMC " << name() << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
    5233                     << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
    5234                     << " / trt_index = " << r_cas_trt_index.read() << std::endl;
    5235         }
     5199if(m_debug_cas_fsm)
     5200std::cout << "  <MEMC " << name()
     5201          << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
     5202          << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
     5203          << " / trt_index = " << r_cas_trt_index.read() << std::endl;
    52365204#endif
    52375205      }
    52385206      else
    52395207      {
    5240         std::cout << "MEM_CACHE, CAS_BC_XRAM_REQ state : request should not have been previously set"
    5241                   << std::endl;
     5208        std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state"
     5209                  << " : request should not have been previously set" << std::endl;
    52425210      }
    52435211      break;
    … …  
    52585226
    52595227#if DEBUG_MEMC_CAS
    5260         if(m_debug_cas_fsm)
    5261         {
    5262           std::cout << "  <MEMC " << name() << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
    5263         }
     5228if(m_debug_cas_fsm)
     5229std::cout << "  <MEMC " << name()
     5230          << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
    52645231#endif
    52655232      }
    … …  
    52815248
    52825249#if DEBUG_MEMC_CAS
    5283         if(m_debug_cas_fsm)
    5284         {
    5285           std::cout << "  <MEMC " << name() << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
    5286         }
     5250if(m_debug_cas_fsm)
     5251std::cout << "  <MEMC " << name()
     5252          << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
    52875253#endif
    52885254      }
    … …  
    56495615
    56505616#if DEBUG_MEMC_CC_SEND
    5651         if(m_debug_cc_send_fsm)
    5652         {
    5653           std::cout
    5654             << "  <MEMC " << name()
    5655             << " CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid "
    5656             << r_cleanup_to_cc_send_srcid.read()
    5657             << std::endl;
    5658         }
     5617if(m_debug_cc_send_fsm)
     5618std::cout << "  <MEMC " << name()
     5619          << " CC_SEND_CLEANUP_ACK> Cleanup Ack for srcid "
     5620          << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl;
    56595621#endif
    56605622        break;
    … …  
    56925654
    56935655#if DEBUG_MEMC_CC_SEND
    5694         if(m_debug_cc_send_fsm)
    5695         {
    5696           std::cout
    5697             << "  <MEMC " << name()
    5698             << " CC_SEND_XRAM_RSP_INVAL_NLINE> Broadcast-Inval for line "
    5699             << r_xram_rsp_to_cc_send_nline.read()
    5700             << std::endl;
    5701         }
     5656if(m_debug_cc_send_fsm)
     5657std::cout << "  <MEMC " << name()
     5658          << " CC_SEND_XRAM_RSP_INVAL_NLINE> BC-Inval for line "
     5659          << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl;
    57025660#endif
    57035661        break;
    … …  
    57245682
    57255683#if DEBUG_MEMC_CC_SEND
    5726         if(m_debug_cc_send_fsm)
    5727         {
    5728           std::cout
    5729             << "  <MEMC " << name()
    5730             << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> Broadcast-Inval for line "
    5731             << r_xram_rsp_to_cc_send_nline.read()
    5732             << std::endl;
    5733         }
     5684if(m_debug_cc_send_fsm)
     5685std::cout << "  <MEMC " << name()
     5686          << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> BC-Inval for line "
     5687          << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl;
    57345688#endif
    57355689        break;
    … …  
    57565710
    57575711#if DEBUG_MEMC_CC_SEND
    5758         if(m_debug_cc_send_fsm)
    5759         {
    5760           std::cout
    5761             << "  <MEMC " << name()
    5762             << " CC_SEND_WRITE_BRDCAST_NLINE> Broadcast-Inval for line "
    5763             << r_write_to_cc_send_nline.read()
    5764             << std::endl;
    5765         }
     5712if(m_debug_cc_send_fsm)
     5713std::cout << "  <MEMC " << name()
     5714          << " CC_SEND_WRITE_BRDCAST_NLINE> BC-Inval for line "
     5715          << std::hex << r_write_to_cc_send_nline.read() << std::endl;
    57665716#endif
    57675717        break;
    … …  
    61536103  std::cout
    61546104    << "  <MEMC " << name() << " TGT_RSP_READ> Read response"
    6155     << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read()
     6105    << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read()
    61566106    << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read()
    61576107    << " / rpktid = " << r_read_to_tgt_rsp_pktid.read()
    6158     << " / rdata = " << std::hex << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
     6108    << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
    61596109    << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
    61606110}
    … …  
    61936143
    61946144#if DEBUG_MEMC_TGT_RSP
    6195         if(m_debug_tgt_rsp_fsm)
    6196         {
    6197           std::cout << "  <MEMC " << name() << " TGT_RSP_WRITE> Write response"
    6198                     << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read()
    6199                     << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read()
    6200                     << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl;
    6201         }
     6145if(m_debug_tgt_rsp_fsm)
     6146std::cout << "  <MEMC " << name() << " TGT_RSP_WRITE> Write response"
     6147          << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read()
     6148          << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read()
     6149          << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl;
    62026150#endif
    62036151        r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
    … …  
    62136161
    62146162#if DEBUG_MEMC_TGT_RSP
    6215         if(m_debug_tgt_rsp_fsm)
    6216         {
    6217           std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
    6218                     << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read()
    6219                     << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
    6220                     << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl;
    6221         }
     6163if(m_debug_tgt_rsp_fsm)
     6164std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
     6165          << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read()
     6166          << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
     6167          << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl;
    62226168#endif
    62236169        r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
    … …  
    62336179
    62346180#if DEBUG_MEMC_TGT_RSP
    6235         if(m_debug_tgt_rsp_fsm)
    6236         {
    6237           std::cout << "  <MEMC " << name() << " TGT_RSP_CAS> CAS response"
    6238                     << " / rsrcid = " << std::dec << r_cas_to_tgt_rsp_srcid.read()
    6239                     << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read()
    6240                     << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl;
    6241         }
     6181if(m_debug_tgt_rsp_fsm)
     6182std::cout << "  <MEMC " << name() << " TGT_RSP_CAS> CAS response"
     6183          << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read()
     6184          << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read()
     6185          << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl;
    62426186#endif
    62436187        r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE;
    … …  
    62556199#if DEBUG_MEMC_TGT_RSP
    62566200if( m_debug_tgt_rsp_fsm )
    6257 {
    6258   std::cout
    6259     << "  <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access"
    6260     << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read()
    6261     << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
    6262     << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read()
    6263     << " / rdata = " << std::hex << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
    6264     << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
    6265 }
     6201std::cout << "  <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access"
     6202          << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read()
     6203          << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
     6204          << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read()
     6205          << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
     6206          << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
    62666207#endif
    62676208        uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1;
    … …  
    62996240
    63006241#if DEBUG_MEMC_TGT_RSP
    6301         if(m_debug_tgt_rsp_fsm)
    6302         {
    6303           std::cout << "  <MEMC " << name() << " TGT_RSP_INIT> Write response after coherence transaction"
    6304                     << " / rsrcid = " << std::dec << r_multi_ack_to_tgt_rsp_srcid.read()
    6305                     << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read()
    6306                     << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl;
    6307         }
     6242if(m_debug_tgt_rsp_fsm)
     6243std::cout << "  <MEMC " << name() << " TGT_RSP_INIT> Write response after coherence transaction"
     6244          << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read()
     6245          << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read()
     6246          << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl;
    63086247#endif
    63096248        r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
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