Index: /trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- /trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 421) +++ /trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 422) @@ -9,6 +9,10 @@ tmpl_parameters = [ - parameter.Module('vci_param_int'), - parameter.Module('vci_param_ext'), + parameter.Module('vci_param_int', + default = 'caba:vci_param', + cell_size = parameter.Reference('memc_cell_size_int')), + parameter.Module('vci_param_ext', + default = 'caba:vci_param', + cell_size = parameter.Reference('memc_cell_size_ext')), parameter.Int('dspin_in_width'), parameter.Int('dspin_out_width'), @@ -22,5 +26,7 @@ ], - implementation_files = [ '../source/src/vci_mem_cache.cpp' ], + implementation_files = [ + '../source/src/vci_mem_cache.cpp' + ], uses = [ Index: /trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 421) +++ /trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 422) @@ -13,5 +13,6 @@ //////////////////////////////////////////////////////////////////////// -class TransactionTabEntry { +class TransactionTabEntry +{ typedef sc_dt::sc_uint<64> wide_data_t; typedef sc_dt::sc_uint<40> addr_t; @@ -84,5 +85,6 @@ // The print() function prints the entry //////////////////////////////////////////////////////////////////// - void print(){ + void print() + { std::cout << "valid = " << valid << std::endl; std::cout << "xram_read = " << xram_read << std::endl; @@ -137,5 +139,6 @@ // The transaction tab //////////////////////////////////////////////////////////////////////// -class TransactionTab{ +class TransactionTab +{ typedef sc_dt::sc_uint<64> wide_data_t; typedef sc_dt::sc_uint<40> addr_t; @@ -144,5 +147,6 @@ private: - size_t size_tab; // The size of the tab + const std::string tab_name; // the name for logs + size_t size_tab; // the size of the tab data_t be_to_mask(be_t be) @@ -176,9 +180,13 @@ } - TransactionTab(size_t n_entries, size_t n_words) - { - size_tab = n_entries; + TransactionTab(const std::string &name, + size_t n_entries, + size_t n_words ) + : tab_name( name ), + size_tab( n_entries ) + { tab = new TransactionTabEntry[size_tab]; - for ( size_t i=0; i= size_tab ) + { + std::cout << "VCI_MEM_CACHE ERRROR " << tab_name + << " TRT entry out of range in write_rsp()" << std::endl; + exit(0); + } + if ( word > tab[index].wdata_be.size() ) + { + std::cout << "VCI_MEM_CACHE ERRROR " << tab_name + << " Bad word_index in write_rsp() in TRT" << std::endl; + exit(0); + } + if ( not tab[index].valid ) + { + std::cout << "VCI_MEM_CACHE ERRROR " << tab_name + << " TRT Entry invalid in write_rsp()" << std::endl; + exit(0); + } + if ( not tab[index].xram_read ) + { + std::cout << "VCI_MEM_CACHE ERRROR " << tab_name + << " TRT entry is not an XRAM GET in write_rsp()" << std::endl; + exit(0); + } // first 32 bits word Index: /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 421) +++ /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 422) @@ -322,5 +322,5 @@ m_debug_ok( debug_ok ), m_trt_lines(trt_lines), - m_trt(trt_lines, nwords), + m_trt(this->name(), trt_lines, nwords), m_upt_lines(upt_lines), m_upt(upt_lines), @@ -414,4 +414,6 @@ r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") { + std::cout << " - Building VciMemCache : " << name << std::endl; + assert(IS_POW_OF_2(nsets)); assert(IS_POW_OF_2(nwords)); @@ -423,16 +425,16 @@ // check Transaction table size assert((uint32_log2(trt_lines) <= vci_param_ext::T) and - "MEMC ERROR : Need more bits for VCI TRDID field"); + "MEMC ERROR : Need more bits for VCI TRDID field"); // check internal and external data width assert( (vci_param_int::B == 4 ) and - "MEMC ERROR : VCI internal data width must be 32 bits"); + "MEMC ERROR : VCI internal data width must be 32 bits"); assert( (vci_param_ext::B == 8) and - "MEMC ERROR : VCI external data width must be 64 bits"); + "MEMC ERROR : VCI external data width must be 64 bits"); // Check coherence between internal & external addresses assert( (vci_param_int::N == vci_param_ext::N) and - "MEMC ERROR : VCI internal & external addresses must have the same width"); + "MEMC ERROR : VCI internal & external addresses must have the same width"); // Get the segments associated to the MemCache @@ -442,4 +444,7 @@ for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) { + std::cout << " => segment " << seg->name() + << " / base = " << std::hex << seg->baseAddress() + << " / size = " << seg->size() << std::endl; m_nseg++; } @@ -999,13 +1004,11 @@ #if DEBUG_MEMC_TGT_CMD - if(m_debug_tgt_cmd_fsm) - { - std::cout << " Push into read_fifo:" - << " address = " << std::hex << p_vci_tgt.address.read() - << " srcid = " << std::dec << p_vci_tgt.srcid.read() - << " trdid = " << p_vci_tgt.trdid.read() - << " pktid = " << p_vci_tgt.pktid.read() - << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; - } +if(m_debug_tgt_cmd_fsm) +std::cout << " Push into read_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / srcid = " << p_vci_tgt.srcid.read() + << " / trdid = " << p_vci_tgt.trdid.read() + << " / pktid = " << p_vci_tgt.pktid.read() + << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; #endif cmd_read_fifo_put = true; @@ -1024,15 +1027,13 @@ #if DEBUG_MEMC_TGT_CMD - if(m_debug_tgt_cmd_fsm) - { - std::cout << " Push into write_fifo:" - << " address = " << std::hex << p_vci_tgt.address.read() - << " srcid = " << std::dec << p_vci_tgt.srcid.read() - << " trdid = " << p_vci_tgt.trdid.read() - << " pktid = " << p_vci_tgt.pktid.read() - << " wdata = " << std::hex << p_vci_tgt.wdata.read() - << " be = " << p_vci_tgt.be.read() - << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; - } +if(m_debug_tgt_cmd_fsm) +std::cout << " Push into write_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / srcid = " << p_vci_tgt.srcid.read() + << " / trdid = " << p_vci_tgt.trdid.read() + << " / pktid = " << p_vci_tgt.pktid.read() + << " / wdata = " << p_vci_tgt.wdata.read() + << " / be = " << p_vci_tgt.be.read() + << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; #endif cmd_write_fifo_put = true; @@ -1057,15 +1058,13 @@ #if DEBUG_MEMC_TGT_CMD - if(m_debug_tgt_cmd_fsm) - { - std::cout << " Pushing command into cmd_cas_fifo:" - << " address = " << std::hex << p_vci_tgt.address.read() - << " srcid = " << std::dec << p_vci_tgt.srcid.read() - << " trdid = " << p_vci_tgt.trdid.read() - << " pktid = " << p_vci_tgt.pktid.read() - << " wdata = " << std::hex << p_vci_tgt.wdata.read() - << " be = " << p_vci_tgt.be.read() - << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; - } +if(m_debug_tgt_cmd_fsm) +std::cout << " Pushing command into cmd_cas_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " srcid = " << p_vci_tgt.srcid.read() + << " trdid = " << p_vci_tgt.trdid.read() + << " pktid = " << p_vci_tgt.pktid.read() + << " wdata = " << p_vci_tgt.wdata.read() + << " be = " << p_vci_tgt.be.read() + << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; #endif cmd_cas_fifo_put = true; @@ -1293,8 +1292,9 @@ #if DEBUG_MEMC_READ if(m_debug_read_fsm) -std::cout << " Read request:" - << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read() +std::cout << " Read request" + << " : address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << m_cmd_read_srcid_fifo.read() + << " / trdid = " << m_cmd_read_trdid_fifo.read() + << " / pktid = " << m_cmd_read_pktid_fifo.read() << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; #endif @@ -1462,6 +1462,6 @@ << " / set = " << std::dec << set << " / way = " << way - << " / owner_id = " << entry.owner.srcid - << " / owner_ins = " << entry.owner.inst + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst << " / count = " << entry.count << " / is_cnt = " << entry.is_cnt << std::endl; @@ -1626,6 +1626,6 @@ if(m_debug_read_fsm) std::cout << " Add an entry in the heap:" - << " owner_id = " << heap_entry.owner.srcid - << " owner_ins = " << heap_entry.owner.inst << std::endl; + << " owner_id = " << std::hex << heap_entry.owner.srcid + << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl; #endif } @@ -1714,5 +1714,5 @@ if(m_debug_read_fsm) std::cout << " Request TGT_RSP FSM to return data:" - << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read() + << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() << " / address = " << std::hex << m_cmd_read_addr_fifo.read() << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; @@ -2497,16 +2497,16 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Post a request to TGT_RSP FSM: rsrcid = " - << std::dec << r_write_srcid.read() << std::endl; - if(m_cmd_write_addr_fifo.rok()) - { - std::cout << " New Write request: " - << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_write_addr_fifo.read() - << " / data = " << m_cmd_write_data_fifo.read() << std::endl; - } - } +if(m_debug_write_fsm) +{ + std::cout << " Post a request to TGT_RSP FSM" + << " : rsrcid = " << std::hex << r_write_srcid.read() << std::endl; + if(m_cmd_write_addr_fifo.rok()) + { + std::cout << " New Write request: " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; + } +} #endif } @@ -2521,8 +2521,6 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Check the TRT" << std::endl; - } +if(m_debug_write_fsm) +std::cout << " Check the TRT" << std::endl; #endif size_t hit_index = 0; @@ -2557,9 +2555,8 @@ case WRITE_WAIT: // release the locks protecting the shared ressources { + #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Releases the locks before retry" << std::endl; - } +if(m_debug_write_fsm) +std::cout << " Releases the locks before retry" << std::endl; #endif r_write_fsm = WRITE_DIR_REQ; @@ -2595,8 +2592,6 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Set a new entry in TRT" << std::endl; - } +if(m_debug_write_fsm) +std::cout << " Set a new entry in TRT" << std::endl; #endif } @@ -2624,9 +2619,6 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Modify an existing entry in TRT" << std::endl; - m_trt.print(r_write_trt_index.read()); - } +if(m_debug_write_fsm) +std::cout << " Modify an existing entry in TRT" << std::endl; #endif } @@ -2646,8 +2638,6 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Post a GET request to the IXR_CMD FSM" << std::endl; - } +if(m_debug_write_fsm) +std::cout << " Post a GET request to the IXR_CMD FSM" << std::endl; #endif } @@ -2673,9 +2663,7 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Check TRT : wok = " - << wok << " / index = " << wok_index << std::endl; - } +if(m_debug_write_fsm) +std::cout << " Check TRT" + << " : wok = " << wok << " / index = " << wok_index << std::endl; #endif } @@ -2707,12 +2695,7 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - if(wok) - { - std::cout << " Register the broadcast inval in UPT / " - << " nb_copies = " << r_write_count.read() << std::endl; - } - } +if( m_debug_write_fsm and wok ) +std::cout << " Register broadcast inval in UPT" + << " / nb_copies = " << r_write_count.read() << std::endl; #endif r_write_upt_index = index; @@ -2771,9 +2754,7 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Invalidate the directory entry: @ = " - << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; - } +if(m_debug_write_fsm) +std::cout << " Invalidate the directory entry: @ = " + << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; #endif r_write_fsm = WRITE_BC_CC_SEND; @@ -3428,6 +3409,6 @@ << " way = " << std::dec << way << " / set = " << set - << " / owner_id = " << entry.owner.srcid - << " / owner_ins = " << entry.owner.inst + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst << " / count = " << entry.count << " / is_cnt = " << entry.is_cnt << std::endl; @@ -3505,5 +3486,5 @@ std::cout << " " << " Request the TGT_RSP FSM to return data:" - << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid + << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; @@ -4515,6 +4496,6 @@ << " CLEANUP_WRITE_RSP> Send a response to a previous" << " write request waiting for coherence transaction completion: " - << " rsrcid = " << std::dec << r_cleanup_write_srcid.read() - << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read() + << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() + << " / rtrdid = " << std::hex << r_cleanup_write_trdid.read() << std::endl; } @@ -4722,11 +4703,7 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout - << " Read data from " - << " cache and store it in buffer" - << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Read data from " + << " cache and store it in buffer" << std::endl; #endif break; @@ -4759,12 +4736,10 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout << " Compare the old" - << " and the new data" - << " / expected value = " << r_cas_rdata[0].read() - << " / actual value = " << r_cas_data[word].read() - << " / forced_fail = " << forced_fail << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Compare the old" + << " and the new data" + << " / expected value = " << r_cas_rdata[0].read() + << " / actual value = " << r_cas_data[word].read() + << " / forced_fail = " << forced_fail << std::endl; #endif break; @@ -4821,15 +4796,12 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout << " Update cache:" - << " way = " << std::dec << way - << " / set = " << set - << " / word = " << word - << " / value = " << r_cas_wdata.read() - << " / count = " << r_cas_count.read() << std::endl; - std::cout << " global_llsc_table SW access" << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Update cache:" + << " way = " << std::dec << way + << " / set = " << set + << " / word = " << word + << " / value = " << r_cas_wdata.read() + << " / count = " << r_cas_count.read() + << " / global_llsc_table access" << std::endl; #endif } @@ -4893,12 +4865,10 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout << " Register multi-update transaction in UPT" - << " / wok = " << wok - << " / nline = " << std::hex << nline - << " / count = " << nb_copies << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Register multi-update transaction in UPT" + << " / wok = " << wok + << " / nline = " << std::hex << nline + << " / count = " << nb_copies << std::endl; #endif } @@ -5125,12 +5095,12 @@ r_cas_upt_index = index; r_cas_fsm = CAS_BC_DIR_INVAL; + #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout << " Register a broadcast inval transaction in UPT" - << " / nline = " << nline - << " / count = " << nb_copies - << " / upt_index = " << index << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Register a broadcast inval transaction in UPT" + << " / nline = " << std::hex << nline + << " / count = " << std::dec << nb_copies + << " / upt_index = " << index << std::endl; #endif } @@ -5142,5 +5112,5 @@ break; } - ////////////////// + ////////////////////// case CAS_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry { @@ -5183,10 +5153,9 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout << " Register the PUT in TRT and invalidate DIR entry" - << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())] - << " / set = " << std::dec << set << " / way = " << way << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Register the PUT in TRT and invalidate DIR entry" + << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())] + << " / set = " << std::dec << set << " / way = " << way << std::endl; #endif } @@ -5228,16 +5197,15 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex - << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] - << " / trt_index = " << r_cas_trt_index.read() << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex + << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] + << " / trt_index = " << r_cas_trt_index.read() << std::endl; #endif } else { - std::cout << "MEM_CACHE, CAS_BC_XRAM_REQ state : request should not have been previously set" - << std::endl; + std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state" + << " : request should not have been previously set" << std::endl; } break; @@ -5258,8 +5226,7 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout << " Request TGT_RSP to send a failure response" << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Request TGT_RSP to send a failure response" << std::endl; #endif } @@ -5281,8 +5248,7 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) - { - std::cout << " Request TGT_RSP to send a success response" << std::endl; - } +if(m_debug_cas_fsm) +std::cout << " Request TGT_RSP to send a success response" << std::endl; #endif } @@ -5649,12 +5615,8 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug_cc_send_fsm) - { - std::cout - << " Cleanup Acknowledgement for srcid " - << r_cleanup_to_cc_send_srcid.read() - << std::endl; - } +if(m_debug_cc_send_fsm) +std::cout << " Cleanup Ack for srcid " + << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl; #endif break; @@ -5692,12 +5654,8 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug_cc_send_fsm) - { - std::cout - << " Broadcast-Inval for line " - << r_xram_rsp_to_cc_send_nline.read() - << std::endl; - } +if(m_debug_cc_send_fsm) +std::cout << " BC-Inval for line " + << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; #endif break; @@ -5724,12 +5682,8 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug_cc_send_fsm) - { - std::cout - << " Broadcast-Inval for line " - << r_xram_rsp_to_cc_send_nline.read() - << std::endl; - } +if(m_debug_cc_send_fsm) +std::cout << " BC-Inval for line " + << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; #endif break; @@ -5756,12 +5710,8 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug_cc_send_fsm) - { - std::cout - << " Broadcast-Inval for line " - << r_write_to_cc_send_nline.read() - << std::endl; - } +if(m_debug_cc_send_fsm) +std::cout << " BC-Inval for line " + << std::hex << r_write_to_cc_send_nline.read() << std::endl; #endif break; @@ -6153,8 +6103,8 @@ std::cout << " Read response" - << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read() + << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read() << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() << " / rpktid = " << r_read_to_tgt_rsp_pktid.read() - << " / rdata = " << std::hex << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() + << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; } @@ -6193,11 +6143,9 @@ #if DEBUG_MEMC_TGT_RSP - if(m_debug_tgt_rsp_fsm) - { - std::cout << " Write response" - << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; - } +if(m_debug_tgt_rsp_fsm) +std::cout << " Write response" + << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; #endif r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE; @@ -6213,11 +6161,9 @@ #if DEBUG_MEMC_TGT_RSP - if(m_debug_tgt_rsp_fsm) - { - std::cout << " Cleanup response" - << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; - } +if(m_debug_tgt_rsp_fsm) +std::cout << " Cleanup response" + << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; #endif r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE; @@ -6233,11 +6179,9 @@ #if DEBUG_MEMC_TGT_RSP - if(m_debug_tgt_rsp_fsm) - { - std::cout << " CAS response" - << " / rsrcid = " << std::dec << r_cas_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; - } +if(m_debug_tgt_rsp_fsm) +std::cout << " CAS response" + << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; #endif r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE; @@ -6255,13 +6199,10 @@ #if DEBUG_MEMC_TGT_RSP if( m_debug_tgt_rsp_fsm ) -{ - std::cout - << " Response following XRAM access" - << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() - << " / rdata = " << std::hex << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() - << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; -} +std::cout << " Response following XRAM access" + << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() + << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() + << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; #endif uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1; @@ -6299,11 +6240,9 @@ #if DEBUG_MEMC_TGT_RSP - if(m_debug_tgt_rsp_fsm) - { - std::cout << " Write response after coherence transaction" - << " / rsrcid = " << std::dec << r_multi_ack_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl; - } +if(m_debug_tgt_rsp_fsm) +std::cout << " Write response after coherence transaction" + << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl; #endif r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;