Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 427) +++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 429) @@ -290,7 +290,7 @@ const IntTab &srcid_x, // global index on external network const IntTab &tgtid_d, // global index on direct network - const size_t cc_global_id, // global index on cc network + const size_t cc_global_id, // global index on cc network const size_t nways, // number of ways per set - const size_t nsets, // number of associative sets + const size_t nsets, // number of associative sets const size_t nwords, // number of words in cache line const size_t max_copies, // max number of copies in heap @@ -430,5 +430,5 @@ assert( (vci_param_int::B == 4 ) and "MEMC ERROR : VCI internal data width must be 32 bits"); - + assert( (vci_param_ext::B == 8) and "MEMC ERROR : VCI external data width must be 64 bits"); @@ -437,5 +437,5 @@ assert( (vci_param_int::N == vci_param_ext::N) and "MEMC ERROR : VCI internal & external addresses must have the same width"); - + // Get the segments associated to the MemCache std::list::iterator seg; @@ -446,5 +446,5 @@ std::cout << " => segment " << seg->name() << " / base = " << std::hex << seg->baseAddress() - << " / size = " << seg->size() << std::endl; + << " / size = " << seg->size() << std::endl; m_nseg++; } @@ -509,6 +509,6 @@ //////////////////////////////////////////////// -tmpl(void) ::check_monitor( const char *buf, - addr_t addr, +tmpl(void) ::check_monitor( const char *buf, + addr_t addr, data_t data, bool read ) @@ -519,8 +519,8 @@ { if ( read ) std::cout << " Monitor MEMC Read "; - else std::cout << " Monitor MEMC Write "; - std::cout << buf + else std::cout << " Monitor MEMC Write "; + std::cout << buf << " / Address = " << std::hex << addr - << " / Data = " << data + << " / Data = " << data << " at cycle " << std::dec << m_cpt_cycles << std::endl; } @@ -780,5 +780,5 @@ bool cc_receive_to_cleanup_fifo_get = false; bool cc_receive_to_cleanup_fifo_put = false; - + bool cc_receive_to_multi_ack_fifo_get = false; bool cc_receive_to_multi_ack_fifo_put = false; @@ -830,5 +830,5 @@ std::cout << "---------------------------------------------" << std::dec << std::endl - << "MEM_CACHE " << name() + << "MEM_CACHE " << name() << " ; Time = " << m_cpt_cycles << std::endl << " - TGT_CMD FSM = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()] << std::endl @@ -969,5 +969,5 @@ // This test checks that the read does not cross a cache line limit. // It must not be taken into account when dealing with an LL CMD. - if(((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) && + if(((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) && (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ)) { @@ -1103,38 +1103,52 @@ // No CC_RECEIVE FSM request and no WRITE FSM request - if( not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read()) break; - - // handling WRITE FSM request to decrement update table response counter - // if no CC_RECEIVE FSM request + if( not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read()) + break; + + uint8_t updt_index; + + // handling WRITE FSM request to decrement update table response + // counter if no CC_RECEIVE FSM request if(not multi_ack_fifo_rok) { + updt_index = r_write_to_multi_ack_upt_index.read(); r_write_to_multi_ack_req = false; - r_multi_ack_upt_index = r_write_to_multi_ack_upt_index.read(); - r_multi_ack_fsm = MULTI_ACK_UPT_LOCK; - - break; - } - - // Handling CC_RECEIVE FSM request - uint64_t flit = m_cc_receive_to_multi_ack_fifo.read(); - - uint8_t updt_index = - DspinDhccpParam::dspin_get(flit, DspinDhccpParam::MULTI_ACK_UPDT_INDEX); - - assert( (updt_index < m_upt.size()) and - "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : index too large for UPT"); - - cc_receive_to_multi_ack_fifo_get = true; - r_multi_ack_upt_index = updt_index; - r_multi_ack_fsm = MULTI_ACK_UPT_LOCK; + } + // Handling CC_RECEIVE FSM request + else + { + uint64_t flit = m_cc_receive_to_multi_ack_fifo.read(); + updt_index = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + + cc_receive_to_multi_ack_fifo_get = true; + } + + assert((updt_index < m_upt.size()) and + "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : " + "index too large for UPT"); + + r_multi_ack_upt_index = updt_index; + r_multi_ack_fsm = MULTI_ACK_UPT_LOCK; #if DEBUG_MEMC_MULTI_ACK if(m_debug_multi_ack_fsm) { - std::cout - << " Response for UPT entry " - << updt_index - << std::endl; + if (multi_ack_fifo_rok) + { + std::cout + << " Response for UPT entry " + << updt_index + << std::endl; + } + else + { + std::cout + << " Write FSM request to decrement UPT entry " + << updt_index + << std::endl; + } } #endif @@ -1383,5 +1397,5 @@ else { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state" + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state" << "Bad DIR allocation" << std::endl; exit(0); @@ -1471,6 +1485,6 @@ { char buf[80]; - snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", - (int)m_cmd_read_srcid_fifo.read(), + snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", + (int)m_cmd_read_srcid_fifo.read(), (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0)); check_monitor(buf, m_cmd_read_addr_fifo.read(), r_read_data[0], true); @@ -1494,5 +1508,5 @@ #if DEBUG_MEMC_READ if(m_debug_read_fsm) -std::cout << " " +std::cout << " " << " Requesting HEAP lock " << std::endl; #endif @@ -1591,5 +1605,5 @@ else { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" << "Bad HEAP allocation" << std::endl; exit(0); @@ -1632,5 +1646,5 @@ else { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" << "Bad HEAP allocation" << std::endl; exit(0); @@ -1656,5 +1670,5 @@ else { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" << "Bad HEAP allocation" << std::endl; exit(0); @@ -1689,5 +1703,5 @@ else { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST" + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST" << "Bad HEAP allocation" << std::endl; exit(0); @@ -2139,5 +2153,5 @@ addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; char buf[80]; - snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", + snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", (int)r_write_srcid.read()); check_monitor(buf, address, r_write_data[word].read(), false); @@ -2219,8 +2233,8 @@ for(size_t word=0 ; word Post a broadcast request to CC_SEND FSM" << std::endl; } @@ -2814,5 +2828,5 @@ if(m_debug_write_fsm) { - std::cout << " Post a put request to IXR_CMD FSM" << std::endl; } @@ -3042,5 +3056,5 @@ if(m_debug_ixr_rsp_fsm) { - std::cout << " Response from XRAM to a put transaction" << std::endl; } @@ -3054,5 +3068,5 @@ if(m_debug_ixr_rsp_fsm) { - std::cout << " Response from XRAM to a get transaction" << std::endl; } @@ -3192,5 +3206,5 @@ // copy the TRT entry in the r_xram_rsp_trt_buf local buffer size_t index = r_xram_rsp_trt_index.read(); - r_xram_rsp_trt_buf.copy( m_trt.read(index) ); + r_xram_rsp_trt_buf.copy( m_trt.read(index) ); r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; @@ -3260,5 +3274,5 @@ else { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY" + std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY" << " bad TRT or DIR allocation" << std::endl; exit(0); @@ -3279,6 +3293,6 @@ if(m_debug_xram_rsp_fsm) std::cout << " " - << " Get acces to UPT, but line invalidation registered" - << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline + << " Get acces to UPT, but line invalidation registered" + << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline << " / index = " << std::dec << index << std::endl; #endif @@ -3410,5 +3424,5 @@ if(m_debug_xram_rsp_fsm) { -std::cout << " " +std::cout << " " << " Cache update: " << " way = " << std::dec << way @@ -3473,5 +3487,5 @@ r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; - for(size_t i=0; i < m_words; i++) + for(size_t i=0; i < m_words; i++) { r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; @@ -3541,5 +3555,5 @@ r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read(); r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read(); - for(size_t i=0; i Request a response error to TGT_RSP FSM:" << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; @@ -4792,5 +4806,5 @@ addr_t address = m_cmd_cas_addr_fifo.read(); char buf[80]; - snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", + snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", (int)m_cmd_cas_srcid_fifo.read()); check_monitor(buf, address, r_cas_wdata.read(), false); @@ -4807,5 +4821,5 @@ << " / word = " << word << " / value = " << r_cas_wdata.read() - << " / count = " << r_cas_count.read() + << " / count = " << r_cas_count.read() << " / global_llsc_table access" << std::endl; #endif @@ -4856,5 +4870,5 @@ addr_t address = m_cmd_cas_addr_fifo.read(); char buf[80]; - snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", + snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", (int)m_cmd_cas_srcid_fifo.read()); check_monitor(buf, address, r_cas_wdata.read(), false); @@ -5092,5 +5106,5 @@ addr_t address = m_cmd_cas_addr_fifo.read(); char buf[80]; - snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", + snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", (int)m_cmd_cas_srcid_fifo.read()); check_monitor(buf, address, r_cas_wdata.read(), false); @@ -5103,5 +5117,5 @@ #if DEBUG_MEMC_CAS if(m_debug_cas_fsm) -std::cout << " Register a broadcast inval transaction in UPT" << " / nline = " << std::hex << nline @@ -5159,5 +5173,5 @@ #if DEBUG_MEMC_CAS if(m_debug_cas_fsm) -std::cout << " Register the PUT in TRT and invalidate DIR entry" << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())] @@ -5203,5 +5217,5 @@ #if DEBUG_MEMC_CAS if(m_debug_cas_fsm) -std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()] @@ -5211,5 +5225,5 @@ else { - std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state" + std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state" << " : request should not have been previously set" << std::endl; } @@ -5232,5 +5246,5 @@ #if DEBUG_MEMC_CAS if(m_debug_cas_fsm) -std::cout << " Request TGT_RSP to send a failure response" << std::endl; #endif @@ -5254,5 +5268,5 @@ #if DEBUG_MEMC_CAS if(m_debug_cas_fsm) -std::cout << " Request TGT_RSP to send a success response" << std::endl; #endif @@ -5621,5 +5635,5 @@ #if DEBUG_MEMC_CC_SEND if(m_debug_cc_send_fsm) -std::cout << " Cleanup Ack for srcid " << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl; @@ -5660,5 +5674,5 @@ #if DEBUG_MEMC_CC_SEND if(m_debug_cc_send_fsm) -std::cout << " BC-Inval for line " << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; @@ -5688,5 +5702,5 @@ #if DEBUG_MEMC_CC_SEND if(m_debug_cc_send_fsm) -std::cout << " BC-Inval for line " << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; @@ -5891,5 +5905,5 @@ // The CC_RECEIVE fsm controls the DSPIN target port on the coherence // network. - /////////////////////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////////////////////// switch(r_cc_receive_fsm.read()) @@ -5906,10 +5920,10 @@ if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) || - (type == DspinDhccpParam::TYPE_CLEANUP_INST) ) - { + (type == DspinDhccpParam::TYPE_CLEANUP_INST)) + { r_cc_receive_fsm = CC_RECEIVE_CLEANUP; break; } - + if(type == DspinDhccpParam::TYPE_MULTI_ACK) { @@ -5918,17 +5932,21 @@ } - assert( - false && - "VCI_MEM_CACHE ERROR: Illegal type in coherence request"); - + assert(false && + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "Illegal type in coherence request"); + break; } //////////////////////// - case CC_RECEIVE_CLEANUP: // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo - { - if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - - assert( not p_dspin_in.eop.read() and - "VCI_MEM_CACHE ERROR in CC_RECEIVE : CLEANUP command must have two flits"); + case CC_RECEIVE_CLEANUP: + { + // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo + + if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) + break; + + assert(not p_dspin_in.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "CLEANUP command must have two flits"); cc_receive_to_cleanup_fifo_put = true; @@ -5938,10 +5956,14 @@ } //////////////////////////// - case CC_RECEIVE_CLEANUP_EOP: // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo - { - if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - - assert( p_dspin_in.eop.read() and - "VCI_MEM_CACHE ERROR in CC_RECEIVE : CLEANUP command must have two flits"); + case CC_RECEIVE_CLEANUP_EOP: + { + // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo + + if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) + break; + + assert(p_dspin_in.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "CLEANUP command must have two flits"); cc_receive_to_cleanup_fifo_put = true; @@ -5954,12 +5976,16 @@ case CC_RECEIVE_MULTI_ACK: { + // write MULTI_ACK flit in CC_RECEIVE to MULTI_ACK fifo + // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo - if(not p_dspin_in.write or not m_cc_receive_to_multi_ack_fifo.wok()) break; - - assert( p_dspin_in.eop.read() and - "VCI_MEM_CACHE ERROR in CC_RECEIVE : MULTI_ACK command must have one flit"); - - cc_receive_to_multi_ack_fifo_put = true; - r_cc_receive_fsm = CC_RECEIVE_IDLE; + if(not p_dspin_in.write or not m_cc_receive_to_multi_ack_fifo.wok()) + break; + + assert(p_dspin_in.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "MULTI_ACK command must have one flit"); + + cc_receive_to_multi_ack_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_IDLE; break; } @@ -5982,5 +6008,5 @@ { case TGT_RSP_READ_IDLE: - { + { // write requests have the highest priority if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; @@ -6115,10 +6141,12 @@ } #endif - - uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length.read() - 1; + + uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + + r_read_to_tgt_rsp_length.read() - 1; bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); - if ( (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll)) + if ((is_last_word and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)) { // Last word in case of READ or second flit in case if LL @@ -6211,5 +6239,6 @@ << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; #endif - uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1; + uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + + r_xram_rsp_to_tgt_rsp_length.read() - 1; bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); @@ -6229,5 +6258,5 @@ { r_tgt_rsp_key_sent = true; // Send second flit of ll - } + } else { @@ -6388,5 +6417,5 @@ switch(r_alloc_dir_fsm.read()) { - case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. + case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. // All the WAYS of a SET initialized in parallel @@ -7154,5 +7183,5 @@ (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || (r_ixr_rsp_fsm.read() == IXR_RSP_ACK)) - + p_vci_ixr.rspack = true; @@ -7331,5 +7360,5 @@ cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_INST; } - else + else { cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_DATA; @@ -7338,5 +7367,5 @@ uint64_t flit = 0; uint64_t dest = - r_cleanup_to_cc_send_srcid.read() << + r_cleanup_to_cc_send_srcid.read() << (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); @@ -7378,5 +7407,5 @@ multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; } - else + else { multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; @@ -7385,5 +7414,5 @@ uint64_t flit = 0; uint64_t dest = - m_xram_rsp_to_cc_send_srcid_fifo.read() << + m_xram_rsp_to_cc_send_srcid_fifo.read() << (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); @@ -7409,5 +7438,5 @@ p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_out.data = flit; break; @@ -7423,5 +7452,5 @@ r_xram_rsp_to_cc_send_nline.read(), DspinDhccpParam::MULTI_INVAL_NLINE); - + p_dspin_out.eop = true; @@ -7517,5 +7546,5 @@ multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; } - else + else { multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; @@ -7524,5 +7553,5 @@ uint64_t flit = 0; uint64_t dest = - m_write_to_cc_send_srcid_fifo.read() << + m_write_to_cc_send_srcid_fifo.read() << (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); @@ -7576,5 +7605,5 @@ { - uint8_t multi_updt_cpt = + uint8_t multi_updt_cpt = r_cc_send_cpt.read() + r_write_to_cc_send_index.read(); @@ -7610,5 +7639,5 @@ multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; } - else + else { multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; @@ -7617,5 +7646,5 @@ uint64_t flit = 0; uint64_t dest = - m_cas_to_cc_send_srcid_fifo.read() << + m_cas_to_cc_send_srcid_fifo.read() << (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);