Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 433) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 434) @@ -5276,5 +5276,5 @@ break; } - //////////////////// + ///////////////// case RSP_DATA_LL: { @@ -5285,4 +5285,5 @@ r_vci_rsp_data_error = true; r_vci_rsp_fsm = RSP_IDLE; + break; } if (r_vci_rsp_cpt.read() == 0) //first flit Index: trunk/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd =================================================================== --- trunk/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd (revision 433) +++ trunk/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd (revision 434) @@ -6,93 +6,61 @@ Module('caba:vci_io_bridge', classname = 'soclib::caba::VciIoBridge', - tmpl_parameters = [ - parameter.Module('vci_param_d', default = 'caba:vci_param', - cell_size = parameter.Reference("cell_size_d"), - plen_size = parameter.Reference("plen_size_d"), - addr_size = parameter.Reference("addr_size_d"), - rerror_size = parameter.Reference("rerror_size_d"), - clen_size = parameter.Reference("clen_size_d"), - rflag_size = parameter.Reference("rflag_size_d"), - srcid_size = parameter.Reference("srcid_size_d"), - pktid_size = parameter.Reference("pktid_size_d"), - trdid_size = parameter.Reference("trdid_size_d"), - wrplen_size = parameter.Reference("wrplen_size_d")), - parameter.Module('vci_param_x', default = 'caba:vci_param', - cell_size = parameter.Reference("cell_size_x"), - plen_size = parameter.Reference("plen_size_x"), - addr_size = parameter.Reference("addr_size_x"), - rerror_size = parameter.Reference("rerror_size_x"), - clen_size = parameter.Reference("clen_size_x"), - rflag_size = parameter.Reference("rflag_size_x"), - srcid_size = parameter.Reference("srcid_size_x"), - pktid_size = parameter.Reference("pktid_size_x"), - trdid_size = parameter.Reference("trdid_size_x"), - wrplen_size = parameter.Reference("wrplen_size_x")), - parameter.Module('vci_param_io', default = 'caba:vci_param', - cell_size = parameter.Reference("cell_size_io"), - plen_size = parameter.Reference("plen_size_io"), - addr_size = parameter.Reference("addr_size_io"), - rerror_size = parameter.Reference("rerror_size_io"), - clen_size = parameter.Reference("clen_size_io"), - rflag_size = parameter.Reference("rflag_size_io"), - srcid_size = parameter.Reference("srcid_size_io"), - pktid_size = parameter.Reference("pktid_size_io"), - trdid_size = parameter.Reference("trdid_size_io"), - wrplen_size = parameter.Reference("wrplen_size_io")), + + tmpl_parameters = [ + parameter.Module('vci_param_int', + default = 'caba:vci_param', + cell_size = parameter.Reference('iob_cell_size_int')), + parameter.Module('vci_param_ext', + default = 'caba:vci_param', + cell_size = parameter.Reference('iob_cell_size_ext')), ], - header_files = [ '../source/include/vci_io_bridge.h', - '../source/include/transaction_tab_io.h'], + + header_files = [ + '../source/include/vci_io_bridge.h', + '../source/include/transaction_tab_io.h' + ], + implementation_files = [ '../source/src/vci_io_bridge.cpp' ], + uses = [ Uses('caba:base_module'), - Uses('common:mapping_table'), - Uses('caba:generic_fifo'), - Uses('caba:generic_tlb', - addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', - parameter.Reference('addr_size'))), - Uses('common:address_decoding_table', - input_t = 'unsigned long', - output_t = 'bool'), - Uses('common:address_decoding_table', - input_t = 'unsigned long', - output_t = 'int'), -# Uses('common:address_masking_table', -# data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', -# parameter.Reference('addr_size'))), - ], - ports = [ Port('caba:vci_initiator', 'p_vci_ini_dma'), - Port('caba:vci_target', 'p_vci_tgt_dma'), - Port('caba:vci_initiator', 'p_vci_ini_config'), - Port('caba:vci_target', 'p_vci_tgt_config'), - Port('caba:vci_initiator', 'p_vci_ini_miss'), - Port('caba:bit_in','p_irq', parameter.Reference('nb_periph')), + Uses('common:mapping_table'), + Uses('caba:generic_fifo'), + Uses('caba:generic_tlb', + addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', + parameter.Reference('addr_size'))), + Uses('common:address_decoding_table', + input_t = 'unsigned long', + output_t = 'bool'), + Uses('common:address_decoding_table', + input_t = 'unsigned long', + output_t = 'int'), + ], + + ports = [ + Port('caba:vci_initiator', 'p_vci_ini_ram'), + Port('caba:vci_target', 'p_vci_tgt_iox'), + Port('caba:vci_initiator', 'p_vci_ini_iox'), + Port('caba:vci_target', 'p_vci_tgt_int'), + Port('caba:vci_initiator', 'p_vci_ini_int'), + Port('caba:bit_in','p_irq', 32), Port('caba:bit_in', 'p_resetn', auto = 'resetn'), - Port('caba:clock_in', 'p_clk', auto = 'clock'), ], - instance_parameters = [ parameter.Int('nd_periph'), - parameter.Module('mtx', 'common:mapping_table'), - parameter.Module('mtd', 'common:mapping_table'), - parameter.Module('mtio', 'common:mapping_table'), - parameter.Module('seg_config_iob', 'common:segment'), - parameter.IntTab('tgt_index_iocluster'), -# parameter.IntTab('tgt_index_config'), - parameter.IntTab('init_index_direct'), - parameter.IntTab('tgt_index_iospace'), - parameter.IntTab('init_index_iospace'), - parameter.IntTab('init_index_dma'), - parameter.Int('dcache_words'), - parameter.Int('iotlb_ways'), - parameter.Int('iotlb_sets'), - parameter.Int('max_frozen_cycles'), ], - extensions = [ 'dsx:get_ident=' - 'tgt_index_config:p_vci_tgt_config:mtd,' - 'init_index_direct:p_vci_init_miss:mtd,' - 'tgt_index_iospace:p_vci_tgt_dma:mtio,' - 'init_index_iospace:p_vci_init_config:mtio,' - 'init_index_dma:p_vci_ini_dma:mtx,' - 'dsx:cpu=wrapper:iss_t', - 'dsx:addressable=tgt_index_config,tgt_index_iospace', -# 'dsx:on_segment=mc:add_index:initiator_rw_index', - ], + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], -# debug = True, + instance_parameters = [ + parameter.Module('mt_ext', 'common:mapping_table'), + parameter.Module('mt_int', 'common:mapping_table'), + parameter.Module('mt_iox', 'common:mapping_table'), + parameter.IntTab('int_tgtid'), + parameter.IntTab('int_srcid'), + parameter.IntTab('iox_tgtid'), + parameter.IntTab('iox_srcid'), + parameter.IntTab('ext_srcid'), + parameter.Int('dcache_words'), + parameter.Int('iotlb_ways'), + parameter.Int('iotlb_sets'), + parameter.Int('debug_start_cycle'), + parameter.Bool('debug_ok'), + ], ) Index: trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h =================================================================== --- trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h (revision 433) +++ trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h (revision 434) @@ -3,4 +3,5 @@ * Copyright (c) UPMC, Lip6, SoC * Date : 16/04/2012 + * Authors: Cassio Fraga, Alain Greiner * * SOCLIB_LGPL_HEADER_BEGIN @@ -24,38 +25,43 @@ * SOCLIB_LGPL_HEADER_END */ - -//////Utilisation Considerations//////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////// +// This TSAR component is a bridge to access external peripherals +// connected to an external I/O bus (such as Hypertransport or PCIe). +// AT the moment, the external I/O bus is modeled by a VCI VGMN component. +// It connects three VCI networks: +// - INT network : to receive both configuration requests from processors +// or software driven data access to peripherals. +// - RAM network : to send DMA transactions initiated by peripherals +// directly to the RAM (or L3 caches). +// - IOX network : to receive DMA transactions from peripherals, or to send +// configuration or data transactions to peripherals. // -// - IOMMU PTPR pointer must fit in 32 bits (with a classical 2 level 4K page -// table in a 32 bit virtual space, it means a maximum of 45 bits in physical -// address) +// Regarding DMA transactions initiated by external peripherals, it provides +// an - optional - IOMMU service : the 32 bits virtual address is translated +// to a (up to) 40 bits physical address by a standard SoCLib generic TLB. +// In case of TLB MISS, the DMA is stalled until the TLB is updated. +// In case of page fault (illegal access), a VCI error is returned to the +// faulty peripheral. +///////////////////////////////////////////////////////////////////////////////// +// General Constraints: // -// - Physical address must fit in two 32 bit words -// -// - Maximal number of flits in a write transaction cannot be bigger than (n° of -// words in a chache line)/2 -// -// - Page Tables must have the format used in TSAR (compatible with component -// generic_tlb) -// -// - IO's segment size must be the same in both networks -// +// - All VCI fields have the same widths on the EXT and IOX networks. +// - Only the VCI DATA field can differ between INT and EXT networks, +// and the width must be 32 or 64 bits. +// - The common VCI ADDRESS width cannot be larger than 64 bits. +// - All VCI transactions must be included in a single cache line. +// - Page Tables must have the format required by the SoCLib generic_tlb. +// - IO's segments must be the same in INT and IOX networks // - Write operations on IOMMU configuration registers (PTPR, ACTIVE) can only // be done when DMA_TLB FSM is IDLE. It should, preferably, be done before // starting any transfers. Pseudo register INVAL may be modified any time. -// -// - Similarly, write operations on the interruptions registers can only be done -// when the dedicated FSM is IDLE. //////////////////////////////////////////////////////////////////////////////// ///////TODO List/////////////////////////////////////////////////////////////// -// -// Tableau de correspondance d'adresses physique - IO (pour CONFIG_CMD) -// -// Conversion 32 (entree) à 64 (sortie) bits (champ data). Dans les deux senses (CMD et RSP) -// -// Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit -// (seulement 'data' et 'be') +// - Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit +// (seulement 'data' et 'be') +// - Traiter complêtement les codes d'erreur en réponse à une transaction +// WTI write /////////////////////////////////////////////////////////////////////////////// @@ -71,7 +77,7 @@ #include "address_decoding_table.h" #include "static_assert.h" -#include "transaction_tab_io.h" #include "vci_initiator.h" #include "vci_target.h" +#include "../../../include/soclib/io_bridge.h" namespace soclib { @@ -80,45 +86,36 @@ using namespace soclib::common; -//////////////////////////////////////////// -template +/////////////////////////////////////////////////////////////////////////////////// +template class VciIoBridge -//////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// : public soclib::caba::BaseModule { - typedef uint32_t tag_t; - typedef uint32_t type_t; - - // Address field may change between direct, extenal and IO network - typedef typename vci_param_d::addr_t paddr_t; - typedef typename vci_param_x::addr_t paddr_t_x; // Just the cache line, for example - typedef typename vci_param_io::addr_t vaddr_t; - - // Data field may change for external network - typedef typename vci_param_x::data_t vci_data_t_x; - typedef typename vci_param_x::be_t vci_be_t_x; - // Srcid field may change for external network - typedef typename vci_param_x::srcid_t vci_srcid_t_x; - - // Other fields must coincide - typedef typename vci_param_d::srcid_t vci_srcid_t; - typedef typename vci_param_d::data_t vci_data_t; - typedef typename vci_param_d::be_t vci_be_t; - typedef typename vci_param_d::trdid_t vci_trdid_t; - typedef typename vci_param_d::pktid_t vci_pktid_t; - typedef typename vci_param_d::plen_t vci_plen_t; - typedef typename vci_param_d::cmd_t vci_cmd_t; - typedef typename vci_param_d::contig_t vci_contig_t; - typedef typename vci_param_d::eop_t vci_eop_t; - typedef typename vci_param_d::const_t vci_cons_t; - typedef typename vci_param_d::wrap_t vci_wrap_t; - typedef typename vci_param_d::clen_t vci_clen_t; - typedef typename vci_param_d::cfixed_t vci_cfixed_t; - - typedef typename vci_param_d::rerror_t vci_rerror_t; - - enum { - CACHE_LINE_MASK = 0xFFFFFFFFC0, - PPN1_MASK = 0x0007FFFF, - PPN2_MASK = 0x0FFFFFFF, + // Data field can have different widths on INT and EXT networks + typedef typename vci_param_ext::fast_data_t ext_data_t; + typedef typename vci_param_int::fast_data_t int_data_t; + + // Other fields must be equal + typedef typename vci_param_int::fast_addr_t vci_addr_t; + typedef typename vci_param_int::srcid_t vci_srcid_t; + typedef typename vci_param_int::be_t vci_be_t; + typedef typename vci_param_int::trdid_t vci_trdid_t; + typedef typename vci_param_int::pktid_t vci_pktid_t; + typedef typename vci_param_int::plen_t vci_plen_t; + typedef typename vci_param_int::cmd_t vci_cmd_t; + typedef typename vci_param_int::contig_t vci_contig_t; + typedef typename vci_param_int::eop_t vci_eop_t; + typedef typename vci_param_int::const_t vci_cons_t; + typedef typename vci_param_int::wrap_t vci_wrap_t; + typedef typename vci_param_int::clen_t vci_clen_t; + typedef typename vci_param_int::cfixed_t vci_cfixed_t; + typedef typename vci_param_int::rerror_t vci_rerror_t; + + enum + { + CACHE_LINE_MASK = 0xFFFFFFFFC0LL, + PPN1_MASK = 0x0007FFFF, + PPN2_MASK = 0x0FFFFFFF, K_PAGE_OFFSET_MASK = 0x00000FFF, M_PAGE_OFFSET_MASK = 0x001FFFFF, @@ -127,226 +124,219 @@ }; - //DMA (from Peripherals to XRAM) - enum dma_cmd_fsm_state { + // States for DMA_CMD FSM (from IOX to RAM) + enum dma_cmd_fsm_state + { DMA_CMD_IDLE, - DMA_CMD_TRT_LOCK, - DMA_CMD_TRT_WAIT, - DMA_CMD_TRT_SET, - DMA_CMD_FIFO_PUT, - DMA_CMD_FIFO_MISS_PUT, - DMA_CMD_TLB_MISS_WAIT, - DMA_CMD_TLB_MISS_STORE, - DMA_CMD_ERROR, + DMA_CMD_FIFO_PUT_CMD, + DMA_CMD_FIFO_PUT_RSP, + DMA_CMD_MISS_WAIT, + DMA_CMD_WAIT_EOP, }; - enum dma_rsp_fsm_state { + // States for DMA_RSP FSM (from RAM to IOX) + enum dma_rsp_fsm_state + { DMA_RSP_IDLE, - DMA_RSP_TRT_LOCK, DMA_RSP_FIFO_PUT, - DMA_RSP_FIFO_ERROR_PUT, }; - // Allocates the transaction_tab_dma - enum alloc_trt_dma_fsm_state { - ALLOC_TRT_DMA_CMD, - ALLOC_TRT_DMA_RSP + // States for TLB_MISS FSM + enum dma_tlb_fsm_state + { + TLB_IDLE, + TLB_MISS, + TLB_PTE1_GET, + TLB_PTE1_SELECT, + TLB_PTE1_UPDT, + TLB_PTE2_GET, + TLB_PTE2_SELECT, + TLB_PTE2_UPDT, + TLB_WAIT, + TLB_RETURN, + TLB_INVAL_CHECK, + }; + + // States for CONFIG_CMD FSM (from INT to IOX) + enum config_cmd_fsm_state + { + CONFIG_CMD_IDLE, + CONFIG_CMD_FIFO_PUT_CMD, + CONFIG_CMD_FIFO_PUT_RSP, + }; + + // states for CONFIG_RSP FSM (from IOX to INT) + enum config_rsp_fsm_state + { + CONFIG_RSP_IDLE, + CONFIG_RSP_FIFO_PUT, }; - - - enum dma_tlb_fsm_state { - DMA_TLB_IDLE, - DMA_TLB_MISS, - DMA_TLB_PTE1_GET, - DMA_TLB_PTE1_SELECT, - DMA_TLB_PTE1_UPDT, - DMA_TLB_PTE2_GET, - DMA_TLB_PTE2_SELECT, - DMA_TLB_PTE2_UPDT, - DMA_TLB_WAIT_TRANSACTION, - DMA_TLB_RETURN, - // Treatment of CONFIG FSM request - DMA_TLB_INVAL_CHECK, - DMA_TLB_INVAL_SCAN + + // States for MISS_WTI_CMD FSM (to INT network) + enum miss_wti_cmd_state + { + MISS_WTI_CMD_IDLE, + MISS_WTI_CMD_WTI, + MISS_WTI_CMD_MISS, }; - //CONFIG (from Direct Network to Peripherals) - enum config_cmd_fsm_state { - CONFIG_CMD_IDLE, - CONFIG_CMD_TRT_LOCK, - CONFIG_CMD_TRT_WAIT, - CONFIG_CMD_TRT_SET, - CONFIG_CMD_FIFO_PUT, - - // IOB private configuration segment - CONFIG_CMD_PTPR_WRITE, - CONFIG_CMD_PTPR_READ, - CONFIG_CMD_ACTIVE_WRITE, - CONFIG_CMD_ACTIVE_READ, - CONFIG_CMD_BVAR_READ, - CONFIG_CMD_ETR_READ, - CONFIG_CMD_BAD_ID_READ, - CONFIG_CMD_INVAL_REQ, - CONFIG_CMD_INVAL, - CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1, - CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2, - CONFIG_CMD_IT_ADDR_IOMMU_READ_1, - CONFIG_CMD_IT_ADDR_IOMMU_READ_2, - CONFIG_CMD_IT_ADDR_WRITE_1, - CONFIG_CMD_IT_ADDR_WRITE_2, - CONFIG_CMD_IT_ADDR_READ_1, - CONFIG_CMD_IT_ADDR_READ_2, - CONFIG_CMD_ERROR_WAIT, - CONFIG_CMD_ERROR_RSP + // States for MISS_WTI_RSP FSM (from INT network) + enum miss_wti_rsp_state + { + MISS_WTI_RSP_IDLE, + MISS_WTI_RSP_WTI, + MISS_WTI_RSP_MISS, }; - - enum config_rsp_fsm_state { - CONFIG_RSP_IDLE, - CONFIG_RSP_TRT_LOCK, - CONFIG_RSP_FIFO_PUT + + // PKTID values for TLB MISS and WTI transactions + enum pktid_values_e + { + PKTID_READ = 0x0, // TSAR code for read data uncached + PKTID_WRITE = 0x4, // TSAR code for write }; - - // Allocates the transaction_tab_dma - enum alloc_trt_config_fsm_state { - ALLOC_TRT_CONFIG_CMD, - ALLOC_TRT_CONFIG_RSP - }; - - //MISS TRANSACTIONS (to Direct Network) - enum miss_init_fsm_state { - MISS_INIT_IDLE_MISS, - MISS_INIT_IDLE_IRQ, - MISS_INIT_IRQ_CMD, - MISS_INIT_IRQ_RSP, - MISS_INIT_TLB_MISS_CMD, - MISS_INIT_TLB_MISS_RSP - }; - - ///////////////////////////////////////////////////////////////// - - // Configuration Error Type - enum config_error_type { - READ_OK = 0, - READ_ERROR = 1, - WRITE_OK = 2, - WRITE_ERROR = 3 - }; - + // Miss types for iotlb enum tlb_miss_type_e { PTE1_MISS, - PTE2_MISS + PTE2_MISS, }; - // IOB Configuration registers - // Required segment size = (8 + 2*nb_periph) words - enum { - IOB_IOMMU_PTPR = 0, // R/W : Page Table Pointer Register - IOB_IOMMU_ACTIVE = 1, // R/W : IOMMU activated if not 0 - IOB_IOMMU_BVAR = 2, // R : Bad Virtual Address - IOB_IOMMU_ETR = 3, // R : Error type - IOB_IOMMU_BAD_ID = 4, // R : Faulty peripheral Index - IOB_INVAL_PTE = 5, // W : Invalidate PTE. Virtual Address - IOB_IT_ADDR_IOMMU_LO = 6, // R/W - IOB_IT_ADDR_IOMMU_HI = 7, // R/W - IOB_IT_ADDR_BEGIN = 8 // R/W : One register by IO - // Addressed by two 32-bit words each - }; - - - // Error Type - enum mmu_error_type_e - { - MMU_NONE = 0x0000, // None - MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access of write access to a non writable page (bit W in flags) - MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write access of Bus Error accessing Table 1 - MMU_READ_PT1_UNMAPPED = 0x1001, // Read access of Page fault on Page Table 1 - MMU_READ_PT2_UNMAPPED = 0x1002, // Read access of Page fault on Page Table 2 - MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read access of Bus Error in Table1 access - MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read access of Bus Error in Table2 access - MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read access of Bus Error in cache access - }; - - public: - sc_in p_clk; - sc_in p_resetn; - sc_in *p_irq_in; - - soclib::caba::VciInitiator p_vci_ini_dma; // XRAM Noc - soclib::caba::VciTarget p_vci_tgt_dma; - - soclib::caba::VciInitiator p_vci_ini_config; - soclib::caba::VciTarget p_vci_tgt_config; - - soclib::caba::VciInitiator p_vci_ini_miss; + sc_in p_clk; + sc_in p_resetn; + sc_in* p_irq[32]; // not always constructed + + soclib::caba::VciInitiator p_vci_ini_ram; + + soclib::caba::VciTarget p_vci_tgt_iox; + soclib::caba::VciInitiator p_vci_ini_iox; + + soclib::caba::VciTarget p_vci_tgt_int; + soclib::caba::VciInitiator p_vci_ini_int; private: - const size_t m_words; - const size_t m_nb_periph; - - // STRUCTURAL PARAMETERS - // soclib::common::AddressDecodingTable m_locality_table_config; - // soclib::common::AddressDecodingTable m_routing_table_config; - //const soclib::common::MappingTable& m_mtio; - - uint32_t m_transaction_tab_dma_lines; - TransactionTabIO m_transaction_tab_dma; // dma transaction table - - uint32_t m_transaction_tab_config_lines; - TransactionTabIO m_transaction_tab_config; // config transaction table - - // Direct Network - const soclib::common::Segment m_segment_config; - const vci_srcid_t m_srcid_miss; - // XRAM Network - const vci_srcid_t_x m_srcid_dma; - // IO Network - const soclib::common::Segment m_segment_io; - const vci_srcid_t m_srcid_config; - - const size_t m_iotlb_ways; - const size_t m_iotlb_sets; - const size_t m_paddr_nbits; - - - ///////////////////////////////////////////// - // debug variables (for each FSM) - ///////////////////////////////////////////// - uint32_t m_debug_start_cycle; - bool m_debug_ok; - - bool m_debug_dma_cmd_fsm; - bool m_debug_dma_rsp_fsm; - bool m_debug_dma_tlb_fsm; - bool m_debug_config_cmd_fsm; - bool m_debug_config_rsp_fsm; - bool m_debug_miss_init_fsm; + const size_t m_words; + const bool m_has_irqs; + + // INT & IOX Networks + std::list m_int_seglist; + const vci_srcid_t m_int_srcid; // local SRCID on INT network + std::list m_iox_seglist; + + // TLB parameters + const size_t m_iotlb_ways; + const size_t m_iotlb_sets; + + // debug variables + uint32_t m_debug_start_cycle; + bool m_debug_ok; + bool m_debug_activated; /////////////////////////////// // MEMORY MAPPED REGISTERS /////////////////////////////// - sc_signal r_iommu_ptpr; // page table pointer register - sc_signal r_iommu_active; // iotlb mode - sc_signal r_iommu_bvar; // iommu bad address - sc_signal r_iommu_etr; // iommu error type - sc_signal r_iommu_bad_id; // ID of the peripheral that tried bad operation - - sc_signal r_it_addr_iommu; // iommu error type - paddr_t *r_it_addr; // iommu error type + sc_signal r_iommu_ptpr; // page table pointer register + sc_signal r_iommu_active; // iotlb mode + sc_signal r_iommu_bvar; // iommu bad virtual address + sc_signal r_iommu_etr; // iommu error type + sc_signal r_iommu_bad_id; // SRCID of faulty peripheral + sc_signal r_iommu_wti_enable; // enable WTI transactions when true + sc_signal r_iommu_wti_paddr; // address of IOMMU WTI + sc_signal* r_iommu_peri_wti; // array[32] WTI for peripherals /////////////////////////////////// // DMA_CMD FSM REGISTERS /////////////////////////////////// - sc_signal r_dma_cmd_fsm; // state register - sc_signal r_dma_cmd_fsm_save; //saves current state when miss interruption happens - sc_signal r_miss_interrupt; - - sc_signal r_dma_cmd_count; - sc_signal r_dma_cmd_trt_index; - sc_signal r_dma_paddr; - - GenericFifo m_dma_cmd_addr_fifo; - //GenericFifo m_dma_cmd_length_fifo; + sc_signal r_dma_cmd_fsm; + sc_signal r_dma_cmd_vaddr; // input virtual address + sc_signal r_dma_cmd_paddr; // output physical address + + /////////////////////////////////// + // DMA_RSP FSM REGISTERS + /////////////////////////////////// + sc_signal r_dma_rsp_fsm; + + /////////////////////////////////// + // CONFIG_CMD FSM REGISTERS + /////////////////////////////////// + sc_signal r_config_cmd_fsm; + sc_signal r_config_cmd_rdata; + sc_signal r_config_cmd_error; + sc_signal r_config_cmd_inval_vaddr; + + /////////////////////////////////// + // CONFIG_RSP FSM REGISTERS + /////////////////////////////////// + sc_signal r_config_rsp_fsm; + + /////////////////////////////////// + // TLB FSM REGISTERS + /////////////////////////////////// + sc_signal r_tlb_fsm; // state register + sc_signal r_waiting_transaction; // Flag for returning from + sc_signal r_tlb_miss_type; + sc_signal r_tlb_miss_error; + + sc_signal r_tlb_paddr; // physical address of pte + sc_signal r_tlb_pte_flags; // pte1 or first word of pte2 + sc_signal r_tlb_pte_ppn; // second word of pte2 + sc_signal r_tlb_way; // selected way in tlb + sc_signal r_tlb_set; // selected set in tlb + + uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs + sc_signal r_tlb_buf_valid; // one valit flag for all PTEs + sc_signal r_tlb_buf_tag; // cache line number + sc_signal r_tlb_buf_vaddr; // virtual address first PTE + sc_signal r_tlb_buf_big_page; // ??? + + /////////////////////////////////// + // MISS_WTI_CMD FSM REGISTERS + /////////////////////////////////// + sc_signal r_miss_wti_cmd_fsm; + sc_signal r_miss_wti_cmd_index; + + /////////////////////////////////// + // MISS_WTI_RSP FSM REGISTERS + /////////////////////////////////// + sc_signal r_miss_wti_rsp_fsm; + sc_signal r_miss_wti_rsp_error; + sc_signal r_miss_wti_rsp_count; + + ///////////////////////////////////////////////////// + // ALLOCATORS for CONFIG_RSP fifo & DMA_RSP fifo + ///////////////////////////////////////////////////// + sc_signal r_alloc_fifo_config_rsp_local; + sc_signal r_alloc_fifo_dma_rsp_local; + + ////////////////////////////////// + // IRQ FSM registers + ////////////////////////////////// + sc_signal* r_irq_pending; // array[32] + sc_signal* r_irq_request; // array[32] + + ////////////////////////////////////////////////////////////////// + // IOTLB + ////////////////////////////////////////////////////////////////// + GenericTlb r_iotlb; + + ////////////////////////////////////////////////////////////////// + // Inter-FSM communications + ////////////////////////////////////////////////////////////////// + + // between DMA_CMD and TLB FSM + sc_signal r_dma_tlb_req; + + // between CONFIG_CMD FSM and TLB FSM + sc_signal r_config_tlb_req; + + // between TLB FSM and MISS_WTI FSM + sc_signal r_tlb_miss_req; + + ///////////////////////// + // FIFOs + ///////////////////////// + + // ouput FIFO to VCI INI port on RAM network (VCI command) + GenericFifo m_dma_cmd_addr_fifo; GenericFifo m_dma_cmd_srcid_fifo; GenericFifo m_dma_cmd_trdid_fifo; @@ -355,5 +345,5 @@ GenericFifo m_dma_cmd_cmd_fifo; GenericFifo m_dma_cmd_contig_fifo; - GenericFifo m_dma_cmd_data_fifo; + GenericFifo m_dma_cmd_data_fifo; GenericFifo m_dma_cmd_eop_fifo; GenericFifo m_dma_cmd_cons_fifo; @@ -363,53 +353,6 @@ GenericFifo m_dma_cmd_clen_fifo; - // Command storage registers (in case of miss tlb) - sc_signal r_miss_paddr; - sc_signal r_miss_cmd ; - sc_signal r_miss_contig; - sc_signal r_miss_cons ; - sc_signal r_miss_plen ; - sc_signal r_miss_wrap ; - sc_signal r_miss_cfixed; - sc_signal r_miss_clen ; - sc_signal r_miss_srcid ; - sc_signal r_miss_trdid ; - sc_signal r_miss_pktid ; - vci_data_t_x *r_miss_data ; - vci_be_t *r_miss_be; - - // Error registers - sc_signal r_dma_error_type; - sc_signal r_dma_error_trdid; - sc_signal r_dma_error_pktid; - - /////////////////////////////////// - // DMA_TLB FSM REGISTERS - /////////////////////////////////// - sc_signal r_dma_tlb_fsm; // state register - sc_signal r_waiting_transaction; // Flag for returning from - // invalidation interruptions - sc_signal r_tlb_miss_type; - - sc_signal r_iotlb_vaddr; // virtual address for a tlb miss - sc_signal r_iotlb_paddr; // physical address of pte - sc_signal r_iotlb_pte_flags; // pte1 or first word of pte2 - sc_signal r_iotlb_pte_ppn; // second word of pte2 - sc_signal r_iotlb_way; // selected way in tlb - sc_signal r_iotlb_set; // selected set in tlb - - ////////////////////////////////////////////////////////////////// - // IOTLB - ////////////////////////////////////////////////////////////////// - GenericTlb r_iotlb; - - /////////////////////////////////// - // DMA_RSP FSM REGISTERS - /////////////////////////////////// - sc_signal r_dma_rsp_fsm; - - sc_signal r_dma_rtrdid; - sc_signal r_dma_rsrcid; - - GenericFifo m_dma_rsp_data_fifo; + // output FIFO to VCI TGT port on IOX network (VCI response) + GenericFifo m_dma_rsp_data_fifo; GenericFifo m_dma_rsp_rsrcid_fifo; GenericFifo m_dma_rsp_rtrdid_fifo; @@ -418,31 +361,6 @@ GenericFifo m_dma_rsp_rerror_fifo; - //Communication between DMA_CMD and DMA_RSP - sc_signal r_dma_cmd_rsp_erase_req; - sc_signal r_dma_cmd_error_req; - //Communication between DMA_CMD and TLB - sc_signal r_dma_tlb_req; - sc_signal r_tlb_dma_untreated; - sc_signal r_dma_tlb_error_req; - sc_signal r_tlb_error_type; - //Communication betweeen TLB and CONFIG_CMD - sc_signal r_config_tlb_req; - sc_signal r_config_tlb_inval_vaddr; - - /////////////////////////////////// - // ALLOC_TRT_DMA FSM REGISTERS - /////////////////////////////////// - sc_signal r_alloc_trt_dma_fsm; // state register - - - /////////////////////////////////// - // CONFIG_CMD FSM REGISTERS - /////////////////////////////////// - sc_signal r_config_cmd_fsm; // state register - - sc_signal r_config_cmd_trt_index; - - GenericFifo m_config_cmd_addr_fifo; - //GenericFifo m_config_cmd_length_fifo; + // output FIFO to VCI INI port on IOX network (VCI command) + GenericFifo m_config_cmd_addr_fifo; GenericFifo m_config_cmd_srcid_fifo; GenericFifo m_config_cmd_trdid_fifo; @@ -451,5 +369,5 @@ GenericFifo m_config_cmd_cmd_fifo; GenericFifo m_config_cmd_contig_fifo; - GenericFifo m_config_cmd_data_fifo; + GenericFifo m_config_cmd_data_fifo; GenericFifo m_config_cmd_eop_fifo; GenericFifo m_config_cmd_cons_fifo; @@ -459,86 +377,13 @@ GenericFifo m_config_cmd_clen_fifo; - - // Private configuration registers - sc_signal r_config_error_type; // rerror field - sc_signal r_config_first_word; - sc_signal r_it_index; - - GenericFifo m_config_local_data_fifo; - GenericFifo m_config_local_rsrcid_fifo; - GenericFifo m_config_local_rtrdid_fifo; - GenericFifo m_config_local_rpktid_fifo; - GenericFifo m_config_local_reop_fifo; - GenericFifo m_config_local_rerror_fifo; - sc_signal r_config_vaddr; - - - /////////////////////////////////// - // CONFIG_RSP FSM REGISTERS - /////////////////////////////////// - sc_signal r_config_rsp_fsm; - - sc_signal r_config_rtrdid; - sc_signal r_config_rsrcid; - - GenericFifo m_config_rsp_data_fifo; - GenericFifo m_config_rsp_rsrcid_fifo; - GenericFifo m_config_rsp_rtrdid_fifo; - GenericFifo m_config_rsp_rpktid_fifo; - GenericFifo m_config_rsp_reop_fifo; - GenericFifo m_config_rsp_rerror_fifo; + // output FIFO to VCI TGT port on INT network (VCI response) + GenericFifo m_config_rsp_data_fifo; + GenericFifo m_config_rsp_rsrcid_fifo; + GenericFifo m_config_rsp_rtrdid_fifo; + GenericFifo m_config_rsp_rpktid_fifo; + GenericFifo m_config_rsp_reop_fifo; + GenericFifo m_config_rsp_rerror_fifo; - // Defines priority between the two response FIFOs (local and remote) - sc_signal r_config_rsp_fifo_local_priority; - - //Communication between CONFIG_CMD and CONFIG_RSP - sc_signal r_config_cmd_rsp_erase_req; // used to signal an erasing on TRT table - - /////////////////////////////////// - // ALLOC_TRT_CONFIG FSM REGISTERS - /////////////////////////////////// - sc_signal r_alloc_trt_config_fsm; // state register - - /////////////////////////////////// - // MISS_INIT FSM REGISTERS - /////////////////////////////////// - sc_signal r_miss_init_fsm; - - sc_signal r_miss_rdata; - sc_signal r_miss_rpktid; - sc_signal r_miss_rtrdid; - sc_signal r_miss_rerror; - sc_signal r_miss_reop; - //sc_signal r_miss_rsrcid; - - sc_signal r_miss_rsp_cpt; - - //IRQ - sc_signal r_irq_pending; - sc_signal r_irq_mask; - sc_signal r_irq_chosen; - - - //Communication between TLB and MISS_INIT - sc_signal r_tlb_miss_init_req; - sc_signal r_miss_init_error; - - //////////////////////////////////// - // MISS PREFETCH BUFFER - /////////////////////////////////// - //DMA_TLB FSM is its owner. - //CONFIG FSM must set a request in order to access the resource (invalidation) - - // Proposition : Buffer with some lines (4, for example). It could be - // indexed from the bit 20. - - vci_data_t *r_miss_buf_data; // cache line data buffer - bool r_miss_buf_valid; // For individual invalidation, - // we could rather use the Valid bit at each PTE - sc_signal r_miss_buf_tag; // chache line number - sc_signal r_miss_buf_vaddr_begin; // Virtual address of the first PTE on the line - - bool r_miss_buf_first_level; // useful only if using both types of pages - + //////////////////////////////// // Activity counters @@ -550,7 +395,7 @@ uint32_t m_cpt_iotlb_read; // number of iotlb read uint32_t m_cpt_iotlb_miss; // number of iotlb miss - uint32_t m_cost_iotlb_miss; // number of blocking cycles (not the treatment cycles itself) - uint32_t m_cpt_iotlbmiss_transaction; // number of iotlb miss transactions to Mem Cache - uint32_t m_cost_iotlbmiss_transaction; // cumulated duration for iotlb miss transactions + uint32_t m_cost_iotlb_miss; // number of wait cycles (not treatment itself) + uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions + uint32_t m_cost_iotlbmiss_transaction; // cumulated duration tlb miss transactions //Transaction Tabs (TRTs) activity counters @@ -564,10 +409,9 @@ uint32_t m_cpt_fsm_dma_cmd [32]; uint32_t m_cpt_fsm_dma_rsp [32]; - uint32_t m_cpt_fsm_dma_tlb [32]; - uint32_t m_cpt_fsm_alloc_trt_dma [32]; + uint32_t m_cpt_fsm_tlb [32]; uint32_t m_cpt_fsm_config_cmd [32]; uint32_t m_cpt_fsm_config_rsp [32]; - uint32_t m_cpt_fsm_alloc_trt_config [32]; - uint32_t m_cpt_fsm_miss_init [32]; + uint32_t m_cpt_fsm_miss_wti_cmd [32]; + uint32_t m_cpt_fsm_miss_wti_rsp [32]; protected: @@ -577,20 +421,16 @@ VciIoBridge( sc_module_name insname, - size_t nb_periph, // maximun is 32 - const soclib::common::MappingTable &mtx, //external network - const soclib::common::MappingTable &mtd, //direct network - const soclib::common::MappingTable &mtio, //io network - const soclib::common::Segment &seg_config_iob, - const soclib::common::IntTab &tgt_index_iocluster, -// const soclib::common::IntTab &tgt_index_config, // Direct Noc - const soclib::common::IntTab &init_index_direct, // Direct Noc - const soclib::common::IntTab &tgt_index_iospace, // IO Noc - const soclib::common::IntTab &init_index_iospace, // IO Noc - const soclib::common::IntTab &init_index_dma, // XRAM Noc - size_t dcache_words, - size_t iotlb_ways, - size_t iotlb_sets, - uint32_t debug_start_cycle, - bool debug_ok); + const soclib::common::MappingTable &mt_ext, // external network + const soclib::common::MappingTable &mt_int, // internal network + const soclib::common::MappingTable &mt_iox, // iox network + const soclib::common::IntTab &int_tgtid, // INT network TGTID + const soclib::common::IntTab &int_srcid, // INT network SRCID + const soclib::common::IntTab &iox_tgtid, // IOX network TGTID + const bool has_irqs, // component has irq ports + const size_t dcache_words, + const size_t iotlb_ways, + const size_t iotlb_sets, + const uint32_t debug_start_cycle, + const bool debug_ok ); ~VciIoBridge(); Index: trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp =================================================================== --- trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 433) +++ trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 434) @@ -1,5 +1,6 @@ -/* i*- c++ -*-C +/* -*- c++ -*- * File : vci_io_bridge.cpp * Copyright (c) UPMC, Lip6, SoC + * Authors: Cassio Fraga, Alain Greiner * * SOCLIB_LGPL_HEADER_BEGIN @@ -29,21 +30,18 @@ #include "../include/vci_io_bridge.h" + ////// debug services /////////////////////////////////////////////////////// // All debug messages are conditionned by two variables: // - compile time : DEBUG_*** : defined below // - execution time : m_debug_*** : defined by constructor arguments -// m_debug_* = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) +// m_debug_activated = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) ///////////////////////////////////////////////////////////////////////////////// #define DEBUG_DMA_CMD 1 #define DEBUG_DMA_RSP 1 -#define DEBUG_DMA_TLB 1 +#define DEBUG_TLB_MISS 1 #define DEBUG_CONFIG_CMD 1 #define DEBUG_CONFIG_RSP 1 -#define DEBUG_MISS_INIT 1 - -#define NEW_XRAM_VCI 0 - -#define IOMMU_ID 4097 +#define DEBUG_MISS_WTI 1 namespace soclib { @@ -52,156 +50,99 @@ namespace { -//DMA -const char *dma_cmd_fsm_state_str[] = { +const char *dma_cmd_fsm_state_str[] = + { "DMA_CMD_IDLE", - "DMA_CMD_TRT_LOCK", - "DMA_CMD_TRT_WAIT", - "DMA_CMD_TRT_SET", - "DMA_CMD_FIFO_PUT", - "DMA_CMD_FIFO_MISS_PUT", - "DMA_CMD_TLB_MISS_WAIT", - "DMA_CMD_TLB_MISS_STORE", - "DMA_CMD_ERROR", + "DMA_CMD_FIFO_PUT_CMD", + "DMA_CMD_FIFO_PUT_RSP", + "DMA_CMD_MISS_WAIT", + "DMA_CMD_WAIT_EOP", }; -const char *dma_rsp_fsm_state_str[] = { +const char *dma_rsp_fsm_state_str[] = + { "DMA_RSP_IDLE", - "DMA_RSP_TRT_LOCK", "DMA_RSP_FIFO_PUT", - "DMA_RSP_FIFO_ERROR_PUT", - }; - -const char *alloc_trt_dma_fsm_state_str[] = { - "ALLOC_TRT_DMA_CMD", - "ALLOC_TRT_DMA_RSP", }; -const char *dma_tlb_fsm_state_str[] = { - "DMA_TLB_IDLE", - "DMA_TLB_MISS", - "DMA_TLB_PTE1_GET", - "DMA_TLB_PTE1_SELECT", - "DMA_TLB_PTE1_UPDT", - "DMA_TLB_PTE2_GET", - "DMA_TLB_PTE2_SELECT", - "DMA_TLB_PTE2_UPDT", - "DMA_TLB_WAIT_TRANSACTION", - "DMA_TLB_RETURN", - "DMA_TLB_INVAL_CHECK", - "DMA_TLB_INVAL_SCAN", +const char *tlb_fsm_state_str[] = + { + "TLB_IDLE", + "TLB_MISS", + "TLB_PTE1_GET", + "TLB_PTE1_SELECT", + "TLB_PTE1_UPDT", + "TLB_PTE2_GET", + "TLB_PTE2_SELECT", + "TLB_PTE2_UPDT", + "TLB_WAIT", + "TLB_RETURN", + "TLB_INVAL_CHECK", }; -//CONFIG -const char *config_cmd_fsm_state_str[] = { +const char *config_cmd_fsm_state_str[] = + { "CONFIG_CMD_IDLE", - "CONFIG_CMD_TRT_LOCK", - "CONFIG_CMD_TRT_WAIT", - "CONFIG_CMD_TRT_SET", - "CONFIG_CMD_FIFO_PUT", - - // IOB private configuration segment - "CONFIG_CMD_PTPR_WRITE", - "CONFIG_CMD_PTPR_READ", - "CONFIG_CMD_ACTIVE_WRITE", - "CONFIG_CMD_ACTIVE_READ", - "CONFIG_CMD_BVAR_READ", - "CONFIG_CMD_ETR_READ", - "CONFIG_CMD_BAD_ID_READ", - "CONFIG_CMD_INVAL_REQ", - "CONFIG_CMD_INVAL", - "CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1", - "CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2", - "CONFIG_CMD_IT_ADDR_IOMMU_READ_1", - "CONFIG_CMD_IT_ADDR_IOMMU_READ_2", - "CONFIG_CMD_IT_ADDR_WRITE_1", - "CONFIG_CMD_IT_ADDR_WRITE_2", - "CONFIG_CMD_IT_ADDR_READ_1", - "CONFIG_CMD_IT_ADDR_READ_2", - "CONFIG_CMD_ERROR_WAIT", - "CONFIG_CMD_ERROR_RSP", + "CONFIG_CMD_FIFO_PUT_CMD", + "CONFIG_CMD_FIFO_PUT_RSP", }; -const char *config_rsp_fsm_state_str[] = { +const char *config_rsp_fsm_state_str[] = + { "CONFIG_RSP_IDLE", - "CONFIG_RSP_TRT_LOCK", "CONFIG_RSP_FIFO_PUT", }; -const char *alloc_trt_config_fsm_state_str[] = { - "ALLOC_TRT_CONFIG_CMD", - "ALLOC_TRT_CONFIG_RSP", - }; - -//MISS TRANSACTIONS (to Direct Network) -const char *miss_init_fsm_state_str[] = { - "MISS_INIT_IDLE_MISS", - "MISS_INIT_IDLE_IRQ", - "MISS_INIT_IRQ_CMD", - "MISS_INIT_IRQ_RSP", - "MISS_INIT_TLB_MISS_CMD", - "MISS_INIT_TLB_MISS_RSP", +const char *miss_wti_fsm_state_str[] = { + "MISS_WTI_IDLE_MISS", + "MISS_WTI_IDLE_WTI", + "MISS_WTI_CMD_WTI", + "MISS_WTI_RSP_WTI", + "MISS_WTI_CMD_MISS", + "MISS_WTI_RSP_MISS", }; } -#define tmpl(...) template __VA_ARGS__ VciIoBridge - -///////////////////////////////// +#define tmpl(...) template __VA_ARGS__ VciIoBridge + +//////////////////////// tmpl(/**/)::VciIoBridge( sc_module_name name, - size_t nb_periph, - const soclib::common::MappingTable &mtx, - const soclib::common::MappingTable &mtd, - const soclib::common::MappingTable &mtio, - const soclib::common::Segment &seg_config_iob, - const soclib::common::IntTab &tgt_index_iocluster, -// const soclib::common::IntTab &tgt_index_config, - const soclib::common::IntTab &init_index_direct, - const soclib::common::IntTab &tgt_index_iospace, - const soclib::common::IntTab &init_index_iospace, - const soclib::common::IntTab &init_index_dma, - size_t dcache_words, - size_t iotlb_ways, - size_t iotlb_sets, - uint32_t debug_start_cycle, - bool debug_ok) + const soclib::common::MappingTable &mt_ext, + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_iox, + const soclib::common::IntTab &int_tgtid, // INT network TGTID + const soclib::common::IntTab &int_srcid, // INT network SRCID + const soclib::common::IntTab &iox_tgtid, // IOX network TGTID + const bool has_irqs, + const size_t dcache_words, + const size_t iotlb_ways, + const size_t iotlb_sets, + const uint32_t debug_start_cycle, + const bool debug_ok) : soclib::caba::BaseModule(name), - p_clk("clk"), - p_resetn("resetn"), - p_irq_in(soclib::common::alloc_elems >("irq_in", nb_periph)), - p_vci_ini_dma("vci_ini_dma"), - p_vci_tgt_dma("vci_tgt_dma"), - p_vci_ini_config("vci_ini_config"), - p_vci_tgt_config("vci_tgt_config"), - p_vci_ini_miss("vci_ini_miss"), - - m_words(dcache_words), - m_nb_periph(nb_periph), - - // m_locality_table_config(mtd.getLocalityTable(tgt_index_iocluster)), - // These structures simulate what in hardware will be a correspondence table - // Between segments' base address on the direct space and on the IO space - // m_routing_table_config(mtd.getRoutingTable(tgt_index_iocluster)), - //m_mtio(mtio), - - m_transaction_tab_dma(2), - m_transaction_tab_config(1), - //Direct Network -// m_segment_config(mtd.getSegment(tgt_index_config)), - m_segment_config(seg_config_iob), - m_srcid_miss(mtx.indexForId(init_index_direct)), - //XRAM Network - m_srcid_dma(mtx.indexForId(init_index_dma)), - //IO Network - m_segment_io(mtio.getSegment(tgt_index_iospace)), - m_srcid_config(mtio.indexForId(init_index_iospace)), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_vci_ini_ram("p_vci_ini_ram"), + p_vci_tgt_iox("p_vci_tgt_iox"), + p_vci_ini_iox("p_vci_ini_iox"), + p_vci_tgt_int("p_vci_tgt_int"), + p_vci_ini_int("p_vci_ini_int"), + + m_words( dcache_words ), + m_has_irqs( has_irqs ), + + // INT & IOX Network + m_int_seglist( mt_int.getSegmentList( int_tgtid )), + m_int_srcid( mt_int.indexForId( int_srcid )), + m_iox_seglist( mt_iox.getSegmentList( iox_tgtid )), m_iotlb_ways(iotlb_ways), m_iotlb_sets(iotlb_sets), - m_paddr_nbits(vci_param_d::N), m_debug_start_cycle(debug_start_cycle), m_debug_ok(debug_ok), + // addressable registers r_iommu_ptpr("r_iommu_ptpr"), r_iommu_active("r_iommu_active"), @@ -209,170 +150,161 @@ r_iommu_etr("r_iommu_etr"), r_iommu_bad_id("r_iommu_bad_id"), - r_it_addr_iommu("r_it_addr_iommu"), - - // DMA_CMD + r_iommu_wti_paddr("r_iommu_wti_paddr"), + r_iommu_peri_wti(alloc_elems >("r_peri_wti_paddr", 32)), + + // DMA_CMD FSM registers r_dma_cmd_fsm("r_dma_cmd_fsm"), - r_dma_cmd_fsm_save("r_dma_cmd_fsm_save"), - r_miss_interrupt("r_miss_interrupt"), - r_dma_cmd_count("r_dma_cmd_count"), - r_dma_cmd_trt_index("r_dma_cmd_trt_index"), - r_dma_paddr("r_dma_paddr"), - // FIFOs - m_dma_cmd_addr_fifo("m_dma_cmd_addr_fifo",4), - //m_dma_cmd_length_fifo("m_dma_cmd_length_fifo",4), - m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",4), - m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",4), - m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",4), - m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",4), - m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",4), - m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",4), - m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",4), - m_dma_cmd_eop_fifo("m_dma_cmd_eop_fifo",4), - m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",4), - m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",4), - m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",4), - m_dma_cmd_cfixed_fifo("m_dma_cmd_cfixed_fifo",4), - m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",4), - - r_miss_paddr ("r_miss_paddr"), - r_miss_cmd ("r_miss_cmd"), - r_miss_contig ("r_miss_contig"), - r_miss_cons ("r_miss_cons"), - r_miss_plen ("r_miss_plen"), - r_miss_wrap ("r_miss_wrap"), - r_miss_cfixed ("r_miss_cfixed"), - r_miss_clen ("r_miss_clen"), - r_miss_srcid ("r_miss_srcid"), - r_miss_trdid ("r_miss_trdid"), - r_miss_pktid ("r_miss_pktid"), - - r_dma_error_type("r_dma_error_type"), - r_dma_error_trdid("r_dma_error_trdid"), - r_dma_error_pktid("r_dma_error_pktid"), - - - r_dma_tlb_fsm("r_dma_tlb_fsm"), + r_dma_cmd_vaddr("r_dma_cmd_vaddr"), + r_dma_cmd_paddr("r_dma_cmd_paddr"), + + //DMA_RSP FSM registers + r_dma_rsp_fsm("r_dma_rsp_fsm"), + + // CONFIG_CMD FSM registers + r_config_cmd_fsm("r_config_cmd_fsm"), + r_config_cmd_rdata("r_config_cmd_rdata"), + r_config_cmd_error("r_config_cmd_error"), + r_config_cmd_inval_vaddr("r_config_cmd_inval_vaddr"), + + // CONFIG_RSP FSM registers + r_config_rsp_fsm("r_config_rsp_fsm"), + + // TLB FSM registers + r_tlb_fsm("r_tlb_fsm"), r_waiting_transaction("r_waiting_transaction"), r_tlb_miss_type("r_tlb_miss_type"), - - - r_iotlb_vaddr("r_iotlb_vaddr"), // virtual address for a tlb miss - r_iotlb_paddr("r_iotlb_paddr"), // physical address of pte - r_iotlb_pte_flags("r_iotlb_pte_flags"),// pte1 or first word of pte2 - r_iotlb_pte_ppn("r_iotlb_pte_ppn"), // second word of pte2 - r_iotlb_way("r_iotlb_way"), // selected way in tlb - r_iotlb_set("r_iotlb_set"), // selected set in tlb - - r_iotlb("iotlb", IOMMU_ID, iotlb_ways,iotlb_sets,vci_param_d::N), + r_tlb_miss_error("r_tlb_miss_error"), + r_tlb_paddr("r_tlb_paddr"), + r_tlb_pte_flags("r_tlb_pte_flags"), + r_tlb_pte_ppn("r_tlb_pte_ppn"), + r_tlb_way("r_tlb_way"), + r_tlb_set("r_tlb_set"), + r_tlb_buf_valid("r_tlb_buf_valid"), + r_tlb_buf_tag("r_tlb_buf_tag"), + r_tlb_buf_vaddr("r_tlb_buf_vaddr"), + r_tlb_buf_big_page("r_tlb_buf_big_page"), + + // MISS_WTI_CMD FSM registers + r_miss_wti_cmd_fsm("r_miss_wti_cmd_fsm"), + r_miss_wti_cmd_index("r_miss_wti_cmd_index"), + + // MISS_WTI_CMD FSM registers + r_miss_wti_rsp_fsm("r_miss_wti_rsp_fsm"), + r_miss_wti_rsp_error("r_miss_wti_rsp_error"), + + // allocator for CONFIG_RSP & DMA_RSP fifos + r_alloc_fifo_config_rsp_local("r_alloc_fifo_config_rsp_local"), + r_alloc_fifo_dma_rsp_local("r_alloc_fifo_dma_rsp_local"), + + // IRQs registers + r_irq_pending(alloc_elems >("r_irq_pending", 32)), + r_irq_request(alloc_elems >("r_irq_request", 32)), - //DMA_RSP - r_dma_rsp_fsm("r_dma_rsp_fsm"), - r_dma_rtrdid("r_dma_rtrdid"), - r_dma_rsrcid("r_dma_rsrcid"), - //Fifo's - m_dma_rsp_data_fifo("m_dma_rsp_data_fifo",4), - m_dma_rsp_rsrcid_fifo("m_dma_rsp_rsrcid_fifo",4), - m_dma_rsp_rtrdid_fifo("m_dma_rsp_rtrdid_fifo",4), - m_dma_rsp_rpktid_fifo("m_dma_rsp_rpktid_fifo",4), - m_dma_rsp_reop_fifo("m_dma_rsp_reop_fifo",4), - m_dma_rsp_rerror_fifo("m_dma_rsp_rerror_fifo",4), + // TLB for IOMMU + r_iotlb("iotlb", 0, iotlb_ways, iotlb_sets, vci_param_int::N), + + // Inter-FSM communications + r_dma_tlb_req("r_dma_tlb_req"), + r_config_tlb_req("r_config_tlb_req"), + r_tlb_miss_req("r_tlb_miss_req"), - r_dma_cmd_rsp_erase_req("r_dma_cmd_rsp_erase_req"), - r_dma_cmd_error_req("r_dma_cmd_error_req"), - r_dma_tlb_req("r_dma_tlb_req"), - r_tlb_dma_untreated("r_tlb_dma_untreated"), - r_dma_tlb_error_req("r_dma_tlb_error_req"), - r_config_tlb_req("r_config_tlb_req"), - r_config_tlb_inval_vaddr("r_config_tlb_inval_vaddr"), - - // ALLOC TRT DMA - r_alloc_trt_dma_fsm("r_alloc_trt_dma_fsm"), - - // CONFIG CMD - r_config_cmd_fsm("r_config_cmd_fsm"), - r_config_cmd_trt_index("r_config_cmd_trt_index"), - - m_config_cmd_addr_fifo("m_config_cmd_addr_fifo",4), - //m_config_cmd_length_fifo("m_config_cmd_length_fifo",4), - m_config_cmd_srcid_fifo("m_config_cmd_srcid_fifo",4), - m_config_cmd_trdid_fifo("m_config_cmd_trdid_fifo",4), - m_config_cmd_pktid_fifo("m_config_cmd_pktid_fifo",4), - m_config_cmd_be_fifo("m_config_cmd_be_fifo",4), - m_config_cmd_cmd_fifo("m_config_cmd_cmd_fifo",4), - m_config_cmd_contig_fifo("m_config_cmd_contig_fifo",4), - m_config_cmd_data_fifo("m_config_cmd_data_fifo",4), - m_config_cmd_eop_fifo("m_config_cmd_eop_fifo",4), - m_config_cmd_cons_fifo("m_config_cmd_cons_fifo",4), - m_config_cmd_plen_fifo("m_config_cmd_plen_fifo",4), - m_config_cmd_wrap_fifo("m_config_cmd_wrap_fifo",4), - m_config_cmd_cfixed_fifo("m_config_cmd_cfixed_fifo",4), - m_config_cmd_clen_fifo("m_config_cmd_clen_fifo",4), - // Private configuration registers - r_config_error_type("r_config_error_type"), - r_config_first_word("r_config_first_word"), - r_it_index("r_it_index"), - //Fifo's - m_config_local_data_fifo("m_config_local_data_fifo",4), - m_config_local_rsrcid_fifo("m_config_local_rsrcid_fifo",4), - m_config_local_rtrdid_fifo("m_config_local_rtrdid_fifo",4), - m_config_local_rpktid_fifo("m_config_local_rpktid_fifo",4), - m_config_local_reop_fifo("m_config_local_reop_fifo",4), - m_config_local_rerror_fifo("m_config_local_rerror_fifo",4), - r_config_vaddr("r_config_vaddr"), + // DMA_CMD FIFOs + m_dma_cmd_addr_fifo("m_dma_cmd_addr_fifo",2), + m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",2), + m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",2), + m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",2), + m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",2), + m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",2), + m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",2), + m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",2), + m_dma_cmd_eop_fifo("m_dma_cmd_eop_fifo",2), + m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",2), + m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",2), + m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",2), + m_dma_cmd_cfixed_fifo("m_dma_cmd_cfixed_fifo",2), + m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",2), + + // DMA_RSP FIFOs + m_dma_rsp_data_fifo("m_dma_rsp_data_fifo",2), + m_dma_rsp_rsrcid_fifo("m_dma_rsp_rsrcid_fifo",2), + m_dma_rsp_rtrdid_fifo("m_dma_rsp_rtrdid_fifo",2), + m_dma_rsp_rpktid_fifo("m_dma_rsp_rpktid_fifo",2), + m_dma_rsp_reop_fifo("m_dma_rsp_reop_fifo",2), + m_dma_rsp_rerror_fifo("m_dma_rsp_rerror_fifo",2), + + // CONFIG_CMD FIFOs + m_config_cmd_addr_fifo("m_config_cmd_addr_fifo",2), + m_config_cmd_srcid_fifo("m_config_cmd_srcid_fifo",2), + m_config_cmd_trdid_fifo("m_config_cmd_trdid_fifo",2), + m_config_cmd_pktid_fifo("m_config_cmd_pktid_fifo",2), + m_config_cmd_be_fifo("m_config_cmd_be_fifo",2), + m_config_cmd_cmd_fifo("m_config_cmd_cmd_fifo",2), + m_config_cmd_contig_fifo("m_config_cmd_contig_fifo",2), + m_config_cmd_data_fifo("m_config_cmd_data_fifo",2), + m_config_cmd_eop_fifo("m_config_cmd_eop_fifo",2), + m_config_cmd_cons_fifo("m_config_cmd_cons_fifo",2), + m_config_cmd_plen_fifo("m_config_cmd_plen_fifo",2), + m_config_cmd_wrap_fifo("m_config_cmd_wrap_fifo",2), + m_config_cmd_cfixed_fifo("m_config_cmd_cfixed_fifo",2), + m_config_cmd_clen_fifo("m_config_cmd_clen_fifo",2), + + // CONFIG_RSP FIFOs + m_config_rsp_data_fifo("m_config_rsp_data_fifo",2), + m_config_rsp_rsrcid_fifo("m_config_rsp_rsrcid_fifo",2), + m_config_rsp_rtrdid_fifo("m_config_rsp_rtrdid_fifo",2), + m_config_rsp_rpktid_fifo("m_config_rsp_rpktid_fifo",2), + m_config_rsp_reop_fifo("m_config_rsp_reop_fifo",2), + m_config_rsp_rerror_fifo("m_config_rsp_rerror_fifo",2) +{ + std::cout << " - Building VciIoBridge : " << name << std::endl; + + // checking segments on INT network + assert ( ( not m_int_seglist.empty() ) and + "VCI_IO_BRIDGE ERROR : no segment allocated on INT network"); + + std::list::iterator int_seg; + for ( int_seg = m_int_seglist.begin() ; int_seg != m_int_seglist.end() ; int_seg++ ) + { + std::cout << " => segment " << int_seg->name() + << " / base = " << std::hex << int_seg->baseAddress() + << " / size = " << int_seg->size() << std::endl; + } + + // checking segments on IOX network + assert ( ( not m_iox_seglist.empty() ) and + "VCI_IO_BRIDGE ERROR : no segment allocated on IOX network"); + + std::list::iterator iox_seg; + for ( iox_seg = m_iox_seglist.begin() ; iox_seg != m_iox_seglist.end() ; iox_seg++ ) + { + std::cout << " => segment " << iox_seg->name() + << " / base = " << std::hex << iox_seg->baseAddress() + << " / size = " << iox_seg->size() << std::endl; + } + + assert( (vci_param_int::N == vci_param_ext::N) and + "VCI_IO_BRIDGE ERROR: VCI ADDRESS widths must be equal on the 3 networks"); + + assert( (vci_param_int::N <= 64) and + "VCI_IO_BRIDGE ERROR: VCI ADDRESS width cannot be bigger than 64 bits"); + + assert( ((vci_param_int::B == 4) or (vci_param_int::B == 8)) and + "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 or 64 bits on internal network"); + + assert( ((vci_param_ext::B == 4) or (vci_param_ext::B == 8)) and + "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 or 64 bits on external network"); + + assert( (vci_param_int::S == vci_param_ext::S) and + "VCI_IO_BRIDGE ERROR: SRCID widths must be equal on the 3 networks"); + + // contruct 32 IRQ ports if required + if ( has_irqs ) + { + for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_core::sc_in; + } - // CONFIG RSP - r_config_rsp_fsm("r_config_rsp_fsm"), - r_config_rtrdid("r_config_rtrdid"), - r_config_rsrcid("r_config_rsrcid"), - //Fifo's - m_config_rsp_data_fifo("m_config_rsp_data_fifo",4), - m_config_rsp_rsrcid_fifo("m_config_rsp_rsrcid_fifo",4), - m_config_rsp_rtrdid_fifo("m_config_rsp_rtrdid_fifo",4), - m_config_rsp_rpktid_fifo("m_config_rsp_rpktid_fifo",4), - m_config_rsp_reop_fifo("m_config_rsp_reop_fifo",4), - m_config_rsp_rerror_fifo("m_config_rsp_rerror_fifo",4), - - // Communication between CONFIG CMD and CONFIG RSP - r_config_cmd_rsp_erase_req("r_config_cmd_rsp_erase_req"), - - // ALLOC TRT CONFIG - r_alloc_trt_config_fsm("r_alloc_trt_config_fsm"), - // MISS INIT - r_miss_init_fsm("r_miss_init_fsm"), - r_miss_rdata("r_miss_rdata"), - r_miss_rpktid("r_miss_rpktid"), - r_miss_rtrdid("r_miss_rtrdid"), - r_miss_rerror("r_miss_rerror"), - r_miss_reop("r_miss_reop"), - //r_miss_rsrcid("r_miss_rsrcid"), - r_miss_rsp_cpt("r_miss_rsp_cpt"), - //IRQ - r_irq_pending("r_irq_pending"), - r_irq_mask("r_irq_mask"), - r_irq_chosen("r_irq_chosen"), - - r_tlb_miss_init_req("r_tlb_miss_init_req"), - r_miss_init_error("r_miss_init_error"), - - r_miss_buf_valid("r_miss_buf_valid"), - r_miss_buf_tag("r_miss_buf_tag") -{ - assert( (vci_param_d::N <= 64) and - "ADDRESS cannot be bigger than 64 bits"); - assert( (vci_param_x::B)*8 == 64 and (vci_param_io::B)*8 == 64 and - "DATA field must be 64 bits in Extern and IO Network"); - assert ( (vci_param_d::B)*8 == 32 - and "Error: data field in Direct Noc must be 32 bits" ); - - - // Interruption Address vector, one entry for each IO - r_it_addr = new paddr_t[nb_periph]; - // One cache line buffer - r_miss_buf_data = new vci_data_t[dcache_words]; - // Command storage in case of miss TLB - // (dcache_words/2) => Maximal size of a write command - r_miss_data = new vci_data_t[dcache_words]; - r_miss_be = new vci_be_t[dcache_words]; - + // Cache line buffer + r_tlb_buf_data = new uint32_t[dcache_words]; + SC_METHOD(transition); dont_initialize(); @@ -389,9 +321,9 @@ ///////////////////////////////////// { - delete [] r_it_addr; - delete [] r_miss_buf_data; - delete [] r_miss_data; - delete [] r_miss_be; - soclib::common::dealloc_elems(p_irq_in, m_nb_periph); + delete [] r_iommu_peri_wti; + delete [] r_tlb_buf_data; + soclib::common::dealloc_elems(p_irq, 32); + soclib::common::dealloc_elems(r_irq_request, 32); + soclib::common::dealloc_elems(r_irq_pending, 32); } @@ -404,13 +336,11 @@ std::cout << std::dec << "IO_BRIDGE " << name() << std::endl; - std::cout << " " << dma_cmd_fsm_state_str[r_dma_cmd_fsm.read()] + std::cout << " " << dma_cmd_fsm_state_str[r_dma_cmd_fsm.read()] << " | " << dma_rsp_fsm_state_str[r_dma_rsp_fsm.read()] - << " | " << dma_tlb_fsm_state_str[r_dma_tlb_fsm.read()] - << " | " << alloc_trt_dma_fsm_state_str[r_alloc_trt_dma_fsm.read()] + << " | " << tlb_fsm_state_str[r_tlb_fsm.read()] << " | " << config_cmd_fsm_state_str[r_config_cmd_fsm.read()] << " | " << config_rsp_fsm_state_str[r_config_rsp_fsm.read()] - << " | " << alloc_trt_config_fsm_state_str[r_alloc_trt_config_fsm.read()] - << " | " << miss_init_fsm_state_str[r_miss_init_fsm.read()]; - std::cout << std::endl; + << " | " << miss_wti_fsm_state_str[r_miss_wti_cmd_fsm.read()] + << std::endl; if(mode & 0x01) @@ -424,6 +354,4 @@ } } - - //////////////////////// @@ -447,9 +375,4 @@ m_cpt_iotlbmiss_transaction = 0; m_cost_iotlbmiss_transaction = 0; - - m_cpt_trt_dma_full = 0; - m_cpt_trt_dma_full_cost = 0; - m_cpt_trt_config_full = 0; - m_cpt_trt_config_full_cost = 0; } @@ -460,20 +383,18 @@ if ( not p_resetn.read() ) { - - r_dma_cmd_fsm = DMA_CMD_IDLE; - r_dma_rsp_fsm = DMA_RSP_IDLE; - r_alloc_trt_dma_fsm = ALLOC_TRT_DMA_CMD; - r_dma_tlb_fsm = DMA_TLB_IDLE; - r_config_cmd_fsm = CONFIG_CMD_IDLE; - r_config_rsp_fsm = CONFIG_RSP_IDLE; - r_alloc_trt_config_fsm = ALLOC_TRT_CONFIG_CMD; - r_miss_init_fsm = MISS_INIT_IDLE_MISS; - - //miss buffer invalidation - r_miss_buf_valid = false; - - r_iommu_active = false; - - r_dma_cmd_count = 0; + r_dma_cmd_fsm = DMA_CMD_IDLE; + r_dma_rsp_fsm = DMA_RSP_IDLE; + r_tlb_fsm = TLB_IDLE; + r_config_cmd_fsm = CONFIG_CMD_IDLE; + r_config_rsp_fsm = CONFIG_RSP_IDLE; + r_miss_wti_cmd_fsm = MISS_WTI_CMD_IDLE; + r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; + + r_alloc_fifo_config_rsp_local = true; + r_alloc_fifo_dma_rsp_local = true; + + r_tlb_buf_valid = false; + r_iommu_active = false; + r_iommu_wti_enable = false; // initializing FIFOs @@ -522,206 +443,137 @@ m_config_rsp_reop_fifo.init(); - m_config_local_rsrcid_fifo.init(); - m_config_local_rtrdid_fifo.init(); - m_config_local_rpktid_fifo.init(); - m_config_local_data_fifo.init(); - m_config_local_rerror_fifo.init(); - m_config_local_reop_fifo.init(); - - //Communication between DMA_CMD and DMA_RSP - r_dma_cmd_rsp_erase_req =false; - r_dma_cmd_error_req =false; - //Communication between DMA_CMD and TLB - r_dma_tlb_req =false; - r_tlb_dma_untreated =false; - //Communication betweeen TLB and CONFIG_CMD - r_config_tlb_req =false; - r_config_tlb_inval_vaddr =false; - r_dma_tlb_error_req =false; - r_tlb_error_type =false; - //Communication between CONFIG_CMD and CONFIG_RSP - r_config_cmd_rsp_erase_req =false; - //Communication between TLB_MISS and MISS_INIT - r_tlb_miss_init_req =false; - r_miss_init_error =false; - // Debug variables - m_debug_dma_rsp_fsm = false; - m_debug_dma_cmd_fsm = false; - m_debug_dma_tlb_fsm = false; - m_debug_config_cmd_fsm = false; - m_debug_config_rsp_fsm = false; - m_debug_miss_init_fsm = false; + // SET/RESET Communication flip-flops + r_dma_tlb_req = false; + r_config_tlb_req = false; + r_tlb_miss_req = false; + + // Debug variable + m_debug_activated = false; - r_irq_mask = 0xFFFFFFFF; - r_irq_chosen = 0; + for ( size_t n=0 ; n<32 ; n++ ) + { + r_irq_pending[n] = false; + r_irq_request[n] = false; + } // activity counters - m_cpt_total_cycles = 0; - m_cpt_iotlb_read = 0; - m_cpt_iotlb_miss = 0; - m_cpt_iotlbmiss_transaction = 0; - m_cost_iotlbmiss_transaction = 0; + m_cpt_total_cycles = 0; + m_cpt_iotlb_read = 0; + m_cpt_iotlb_miss = 0; + m_cpt_iotlbmiss_transaction = 0; + m_cost_iotlbmiss_transaction = 0; - m_cpt_trt_dma_full = 0; - m_cpt_trt_dma_full_cost = 0; - m_cpt_trt_config_full = 0; - m_cpt_trt_config_full_cost = 0; + m_cpt_trt_dma_full = 0; + m_cpt_trt_dma_full_cost = 0; + m_cpt_trt_config_full = 0; + m_cpt_trt_config_full_cost = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_cmd [i] = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_rsp [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_tlb [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_alloc_trt_dma [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tlb [i] = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_cmd [i] = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_rsp [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_alloc_trt_config [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_init [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_wti_cmd [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_wti_rsp [i] = 0; + return; } + // default values for FIFOs + bool dma_cmd_fifo_put = false; + bool dma_cmd_fifo_get = false; + + bool dma_rsp_fifo_put = false; + bool dma_rsp_fifo_get = false; - //bool miss_unposted = false; - bool dma_cmd_fifo_put = false; - bool dma_cmd_fifo_get = false; - bool dma_rsp_fifo_put = false; - bool dma_rsp_fifo_get = false; - - bool config_cmd_fifo_put = false; - bool config_cmd_fifo_get = false; - bool config_rsp_fifo_put = false; - bool config_rsp_fifo_get = false; - bool config_local_fifo_put = false; - bool config_local_fifo_get = false; + bool config_cmd_fifo_put = false; + bool config_cmd_fifo_get = false; + + bool config_rsp_fifo_put = false; + bool config_rsp_fifo_get = false; #ifdef INSTRUMENTATION m_cpt_fsm_dma_cmd [r_dma_cmd_fsm.read()] ++; m_cpt_fsm_dma_rsp [r_dma_rsp_fsm.read() ] ++; - m_cpt_fsm_dma_tlb [r_dma_tlb_fsm.read() ] ++; - m_cpt_fsm_alloc_trt_dma [r_alloc_trt_dma_fsm.read() ] ++; + m_cpt_fsm_tlb [r_tlb_fsm.read() ] ++; m_cpt_fsm_config_cmd [r_config_cmd_fsm.read() ] ++; m_cpt_fsm_config_rsp [r_config_rsp_fsm.read() ] ++; - m_cpt_fsm_alloc_trt_config [r_alloc_trt_config_fsm.read() ] ++; - m_cpt_fsm_miss_init [r_miss_init_fsm.read() ] ++; + m_cpt_fsm_miss_wti_cmd [r_miss_wti_cmd_fsm.read() ] ++; + m_cpt_fsm_miss_wti_rsp [r_miss_wti_rsp_fsm.read() ] ++; #endif m_cpt_total_cycles++; - m_debug_dma_cmd_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_dma_rsp_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_dma_tlb_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_config_cmd_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_config_rsp_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_miss_init_fsm = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; - - ///////////////////////////////////////////////////////////////////// - // The DMA_CMD_FSM controls the following ressources: - // - r_dma_cmd_fsm - // - r_dma_srcid - // - r_dma_tlb_req (set) - // - r_tlb_dma_untreated (reset) - // - r_dma_cmd_rsp_erase_req (set) + m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; + + ////////////////////////////////////////////////////////////////////////////// + // The DMA_CMD_FSM handles DMA transactions requested by peripherals + // It makes the address translation if IOMMU is activated. /////////////////////////////////////////////////////////////////////////////// switch( r_dma_cmd_fsm.read() ) { - ////////////// - case DMA_CMD_IDLE: - { - // Treats an eventual request from TLB_MISS fsm - // to send a command whose miss treatment is now finished - if ( r_tlb_dma_untreated.read() ) - { - r_dma_cmd_fsm = DMA_CMD_TRT_LOCK;//before posting we must update TRT - r_dma_cmd_fsm_save = DMA_CMD_IDLE; - r_miss_interrupt = true; - break; - } - // Error during miss treatment - else if (r_dma_tlb_error_req.read()) - { - r_iommu_etr = r_tlb_error_type.read(); - r_iommu_bvar = r_iotlb_vaddr.read(); - r_iommu_bad_id = r_miss_srcid.read(); - // For DMA_RSP FSM - if(r_miss_cmd.read() == vci_param_io::CMD_WRITE) r_dma_error_type = WRITE_ERROR; - else r_dma_error_type = READ_ERROR; - r_dma_error_trdid = r_miss_trdid.read(); - r_dma_error_pktid = r_miss_pktid.read(); - - r_dma_tlb_error_req = false; - r_dma_cmd_fsm = DMA_CMD_ERROR; - } - - if ( p_vci_tgt_dma.cmdval.read() ) + ////////////////// + case DMA_CMD_IDLE: // waiting DMA VCI transaction + { + if ( p_vci_tgt_iox.cmdval.read() ) // compute physical address { - if ( not r_iommu_active.read()) // iotlb not activated + if ( not r_iommu_active.read() ) // tlb not activated { - // physical address - r_dma_paddr = (paddr_t)p_vci_tgt_dma.address.read(); - r_dma_cmd_fsm = DMA_CMD_TRT_LOCK; +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << " IOMMU not activated" << std::endl; +#endif + // put DMA transaction into DMA_CMD fifo + r_dma_cmd_paddr = p_vci_tgt_iox.address.read(); + r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_CMD; } - else if (r_dma_tlb_fsm.read() == DMA_TLB_IDLE || - r_dma_tlb_fsm.read() == DMA_TLB_WAIT_TRANSACTION ) // iotlb activated + else if (r_tlb_fsm.read() == TLB_IDLE || + r_tlb_fsm.read() == TLB_WAIT ) // tlb access possible { - paddr_t paddr; - - - // We compute physical address and check access rights : - // - If MMU not activated :the physical address is equal to the virtual - //address (identity mapping) and there is no access rights checking - // - If MMU activated : cacheability is defined by the C bit in the PTE, - // the physical address is obtained from the TLB, and the access rights are - // defined by the W bit in the PTE. - - paddr_t iotlb_paddr; + vci_addr_t iotlb_paddr; pte_info_t iotlb_flags; size_t iotlb_way; size_t iotlb_set; - paddr_t iotlb_nline; - bool iotlb_hit = false;; - + vci_addr_t iotlb_nline; + bool iotlb_hit; #ifdef INSTRUMENTATION m_cpt_iotlb_read++; #endif - - iotlb_hit = r_iotlb.translate(p_vci_tgt_dma.address.read(), - &iotlb_paddr, - &iotlb_flags, - &iotlb_nline,// unused - &iotlb_way, // unused - &iotlb_set );// unused + iotlb_hit = r_iotlb.translate(p_vci_tgt_iox.address.read(), + &iotlb_paddr, + &iotlb_flags, + &iotlb_nline, // unused + &iotlb_way, // unused + &iotlb_set ); // unused - - if ( iotlb_hit ) // tlb hit + if ( iotlb_hit ) // tlb hit { - paddr = iotlb_paddr; - - // access rights checking - if ( not iotlb_flags.w and - (p_vci_tgt_dma.cmd.read() == vci_param_io::CMD_WRITE) ) + if ( not iotlb_flags.w and // access right violation + (p_vci_tgt_iox.cmd.read() == vci_param_ext::CMD_WRITE) ) { - r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; - r_iommu_bvar = p_vci_tgt_dma.address.read(); - r_iommu_bad_id = p_vci_tgt_dma.srcid.read(); - r_dma_cmd_fsm = DMA_CMD_ERROR; - // For DMA_RSP - r_dma_error_type = WRITE_ERROR; - r_dma_error_trdid = p_vci_tgt_dma.trdid.read(); - r_dma_error_pktid = p_vci_tgt_dma.pktid.read(); + // put DMA response error into DMA_RSP fifo + r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; + r_iommu_bvar = p_vci_tgt_iox.address.read(); + r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); + r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; #if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " HIT in iotlb, but writable violation" << std::endl; -} -#endif - break; +if( m_debug_activated ) +std::cout << " TLB HIT but writable violation" << std::endl; +#endif } - - // Physical address registration - r_dma_paddr = paddr; - r_dma_cmd_fsm = DMA_CMD_TRT_LOCK; - } - // TLB miss: we enter TLB_MISS treatment sub-fsm - else + else // no access rights violation + { +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << " TLB HIT" << std::endl; +#endif + // put DMA transaction into DMA_CMD fifo + r_dma_cmd_paddr = iotlb_paddr; + r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_CMD; + } + } + else // TLB miss { @@ -729,32 +581,12 @@ m_cpt_iotlb_miss++; #endif - if( r_dma_tlb_req.read() || r_tlb_dma_untreated.read() || r_dma_tlb_error_req.read() ) - { - // There's already a ongoing request - // or a completed request but not yet put on FIFO. - // We stay blocked - r_dma_cmd_fsm = DMA_CMD_TLB_MISS_WAIT; + // register virtual address, and send request to TLB FSM + r_dma_cmd_vaddr = p_vci_tgt_iox.address.read(); + r_dma_tlb_req = true; + r_dma_cmd_fsm = DMA_CMD_MISS_WAIT; #if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " MISS in iotlb. There is a pending request." << std::endl; -} -#endif - } - else - { - // We register request virtual address, to be used by DMA_TLB_MISS FSM - r_iotlb_vaddr = p_vci_tgt_dma.address.read(); - assert((r_dma_cmd_count.read() == 0) - and "ERROR: TRT counter should be 0"); - r_dma_tlb_req = true; - r_dma_cmd_fsm = DMA_CMD_TLB_MISS_STORE; -#if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " MISS in iotlb. No pending request." << std::endl; -} -#endif - } +if( m_debug_activated ) +std::cout << " TLB MISS" << std::endl; +#endif } // end !hit } // end if tlb_activated @@ -762,604 +594,303 @@ break; } - ///////////////////////// - case DMA_CMD_TRT_LOCK: // Waiting for the lock to modify Transaction Table - { - if ( r_alloc_trt_dma_fsm.read() == ALLOC_TRT_DMA_CMD ) - { - -#if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " Check the TRT" << std::endl; -} -#endif - size_t wok_index = 0; - bool wok = !m_transaction_tab_dma.full(wok_index); - - if ( wok ) // TRT isn't full. Write the new transaction. - { - r_dma_cmd_trt_index = (vci_trdid_t)wok_index; - r_dma_cmd_fsm = DMA_CMD_TRT_SET; - } - else // wait an empty entry in TRT - { - r_dma_cmd_rsp_erase_req = true; - r_dma_cmd_fsm = DMA_CMD_TRT_WAIT; -#if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " TRT is full. Going to TRT_WAIT state" << std::endl; -} -#endif + ////////////////////////// + case DMA_CMD_FIFO_PUT_CMD: // put a DMA transaction in DMA_CMD fifo + // if contig, VCI address must be incremented + { + if ( p_vci_tgt_iox.cmdval && m_dma_cmd_addr_fifo.wok() ) + { + dma_cmd_fifo_put = true; -#ifdef INSTRUMENTATION -m_cpt_trt_dma_full++; -#endif - } - } - break; - } - //////////////// - case DMA_CMD_TRT_WAIT: // release the lock protecting the transaction tab - // waits that RSP erases an entry - { -#ifdef INSTRUMENTATION -m_cpt_trt_dma_full_cost++; -#endif - // DMA_RSP will notify an erase action by reseting this register - if(!r_dma_cmd_rsp_erase_req.read()) - { - r_dma_cmd_fsm = DMA_CMD_TRT_LOCK; // take the lock again - } - break; - } - //////////////////////// - case DMA_CMD_TRT_SET: // register a new transaction in TRT - { - if ( r_alloc_trt_dma_fsm.read() == ALLOC_TRT_DMA_CMD ) - { - if(r_miss_interrupt.read()) - { - m_transaction_tab_dma.set(r_dma_cmd_trt_index.read(), - r_miss_srcid.read(), - r_miss_trdid.read() ); - r_dma_cmd_fsm = DMA_CMD_FIFO_MISS_PUT; - } - else - { - m_transaction_tab_dma.set(r_dma_cmd_trt_index.read(), - p_vci_tgt_dma.srcid.read(), - p_vci_tgt_dma.trdid.read() ); - r_dma_cmd_fsm = DMA_CMD_FIFO_PUT; - } -#if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " Set a new entry in TRT" << std::endl; - if(r_miss_interrupt.read()) std::cout << " From the Network " << std::endl; - else std::cout << " From miss interruption" << std::endl; -} -#endif - } - break; - } - /////////////////////// - case DMA_CMD_FIFO_PUT: - { - if ( p_vci_tgt_dma.cmdval && m_dma_cmd_addr_fifo.wok() ) - { - dma_cmd_fifo_put = true; - //miss_unposted = false; - if( p_vci_tgt_dma.contig ) r_dma_paddr = r_dma_paddr.read() + 4; - if( p_vci_tgt_dma.eop ) r_dma_cmd_fsm = DMA_CMD_IDLE; + if ( p_vci_tgt_iox.contig.read() ) r_dma_cmd_paddr = r_dma_cmd_paddr.read() + + vci_param_ext::B; + + if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_IDLE; #if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " Push into cmd_fifo:" - << " address = " << std::hex << r_dma_paddr.read() - << " srcid = " << std::dec << m_srcid_dma - << " trdid = " << r_dma_cmd_trt_index.read() - << " wdata = " << std::hex << p_vci_tgt_dma.wdata.read() - << " be = " << p_vci_tgt_dma.be.read() - << " contig = " << p_vci_tgt_dma.contig.read() - << " eop = " << std::dec << p_vci_tgt_dma.eop.read() - << " plen = " << std::dec << p_vci_tgt_dma.plen.read() << std::endl; -} -#endif +if( m_debug_activated ) +std::cout << " Push into DMA_CMD fifo:" + << " address = " << std::hex << r_dma_cmd_paddr.read() + << " srcid = " << p_vci_tgt_iox.srcid.read() + << " trdid = " << p_vci_tgt_iox.trdid.read() + << " wdata = " << p_vci_tgt_iox.wdata.read() + << " be = " << p_vci_tgt_iox.be.read() + << " contig = " << p_vci_tgt_iox.contig.read() + << " eop = " << std::dec << p_vci_tgt_iox.eop.read() + << " plen = " << std::dec << p_vci_tgt_iox.plen.read() << std::endl; +#endif + } + break; + } + ////////////////////// + case DMA_CMD_WAIT_EOP: // An error has been detected on the VCI DMA command + // consume the VCI packet before sending the error response + { + if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; + break; + } + ////////////////////////// + case DMA_CMD_FIFO_PUT_RSP: // try to put a response error in DMA_RSP fifo + // The FIFO is shared with DMA_RSP FSM + // and we must we wait for allocation... + { + if ( r_alloc_fifo_dma_rsp_local.read() ) + { + dma_rsp_fifo_put = true; + + if( m_dma_rsp_data_fifo.wok() ) + { + +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << " Put a response error to a DMA transaction." + << std::endl; +#endif + r_dma_cmd_fsm = DMA_CMD_IDLE; + } } break; } /////////////////////// - case DMA_CMD_FIFO_MISS_PUT: - { - if ( m_dma_cmd_addr_fifo.wok() ) - { - dma_cmd_fifo_put = true; - //miss_unposted = true; - if( r_miss_contig.read() ) r_miss_paddr = r_miss_paddr.read() + 4; - - if( r_dma_cmd_count.read() == 1 ) + case DMA_CMD_MISS_WAIT: // waiting completion of a TLB miss + // we must test a possible page fault error... + { + if ( not r_dma_tlb_req.read() ) // TLB miss completed + { + if ( r_tlb_miss_error.read() ) // Error reported by TLB FSM { - r_tlb_dma_untreated = false; - r_miss_interrupt = false; - r_dma_cmd_fsm = r_dma_cmd_fsm_save.read(); + r_iommu_etr = MMU_READ_PT2_UNMAPPED; + r_iommu_bvar = r_dma_cmd_vaddr.read(); + r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); + r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; } - r_dma_cmd_count = r_dma_cmd_count.read() - 1; - -#if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " Push into cmd_fifo:" - << " counter = " << std::hex << r_dma_cmd_count.read() - << " address = " << std::hex << r_miss_paddr.read() - << " srcid = " << std::dec << r_miss_srcid.read() - << " trdid = " << r_miss_trdid.read() - << " wdata = " << std::hex << r_miss_data - << " be = " << r_miss_be - << " plen = " << std::dec << r_miss_plen.read() << std::endl; -} -#endif - } - break; - } - /////////////////// - case DMA_CMD_TLB_MISS_WAIT: // to store the miss request there must be - // neither an ongoing request, nor a unposted finished request - { - // Treats an eventual request from TLB_MISS fsm - // to send a command whose miss treatment is now finished - if ( r_tlb_dma_untreated.read() ) - { - r_dma_cmd_fsm = DMA_CMD_TRT_LOCK; //before posting we must update TRT - r_dma_cmd_fsm_save = DMA_CMD_TLB_MISS_WAIT; - r_miss_interrupt = true; - break; - } - // Error during miss treatment - else if (r_dma_tlb_error_req.read()) - { - r_iommu_etr = r_tlb_error_type.read(); - r_iommu_bvar = r_iotlb_vaddr.read(); - r_iommu_bad_id = r_miss_srcid.read(); - // For DMA_RSP FSM - if(r_miss_cmd.read() == vci_param_io::CMD_WRITE) r_dma_error_type = WRITE_ERROR; - else r_dma_error_type = READ_ERROR; - r_dma_error_trdid = r_miss_trdid.read(); - r_dma_error_pktid = r_miss_pktid.read(); - - r_dma_tlb_error_req = false; - r_dma_cmd_fsm = DMA_CMD_ERROR; - } - -#ifdef INSTRUMENTATION -m_cost_iotlb_miss++; // Now it represents misses' total blocking cost (not the treatment cost itself) -#endif - else if (not r_dma_tlb_req.read()) - { - r_dma_cmd_fsm = DMA_CMD_TLB_MISS_STORE; - assert((r_dma_cmd_count.read() == 0) and "ERROR: TRT counter should be 0"); - } - break; - } - /////////////////// - case DMA_CMD_TLB_MISS_STORE: - { - if ( p_vci_tgt_dma.cmdval.read()) - { - if(r_dma_cmd_count.read() == 0) + else // No error { - r_miss_cmd = p_vci_tgt_dma.cmd.read(); - r_miss_contig = p_vci_tgt_dma.contig.read(); - r_miss_cons = p_vci_tgt_dma.cons.read(); - r_miss_plen = p_vci_tgt_dma.plen.read(); - r_miss_wrap = p_vci_tgt_dma.wrap.read(); - r_miss_cfixed = p_vci_tgt_dma.cfixed.read(); - r_miss_clen = p_vci_tgt_dma.clen.read(); - r_miss_srcid = p_vci_tgt_dma.srcid.read(); - r_miss_trdid = p_vci_tgt_dma.trdid.read(); - r_miss_pktid = p_vci_tgt_dma.pktid.read(); - -// r_dma_tlb_req = true; + r_dma_cmd_fsm = DMA_CMD_IDLE; } - - r_miss_data[r_dma_cmd_count.read()] = p_vci_tgt_dma.wdata.read(); - r_miss_be[r_dma_cmd_count.read()] = p_vci_tgt_dma.be.read(); - - r_dma_cmd_count = r_dma_cmd_count.read() + 1; - - if( p_vci_tgt_dma.eop ) r_dma_cmd_fsm = DMA_CMD_IDLE; - -#if DEBUG_DMA_CMD -if( m_debug_dma_cmd_fsm ) -{ - std::cout << " Storing VCI fields of command that originate the Miss:" - << " counter = " << std::hex << r_dma_cmd_count.read() - << " address = " << std::hex << p_vci_tgt_dma.address.read() - << " srcid = " << std::dec << p_vci_tgt_dma.srcid.read() - << " trdid = " << p_vci_tgt_dma.trdid.read() - << " wdata = " << std::hex << p_vci_tgt_dma.wdata.read() - << " be = " << p_vci_tgt_dma.be.read() - << " plen = " << std::dec << p_vci_tgt_dma.plen.read() << std::endl; -} -#endif - } - break; - } - /////////////////// - case DMA_CMD_ERROR: - { - // Wait in case of pending request - // it isn't the case, generally - if(!r_dma_cmd_error_req.read()) - { - r_dma_cmd_error_req = true; - r_dma_cmd_fsm = DMA_CMD_IDLE; - } - break; - } - } // end switch DMA_CMD_FSM - - ///////////////////////////////////////////////////////////////////// - // The DMA_RSP_FSM controls the following ressources: - // - r_dma_rsp_fsm - // - r_dma_cmd_rsp_erase_req (reset) - // - r_fma_error_req (reset) - // - + } + break; + } + } // end switch DMA_CMD FSM + ////////////////////////////////////////////////////////////////////////////// + // The DMA_RSP_FSM handles the RAM responses to peripherals DMA transactions. + ////////////////////////////////////////////////////////////////////////////// + switch( r_dma_rsp_fsm.read() ) { - ///////////////////// - case DMA_RSP_IDLE: + ////////////////// + case DMA_RSP_IDLE: // waiting a response from RAM betwork { - // Interruption from DMA_CMD following an error - if(r_dma_cmd_error_req.read()) r_dma_rsp_fsm = DMA_RSP_FIFO_ERROR_PUT; - - if(p_vci_ini_dma.rspval.read()) + if ( p_vci_ini_ram.rspval.read() ) { - r_dma_rsp_fsm = DMA_RSP_TRT_LOCK; + r_dma_rsp_fsm = DMA_RSP_FIFO_PUT; } break; } - ///////////////////// - case DMA_RSP_TRT_LOCK: - { - if ( r_alloc_trt_dma_fsm.read() == ALLOC_TRT_DMA_RSP ) - { - -#if DEBUG_DMA_RSP -if( m_debug_dma_rsp_fsm ) -{ - std::cout << " Erase entry" << std::endl; -} -#endif - uint32_t trdid_xram = p_vci_ini_dma.rtrdid.read(); - - r_dma_rsrcid = (vci_srcid_t)m_transaction_tab_dma.readSrcid(trdid_xram); - r_dma_rtrdid = (vci_trdid_t)m_transaction_tab_dma.readTrdid(trdid_xram); - m_transaction_tab_dma.erase(trdid_xram); - if (r_dma_cmd_rsp_erase_req.read()) r_dma_cmd_rsp_erase_req = false; - r_dma_rsp_fsm = DMA_RSP_FIFO_PUT; - } - break; - } - ////////////////// + ////////////////////// case DMA_RSP_FIFO_PUT: { - if(p_vci_ini_dma.rspval.read() && m_dma_rsp_data_fifo.wok()) + if(p_vci_ini_ram.rspval.read() and not r_alloc_fifo_dma_rsp_local.read() ) { dma_rsp_fifo_put = true; - if(p_vci_ini_dma.reop.read()) r_dma_rsp_fsm = DMA_RSP_IDLE; + + if(p_vci_ini_ram.reop.read()) r_dma_rsp_fsm = DMA_RSP_IDLE; #if DEBUG_DMA_RSP -if( m_debug_dma_rsp_fsm ) -{ - std::cout << " Push into rsp_fifo:" - << " rsrcid = " << std::dec << r_dma_rsrcid.read() - << " rtrdid = " << r_dma_rtrdid.read() - << " rdata = " << std::hex << p_vci_ini_dma.rdata.read() - << std::endl; -} -#endif - +if( m_debug_activated ) +std::cout << " Push response into DMA_RSP fifo:" + << " / rsrcid = " << std::hex << p_vci_ini_ram.rsrcid.read() + << " / rtrdid = " << p_vci_ini_ram.rtrdid.read() + << " / rdata = " << std::hex << p_vci_ini_ram.rdata.read() + << " / rerror = " << p_vci_ini_ram.rerror.read() + << " / reop = " << p_vci_ini_ram.reop.read() << std::endl; +#endif } break; } - ////////////////// - case DMA_RSP_FIFO_ERROR_PUT: - { - if(m_dma_rsp_data_fifo.wok()) - { - dma_rsp_fifo_put = true; - r_dma_rsp_fsm = DMA_RSP_IDLE; - -#if DEBUG_DMA_RSP -if( m_debug_dma_rsp_fsm ) -{ - std::cout << " Push into rsp_fifo:" - << " rsrcid = " << std::dec << r_iommu_bad_id.read() - << " rtrdid = " << r_dma_error_trdid.read() - << " rerror = " << r_dma_error_type.read() - << " rdata = " << std::hex << 0 - << std::endl; -} -#endif - - } - break; - } } // end switch DMA_RSP_FSM - //////////////////////////////////////////////////////////////////////////// - // The ALLOC_TRT_DMA fsm allocates the access to the Transaction Table (m_transaction_tab_dma) - // with a round robin priority between 2 user FSMs : - // - DMA_CMD : to set a new entry - // - DMA_RSP : to read and erase an entry - // The ressource is always allocated. - //////////////////////////////////////////////////////////////////////////// - - switch ( r_alloc_trt_dma_fsm.read() ) - { - /////////////////// - case ALLOC_TRT_DMA_CMD: - { - if ( r_dma_cmd_fsm.read() != DMA_CMD_TRT_LOCK ) - { - if (r_dma_rsp_fsm.read() == DMA_RSP_TRT_LOCK) r_alloc_trt_dma_fsm = ALLOC_TRT_DMA_RSP; - } - break; - } - /////////////////// - case ALLOC_TRT_DMA_RSP: - { - if (r_dma_rsp_fsm.read() != DMA_RSP_TRT_LOCK) - { - if (r_dma_cmd_fsm.read() == DMA_CMD_TRT_LOCK) r_alloc_trt_dma_fsm = ALLOC_TRT_DMA_CMD; - } - break; - } - } // end switch r_alloc_trt_dma_fsm - - - //////////////////////////////////////////////////////////////////////////// - // The DMA_TLB_MISS FSM handles an IOTLB miss. It blocks the TGT_FSM. - // Input argument is: - // - r_iotlb_vaddr - // - r_dma_tlb_req (reset) - // - r_tlb_miss_init_req (set) - // - r_config_tlb_req (reset) - // - r_tlb_dma_untreated (set) - // - // This fsm searchs the requested PTE on the prefetch buffer. - // In case of miss, it accesses the XRAM to find the missing TLB entry, + ////////////////////////////////////////////////////////////////////////////////// + // The TLB FSM handles TLB miss request (from DMA_CMD FSM), + // and the PTE inval request (from CONFIG_CMD FSM). + // PTE inval request have highest priority. In case of TLB miss, + // this fsm searchs the requested PTE on the prefetch buffer. + // In case of buffer miss, it request the MISS_WTI FSM to access the memory. // It bypass the first level page table access if possible. - // It directly updates the iotlb, and writes into the - // r_mmu_ins_* or r_mmu_data* error reporting registers. + // It reset the r_dma_tlb_req flip-flop to signal TLB miss completion. + // An unexpected, but possible page fault is signaled in r_tlb_miss_error flip_flop. //////////////////////////////////////////////////////////////////////////////////// - switch (r_dma_tlb_fsm.read()) - { - case DMA_TLB_IDLE: - { - if(r_config_tlb_req) - { - r_config_tlb_req = false; + + switch (r_tlb_fsm.read()) + { + ////////////// + case TLB_IDLE: // In case of TLB miss request, chek the prefetch buffer first + // PTE inval request are handled as unmaskable interrupts + { + if ( r_config_tlb_req ) // Request from CONFIG FSM for a PTE invalidation + { + r_config_tlb_req = false; r_waiting_transaction = false; - r_dma_tlb_fsm = DMA_TLB_INVAL_CHECK; - // Request from CONFIG FSM following an PTE invalidation signal by OS - } - // Miss in IOTLB - else if(r_dma_tlb_req.read()) - { - // Checking prefetch buffer, by the virtual address - if(!r_miss_buf_first_level) - { - if( r_miss_buf_valid && - (r_miss_buf_vaddr_begin.read() == - (r_iotlb_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK))) + r_tlb_fsm = TLB_INVAL_CHECK; + } + + else if ( r_dma_tlb_req.read() ) // request from DMA_CMD for a TLB Miss + { + // Checking prefetch buffer + if( not r_tlb_buf_big_page ) // small page => PTE2 { - // Hit - size_t pte_offset = (r_iotlb_vaddr.read()& PTE2_LINE_OFFSET)>>12; - - - uint32_t pte_flags = r_miss_buf_data[2*pte_offset]; - uint32_t pte_ppn = r_miss_buf_data[2*pte_offset+1]; //because PTE2 is 2 words long + if( r_tlb_buf_valid && // Hit on prefetch buffer + (r_tlb_buf_vaddr.read() == + (r_dma_cmd_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK))) + { + size_t pte_offset = (r_dma_cmd_vaddr.read()& PTE2_LINE_OFFSET)>>12; + uint32_t pte_flags = r_tlb_buf_data[2*pte_offset]; + uint32_t pte_ppn = r_tlb_buf_data[2*pte_offset+1]; - // Bit valid checking - if ( not ( pte_flags & PTE_V_MASK) ) // unmapped - { - //must not occur! - std::cout << "IOMMU ERROR : " << name() << " DMA_TLB_IDLE state" << std::endl - << "The Page Table entry ins't valid (unmapped)" << std::endl; + // Bit valid checking + if ( not ( pte_flags & PTE_V_MASK) ) // unmapped + { + std::cout << "VCI_IO_BRIDGE ERROR : " << name() + << " Page Table entry unmapped" << std::endl; - r_tlb_error_type = MMU_READ_PT2_UNMAPPED; - r_dma_tlb_error_req = true; - r_dma_tlb_req = false; - -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " PTE2 Unmapped" - << std::hex << " / paddr = " << r_iotlb_paddr.read() - << std::hex << " / PTE (first word) = " << pte_flags << std::endl; -} -#endif - break; - } - - r_iotlb_pte_flags = pte_flags; - r_iotlb_pte_ppn = pte_ppn; - r_dma_tlb_fsm = DMA_TLB_PTE2_SELECT; - -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " Hit on the prefetch buffer for PTE2:" - << " PTE_FLAGS = " << std::hex << pte_flags - << " PTE_PPN = " << std::hex << pte_ppn << std::endl; -} -#endif - break; + r_tlb_miss_error = true; + r_dma_tlb_req = false; +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " PTE2 Unmapped" << std::hex + << " / paddr = " << r_tlb_paddr.read() + << " / PTE_FLAGS = " << pte_flags + << " / PTE_PPN = " << pte_ppn << std::endl; +#endif + break; + } + + // valid PTE2 : we must update the TLB + r_tlb_pte_flags = pte_flags; + r_tlb_pte_ppn = pte_ppn; + r_tlb_fsm = TLB_PTE2_SELECT; +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Hit on prefetch buffer: PTE2" << std::hex + << " / PTE_FLAGS = " << pte_flags + << " / PTE_PPN = " << pte_ppn << std::endl; +#endif + break; + } } - } - else // First level entries on buffer. Unused if only small pages - { - if( r_miss_buf_valid && - (r_miss_buf_vaddr_begin.read() == - (r_iotlb_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) - // The virtual address corresponds to one entry on the buffer line + else // big page => PTE1 { - // Hit - size_t pte_offset = (r_iotlb_vaddr.read()& PTE1_LINE_OFFSET)>>21; - - uint32_t pte_flags = r_miss_buf_data[pte_offset]; + if( r_tlb_buf_valid && // Hit on prefetch buffer + (r_tlb_buf_vaddr.read() == + (r_dma_cmd_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) + { + size_t pte_offset = (r_dma_cmd_vaddr.read()& PTE1_LINE_OFFSET)>>21; + uint32_t pte_flags = r_tlb_buf_data[pte_offset]; - // Bit valid checking - if ( not ( pte_flags & PTE_V_MASK) ) // unmapped - { - //must not occur! - std::cout << "IOMMU ERROR " << name() << "DMA_TLB_IDLE state" << std::endl - << "The Page Table entry ins't valid (unmapped)" << std::endl; + // Bit valid checking + if ( not ( pte_flags & PTE_V_MASK) ) // unmapped + { + std::cout << "VCI_IO_BRIDGE ERROR : " << name() + << " Page Table entry unmapped" << std::endl; - r_tlb_error_type = MMU_READ_PT1_UNMAPPED; - r_dma_tlb_error_req = true; - r_dma_tlb_req = false; - -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " First level entry Unmapped" - << std::hex << " / paddr = " << r_iotlb_paddr.read() - << std::hex << " / PTE = " << pte_flags << std::endl; -} -#endif - break; - } - - if( pte_flags & PTE_T_MASK ) // PTD : me must access PT2 - { - // register bypass - r_iotlb.set_bypass( r_iotlb_vaddr.read(), - pte_flags & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), - 0); //nline, unused - - //&PTE2 = PTBA + IX2 * 8 - // ps: PAGE_K_NBITS corresponds also to the size of a second level page table - r_iotlb_paddr = (paddr_t)(pte_flags & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | - (paddr_t)(((r_iotlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); - r_tlb_miss_init_req = true; - r_tlb_miss_type = PTE2_MISS; - r_dma_tlb_fsm = DMA_TLB_WAIT_TRANSACTION; + r_tlb_miss_error = true; + r_dma_tlb_req = false; +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " PTE1 Unmapped" << std::hex + << " / paddr = " << r_tlb_paddr.read() + << " / PTE = " << pte_flags << std::endl; +#endif + break; + } + + // valid PTE1 : we must update the TLB + r_tlb_pte_flags = pte_flags; + r_tlb_fsm = TLB_PTE1_SELECT; +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Hit on prefetch buffer: PTE1" << std::hex + << " / paddr = " << r_tlb_paddr.read() + << std::hex << " / PTE1 = " << pte_flags << std::endl; +#endif + break; + } + } + + // prefetch buffer miss + r_tlb_fsm = TLB_MISS; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Miss on prefetch buffer" + << std::hex << " / vaddr = " << r_dma_cmd_vaddr.read() << std::endl; +#endif + } + break; + } + ////////////// + case TLB_MISS: // handling tlb miss + { + uint32_t ptba = 0; + bool bypass; + vci_addr_t pte_paddr; + #ifdef INSTRUMENTATION m_cpt_iotlbmiss_transaction++; #endif - -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " Hit on prefetch, but it is a PTD.Search PTE2" - << std::hex << " / paddr = " << r_iotlb_paddr.read() - << std::hex << " / PTD = " << pte_flags << std::endl; -} -#endif - } - else // PTE1 : we must update the TLB - // Should not occur if working only with small pages - { - r_iotlb_pte_flags = pte_flags; - r_dma_tlb_fsm = DMA_TLB_PTE1_SELECT; - -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " Success. Big page" - << std::hex << " / paddr = " << r_iotlb_paddr.read() - << std::hex << " / PTE1 = " << pte_flags << std::endl; -} -#endif - } - break; - } - } - - r_dma_tlb_fsm = DMA_TLB_MISS; - -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " Miss on prefetch." - << std::hex << " / vaddr = " << r_iotlb_vaddr.read() << std::endl; -} -#endif - } - break; - } - ///////////////////// - case DMA_TLB_MISS: // handling all tlb miss - { - uint32_t ptba = 0; //28 bits en TSAR - bool bypass; - paddr_t pte_paddr; - // evaluate bypass in order to skip first level page table access - bypass = r_iotlb.get_bypass(r_iotlb_vaddr.read(), &ptba); + bypass = r_iotlb.get_bypass(r_dma_cmd_vaddr.read(), &ptba); - //Request to MISS_INIT_FSM to start transaction on Direct Network + // Request MISS_WTI_FSM a transaction on INT Network if ( not bypass ) // Read PTE1/PTD1 in XRAM { - // VOIR CONVENTION >> 13 - pte_paddr = (paddr_t)((r_iommu_ptpr.read()) << (INDEX1_NBITS+2)) | - (paddr_t)((r_iotlb_vaddr.read() >> PAGE_M_NBITS) << 2); - r_iotlb_paddr = pte_paddr; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Read PTE1/PTD1 in memory" << std::endl; +#endif + pte_paddr = (vci_addr_t)((r_iommu_ptpr.read()) << (INDEX1_NBITS+2)) | + (vci_addr_t)((r_dma_cmd_vaddr.read() >> PAGE_M_NBITS) << 2); + r_tlb_paddr = pte_paddr; - r_tlb_miss_init_req = true; - r_tlb_miss_type = PTE1_MISS; - r_dma_tlb_fsm = DMA_TLB_WAIT_TRANSACTION; -#ifdef INSTRUMENTATION -m_cpt_iotlbmiss_transaction++; -#endif + r_tlb_miss_req = true; + r_tlb_miss_type = PTE1_MISS; + r_tlb_fsm = TLB_WAIT; } else // Read PTE2 in XRAM { + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Read PTE2 in memory" << std::endl; +#endif //&PTE2 = PTBA + IX2 * 8 - pte_paddr = (paddr_t)ptba << PAGE_K_NBITS | - (paddr_t)(r_iotlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); + pte_paddr = (vci_addr_t)ptba << PAGE_K_NBITS | + (vci_addr_t)(r_dma_cmd_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); - r_iotlb_paddr = pte_paddr; + r_tlb_paddr = pte_paddr; - r_tlb_miss_init_req = true; - r_tlb_miss_type = PTE2_MISS; - r_dma_tlb_fsm = DMA_TLB_WAIT_TRANSACTION; -#ifdef INSTRUMENTATION -m_cpt_iotlbmiss_transaction++; -#endif - } - -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " IOTLB miss"; - std::cout << " / VADDR = " << std::hex << r_iotlb_vaddr.read() - << " / BYPASS = " << bypass - << " / PTE_ADR = " << pte_paddr << std::endl; -} -#endif - - break; - } - ///////////////////////// - case DMA_TLB_PTE1_GET: // Try to read a PT1 entry in the miss buffer + r_tlb_miss_req = true; + r_tlb_miss_type = PTE2_MISS; + r_tlb_fsm = TLB_WAIT; + } + + break; + } + ////////////////// + case TLB_PTE1_GET: // Try to read a PT1 entry in the miss buffer { uint32_t entry; - paddr_t line_number = (paddr_t)((r_iotlb_paddr.read())&(CACHE_LINE_MASK)); - size_t word_position = (size_t)( ((r_iotlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); + vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); + size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); // Hit test. Just to verify. // Hit must happen, since we've just finished its' miss transaction - bool hit = (r_miss_buf_valid && (r_miss_buf_tag.read()== line_number) ); + bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); - entry = r_miss_buf_data[word_position]; + entry = r_tlb_buf_data[word_position]; // Bit valid checking @@ -1367,16 +898,16 @@ { //must not occur! - std::cout << "IOMMU ERROR " << name() << "DMA_TLB_IDLE state" << std::endl + std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl << "The Page Table entry ins't valid (unmapped)" << std::endl; - r_tlb_error_type = MMU_READ_PT1_UNMAPPED; - r_dma_tlb_error_req = true; - r_dma_tlb_req = false; - r_dma_tlb_fsm = DMA_TLB_IDLE; -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) + r_tlb_miss_error = true; + r_dma_tlb_req = false; + r_tlb_fsm = TLB_IDLE; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) { - std::cout << " First level entry Unmapped" - << std::hex << " / paddr = " << r_iotlb_paddr.read() + std::cout << " First level entry Unmapped" + << std::hex << " / paddr = " << r_tlb_paddr.read() << std::hex << " / PTE = " << entry << std::endl; } @@ -1388,26 +919,25 @@ { // register bypass - r_iotlb.set_bypass( r_iotlb_vaddr.read(), - entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), + r_iotlb.set_bypass( r_dma_cmd_vaddr.read(), + entry & ((1 << (vci_param_int::N-PAGE_K_NBITS)) - 1), 0); //nline, unused //&PTE2 = PTBA + IX2 * 8 // ps: PAGE_K_NBITS corresponds also to the size of a second level page table - r_iotlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | - (paddr_t)(((r_iotlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); - r_tlb_miss_init_req = true; - r_tlb_miss_type = PTE2_MISS; - r_dma_tlb_fsm = DMA_TLB_WAIT_TRANSACTION; + r_tlb_paddr = (vci_addr_t)(entry & ((1<<(vci_param_int::N-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | + (vci_addr_t)(((r_dma_cmd_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); + r_tlb_miss_req = true; + r_tlb_miss_type = PTE2_MISS; + r_tlb_fsm = TLB_WAIT; + #ifdef INSTRUMENTATION m_cpt_iotlbmiss_transaction++; #endif -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " Success. Search PTE2" - << std::hex << " / paddr = " << r_iotlb_paddr.read() - << std::hex << " / PTD = " << entry << std::endl; -} +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Success. Search PTE2" << std::hex + << " / PADDR = " << r_tlb_paddr.read() + << " / PTD = " << entry << std::endl; #endif } @@ -1415,26 +945,23 @@ // Should not occur if working only with small pages { - r_iotlb_pte_flags = entry; - r_dma_tlb_fsm = DMA_TLB_PTE1_SELECT; - -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " Success. Big page" - << std::hex << " / paddr = " << r_iotlb_paddr.read() - << std::hex << " / PTE1 = " << entry << std::endl; -} -#endif - } - - break; - } - //////////////////////////// - case DMA_TLB_PTE1_SELECT: // select a slot for PTE1 + r_tlb_pte_flags = entry; + r_tlb_fsm = TLB_PTE1_SELECT; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Success. Big page" + << std::hex << " / paddr = " << r_tlb_paddr.read() + << std::hex << " / PTE1 = " << entry << std::endl; +#endif + } + break; + } + ///////////////////// + case TLB_PTE1_SELECT: // select a slot for PTE1 { size_t way; size_t set; - r_iotlb.select( r_iotlb_vaddr.read(), + r_iotlb.select( r_dma_cmd_vaddr.read(), true, // PTE1 &way, @@ -1444,26 +971,23 @@ #endif -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " Select a slot in IOTLB:"; - std::cout << " way = " << std::dec << way - << " / set = " << set << std::endl; -} -#endif - r_iotlb_way = way; - r_iotlb_set = set; - r_dma_tlb_fsm = DMA_TLB_PTE1_UPDT; - break; - } - ////////////////////////// - case DMA_TLB_PTE1_UPDT: // write a new PTE1 in tlb - // not necessary to treat the L/R bit - { - //(OLD) paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); - uint32_t pte = r_iotlb_pte_flags.read(); +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Select a slot in TLB" + << " / way = " << std::dec << way + << " / set = " << set << std::endl; +#endif + r_tlb_way = way; + r_tlb_set = set; + r_tlb_fsm = TLB_PTE1_UPDT; + break; + } + /////////////////// + case TLB_PTE1_UPDT: // write a new PTE1 in tlb + // not necessary to treat the L/R bit + { + uint32_t pte = r_tlb_pte_flags.read(); - r_miss_paddr = (paddr_t)( ((r_iotlb_pte_flags.read() & PPN1_MASK) << 21) - | (r_iotlb_vaddr.read()& M_PAGE_OFFSET_MASK) ); + r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_flags.read() & PPN1_MASK) << 21) + | (r_dma_cmd_vaddr.read()& M_PAGE_OFFSET_MASK) ); // update TLB @@ -1471,7 +995,7 @@ pte, 0, // argument unused for a PTE1 - r_iotlb_vaddr.read(), - r_iotlb_way.read(), - r_iotlb_set.read(), + r_dma_cmd_vaddr.read(), + r_tlb_way.read(), + r_tlb_set.read(), 0 ); //we set nline = 0 #ifdef INSTRUMENTATION @@ -1479,75 +1003,71 @@ #endif -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) +#if DEBUG_TLB_MISS +if ( m_debug_activated ) { - std::cout << " write PTE1 in IOTLB"; - std::cout << " / set = " << std::dec << r_iotlb_set.read() - << " / way = " << r_iotlb_way.read() << std::endl; - r_iotlb.printTrace(); +std::cout << " write PTE1 in TLB" + << " / set = " << std::dec << r_tlb_set.read() + << " / way = " << r_tlb_way.read() << std::endl; +r_iotlb.printTrace(); } #endif // next state - r_dma_tlb_fsm = DMA_TLB_RETURN; // exit sub-fsm - break; - } - ///////////////////////// - case DMA_TLB_PTE2_GET: // Try to read a PTE2 (64 bits) in the miss buffer + r_tlb_fsm = TLB_RETURN; // exit sub-fsm + break; + } + ////////////////// + case TLB_PTE2_GET: // Try to read a PTE2 (64 bits) in the miss buffer { uint32_t pte_flags; uint32_t pte_ppn; - paddr_t line_number = (paddr_t)((r_iotlb_paddr.read())&(CACHE_LINE_MASK)); - size_t word_position = (size_t)( ((r_iotlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); + vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); + size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); // Hit test. Just to verify. - bool hit = (r_miss_buf_valid && (r_miss_buf_tag.read()== line_number) ); + bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); - pte_flags= r_miss_buf_data[word_position]; - pte_ppn= r_miss_buf_data[word_position+1]; //because PTE2 is 2 words long + pte_flags= r_tlb_buf_data[word_position]; + pte_ppn= r_tlb_buf_data[word_position+1]; //because PTE2 is 2 words long // Bit valid checking if ( not ( pte_flags & PTE_V_MASK) ) // unmapped { //must not occur! - std::cout << "IOMMU ERROR " << name() << "DMA_TLB_IDLE state" << std::endl + std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl << "The Page Table entry ins't valid (unmapped)" << std::endl; - r_tlb_error_type = MMU_READ_PT2_UNMAPPED; - r_dma_tlb_error_req = true; - r_dma_tlb_req = false; - r_dma_tlb_fsm = DMA_TLB_IDLE; -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " PTE2 Unmapped" - << std::hex << " / paddr = " << r_iotlb_paddr.read() - << std::hex << " / PTE = " << pte_flags << std::endl; -} -#endif - break; + r_tlb_miss_error = true; + r_dma_tlb_req = false; + r_tlb_fsm = TLB_IDLE; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " PTE2 Unmapped" << std::hex + << " / PADDR = " << r_tlb_paddr.read() + << " / PTE = " << pte_flags << std::endl; +#endif + break; } - r_iotlb_pte_flags = pte_flags; - r_iotlb_pte_ppn = pte_ppn; - r_dma_tlb_fsm = DMA_TLB_PTE2_SELECT; + r_tlb_pte_flags = pte_flags; + r_tlb_pte_ppn = pte_ppn; + r_tlb_fsm = TLB_PTE2_SELECT; -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " Mapped:" - << " PTE_FLAGS = " << std::hex << pte_flags - << " PTE_PPN = " << std::hex << pte_ppn << std::endl; -} +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " Mapped" << std::hex + << " / PTE_FLAGS = " << pte_flags + << " / PTE_PPN = " << pte_ppn << std::endl; #endif break; } //////////////////////////// - case DMA_TLB_PTE2_SELECT: // select a slot for PTE2 + case TLB_PTE2_SELECT: // select a slot for PTE2 { size_t way; size_t set; - r_iotlb.select( r_iotlb_vaddr.read(), + r_iotlb.select( r_dma_cmd_vaddr.read(), false, // PTE2 &way, @@ -1557,27 +1077,26 @@ #endif -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) +#if DEBUG_TLB_MISS +if ( m_debug_activated ) { - std::cout << " Select a slot in IOTLB:"; + std::cout << " Select a slot in IOTLB:"; std::cout << " way = " << std::dec << way << " / set = " << set << std::endl; } #endif - r_iotlb_way = way; - r_iotlb_set = set; - r_dma_tlb_fsm = DMA_TLB_PTE2_UPDT; - break; - } - ////////////////////////// - case DMA_TLB_PTE2_UPDT: // write a new PTE2 in tlb - // not necessary to treat the L/R bit - { - //(OLD) paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); - uint32_t pte_flags = r_iotlb_pte_flags.read(); - uint32_t pte_ppn = r_iotlb_pte_ppn.read(); + r_tlb_way = way; + r_tlb_set = set; + r_tlb_fsm = TLB_PTE2_UPDT; + break; + } + /////////////////// + case TLB_PTE2_UPDT: // write a new PTE2 in tlb + // not necessary to treat the L/R bit + { + uint32_t pte_flags = r_tlb_pte_flags.read(); + uint32_t pte_ppn = r_tlb_pte_ppn.read(); - r_miss_paddr = (paddr_t)( ((r_iotlb_pte_ppn.read() & PPN2_MASK) << 12) - | (r_iotlb_vaddr.read()& K_PAGE_OFFSET_MASK) ); + r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_ppn.read() & PPN2_MASK) << 12) + | (r_dma_cmd_vaddr.read()& K_PAGE_OFFSET_MASK) ); // update TLB for a PTE2 @@ -1585,7 +1104,7 @@ pte_flags, pte_ppn, - r_iotlb_vaddr.read(), - r_iotlb_way.read(), - r_iotlb_set.read(), + r_dma_cmd_vaddr.read(), + r_tlb_way.read(), + r_tlb_set.read(), 0 ); // nline = 0 #ifdef INSTRUMENTATION @@ -1593,26 +1112,26 @@ #endif -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) +#if DEBUG_TLB_MISS +if ( m_debug_activated ) { - std::cout << " write PTE2 in IOTLB"; - std::cout << " / set = " << std::dec << r_iotlb_set.read() - << " / way = " << r_iotlb_way.read() << std::endl; + std::cout << " write PTE2 in IOTLB"; + std::cout << " / set = " << std::dec << r_tlb_set.read() + << " / way = " << r_tlb_way.read() << std::endl; r_iotlb.printTrace(); } #endif // next state - r_dma_tlb_fsm = DMA_TLB_RETURN; // exit sub-fsm - break; - } - /////////////////////// - case DMA_TLB_WAIT_TRANSACTION: - { - // CONFIG FSM request following a invalidation signal sent by OS. - if(r_config_tlb_req) + r_tlb_fsm = TLB_RETURN; + break; + } + ////////////// + case TLB_WAIT: // waiting completion of a miss transaction from MISS_WTI FSM + // PTE inval request are handled as unmaskable interrupts + { + if ( r_config_tlb_req ) // Request from CONFIG FSM for a PTE invalidation { r_config_tlb_req = false; r_waiting_transaction = true; - r_dma_tlb_fsm = DMA_TLB_INVAL_CHECK; + r_tlb_fsm = TLB_INVAL_CHECK; } @@ -1620,65 +1139,61 @@ m_cost_iotlbmiss_transaction++; #endif - if ( not r_tlb_miss_init_req ) // Miss transaction is done + if ( not r_tlb_miss_req ) // Miss transaction is done { - if ( r_miss_init_error.read() ) // bus error + if ( r_miss_wti_rsp_error.read() ) // bus error { - r_miss_init_error = false; - r_tlb_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; - r_dma_tlb_error_req = true; - r_dma_tlb_req = false; - r_dma_tlb_fsm = DMA_TLB_IDLE; + r_miss_wti_rsp_error = false; + r_tlb_miss_error = true; + r_dma_tlb_req = false; + r_tlb_fsm = TLB_IDLE; } else if(r_tlb_miss_type == PTE1_MISS) { - r_dma_tlb_fsm = DMA_TLB_PTE1_GET; - + r_tlb_fsm = TLB_PTE1_GET; } else { - r_dma_tlb_fsm = DMA_TLB_PTE2_GET; + r_tlb_fsm = TLB_PTE2_GET; } } break; } - /////////////////////// - case DMA_TLB_RETURN: // return to caller depending on tlb miss type - { -#if DEBUG_DMA_TLB -if ( m_debug_dma_tlb_fsm ) -{ - std::cout << " IOTLB MISS completed" << std::endl; -} -#endif - r_dma_tlb_req = false; - r_tlb_dma_untreated = true; - r_dma_tlb_fsm = DMA_TLB_IDLE; - break; - } - ////////////////////// - case DMA_TLB_INVAL_CHECK: // request from CONFIG FSM to invalidate all PTE on a given line - // This state checks the necessity to invalidate prefetch buffer + //////////////// + case TLB_RETURN: // reset r_dma_tlb_req flip-flop to signal TLB miss completion + // possible errors are signaled through r_tlb_miss_error + { +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << " IOTLB MISS completed" << std::endl; +#endif + r_dma_tlb_req = false; + r_tlb_fsm = TLB_IDLE; + break; + } + ///////////////////// + case TLB_INVAL_CHECK: // request from CONFIG_FSM to invalidate all PTE in a given line + // checks the necessity to invalidate prefetch buffer { // If a transaction is pending, no need to invalidate the prefetch // We can ignore it, since we'll replace the line. // The new line is necessarily up-to-date - if(!r_waiting_transaction.read() && r_miss_buf_valid) - { - if(!r_miss_buf_first_level) + if(!r_waiting_transaction.read() && r_tlb_buf_valid) + { + if(!r_tlb_buf_big_page) { - if( r_miss_buf_vaddr_begin.read() == - (r_config_tlb_inval_vaddr.read()& ~PTE2_LINE_OFFSET) ) + if( r_tlb_buf_vaddr.read() == + (r_config_cmd_inval_vaddr.read()& ~PTE2_LINE_OFFSET) ) // The virtual address corresponds to one entry on the buffer line { - r_miss_buf_valid = false; //change here for individual invalidation + r_tlb_buf_valid = false; //change here for individual invalidation } } else // First level entries on buffer. Unused if only small pages { - if( r_miss_buf_vaddr_begin.read() == - (r_config_tlb_inval_vaddr.read()& ~PTE1_LINE_OFFSET) ) + if( r_tlb_buf_vaddr.read() == + (r_config_cmd_inval_vaddr.read()& ~PTE1_LINE_OFFSET) ) // The virtual address corresponds to one entry on the buffer line { - r_miss_buf_valid = false; //change here for individual invalidation + r_tlb_buf_valid = false; //change here for individual invalidation } } @@ -1687,596 +1202,224 @@ // Invalidation on IOTLB bool ok; - ok = r_iotlb.inval(r_config_tlb_inval_vaddr.read()); + ok = r_iotlb.inval(r_config_cmd_inval_vaddr.read()); - if(r_waiting_transaction.read()) r_dma_tlb_fsm =DMA_TLB_WAIT_TRANSACTION; - else r_dma_tlb_fsm = DMA_TLB_IDLE; + if(r_waiting_transaction.read()) r_tlb_fsm =TLB_WAIT; + else r_tlb_fsm = TLB_IDLE; break; } - } //end switch r_dma_tlb_fsm + } //end switch r_tlb_fsm - - ///////////////////////////////////////////////////////////////////// - // The CONFIG_CMD_FSM is similar to the DMA_CMD_FSM, but without miss TLB treatment. - // It controls the following ressources: - // - r_config_cmd_fsm - // - // - r_config_cmd_rsp_erase_req (set) - // - r_config_tlb_req (set) - ///////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + // The CONFIG_CMD_FSM handles the VCI commands from the INT network. + // This FSM is mainly intended to handle single flit config transactions, + // but it can also handle software driven, multi-flits data transactions. + // - The configuration requests can be local (IO_BRIDGE config registers) + // or remote (config registers of peripherals on IOX network). + // - The data requests are always remote. + // In case of local config, this FSM put a VCI response in CONFIG_RSP fifo. + // In case of remote transaction, it put the VCI command in CONFIG_CMD fifo. + /////////////////////////////////////////////////////////////////////////////// switch( r_config_cmd_fsm.read() ) { - ////////////// - case CONFIG_CMD_IDLE: - { - if ( p_vci_tgt_config.cmdval.read() ) - { + ///////////////////// + case CONFIG_CMD_IDLE: // waiting VCI command + { + if ( p_vci_tgt_int.cmdval.read() ) + { + #if DEBUG_CONFIG_CMD -if( m_debug_config_cmd_fsm ) -{ - std::cout << " Configuration command received!" <>2); - - // Treatement of received command - // Verifies error, tests if the the command is for IOB itself +if( m_debug_activated ) +std::cout << " Command received" + << " / address = " << std::hex << p_vci_tgt_int.address.read() + << " / srcid = " << std::dec << p_vci_tgt_int.srcid.read() + << " / trdid = " << p_vci_tgt_int.trdid.read() + << " / wdata = " << std::hex << p_vci_tgt_int.wdata.read() + << " / be = " << p_vci_tgt_int.be.read() + << " / plen = " << std::dec << p_vci_tgt_int.plen.read() + << " / eop = " << p_vci_tgt_int.eop.read() << std::endl; +#endif + vci_addr_t paddr = p_vci_tgt_int.address.read(); + bool read = (p_vci_tgt_int.cmd.read() == vci_param_int::CMD_READ); + uint32_t cell = (uint32_t)((paddr & 0x1FF)>>2); - // To IOB itself - if(m_segment_config.contains(config_paddr)) + // The "local" segment must be the first in the seglist + soclib::common::Segment seg = m_int_seglist.front(); + + if ( seg.contains(paddr) ) // IO_BRIDGE itself { - if(!read && (cell == IOB_IOMMU_PTPR)) - r_config_cmd_fsm = CONFIG_CMD_PTPR_WRITE; - else if(read && (cell == IOB_IOMMU_PTPR)) - r_config_cmd_fsm = CONFIG_CMD_PTPR_READ; - else if(!read && (cell == IOB_IOMMU_ACTIVE)) - r_config_cmd_fsm = CONFIG_CMD_ACTIVE_WRITE; - else if(read && (cell == IOB_IOMMU_ACTIVE)) - r_config_cmd_fsm = CONFIG_CMD_ACTIVE_READ; - else if(read && (cell == IOB_IOMMU_BVAR)) - r_config_cmd_fsm = CONFIG_CMD_BVAR_READ; - else if(read && (cell == IOB_IOMMU_ETR)) - r_config_cmd_fsm = CONFIG_CMD_ETR_READ; - else if(read && (cell == IOB_IOMMU_BAD_ID)) - r_config_cmd_fsm = CONFIG_CMD_BAD_ID_READ; - // PTE invalidation signaled by the OS - else if(!read && (cell == IOB_INVAL_PTE)) - r_config_cmd_fsm = CONFIG_CMD_INVAL_REQ; - else if(!read && (cell == IOB_IT_ADDR_IOMMU_LO)) - r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1; - else if(read && (cell == IOB_IT_ADDR_IOMMU_LO)) - r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_IOMMU_READ_1; - else if( !read && ((cell >= IOB_IT_ADDR_BEGIN)&& - ( cell< (IOB_IT_ADDR_BEGIN +2*m_nb_periph-1) ) ) ) - { - // a factor two shows up because the registres come in couples - r_it_index = (cell - IOB_IT_ADDR_BEGIN)/2; - r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_WRITE_1; + uint32_t rdata = 0; + bool rerror = false; + + if ( not read && (cell == IOB_IOMMU_PTPR) ) // WRITE PTPR + { + r_iommu_ptpr = (uint32_t)p_vci_tgt_int.wdata.read(); + } + else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR + { + rdata = r_iommu_ptpr.read(); + } + else if( not read && (cell == IOB_WTI_ENABLE)) // WRITE WTI_ENABLE + { + r_iommu_wti_enable = p_vci_tgt_int.wdata.read(); + } + else if( read && (cell == IOB_WTI_ENABLE)) // READ WTI ENABLE + { + rdata = r_iommu_wti_enable.read(); + } + else if( read && (cell == IOB_IOMMU_BVAR)) // READ BVAR + { + rdata = r_iommu_bvar.read(); + } + else if( read && (cell == IOB_IOMMU_ETR)) // READ ETR + { + rdata = r_iommu_etr.read(); + } + else if( read && (cell == IOB_IOMMU_BAD_ID)) // READ BAD_ID + { + rdata = r_iommu_bad_id.read(); + } + else if( not read && (cell == IOB_INVAL_PTE)) // WRITE INVAL_PTE + { + r_config_tlb_req = true; + r_config_cmd_inval_vaddr = (uint32_t)p_vci_tgt_int.wdata.read(); + } + else if( not read && (cell == IOB_WTI_ADDR_LO)) // WRITE WTI_PADDR_LO + { + r_iommu_wti_paddr = (vci_addr_t)p_vci_tgt_int.wdata.read(); + } + else if( read && (cell == IOB_WTI_ADDR_LO)) // READ WTI_PADDR_LO + { + rdata = (uint32_t)r_iommu_wti_paddr.read(); + } + else if( not read && (cell == IOB_WTI_ADDR_HI)) // WRITE WTI_PADDR_HI + { + r_iommu_wti_paddr = (r_iommu_wti_paddr.read() & 0x00000000FFFFFFFFLL) | + ((vci_addr_t)p_vci_tgt_int.wdata.read())<<32; + } + else if( read && (cell == IOB_WTI_ADDR_HI)) // READ WTI_PADDR_HI + { + rdata = (uint32_t)(r_iommu_wti_paddr.read()>>32); + } + else if( not read && ((cell >= IOB_PERI_WTI_BEGIN) // WRITE PERI WTI + && (cell< (IOB_PERI_WTI_BEGIN + 64))) ) + { + size_t index = (cell - IOB_PERI_WTI_BEGIN)/2; + bool high = (cell - IOB_PERI_WTI_BEGIN)%2; + if ( high ) r_iommu_peri_wti[index] = // set 32 MSB bits + (r_iommu_peri_wti[index].read() & 0x00000000FFFFFFFFLL) | + ((vci_addr_t)p_vci_tgt_int.wdata.read())<<32; + else r_iommu_peri_wti[index] = // set 32 LSB bits + (vci_addr_t)p_vci_tgt_int.wdata.read(); } - else if( read && ((cell >= IOB_IT_ADDR_BEGIN)&& - (cell< (IOB_IT_ADDR_BEGIN +2*m_nb_periph-1))) ) - { - r_it_index = (cell - IOB_IT_ADDR_BEGIN)/2; - r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_READ_1; - } - else - //Error. Wrong address, or invalid operation. - { - if(read) r_config_error_type = READ_ERROR; - else r_config_error_type = WRITE_ERROR; - r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; - } + else if( read && ((cell >= IOB_PERI_WTI_BEGIN) // READ PERI WTI + && (cell< (IOB_PERI_WTI_BEGIN + 64))) ) + { + size_t index = (cell - IOB_PERI_WTI_BEGIN)/2; + bool high = (cell - IOB_PERI_WTI_BEGIN)%2; + if ( high ) rdata = (uint32_t)(r_iommu_peri_wti[index].read()>>32); + else rdata = (uint32_t)(r_iommu_peri_wti[index].read()); + } + else // Error: Wrong address, or invalid operation. + { + rerror = true; + } + r_config_cmd_rdata = rdata; + r_config_cmd_error = rerror; + r_config_cmd_fsm = CONFIG_CMD_FIFO_PUT_RSP; } - // Must route the command to the correct IO - else + else // remote peripheral { - if(!p_vci_tgt_config.eop.read()) - { - //Error - if(read) r_config_error_type = READ_ERROR; - else r_config_error_type = WRITE_ERROR; - r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; - } - - // Find the corresponding address on IO Space -// int tgt_index = m_routing_table_config[config_paddr]; -//#if DEBUG_CONFIG_CMD -//if( m_debug_config_cmd_fsm ) -//{ -// std::cout << " Routing a configuration packet" < Check the TRT" << std::endl; -} -#endif - size_t wok_index = 0; - bool wok = !m_transaction_tab_config.full(wok_index); - - if ( wok ) // TRT isn't full. Write the new transaction. +if( m_debug_activated ) +std::cout << " Transmit VCI command to IOX network" + << " : address = " << std::hex << p_vci_tgt_int.address.read() + << " / srcid = " << p_vci_tgt_int.srcid.read() + << std::endl; +#endif + if( p_vci_tgt_int.eop.read() ) r_config_cmd_fsm = CONFIG_CMD_IDLE; + } + break; + } + ///////////////////////////// + case CONFIG_CMD_FIFO_PUT_RSP: // Try to put a response in CONFIG_RSP fifo, + // for a local configuration transaction. + // The FIFO is shared with CONFIG_RSP FSM + // and must we wait for allocation... + { + if ( p_vci_tgt_int.cmdval.read() and r_alloc_fifo_config_rsp_local.read() ) + { + config_rsp_fifo_put = true; + + if ( m_config_rsp_data_fifo.wok() ) { - r_config_cmd_trt_index = (vci_trdid_t)wok_index; - r_config_cmd_fsm = CONFIG_CMD_TRT_SET; - } - else // wait an empty entry in TRT - { - r_config_cmd_fsm = CONFIG_CMD_TRT_WAIT; - r_config_cmd_rsp_erase_req = true; + #if DEBUG_CONFIG_CMD -if( m_debug_config_cmd_fsm ) -{ - std::cout << " TRT is full. Going to TRT_WAIT state" << std::endl; -} -#endif - -#ifdef INSTRUMENTATION -m_cpt_trt_config_full++; -#endif +if( m_debug_activated ) +std::cout << " Response to a local configuration request" + << std::endl; +#endif + if( p_vci_tgt_int.eop.read() ) r_config_cmd_fsm = CONFIG_CMD_IDLE; } } break; } - //////////////// - case CONFIG_CMD_TRT_WAIT: // release the lock protecting the transaction tab - // waits that RSP erases an entry - { -#ifdef INSTRUMENTATION -m_cpt_trt_config_full_cost++; -#endif - // CONFIG_RSP will notify an erase action by reseting this register - if(!r_config_cmd_rsp_erase_req.read()) - { - r_config_cmd_fsm = CONFIG_CMD_TRT_LOCK; // take the lock again - } - break; - } - //////////////////////// - case CONFIG_CMD_TRT_SET: // register a new transaction in TRT - { - if ( r_alloc_trt_config_fsm.read() == ALLOC_TRT_CONFIG_CMD ) - { - m_transaction_tab_config.set( r_config_cmd_trt_index.read(), - p_vci_tgt_config.srcid.read(), - p_vci_tgt_config.trdid.read() ); - - r_config_cmd_fsm = CONFIG_CMD_FIFO_PUT; -#if DEBUG_CONFIG_CMD -if( m_debug_config_cmd_fsm ) -{ - std::cout << " Set a new entry in TRT" << std::endl; -} -#endif - } - break; - } - /////////////////////// - case CONFIG_CMD_FIFO_PUT: - { - if ( p_vci_tgt_config.cmdval && m_config_cmd_addr_fifo.wok() ) - { - config_cmd_fifo_put = true; - if( p_vci_tgt_config.eop ) r_config_cmd_fsm = CONFIG_CMD_IDLE; - -#if DEBUG_CONFIG_CMD -if( m_debug_config_cmd_fsm ) -{ - std::cout << " Push into config_cmd_fifo:" - << " address = " << std::hex << r_config_vaddr.read() - << " srcid = " << std::dec << m_srcid_config - << " trdid = " << r_config_cmd_trt_index.read() - << " wdata = " << std::hex << p_vci_tgt_config.wdata.read() - << " be = " << p_vci_tgt_config.be.read() - << " plen = " << std::dec << p_vci_tgt_config.plen.read() << std::endl; -} -#endif - } - break; - } - - /////////////////////////////// - // Private Configuration States - /////////////////////////////// - - ////////////////// - case CONFIG_CMD_PTPR_WRITE: // Convention- The word received is in the format: - // 00000 BASE_ADDRESS[39:13] - // Same pattern as in iommu_ptpr register - { - if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok() - && r_dma_tlb_fsm == DMA_TLB_IDLE ) - { - // This verification could have been done on IDLE state - // It would save us one cycle - if ( !p_vci_tgt_config.eop.read() ) - { - std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_PTPR_WRITE state" << std::endl; - std::cout << " PTPR write command must contain one single flit" << std::endl; - r_config_error_type = WRITE_ERROR; - r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; - break; - } - - // Depends on the convention - r_iommu_ptpr = (uint32_t)(p_vci_tgt_config.wdata.read()); - - config_local_fifo_put = true; - r_config_cmd_fsm = CONFIG_CMD_IDLE; - -#if DEBUG_CONFIG_CMD -if( m_debug_config_cmd_fsm ) -{ - std::cout << " PTPR received:" - << "r_iommu_ptpr = " << std::hex << (p_vci_tgt_config.wdata.read()) - < Read and erase entry" << std::endl; -} -#endif - uint32_t trdid_iospace = p_vci_ini_config.rtrdid.read(); - - r_config_rsrcid = (vci_srcid_t)m_transaction_tab_config.readSrcid(trdid_iospace); - r_config_rtrdid = (vci_trdid_t)m_transaction_tab_config.readTrdid(trdid_iospace); - m_transaction_tab_config.erase(trdid_iospace); - if (r_config_cmd_rsp_erase_req.read()) r_config_cmd_rsp_erase_req = false; - r_config_rsp_fsm = CONFIG_RSP_FIFO_PUT; - } - break; - } - ////////////////// - case CONFIG_RSP_FIFO_PUT: - { - if(p_vci_ini_config.rspval.read() && m_config_rsp_data_fifo.wok()) + ///////////////////////// + case CONFIG_RSP_FIFO_PUT: // try to write into CONFIG_RSP fifo + // as soon as it is allocated + { + if ( p_vci_ini_iox.rspval.read() and not r_alloc_fifo_config_rsp_local.read() ) { config_rsp_fifo_put = true; - if(p_vci_ini_config.reop.read()) r_config_rsp_fsm = CONFIG_RSP_IDLE; + + if ( m_config_rsp_data_fifo.wok() ) + { + if ( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE; #if DEBUG_CONFIG_RSP -if( m_debug_config_rsp_fsm ) -{ - std::cout << " Push into rsp_fifo:" - << " rsrcid = " << std::dec << r_config_rsrcid.read() - << " rtrdid = " << r_config_rtrdid.read() - << " rdata = " << std::hex << p_vci_ini_config.rdata.read() - << std::endl; -} -#endif +if( m_debug_activated ) +std::cout << " Push response into CONFIG_RSP fifo:" + << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() + << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() + << " / rdata = " << p_vci_ini_iox.rdata.read() + << " / reop = " << p_vci_ini_iox.reop.read() + << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; +#endif + } } @@ -2285,619 +1428,432 @@ } // end switch CONFIG_RSP FSM - - //////////////////////////////////////////////////////////////////////////// - // The ALLOC_TRT_CONFIG fsm allocates the access to the Transaction Table (m_transaction_tab_config) - // with a round robin priority between 2 user FSMs : - // - CONFIG_CMD : to set a new entry - // - CONFIG_RSP : to read and erase an entry - // The ressource is always allocated. + ///////////////////////////////////////////////////////////////////////////////// + // If the IOB component has IRQ ports, the IRQ FSM detects all changes + // on the 32 p_irq[i] ports and request a VCI write transaction to the + // MISS_INIT FSM, using the 64 r_irq_request[i] and r_irq_pending[i] flip-flops. + ///////////////////////////////////////////////////////////////////////////////// + + if ( m_has_irqs ) + { + for ( size_t i = 0; i<32; ++i ) + { + r_irq_request[i] = ( p_irq[i]->read() == not r_irq_pending[i].read() ); + r_irq_pending[i] = p_irq[i]->read(); + } + } + + /////////////////////////////////////////////////////////////////////////////////// + // The MISS_WTI_CMD FSM send VCI commands on the Internal Network. + // It handles PTE MISS requests from TLB_MISS FSM and software IRQs. + // It supports several simultaneous VCI transactions. //////////////////////////////////////////////////////////////////////////////////// - - switch ( r_alloc_trt_config_fsm.read() ) - { - /////////////////// - case ALLOC_TRT_CONFIG_CMD: - { - if ( r_config_cmd_fsm.read() != CONFIG_CMD_TRT_LOCK ) - { - if (r_config_rsp_fsm.read() == CONFIG_RSP_TRT_LOCK) r_alloc_trt_config_fsm = ALLOC_TRT_CONFIG_RSP; - } - } - /////////////////// - case ALLOC_TRT_CONFIG_RSP: - { - if (r_config_rsp_fsm.read() != CONFIG_RSP_TRT_LOCK) - { - if (r_config_cmd_fsm.read() == CONFIG_CMD_TRT_LOCK) r_alloc_trt_config_fsm = ALLOC_TRT_CONFIG_CMD; - } - } - } // end switch r_alloc_trt_config_fsm - - //////////////////////////////////////////////////////////////////////////// - // The MISS_INIT FSM sends a page table entry miss request into Direct Noc - // It controls the following ressources: - // - r_miss_init_fsm - // - r_tlb_miss_init_req (reset) - // - r_miss_buf_data - // - r_miss_buf_valid - // - r_miss_buf_tag - //////////////////////////////////////////////////////////////////////////////////// - - // Building the interruption vector (systematically) - uint32_t irq_demands = 0; - for ( size_t i = 0; i Send write (irq) command to XICU" - << " irq ID = " << std::dec << r_irq_chosen.read() - << " new mask = " << std::hex << (r_irq_mask.read() & ~(1< Send WTI write command on Internal Network" + << " / IRQID = " << std::dec << r_miss_wti_cmd_index.read() << std::endl; +#endif } break; } - ///////////////////////// // send a read request to Direct Network - case MISS_INIT_TLB_MISS_CMD: - { - if ( p_vci_ini_miss.cmdack ) - { - r_miss_rsp_cpt = 0; //counter for the response flits - r_miss_buf_tag = ( (r_iotlb_paddr.read()) & CACHE_LINE_MASK ); - r_miss_buf_valid = true; + /////////////////////// + case MISS_WTI_CMD_MISS: // send a TLB MISS request on INT Network + { + if ( p_vci_ini_int.cmdack ) + { + r_tlb_buf_tag = ( (r_tlb_paddr.read()) & CACHE_LINE_MASK ); + r_tlb_buf_valid = true; - if(r_tlb_miss_type.read()== PTE1_MISS) - r_miss_buf_vaddr_begin =(r_iotlb_vaddr.read() & ~M_PAGE_OFFSET_MASK & ~PTE1_LINE_OFFSET); - else - r_miss_buf_vaddr_begin =(r_iotlb_vaddr.read() & ~K_PAGE_OFFSET_MASK & ~PTE2_LINE_OFFSET); + if( r_tlb_miss_type.read() == PTE1_MISS ) + r_tlb_buf_vaddr = (r_dma_cmd_vaddr.read() & + ~M_PAGE_OFFSET_MASK & ~PTE1_LINE_OFFSET); + else + r_tlb_buf_vaddr = (r_dma_cmd_vaddr.read() & + ~K_PAGE_OFFSET_MASK & ~PTE2_LINE_OFFSET); - r_miss_init_fsm = MISS_INIT_TLB_MISS_RSP; - -#if DEBUG_MISS_INIT -if( m_debug_miss_init_fsm ) -{ - std::cout << " Send read (tlb entry) request to MEM CACHE: " - << " | address : "<< std::hex <<(paddr_t)((r_iotlb_paddr.read())& CACHE_LINE_MASK) - << std::endl; -} -#endif - } + r_miss_wti_cmd_fsm = MISS_WTI_RSP_MISS; + +#if DEBUG_MISS_WTI +if( m_debug_activated ) +std::cout << " Send TLB MISS command on Internal Network" << std::hex + << " / address = " <<(vci_addr_t)((r_tlb_paddr.read())& CACHE_LINE_MASK) << std::endl; +#endif + } break; } - ////////////////// - case MISS_INIT_TLB_MISS_RSP: - { - if ( p_vci_ini_miss.rspval.read() ) + } // end switch r_miss_wti_cmd_fsm + + /////////////////////////////////////////////////////////////////////////////////// + // The MISS_WTI_RSP FSM handles VCI responses on the Internal Network. + // it can be response to TLB MISS (read transaction) or WTI (write transaction). + // It supports several simultaneous VCI transactions. + //////////////////////////////////////////////////////////////////////////////////// + + switch ( r_miss_wti_rsp_fsm.read() ) + { + case MISS_WTI_RSP_IDLE: // waiting a VCI response + { + if ( p_vci_ini_int.rspval.read() ) { - if ( (p_vci_ini_miss.rerror.read()&0x1) != 0 ) // error reported - { - r_miss_init_error = true; - if ( p_vci_ini_miss.reop.read() ) + if ( p_vci_ini_int.rpktid.read() == PKTID_READ ) // it's a TLB MISS response + { + r_miss_wti_rsp_fsm = MISS_WTI_RSP_MISS; + r_miss_wti_rsp_count = 0; + } + else // it's a WTI WRITE response + { + r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI; + + } + } + break; + } + ////////////////////// + case MISS_WTI_RSP_WTI: // Handling response to a WTI transaction + { + assert( p_vci_ini_int.reop.read() and + "VCI_IO_BRIDGE ERROR: IRQ Write response should have one single flit" ); + + assert( ( (p_vci_ini_int.rerror.read()&0x1) == 0 ) and + "VCI_IO_BRIDGE ERROR: IRQ Write response error !!!" ); + // TODO traiter error using the IOMMU IRQ + +#if DEBUG_MISS_WTI +if( m_debug_activated ) +std::cout << " Response to WTI write" << std::endl; +#endif + r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; + break; + } + /////////////////////// + case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS transaction + { + if ( p_vci_ini_int.rspval.read() ) + { + if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported + { + r_miss_wti_rsp_error = true; + if ( p_vci_ini_int.reop.read() ) { - r_miss_init_fsm = MISS_INIT_IDLE_IRQ; - r_tlb_miss_init_req = false; + r_miss_wti_cmd_fsm = MISS_WTI_RSP_IDLE; + r_tlb_miss_req = false; } -#if DEBUG_MISS_INIT -if( m_debug_miss_init_fsm ) -{ - std::cout << " ERROR " << std::endl; -} -#endif - } - else +#if DEBUG_MISS_WTI +if( m_debug_activated ) +std::cout << " ERROR " << std::endl; +#endif + } + else // no error { - bool eop = p_vci_ini_miss.reop.read(); - - -#if DEBUG_MISS_INIT -if( m_debug_miss_init_fsm ) -{ - std::cout << " Response from Mem Cache to a read (tlb entry) transaction. Count = " << r_miss_rsp_cpt.read() - <<" | Data = " << std::hex << p_vci_ini_miss.rdata.read() << std::endl; -} -#endif - - assert(((eop == (r_miss_rsp_cpt.read() == (m_words-1))) ) - and "Error : invalid length for a response from MEM CACHE"); - r_miss_buf_data[r_miss_rsp_cpt] = (uint32_t)p_vci_ini_miss.rdata.read(); - - r_miss_rsp_cpt = r_miss_rsp_cpt.read() + 1; + bool eop = p_vci_ini_int.reop.read(); + +#if DEBUG_MISS_WTI +if( m_debug_activated ) +std::cout << " Response to a tlb miss transaction" + << " / Count = " << r_miss_wti_rsp_count.read() + << " / Data = " << std::hex << p_vci_ini_int.rdata.read() << std::endl; +#endif + assert(((eop == (r_miss_wti_rsp_count.read() == (m_words-1)))) and + "VCI_IO_BRIDGE ERROR: invalid length for a TLB MISS response"); + + r_tlb_buf_data[r_miss_wti_rsp_count.read()] = p_vci_ini_int.rdata.read(); + r_miss_wti_rsp_count = r_miss_wti_rsp_count.read() + 1; if ( eop ) { - r_tlb_miss_init_req = false; //reset the request flip-flop - r_miss_init_fsm = MISS_INIT_IDLE_IRQ; + r_tlb_miss_req = false; //reset the request flip-flop + r_miss_wti_cmd_fsm = MISS_WTI_RSP_IDLE; } - } } break; } - - } // end switch r_miss_init_fsm + } // end switch r_miss_wti_rsp_fsm + + ///////////////////////////////////////////////////////////////////////// + // This flip-flop allocates the access to the CONFIG_RSP fifo + // with a round robin priority between 2 clients FSMs : + // - CONFIG_CMD : to put a response to a local config command. + // - CONFIG_RSP : to put a response to a peripheral config command. + // The ressource is always allocated. + // A new allocation occurs when the owner FSM is not using it, + // and the other FSM is requiring it. + ///////////////////////////////////////////////////////////////////////// - ////////////////////////////////// - // Fifo consumption arbitration // - ////////////////////////////////// + if ( r_alloc_fifo_config_rsp_local.read() ) + { + if ( (r_config_rsp_fsm.read() == CONFIG_RSP_FIFO_PUT) and + (r_config_cmd_fsm.read() != CONFIG_CMD_FIFO_PUT_RSP) ) + r_alloc_fifo_config_rsp_local = false; + } + else + { + if ( (r_config_cmd_fsm.read() == CONFIG_CMD_FIFO_PUT_RSP) and + (r_config_rsp_fsm.read() != CONFIG_RSP_FIFO_PUT) ) + r_alloc_fifo_config_rsp_local = true; + } + + ///////////////////////////////////////////////////////////////////////// + // This flip-flop allocates the access to the DMA_RSP fifo + // with a round robin priority between 2 clients FSMs : + // - DMA_CMD : to put a error response in case of bad address translation + // - DMA_RSP : to put a normal response to a DMA transaction. + // The ressource is always allocated. + // A new allocation occurs when the owner FSM is not using it, + // and the other FSM is requiring it. + ///////////////////////////////////////////////////////////////////////// - // Round Robin priority for CONFIG_RSP FIFO consumption - r_config_rsp_fifo_local_priority = ! r_config_rsp_fifo_local_priority.read(); - - //DMA CMD - dma_cmd_fifo_get = (p_vci_ini_dma.cmdack.read() && m_dma_cmd_addr_fifo.rok()); - // DMA RSP - dma_rsp_fifo_get = (p_vci_tgt_dma.rspack.read() && m_dma_rsp_data_fifo.rok()); - // CONFIG CMD - config_cmd_fifo_get = (p_vci_ini_config.cmdack.read() && m_config_cmd_addr_fifo.rok() ); - // CONFIG RSP, detemines wich fifo to consume - if(r_config_rsp_fifo_local_priority) - { - if(m_config_local_data_fifo.rok()) config_local_fifo_get = p_vci_tgt_config.rspack.read(); - else if (m_config_rsp_data_fifo.rok()) config_rsp_fifo_get = p_vci_tgt_config.rspack.read(); - - } - else - { - if (m_config_rsp_data_fifo.rok()) config_rsp_fifo_get = p_vci_tgt_config.rspack.read(); - else if(m_config_local_data_fifo.rok()) config_local_fifo_get = p_vci_tgt_config.rspack.read(); - } - /////////////// - //DMA_CMD Fifo - /////////////// - if(r_miss_interrupt) - { - m_dma_cmd_addr_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_paddr.read() ); - m_dma_cmd_cmd_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_cmd.read() ); - m_dma_cmd_contig_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_contig.read() ); - m_dma_cmd_cons_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_cons.read() ); - m_dma_cmd_plen_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_plen.read() ); - m_dma_cmd_wrap_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_wrap.read() ); - m_dma_cmd_cfixed_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_cfixed.read() ); - m_dma_cmd_clen_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_clen.read() ); - m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - m_srcid_dma ); //r_miss_srcid.read() - m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_trdid.read() ); - m_dma_cmd_pktid_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_pktid.read() ); - m_dma_cmd_data_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_data[r_dma_cmd_count.read()-1] ); - m_dma_cmd_be_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_miss_be[r_dma_cmd_count.read()-1] ); - m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - (r_dma_cmd_count.read() == 1) ); + if ( r_alloc_fifo_dma_rsp_local.read() ) + { + if ( (r_dma_rsp_fsm.read() == DMA_RSP_FIFO_PUT) and + (r_dma_cmd_fsm.read() != DMA_CMD_FIFO_PUT_RSP) ) + r_alloc_fifo_dma_rsp_local = false; } else { - m_dma_cmd_addr_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_dma_paddr.read() ); - m_dma_cmd_cmd_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.cmd.read() ); - m_dma_cmd_contig_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.contig.read() ); - m_dma_cmd_cons_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.cons.read() ); - m_dma_cmd_plen_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.plen.read() ); - m_dma_cmd_wrap_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.wrap.read() ); - m_dma_cmd_cfixed_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.cfixed.read() ); - m_dma_cmd_clen_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.clen.read() ); - m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - m_srcid_dma ); - m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - r_dma_cmd_trt_index.read() ); - m_dma_cmd_pktid_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.pktid.read() ); - m_dma_cmd_data_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.wdata.read() ); // TODO change - // For 64bits XRAM - m_dma_cmd_be_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.be.read() ); - m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get, - dma_cmd_fifo_put, - p_vci_tgt_dma.eop.read() ); - } - - /////////////// - //DMA_RSP Fifo - /////////////// - if(r_dma_rsp_fsm.read() == DMA_RSP_FIFO_ERROR_PUT) - { - m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - 0 ); + if ( (r_dma_cmd_fsm.read() == DMA_CMD_FIFO_PUT_RSP) and + (r_dma_rsp_fsm.read() != DMA_RSP_FIFO_PUT) ) + r_alloc_fifo_dma_rsp_local = true; + } + + // Define GET signals for all output FIFOs + dma_cmd_fifo_get = p_vci_ini_ram.cmdack.read(); + dma_rsp_fifo_get = p_vci_tgt_iox.rspack.read(); + config_cmd_fifo_get = p_vci_ini_iox.cmdack.read(); + config_rsp_fifo_get = p_vci_tgt_int.rspack.read(); + + /////////////////////////////////////////////////////////// + // DMA_CMD fifo update + // One writer : DMA_CMD FSM + /////////////////////////////////////////////////////////// + + m_dma_cmd_addr_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + r_dma_cmd_paddr.read() ); // address translation + m_dma_cmd_cmd_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.cmd.read() ); + m_dma_cmd_contig_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.contig.read() ); + m_dma_cmd_cons_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.cons.read() ); + m_dma_cmd_plen_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.plen.read() ); + m_dma_cmd_wrap_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.wrap.read() ); + m_dma_cmd_cfixed_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.cfixed.read() ); + m_dma_cmd_clen_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.clen.read() ); + m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.srcid.read() ); + m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.trdid.read() ); + m_dma_cmd_pktid_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.pktid.read() ); + m_dma_cmd_data_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.wdata.read() ); + m_dma_cmd_be_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.be.read() ); + m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.eop.read() ); + + ////////////////////////////////////////////////////////////// + // DMA_RSP fifo update + // Two writers : DMA_CMD FSM & DMA_RSP FSM + ////////////////////////////////////////////////////////////// + + if (r_alloc_fifo_dma_rsp_local.read() ) // owner is DMA_CMD FSM + // local response for a translation error + { + m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + 0 ); // no data if error m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - r_iommu_bad_id.read() ); + dma_rsp_fifo_put, + p_vci_tgt_iox.rsrcid.read() ); m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - r_dma_error_trdid.read() ); + dma_rsp_fifo_put, + p_vci_tgt_iox.rtrdid.read() ); m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - r_dma_error_pktid.read() ); - m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - true ); + dma_rsp_fifo_put, + p_vci_tgt_iox.rpktid.read() ); + m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + true ); // single flit response m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, dma_rsp_fifo_put, - r_dma_error_type.read() ); - } - else - { - m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_dma.rdata.read() ); + 1 ); // error + } + else // owner is DMA_RSP FSM + // normal response to a DMA transaction + { + m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + p_vci_ini_ram.rdata.read() ); m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - r_dma_rsrcid.read() ); + dma_rsp_fifo_put, + p_vci_ini_ram.rsrcid.read() ); m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - r_dma_rtrdid.read() ); + dma_rsp_fifo_put, + p_vci_ini_ram.rtrdid.read() ); m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_dma.rpktid.read() ); - m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_dma.reop.read() ); + dma_rsp_fifo_put, + p_vci_ini_ram.rpktid.read() ); + m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + p_vci_ini_ram.reop.read() ); m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, dma_rsp_fifo_put, - p_vci_ini_dma.rerror.read() ); - } - - ////////////////// - //CONFIG_CMD Fifo - ////////////////// - m_config_cmd_addr_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - r_config_vaddr.read() ); - m_config_cmd_cmd_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.cmd.read() ); + p_vci_ini_ram.rerror.read() ); + } + + //////////////////////////////////////////////////////////////// + // CONFIG_CMD fifo update + // One writer : CONFIG_CMD FSM + //////////////////////////////////////////////////////////////// + + m_config_cmd_addr_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.address.read() ); + m_config_cmd_cmd_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.cmd.read() ); m_config_cmd_contig_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.contig.read() ); - m_config_cmd_cons_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.cons.read() ); - m_config_cmd_plen_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.plen.read() ); - m_config_cmd_wrap_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.wrap.read() ); + config_cmd_fifo_put, + p_vci_tgt_int.contig.read() ); + m_config_cmd_cons_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.cons.read() ); + m_config_cmd_plen_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.plen.read() ); + m_config_cmd_wrap_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.wrap.read() ); m_config_cmd_cfixed_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.cfixed.read() ); - m_config_cmd_clen_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.clen.read() ); - m_config_cmd_srcid_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - m_srcid_config ); - m_config_cmd_trdid_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - r_config_cmd_trt_index.read() ); - m_config_cmd_pktid_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.pktid.read() ); - m_config_cmd_data_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.wdata.read() ); - m_config_cmd_be_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.be.read() ); - m_config_cmd_eop_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - p_vci_tgt_config.eop.read() ); + config_cmd_fifo_put, + p_vci_tgt_int.cfixed.read() ); + m_config_cmd_clen_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.clen.read() ); + m_config_cmd_srcid_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.srcid.read() ); + m_config_cmd_trdid_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.trdid.read() ); + m_config_cmd_pktid_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.pktid.read() ); + m_config_cmd_data_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + (ext_data_t)p_vci_tgt_int.wdata.read() ); + m_config_cmd_be_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.be.read() ); + m_config_cmd_eop_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + p_vci_tgt_int.eop.read() ); - ////////////////// - //CONFIG_RSP Fifo - ////////////////// - m_config_rsp_data_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_ini_config.rdata.read() ); - m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - r_config_rsrcid.read() ); - m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - r_config_rtrdid.read() ); - m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_ini_config.rpktid.read() ); - m_config_rsp_reop_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_ini_config.reop.read() ); - m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_ini_config.rerror.read() ); + ////////////////////////////////////////////////////////////////////////// + // CONFIG_RSP fifo update + // There is two writers : CONFIG_CMD FSM & CONFIG_RSP FSM + ////////////////////////////////////////////////////////////////////////// + + if ( r_alloc_fifo_config_rsp_local.read() ) // owner is CONFIG_CMD FSM + // response for a local config transaction + { + m_config_rsp_data_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + (int_data_t)r_config_cmd_rdata.read() ); + m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + p_vci_tgt_int.srcid.read() ); + m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + p_vci_tgt_int.trdid.read() ); + m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + p_vci_tgt_int.pktid.read() ); + m_config_rsp_reop_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + true ); // local config are one flit + m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + r_config_cmd_error.read() ); + } + else // owner is CONFIG_RSP FSM + // response for a remote transaction + { + m_config_rsp_data_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + (int_data_t)p_vci_ini_iox.rdata.read() ); + m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + p_vci_ini_iox.rsrcid.read() ); + m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + p_vci_ini_iox.rtrdid.read() ); + m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + p_vci_ini_iox.rpktid.read() ); + m_config_rsp_reop_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + p_vci_ini_iox.reop.read() ); + m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + p_vci_ini_iox.rerror.read() ); + } - /////////////////////// - //CONFIG Local RSP Fifo - /////////////////////// - m_config_local_rsrcid_fifo.update( config_local_fifo_get, - config_local_fifo_put, - p_vci_tgt_config.srcid.read() ); - m_config_local_rtrdid_fifo.update( config_local_fifo_get, - config_local_fifo_put, - p_vci_tgt_config.trdid.read() ); - m_config_local_rpktid_fifo.update( config_local_fifo_get, - config_local_fifo_put, - p_vci_tgt_config.pktid.read() ); - - switch( r_config_cmd_fsm.read() ) - { - case CONFIG_CMD_PTPR_WRITE: - case CONFIG_CMD_ACTIVE_WRITE: - case CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2: - case CONFIG_CMD_IT_ADDR_WRITE_2: - case CONFIG_CMD_INVAL: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - 0); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - WRITE_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - case CONFIG_CMD_PTPR_READ: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - r_iommu_ptpr.read()); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - case CONFIG_CMD_ACTIVE_READ: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - r_iommu_active.read()); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - case CONFIG_CMD_BVAR_READ: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - r_iommu_bvar.read()); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - case CONFIG_CMD_ETR_READ: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - r_iommu_etr.read()); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - case CONFIG_CMD_BAD_ID_READ: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - r_iommu_bad_id.read()); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - case CONFIG_CMD_IT_ADDR_IOMMU_READ_1: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - (uint32_t)(r_it_addr_iommu.read() & 0xFFFFFFFF) ); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - false ); - break; - case CONFIG_CMD_IT_ADDR_IOMMU_READ_2: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - (uint32_t)((r_it_addr_iommu.read()>>32)&0xFF) ); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - case CONFIG_CMD_IT_ADDR_READ_1: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - (uint32_t)(r_it_addr[r_it_index.read()] & 0xFFFFFFFF) ); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - false ); - break; - case CONFIG_CMD_IT_ADDR_READ_2: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - (uint32_t)((r_it_addr[r_it_index.read()]>>32)&0xFF) ); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - READ_OK ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - case CONFIG_CMD_ERROR_RSP: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - 0); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - r_config_error_type.read() ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - true ); - break; - default: - m_config_local_data_fifo.update( config_local_fifo_get, - config_local_fifo_put, - 0); - m_config_local_rerror_fifo.update( config_local_fifo_get, - config_local_fifo_put, - 0 ); - m_config_local_reop_fifo.update( config_local_fifo_get, - config_local_fifo_put, - false ); - break; - } - } // end transition() @@ -2906,406 +1862,165 @@ /////////////////////// { - ////////////////// - // DMA Commands // - ////////////////// + // VCI initiator command on RAM network + // directly the content of the dma_cmd FIFO + + p_vci_ini_ram.cmdval = m_dma_cmd_addr_fifo.rok(); + p_vci_ini_ram.address = m_dma_cmd_addr_fifo.read(); + p_vci_ini_ram.be = m_dma_cmd_be_fifo.read(); + p_vci_ini_ram.cmd = m_dma_cmd_cmd_fifo.read(); + p_vci_ini_ram.contig = m_dma_cmd_contig_fifo.read(); + p_vci_ini_ram.wdata = m_dma_cmd_data_fifo.read(); + p_vci_ini_ram.eop = m_dma_cmd_eop_fifo.read(); + p_vci_ini_ram.cons = m_dma_cmd_cons_fifo.read(); + p_vci_ini_ram.plen = m_dma_cmd_plen_fifo.read(); + p_vci_ini_ram.wrap = m_dma_cmd_wrap_fifo.read(); + p_vci_ini_ram.cfixed = m_dma_cmd_cfixed_fifo.read(); + p_vci_ini_ram.clen = m_dma_cmd_clen_fifo.read(); + p_vci_ini_ram.trdid = m_dma_cmd_trdid_fifo.read(); + p_vci_ini_ram.pktid = m_dma_cmd_pktid_fifo.read(); + p_vci_ini_ram.srcid = m_dma_cmd_srcid_fifo.read(); - // VCI initiator command on the xram network - if(m_dma_cmd_addr_fifo.rok()) - //&& p_vci_ini_dma.cmdack.read()) - { - p_vci_ini_dma.cmdval = true; - #if NEW_XRAM_VCI - p_vci_ini_dma.address = (paddr_t_x)(m_dma_cmd_addr_fifo.read() >> 6 ) - #else - p_vci_ini_dma.address = m_dma_cmd_addr_fifo.read(); - #endif - - p_vci_ini_dma.be = m_dma_cmd_be_fifo.read(); - p_vci_ini_dma.cmd = m_dma_cmd_cmd_fifo.read(); - p_vci_ini_dma.contig = m_dma_cmd_contig_fifo.read(); - #if NEW_XRAM_VCI - //TODO for 64 bits field - #else - p_vci_ini_dma.wdata = m_dma_cmd_data_fifo.read(); // The first is in param_x - // the second in param_io - #endif - p_vci_ini_dma.eop = m_dma_cmd_eop_fifo.read(); - p_vci_ini_dma.cons = m_dma_cmd_cons_fifo.read(); - p_vci_ini_dma.plen = m_dma_cmd_plen_fifo.read(); - p_vci_ini_dma.wrap = m_dma_cmd_wrap_fifo.read(); - p_vci_ini_dma.cfixed = m_dma_cmd_cfixed_fifo.read(); - p_vci_ini_dma.clen = m_dma_cmd_clen_fifo.read(); - p_vci_ini_dma.trdid = m_dma_cmd_trdid_fifo.read(); - p_vci_ini_dma.pktid = m_dma_cmd_pktid_fifo.read(); - p_vci_ini_dma.srcid = m_dma_cmd_srcid_fifo.read(); - } - else - { - p_vci_ini_dma.cmdval = false; - p_vci_ini_dma.address = 0; - p_vci_ini_dma.be = 0; - p_vci_ini_dma.cmd = vci_param_x::CMD_NOP; - p_vci_ini_dma.contig = false; - p_vci_ini_dma.wdata = 0; - p_vci_ini_dma.eop = false; - p_vci_ini_dma.cons = true; - p_vci_ini_dma.plen = 0; - p_vci_ini_dma.wrap = false; - p_vci_ini_dma.cfixed = false; - p_vci_ini_dma.clen = 0; - p_vci_ini_dma.trdid = 0; - p_vci_ini_dma.pktid = 0; - } - - // VCI target command on the IO network - // it depends on the DMA_CMD FSM state + // VCI target command ack on IOX network + // depends on the DMA_CMD FSM state switch ( r_dma_cmd_fsm.read() ) { case DMA_CMD_IDLE: - case DMA_CMD_TRT_LOCK: - case DMA_CMD_TRT_WAIT: - case DMA_CMD_TRT_SET: - p_vci_tgt_dma.cmdack = false; - break; - case DMA_CMD_FIFO_PUT: - case DMA_CMD_FIFO_MISS_PUT: - p_vci_tgt_dma.cmdack = m_dma_cmd_addr_fifo.wok(); - break; - case DMA_CMD_TLB_MISS_WAIT: - p_vci_tgt_dma.cmdack = false; - break; - case DMA_CMD_TLB_MISS_STORE: - p_vci_tgt_dma.cmdack = true; - break; - case DMA_CMD_ERROR: - p_vci_tgt_dma.cmdack = !r_dma_cmd_error_req.read(); + case DMA_CMD_MISS_WAIT: + p_vci_tgt_iox.cmdack = false; + break; + case DMA_CMD_WAIT_EOP: + p_vci_tgt_iox.cmdack = true; + break; + case DMA_CMD_FIFO_PUT_CMD: + p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); + break; + case DMA_CMD_FIFO_PUT_RSP: + p_vci_tgt_iox.cmdack = m_dma_rsp_data_fifo.wok(); break; }// end switch r_dma_cmd_fsm - ////////////////// - // DMA Responses// - ////////////////// + // VCI target response on IOX network + // directly the content of the DMA_RSP FIFO + + p_vci_tgt_iox.rspval = m_dma_rsp_data_fifo.rok(); + p_vci_tgt_iox.rsrcid = m_dma_rsp_rsrcid_fifo.read(); + p_vci_tgt_iox.rtrdid = m_dma_rsp_rtrdid_fifo.read(); + p_vci_tgt_iox.rpktid = m_dma_rsp_rpktid_fifo.read(); + p_vci_tgt_iox.rdata = m_dma_rsp_data_fifo.read(); + p_vci_tgt_iox.rerror = m_dma_rsp_rerror_fifo.read(); + p_vci_tgt_iox.reop = m_dma_rsp_reop_fifo.read(); + + // VCI initiator response on the RAM Network + // depends on the DMA_RSP FSM state + + p_vci_ini_ram.rspack = m_dma_rsp_data_fifo.wok() and + (r_dma_rsp_fsm.read() == DMA_RSP_FIFO_PUT) and + not r_alloc_fifo_dma_rsp_local.read(); + + // VCI initiator command on IOX network + // directly the content of the CONFIG_CMD FIFO + + p_vci_ini_iox.cmdval = m_config_cmd_addr_fifo.rok(); + p_vci_ini_iox.address = m_config_cmd_addr_fifo.read(); + p_vci_ini_iox.be = m_config_cmd_be_fifo.read(); + p_vci_ini_iox.cmd = m_config_cmd_cmd_fifo.read(); + p_vci_ini_iox.contig = m_config_cmd_contig_fifo.read(); + p_vci_ini_iox.wdata = (ext_data_t)m_config_cmd_data_fifo.read(); + p_vci_ini_iox.eop = m_config_cmd_eop_fifo.read(); + p_vci_ini_iox.cons = m_config_cmd_cons_fifo.read(); + p_vci_ini_iox.plen = m_config_cmd_plen_fifo.read(); + p_vci_ini_iox.wrap = m_config_cmd_wrap_fifo.read(); + p_vci_ini_iox.cfixed = m_config_cmd_cfixed_fifo.read(); + p_vci_ini_iox.clen = m_config_cmd_clen_fifo.read(); + p_vci_ini_iox.trdid = m_config_cmd_trdid_fifo.read(); + p_vci_ini_iox.pktid = m_config_cmd_pktid_fifo.read(); + p_vci_ini_iox.srcid = m_config_cmd_srcid_fifo.read(); - // VCI target response on the IO network - if(m_dma_rsp_data_fifo.rok()) - { - p_vci_tgt_dma.rspval = true; - p_vci_tgt_dma.rsrcid = m_dma_rsp_rsrcid_fifo.read(); - p_vci_tgt_dma.rtrdid = m_dma_rsp_rtrdid_fifo.read(); - - p_vci_tgt_dma.rpktid = m_dma_rsp_rpktid_fifo.read(); + // VCI target command ack on INT network + // it depends on the CONFIG_CMD FSM state + + switch ( r_config_cmd_fsm.read() ) + { + case CONFIG_CMD_IDLE: + p_vci_tgt_int.cmdack = false; + break; + case CONFIG_CMD_FIFO_PUT_CMD: + p_vci_tgt_int.cmdack = m_config_cmd_addr_fifo.wok(); + break; + case CONFIG_CMD_FIFO_PUT_RSP: + p_vci_tgt_int.cmdack = m_config_rsp_data_fifo.wok() and + r_alloc_fifo_config_rsp_local.read(); + break; + }// end switch r_config_cmd_fsm + + // VCI target response on INT network + // directly the content of the CONFIG_RSP FIFO + + p_vci_tgt_int.rspval = m_config_rsp_data_fifo.rok(); + p_vci_tgt_int.rsrcid = m_config_rsp_rsrcid_fifo.read(); + p_vci_tgt_int.rtrdid = m_config_rsp_rtrdid_fifo.read(); + p_vci_tgt_int.rpktid = m_config_rsp_rpktid_fifo.read(); + p_vci_tgt_int.rdata = m_config_rsp_data_fifo.read(); + p_vci_tgt_int.rerror = m_config_rsp_rerror_fifo.read(); + p_vci_tgt_int.reop = m_config_rsp_reop_fifo.read(); - #if NEW_XRAM_VCI - //TODO for 64 bit data field - #else - p_vci_tgt_dma.rdata = m_dma_rsp_data_fifo.read(); // The first is in param_io - // the second in param_x - #endif - - p_vci_tgt_dma.rerror = m_dma_rsp_rerror_fifo.read(); - p_vci_tgt_dma.reop = m_dma_rsp_reop_fifo.read(); - } - else - { - p_vci_tgt_dma.rspval = false; - - p_vci_tgt_dma.rsrcid = 0; - p_vci_tgt_dma.rdata = 0; - p_vci_tgt_dma.rpktid = 0; - p_vci_tgt_dma.rtrdid = 0; - p_vci_tgt_dma.rerror = 0; - p_vci_tgt_dma.reop = false; - - } - - // VCI initiator response on the Xram Network - // it depends on the DMA_RSP FSM state - switch ( r_dma_rsp_fsm.read() ) - { - case DMA_RSP_IDLE: - case DMA_RSP_TRT_LOCK: - case DMA_RSP_FIFO_ERROR_PUT: - { - p_vci_ini_dma.rspack = false; - break; - } - case DMA_RSP_FIFO_PUT: - { - p_vci_ini_dma.rspack = m_dma_rsp_data_fifo.wok(); - break; - } - }// end switch r_dma_rsp_fsm - - ///////////////////// - // CONFIG Commands // - ///////////////////// - - // VCI initiator command on the IO network - if(m_config_cmd_addr_fifo.rok()) - { - p_vci_ini_config.cmdval = true; - #if NEW_XRAM_VCI - p_vci_ini_config.address = (paddr_t_x)(m_config_cmd_addr_fifo.read() >> 6 ) - #else - p_vci_ini_config.address = m_config_cmd_addr_fifo.read(); - #endif - - p_vci_ini_config.be = (vci_be_t_x)m_config_cmd_be_fifo.read(); - p_vci_ini_config.cmd = m_config_cmd_cmd_fifo.read(); - p_vci_ini_config.contig = m_config_cmd_contig_fifo.read(); - #if NEW_XRAM_VCI - //TODO - #else - p_vci_ini_config.wdata = (vci_data_t_x)m_config_cmd_data_fifo.read(); // The first is in param_io - // the second in param_d - #endif - p_vci_ini_config.eop = m_config_cmd_eop_fifo.read(); - p_vci_ini_config.cons = m_config_cmd_cons_fifo.read(); - p_vci_ini_config.plen = m_config_cmd_plen_fifo.read(); - p_vci_ini_config.wrap = m_config_cmd_wrap_fifo.read(); - p_vci_ini_config.cfixed = m_config_cmd_cfixed_fifo.read(); - p_vci_ini_config.clen = m_config_cmd_clen_fifo.read(); - p_vci_ini_config.trdid = m_config_cmd_trdid_fifo.read(); - p_vci_ini_config.pktid = m_config_cmd_pktid_fifo.read(); - } - else - { - p_vci_ini_config.cmdval = false; - p_vci_ini_config.address = 0; - p_vci_ini_config.be = 0; - p_vci_ini_config.cmd = vci_param_io::CMD_NOP; - p_vci_ini_config.contig = false; - p_vci_ini_config.wdata = 0; - p_vci_ini_config.eop = false; - p_vci_ini_config.cons = true; - p_vci_ini_config.plen = 0; - p_vci_ini_config.wrap = false; - p_vci_ini_config.cfixed = false; - p_vci_ini_config.clen = 0; - p_vci_ini_config.trdid = 0; - p_vci_ini_config.pktid = 0; - } + // VCI initiator response on IOX Network + // it depends on the CONFIG_RSP FSM state + + p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and + (r_config_rsp_fsm.read() == CONFIG_RSP_FIFO_PUT) and + not r_alloc_fifo_config_rsp_local.read(); + + // VCI initiator command on INT network + // it depends on the MISS_WTI_CMD FSM state + + // default values + p_vci_ini_int.srcid = m_int_srcid; + p_vci_ini_int.trdid = 0; + p_vci_ini_int.cfixed = false; + p_vci_ini_int.eop = true; + p_vci_ini_int.wrap = false; + p_vci_ini_int.clen = 0; + p_vci_ini_int.contig = false; + p_vci_ini_int.cons = true; + p_vci_ini_int.be = 0xFF; - // VCI target command on the Direct network - // it depends on the CONFIG_CMD FSM state - - switch ( r_config_cmd_fsm.read() ) - { - case CONFIG_CMD_IDLE: - case CONFIG_CMD_TRT_LOCK: - case CONFIG_CMD_TRT_WAIT: - case CONFIG_CMD_TRT_SET: - case CONFIG_CMD_IT_ADDR_IOMMU_READ_1: - case CONFIG_CMD_IT_ADDR_READ_1: - case CONFIG_CMD_ERROR_RSP: - case CONFIG_CMD_INVAL_REQ: - p_vci_tgt_config.cmdack = false; - break; - case CONFIG_CMD_FIFO_PUT: - case CONFIG_CMD_PTPR_WRITE: - case CONFIG_CMD_PTPR_READ: - case CONFIG_CMD_ACTIVE_WRITE: - case CONFIG_CMD_ACTIVE_READ: - case CONFIG_CMD_BVAR_READ: - case CONFIG_CMD_ETR_READ: - case CONFIG_CMD_BAD_ID_READ: - case CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2: - case CONFIG_CMD_IT_ADDR_IOMMU_READ_2: - case CONFIG_CMD_IT_ADDR_WRITE_2: - case CONFIG_CMD_IT_ADDR_READ_2: - case CONFIG_CMD_INVAL: - p_vci_tgt_config.cmdack = m_config_cmd_addr_fifo.wok(); - break; - case CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1: - case CONFIG_CMD_IT_ADDR_WRITE_1: - case CONFIG_CMD_ERROR_WAIT: - p_vci_tgt_config.cmdack = true; - break; - default: - p_vci_tgt_config.cmdack = false; - break; - }// end switch r_config_cmd_fsm - - ///////////////////// - // CONFIG Responses// - ///////////////////// + switch ( r_miss_wti_cmd_fsm.read() ) + { + case MISS_WTI_CMD_IDLE: + p_vci_ini_int.cmdval = false; + p_vci_ini_int.address = 0; + p_vci_ini_int.cmd = vci_param_int::CMD_NOP; + p_vci_ini_int.pktid = PKTID_READ; + p_vci_ini_int.wdata = 0; + p_vci_ini_int.plen = 0; + break; - // VCI target response on the Direct network - if(r_config_rsp_fifo_local_priority) - { - if( m_config_local_data_fifo.rok() ) - { - p_vci_tgt_config.rspval = true; - p_vci_tgt_config.rsrcid = m_config_local_rsrcid_fifo.read(); - p_vci_tgt_config.rtrdid = m_config_local_rtrdid_fifo.read(); - p_vci_tgt_config.rpktid = m_config_local_rpktid_fifo.read(); - p_vci_tgt_config.rdata = (vci_data_t)m_config_local_data_fifo.read(); - p_vci_tgt_config.rerror = m_config_local_rerror_fifo.read(); - p_vci_tgt_config.reop = m_config_local_reop_fifo.read(); - } - else if(m_config_rsp_data_fifo.rok() ) - { - p_vci_tgt_config.rspval = true; - p_vci_tgt_config.rsrcid = m_config_rsp_rsrcid_fifo.read(); - p_vci_tgt_config.rtrdid = m_config_rsp_rtrdid_fifo.read(); - - p_vci_tgt_config.rpktid = m_config_rsp_rpktid_fifo.read(); + case MISS_WTI_CMD_WTI: + p_vci_ini_int.cmdval = true; + p_vci_ini_int.address = r_iommu_peri_wti[r_miss_wti_cmd_index.read()].read(); + p_vci_ini_int.cmd = vci_param_int::CMD_WRITE; + p_vci_ini_int.pktid = PKTID_WRITE; + p_vci_ini_int.wdata = (int_data_t)r_irq_pending[r_miss_wti_cmd_index.read()].read(); + p_vci_ini_int.plen = vci_param_int::B; + break; - p_vci_tgt_config.rdata = (vci_data_t)m_config_rsp_data_fifo.read(); // The first is in param_d - // the second in param_io - p_vci_tgt_config.rerror = m_config_rsp_rerror_fifo.read(); - p_vci_tgt_config.reop = m_config_rsp_reop_fifo.read(); - } - else - { - p_vci_tgt_config.rspval = false; - - p_vci_tgt_config.rsrcid = 0; - p_vci_tgt_config.rdata = 0; - p_vci_tgt_config.rpktid = 0; - p_vci_tgt_config.rtrdid = 0; - p_vci_tgt_config.rerror = 0; - p_vci_tgt_config.reop = false; - - } - } - else - { - if(m_config_rsp_data_fifo.rok() ) - { - p_vci_tgt_config.rspval = true; - p_vci_tgt_config.rsrcid = m_config_rsp_rsrcid_fifo.read(); - p_vci_tgt_config.rtrdid = m_config_rsp_rtrdid_fifo.read(); - - p_vci_tgt_config.rpktid = m_config_rsp_rpktid_fifo.read(); - - p_vci_tgt_config.rdata = (vci_data_t)m_config_rsp_data_fifo.read(); // The first is in param_d - // the second in param_io - p_vci_tgt_config.rerror = m_config_rsp_rerror_fifo.read(); - p_vci_tgt_config.reop = m_config_rsp_reop_fifo.read(); - } - else if( m_config_local_data_fifo.rok() ) - { - p_vci_tgt_config.rspval = true; - p_vci_tgt_config.rsrcid = m_config_local_rsrcid_fifo.read(); - p_vci_tgt_config.rtrdid = m_config_local_rtrdid_fifo.read(); - p_vci_tgt_config.rpktid = m_config_local_rpktid_fifo.read(); - p_vci_tgt_config.rdata = (vci_data_t)m_config_local_data_fifo.read(); - p_vci_tgt_config.rerror = m_config_local_rerror_fifo.read(); - p_vci_tgt_config.reop = m_config_local_reop_fifo.read(); - } - else - { - p_vci_tgt_config.rspval = false; - - p_vci_tgt_config.rsrcid = 0; - p_vci_tgt_config.rdata = 0; - p_vci_tgt_config.rpktid = 0; - p_vci_tgt_config.rtrdid = 0; - p_vci_tgt_config.rerror = 0; - p_vci_tgt_config.reop = false; - - } - } - - // VCI initiator response on the IO Network - // it depends on the CONFIG_RSP FSM state - switch ( r_config_rsp_fsm.read() ) - { - case CONFIG_RSP_IDLE: - case CONFIG_RSP_TRT_LOCK: - p_vci_ini_config.rspack = false; - break; - case CONFIG_RSP_FIFO_PUT: - p_vci_ini_config.rspack = m_config_rsp_data_fifo.wok(); - break; - }// end switch r_config_rsp_fsm - - //////////////////////////////////////////////////////////////// - // VCI initiator command and response on from the Direct network - // for Miss Transactions - p_vci_ini_miss.srcid = m_srcid_miss; - - switch ( r_miss_init_fsm.read() ) - { - case MISS_INIT_IDLE_MISS: - case MISS_INIT_IDLE_IRQ: - p_vci_ini_miss.cmdval = false; - p_vci_ini_miss.address = 0; - p_vci_ini_miss.be = 0; - p_vci_ini_miss.cmd = vci_param_d::CMD_NOP; - p_vci_ini_miss.contig = false; - p_vci_ini_miss.wdata = 0; - p_vci_ini_miss.eop = false; - p_vci_ini_miss.cons = true; - p_vci_ini_miss.plen = 0; - p_vci_ini_miss.wrap = false; - p_vci_ini_miss.cfixed = false; - p_vci_ini_miss.clen = 0; - p_vci_ini_miss.trdid = 0; - p_vci_ini_miss.pktid = 0; - - p_vci_ini_miss.rspack = false; - break; - - case MISS_INIT_IRQ_CMD: - p_vci_ini_miss.cmdval = true; - p_vci_ini_miss.address = (paddr_t)r_it_addr[r_irq_chosen.read()]; - p_vci_ini_miss.wdata = 0; - p_vci_ini_miss.plen = vci_param_d::B; - p_vci_ini_miss.trdid = 0; - p_vci_ini_miss.cmd = vci_param_d::CMD_READ; - p_vci_ini_miss.eop = true; - - p_vci_ini_miss.be = 0xF; - p_vci_ini_miss.pktid = 0; - p_vci_ini_miss.cons = false; - p_vci_ini_miss.wrap = false; - p_vci_ini_miss.contig = true; - p_vci_ini_miss.clen = 0; - p_vci_ini_miss.cfixed = false; - break; - - case MISS_INIT_IRQ_RSP: - case MISS_INIT_TLB_MISS_RSP: - p_vci_ini_miss.cmdval = false; - p_vci_ini_miss.address = 0; - p_vci_ini_miss.be = 0; - p_vci_ini_miss.cmd = vci_param_d::CMD_NOP; - p_vci_ini_miss.contig = false; - p_vci_ini_miss.wdata = 0; - p_vci_ini_miss.eop = false; - p_vci_ini_miss.cons = true; - p_vci_ini_miss.plen = 0; - p_vci_ini_miss.wrap = false; - p_vci_ini_miss.cfixed = false; - p_vci_ini_miss.clen = 0; - p_vci_ini_miss.trdid = 0; - p_vci_ini_miss.pktid = 0; - - p_vci_ini_miss.rspack = true; - - break; - - case MISS_INIT_TLB_MISS_CMD: - p_vci_ini_miss.cmdval = true; - p_vci_ini_miss.address = (paddr_t)((r_iotlb_paddr.read())& CACHE_LINE_MASK); - p_vci_ini_miss.wdata = 0x00000000; - p_vci_ini_miss.plen = m_words*(vci_param_d::B); - p_vci_ini_miss.trdid = 0; //could be used as the index on a miss transaction table - p_vci_ini_miss.cmd = vci_param_d::CMD_READ; - p_vci_ini_miss.eop = true; - - p_vci_ini_miss.be = 0xF; - p_vci_ini_miss.pktid = 0; - p_vci_ini_miss.cons = false; - p_vci_ini_miss.wrap = false; - p_vci_ini_miss.contig = true; - p_vci_ini_miss.clen = 0; - p_vci_ini_miss.cfixed = false; - break; - - } // end switch r_miss_init_fsm + case MISS_WTI_CMD_MISS: + p_vci_ini_int.cmdval = true; + p_vci_ini_int.address = r_tlb_paddr.read() & CACHE_LINE_MASK; + p_vci_ini_int.cmd = vci_param_int::CMD_READ; + p_vci_ini_int.pktid = PKTID_READ; + p_vci_ini_int.wdata = 0; + p_vci_ini_int.plen = m_words*(vci_param_int::B); + break; + } + + // VCI initiator response on INT network + // It depends on the MISS_WTI_RSP FSM state + + if ( r_miss_wti_rsp_fsm.read() == MISS_WTI_RSP_IDLE ) p_vci_ini_int.rspack = false; + else p_vci_ini_int.rspack = true; + } // end genMoore Index: trunk/modules/vci_io_bridge/include/soclib/io_bridge.h =================================================================== --- trunk/modules/vci_io_bridge/include/soclib/io_bridge.h (revision 434) +++ trunk/modules/vci_io_bridge/include/soclib/io_bridge.h (revision 434) @@ -0,0 +1,72 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * alain greiner + * + * Maintainers: alain + */ +#ifndef IO_BRIDGE_REGS_H +#define IO_BRIDGE_REGS_H + +// IOB Configuration registers +// Minimal required segment size = 512 bytes (128 words) +enum +{ + IOB_IOMMU_PTPR = 0, // R/W : Page Table Pointer Register + IOB_IOMMU_ACTIVE = 1, // R/W : IOMMU activated if not 0 + IOB_IOMMU_BVAR = 2, // R : Bad Virtual Address + IOB_IOMMU_ETR = 3, // R : Error type + IOB_IOMMU_BAD_ID = 4, // R : Faulty peripheral Index (SRCID) + IOB_INVAL_PTE = 5, // W : Invalidate PTE (using virtual address) + IOB_WTI_ENABLE = 6, // R/W : Enable WTI (both IOB and external IRQs) + IOB_WTI_ADDR_LO = 7, // R/W : WTI for IOB itself (32 LSB address bits) + IOB_WTI_ADDR_HI = 8, // R/W : WTI for IOB itself (32 MSB address bits) + IOB_PERI_WTI_BEGIN = 64, // R/W : two 32 bits words per IRQ + /**/ + IOB_SPAN = 128, +}; + + +// IOMMU Error Type +enum mmu_error_type_e +{ + MMU_NONE = 0x0000, // None + MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access to a non writable page + MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write Bus Error accessing Table 1 + MMU_READ_PT1_UNMAPPED = 0x1001, // Read Page fault on Page Table 1 + MMU_READ_PT2_UNMAPPED = 0x1002, // Read Page fault on Page Table 2 + MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read Bus Error in Table1 access + MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read Bus Error in Table2 access + MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read Bus Error in cache access +}; + +#endif /* IO_BRIDGE_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 433) +++ trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 434) @@ -24,4 +24,8 @@ '../source/include/mem_cache_directory.h', '../source/include/update_tab.h' + ], + + interface_files = [ + '../../include/soclib/mem_cache.h', ], Index: trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 433) +++ trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 434) @@ -274,4 +274,13 @@ ///////////////////////////////////////////////////////////////////// + // The inval function invalidate an entry defined by the set and + // way arguments. + ///////////////////////////////////////////////////////////////////// + void inval( const size_t &set, const size_t &way ) + { + m_dir_tab[set][way].init(); + } + + ///////////////////////////////////////////////////////////////////// // The read_neutral() function reads a directory entry, without // changing the LRU @@ -320,11 +329,15 @@ // update LRU bits bool all_recent = true; - for ( size_t i=0 ; i addr_t; public: + bool valid; // It is a valid pending transaction bool update; // It is an update transaction bool brdcast; // It is a broadcast invalidate - bool rsp; // It needs a response to the initiator + bool rsp; // Response to the initiator required + bool ack; // Acknowledge to the CONFIG FSM required size_t srcid; // The srcid of the initiator which wrote the data size_t trdid; // The trdid of the initiator which wrote the data @@ -25,9 +28,11 @@ size_t count; // The number of acknowledge responses to receive - UpdateTabEntry(){ + UpdateTabEntry() + { valid = false; update = false; brdcast = false; rsp = false; + ack = false; srcid = 0; trdid = 0; @@ -38,12 +43,13 @@ UpdateTabEntry(bool i_valid, - bool i_update, - bool i_brdcast, - bool i_rsp, - size_t i_srcid, - size_t i_trdid, - size_t i_pktid, - addr_t i_nline, - size_t i_count) + bool i_update, + bool i_brdcast, + bool i_rsp, + bool i_ack, + size_t i_srcid, + size_t i_trdid, + size_t i_pktid, + addr_t i_nline, + size_t i_count) { valid = i_valid; @@ -51,4 +57,5 @@ brdcast = i_brdcast; rsp = i_rsp; + ack = i_ack; srcid = i_srcid; trdid = i_trdid; @@ -64,4 +71,5 @@ brdcast = source.brdcast; rsp = source.rsp; + ack = source.ack; srcid = source.srcid; trdid = source.trdid; @@ -80,4 +88,5 @@ brdcast= false; rsp = false; + ack = false; srcid = 0; trdid = 0; @@ -98,4 +107,5 @@ brdcast= source.brdcast; rsp = source.rsp; + ack = source.ack ; srcid = source.srcid; trdid = source.trdid; @@ -108,14 +118,16 @@ // The print() function prints the entry //////////////////////////////////////////////////////////////////// - void print(){ - std::cout << std::dec << "valid = " << valid << std::endl; - std::cout << "update = " << update << std::endl; - std::cout << "brdcast= " << brdcast<< std::endl; - std::cout << "rsp = " << rsp << std::endl; - std::cout << "srcid = " << srcid << std::endl; - std::cout << "trdid = " << trdid << std::endl; - std::cout << "pktid = " << pktid << std::endl; - std::cout << std::hex << "nline = " << nline << std::endl; - std::cout << std::dec << "count = " << count << std::endl; + void print() + { + std::cout << " val = " << std::dec << valid + << " / updt = " << update + << " / bc = " << brdcast + << " / rsp = " << rsp + << " / ack = " << ack + << " / count = " << count + << " / srcid = " << std::hex << srcid + << " / trdid = " << trdid + << " / pktid = " << pktid + << " / nline = " << nline << std::endl; } }; @@ -126,8 +138,8 @@ class UpdateTab{ - typedef sc_dt::sc_uint<40> addr_t; + typedef uint64_t addr_t; private: - size_t size_tab; + size_t size_tab; std::vector tab; @@ -149,15 +161,18 @@ // The size() function returns the size of the tab //////////////////////////////////////////////////////////////////// - const size_t size(){ + const size_t size() + { return size_tab; } - //////////////////////////////////////////////////////////////////// // The print() function diplays the tab content //////////////////////////////////////////////////////////////////// - void print(){ - for(size_t i=0; i m_seglist; // segments allocated to memcache + std::list m_seglist; // segments allocated size_t m_nseg; // number of segments soclib::common::Segment **m_seg; // array of segments pointers - const size_t m_srcid_x; // global index on external network + size_t m_seg_config; // config segment index + const size_t m_srcid_x; // global index on RAM network const size_t m_initiators; // Number of initiators const size_t m_heap_size; // Size of the heap @@ -458,8 +501,8 @@ size_t m_max_copies; // max number of copies in heap GenericLLSCGlobalTable - < 32 , // number of slots - 4096, // number of processors in the system - 8000, // registration life (# of LL operations) - addr_t > m_llsc_table; // ll/sc global registration table + < 32 , // number of slots + 4096, // number of processors in the system + 8000, // registration life (# of LL operations) + addr_t > m_llsc_table; // ll/sc registration table // adress masks @@ -511,28 +554,64 @@ // (segmentation violation response request) sc_signal r_tgt_cmd_to_tgt_rsp_req; + + sc_signal r_tgt_cmd_to_tgt_rsp_rdata; + sc_signal r_tgt_cmd_to_tgt_rsp_error; sc_signal r_tgt_cmd_to_tgt_rsp_srcid; sc_signal r_tgt_cmd_to_tgt_rsp_trdid; sc_signal r_tgt_cmd_to_tgt_rsp_pktid; + sc_signal r_tgt_cmd_config_addr; + sc_signal r_tgt_cmd_config_cmd; + + /////////////////////////////////////////////////////// + // Registers controlled by the CONFIG fsm + /////////////////////////////////////////////////////// + + sc_signal r_config_fsm; // FSM state + sc_signal r_config_lock; // lock protecting exclusive access + sc_signal r_config_cmd; // config request status + sc_signal r_config_address; // target buffer physical address + sc_signal r_config_srcid; // config request srcid + sc_signal r_config_trdid; // config request trdid + sc_signal r_config_pktid; // config request pktid + sc_signal r_config_nlines; // number of lines covering the buffer + sc_signal r_config_way; // selected way + sc_signal r_config_count; // number of copies + sc_signal r_config_upt_index; // UPT index + sc_signal r_config_is_cnt; // counter mode (broadcast required) + + // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) + sc_signal r_config_to_tgt_rsp_req; // valid request + sc_signal r_config_to_tgt_rsp_error; // error response + sc_signal r_config_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_config_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_config_to_tgt_rsp_pktid; // Transaction pktid + + // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) + sc_signal r_config_to_cc_send_multi_req; // multi-inval request + sc_signal r_config_to_cc_send_brdcast_req; // broadcast-inval request + sc_signal r_config_to_cc_send_nline; // line index + sc_signal r_config_to_cc_send_trdid; // UPT index + /////////////////////////////////////////////////////// // Registers controlled by the READ fsm /////////////////////////////////////////////////////// - sc_signal r_read_fsm; // FSM state - sc_signal r_read_copy; // Srcid of the first copy - sc_signal r_read_copy_cache; // Srcid of the first copy - sc_signal r_read_copy_inst; // Type of the first copy - sc_signal r_read_tag; // cache line tag (in directory) - sc_signal r_read_is_cnt; // is_cnt bit (in directory) - sc_signal r_read_lock; // lock bit (in directory) - sc_signal r_read_dirty; // dirty bit (in directory) - sc_signal r_read_count; // number of copies - sc_signal r_read_ptr; // pointer to the heap - sc_signal * r_read_data; // data (one cache line) - sc_signal r_read_way; // associative way (in cache) - sc_signal r_read_trt_index; // Transaction Table index - sc_signal r_read_next_ptr; // Next entry to point to - sc_signal r_read_last_free; // Last free entry - sc_signal r_read_ll_key; // LL key from the llsc_global_table + sc_signal r_read_fsm; // FSM state + sc_signal r_read_copy; // Srcid of the first copy + sc_signal r_read_copy_cache; // Srcid of the first copy + sc_signal r_read_copy_inst; // Type of the first copy + sc_signal r_read_tag; // cache line tag (in directory) + sc_signal r_read_is_cnt; // is_cnt bit (in directory) + sc_signal r_read_lock; // lock bit (in directory) + sc_signal r_read_dirty; // dirty bit (in directory) + sc_signal r_read_count; // number of copies + sc_signal r_read_ptr; // pointer to the heap + sc_signal * r_read_data; // data (one cache line) + sc_signal r_read_way; // associative way (in cache) + sc_signal r_read_trt_index; // Transaction Table index + sc_signal r_read_next_ptr; // Next entry to point to + sc_signal r_read_last_free; // Last free entry + sc_signal r_read_ll_key; // LL key from the llsc_global_table // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) @@ -626,4 +705,7 @@ sc_signal r_multi_ack_nline; // pending write nline + // signaling completion of multi-inval to CONFIG fsm + sc_signal r_multi_ack_to_config_ack; + // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) sc_signal r_multi_ack_to_tgt_rsp_req; // valid request @@ -662,11 +744,16 @@ sc_signal r_cleanup_way; // associative way (in cache) - sc_signal r_cleanup_write_srcid; // srcid of write response + sc_signal r_cleanup_write_srcid; // srcid of write rsp sc_signal r_cleanup_write_trdid; // trdid of write rsp sc_signal r_cleanup_write_pktid; // pktid of write rsp - sc_signal r_cleanup_write_need_rsp;// needs a write rsp + + sc_signal r_cleanup_need_rsp; // write response required + sc_signal r_cleanup_need_ack; // config acknowledge required sc_signal r_cleanup_index; // index of the INVAL line (in the UPT) + // signaling completion of broadcast-inval to CONFIG fsm + sc_signal r_cleanup_to_config_ack; + // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) sc_signal r_cleanup_to_tgt_rsp_req; // valid request Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 433) +++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 434) @@ -34,12 +34,12 @@ #include "../include/vci_mem_cache.h" -////// debug services /////////////////////////////////////////////////////// +////// debug services ///////////////////////////////////////////////////////////// // All debug messages are conditionned by two variables: // - compile time : DEBUG_MEMC_*** : defined below -// - execution time : m_debug_*** : defined by constructor arguments -// m_debug_* = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) -///////////////////////////////////////////////////////////////////////////////// +// - execution time : m_debug = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) +/////////////////////////////////////////////////////////////////////////////////////// #define DEBUG_MEMC_GLOBAL 0 // synthetic trace of all FSMs +#define DEBUG_MEMC_CONFIG 1 // detailed trace of CONFIG FSM #define DEBUG_MEMC_READ 1 // detailed trace of READ FSM #define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM @@ -64,5 +64,6 @@ "TGT_CMD_READ", "TGT_CMD_WRITE", - "TGT_CMD_CAS" + "TGT_CMD_CAS", + "TGT_CMD_CONFIG" }; const char *tgt_rsp_fsm_str[] = @@ -118,5 +119,6 @@ "MULTI_ACK_UPT_LOCK", "MULTI_ACK_UPT_CLEAR", - "MULTI_ACK_WRITE_RSP" + "MULTI_ACK_WRITE_RSP", + "MULTI_ACK_CONFIG_ACK" }; const char *read_fsm_str[] = @@ -237,5 +239,6 @@ "CLEANUP_UPT_CLEAR", "CLEANUP_WRITE_RSP", - "CLEANUP_SEND_ACK" + "CLEANUP_CONFIG_ACK", + "CLEANUP_SEND_CLACK" }; const char *alloc_dir_fsm_str[] = @@ -457,4 +460,5 @@ for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++) { + if ( seg->special() ) m_seg_config = i; m_seg[i] = & (*seg); i++; @@ -631,4 +635,5 @@ // Initializing FSMs r_tgt_cmd_fsm = TGT_CMD_IDLE; + r_config_fsm = CONFIG_IDLE; r_tgt_rsp_fsm = TGT_RSP_TGT_CMD_IDLE; r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; @@ -647,17 +652,5 @@ r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; - m_debug_global = false; - m_debug_tgt_cmd_fsm = false; - m_debug_tgt_rsp_fsm = false; - m_debug_cc_send_fsm = false; - m_debug_cc_receive_fsm = false; - m_debug_multi_ack_fsm = false; - m_debug_read_fsm = false; - m_debug_write_fsm = false; - m_debug_cas_fsm = false; - m_debug_cleanup_fsm = false; - m_debug_ixr_cmd_fsm = false; - m_debug_ixr_rsp_fsm = false; - m_debug_xram_rsp_fsm = false; + m_debug = false; m_debug_previous_hit = false; m_debug_previous_count = 0; @@ -690,4 +683,7 @@ m_cmd_cas_eop_fifo.init() ; + r_config_cmd = MEMC_CMD_NOP; + r_config_lock = false; + r_tgt_cmd_to_tgt_rsp_req = false; @@ -697,6 +693,6 @@ r_write_to_tgt_rsp_req = false; r_write_to_ixr_cmd_req = false; - r_write_to_cc_send_multi_req = false; - r_write_to_cc_send_brdcast_req = false; + r_write_to_cc_send_multi_req = false; + r_write_to_cc_send_brdcast_req = false; r_write_to_multi_ack_req = false; @@ -816,21 +812,9 @@ #endif - m_debug_global = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_tgt_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_tgt_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_cc_send_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_cc_receive_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_multi_ack_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_read_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_write_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_cas_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_cleanup_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_ixr_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_ixr_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; - m_debug_xram_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; #if DEBUG_MEMC_GLOBAL - if(m_debug_global) - { +if(m_debug) +{ std::cout << "---------------------------------------------" << std::dec << std::endl @@ -853,5 +837,5 @@ << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] << std::endl << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; - } +} #endif @@ -859,130 +843,137 @@ // TGT_CMD FSM //////////////////////////////////////////////////////////////////////////////////// - // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors + // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors, + // and dispatch these commands to the proper FSM through dedicated FIFOs. // - // There are 5 types of accepted commands : - // - READ : A READ request has a length of 1 VCI cell. It can be a single word - // or an entire cache line, depending on the PLEN value. - // - WRITE : A WRITE request has a maximum length of 16 cells, and can only - // concern words in a same line. - // - CAS : A CAS request has a length of 2 cells or 4 cells. - // - LL : An LL request has a length of 1 cell. - // - SC : An SC request has a length of 2 cells. First cell contains the - // acces key, second cell the data to write in case of success. + // There are 5 types of commands accepted in the XRAM segment: + // - READ : A READ request has a length of 1 VCI flit. It can be a single word + // or an entire cache line, depending on the PLEN value => READ FSM + // - WRITE : A WRITE request has a maximum length of 16 flits, and can only + // concern words in a same line => WRITE FSM + // - CAS : A CAS request has a length of 2 flits or 4 flits => CAS FSM + // - LL : An LL request has a length of 1 flit => READ FSM + // - SC : An SC request has a length of 2 flits. First flit contains the + // acces key, second flit the data to write => WRITE FSM. + // + // The READ/WRITE commands accepted in the configuration segment are targeting, + // configuration or status registers. They must contain one single flit. + // - For almost all addressable registers, the response is returned immediately. + // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed. //////////////////////////////////////////////////////////////////////////////////// switch(r_tgt_cmd_fsm.read()) { - ////////////////// - case TGT_CMD_IDLE: - if(p_vci_tgt.cmdval) - { + ////////////////// + case TGT_CMD_IDLE: // waiting a VCI command (RAM or CONFIG) + if(p_vci_tgt.cmdval) + { #if DEBUG_MEMC_TGT_CMD - if(m_debug_tgt_cmd_fsm) - { - std::cout - << " Receive command from srcid " - << std::dec << p_vci_tgt.srcid.read() - << " / for address " - << std::hex << p_vci_tgt.address.read() - << std::endl; - } +if(m_debug) +std::cout << " Receive command from srcid " + << std::dec << p_vci_tgt.srcid.read() + << " / address " << std::hex << p_vci_tgt.address.read() << std::endl; #endif // checking segmentation violation - addr_t address = p_vci_tgt.address.read(); - uint32_t plen = p_vci_tgt.plen.read(); - bool found = false; - for(size_t seg_id = 0 ; seg_id < m_nseg ; seg_id++) - { - if(m_seg[seg_id]->contains(address) && - m_seg[seg_id]->contains(address + plen - vci_param_int::B)) - { - found = true; - } - } - - if(not found) - { - r_tgt_cmd_fsm = TGT_CMD_ERROR; - } - else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) - { - // check that the pktid is either : - // TYPE_READ_DATA_UNC - // TYPE_READ_DATA_MISS - // TYPE_READ_INS_UNC - // TYPE_READ_INS_MISS - // ==> bit2 must be zero with the TSAR encoding - // ==> mask = 0b0100 = 0x4 - assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) && - "The type specified in the pktid field is incompatible with the READ CMD"); - r_tgt_cmd_fsm = TGT_CMD_READ; - } - else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) - { - // check that the pktid is TYPE_WRITE - // ==> TYPE_WRITE = X100 with the TSAR encoding - // ==> mask = 0b0111 = 0x7 - assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) && - "The type specified in the pktid field is incompatible with the WRITE CMD"); - r_tgt_cmd_fsm = TGT_CMD_WRITE; - } - else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) - { - // check that the pktid is TYPE_LL - // ==> TYPE_LL = X110 with the TSAR encoding - // ==> mask = 0b0111 = 0x7 - assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) && - "The type specified in the pktid field is incompatible with the LL CMD"); - r_tgt_cmd_fsm = TGT_CMD_READ; - } - else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) - { - // check that the pktid is either : - // TYPE_CAS - // TYPE_SC - // ==> TYPE_CAS = X101 with the TSAR encoding - // ==> TYPE_SC = X111 with the TSAR encoding - // ==> mask = 0b0101 = 0x5 - assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) && - "The type specified in the pktid field is incompatible with the NOP CMD"); - - if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) - r_tgt_cmd_fsm = TGT_CMD_CAS; - else // TYPE_SC - r_tgt_cmd_fsm = TGT_CMD_WRITE; - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " TGT_CMD_IDLE state" << std::endl; - std::cout << " illegal VCI command type" << std::endl; - exit(0); - } - } - break; - - case TGT_CMD_ERROR: - // A segmentation violation has been detected, thus a response with error - // must be sent - - // wait if pending TGT_CMD request to TGT_RSP FSM - if(r_tgt_cmd_to_tgt_rsp_req.read()) break; - - // consume all the command packet flits and set new request to the - // TGT_RSP FSM - if(p_vci_tgt.cmdval and p_vci_tgt.eop) - { - r_tgt_cmd_to_tgt_rsp_req = true; + addr_t address = p_vci_tgt.address.read(); + uint32_t plen = p_vci_tgt.plen.read(); + bool found = false; + bool config = false; + + // register arguments for response (segmentation violation or config) r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); - r_tgt_cmd_fsm = TGT_CMD_IDLE; + for(size_t seg_id = 0 ; (seg_id < m_nseg) and not found ; seg_id++) + { + if( m_seg[seg_id]->contains(address) and + m_seg[seg_id]->contains(address + plen - vci_param_int::B) ) + { + found = true; + if ( m_seg[seg_id]->special() ) config = true; + } + } + + if ( not found ) /////////// out of segment error + { + r_tgt_cmd_fsm = TGT_CMD_ERROR; + } + else if ( config ) /////////// configuration command + { + if ( not p_vci_tgt.eop.read() ) r_tgt_cmd_fsm = TGT_CMD_ERROR; + else r_tgt_cmd_fsm = TGT_CMD_CONFIG; + } + else //////////// memory access + { + if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ ) + { + // check that the pktid is either : + // TYPE_READ_DATA_UNC + // TYPE_READ_DATA_MISS + // TYPE_READ_INS_UNC + // TYPE_READ_INS_MISS + // ==> bit2 must be zero with the TSAR encoding + // ==> mask = 0b0100 = 0x4 + assert( ((p_vci_tgt.pktid.read() & 0x4) == 0x0) and + "The type specified in the pktid field is incompatible with the READ CMD"); + r_tgt_cmd_fsm = TGT_CMD_READ; + } + else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + { + // check that the pktid is TYPE_WRITE + // ==> TYPE_WRITE = X100 with the TSAR encoding + // ==> mask = 0b0111 = 0x7 + assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) and + "The type specified in the pktid field is incompatible with the WRITE CMD"); + r_tgt_cmd_fsm = TGT_CMD_WRITE; + } + else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) + { + // check that the pktid is TYPE_LL + // ==> TYPE_LL = X110 with the TSAR encoding + // ==> mask = 0b0111 = 0x7 + assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) and + "The type specified in the pktid field is incompatible with the LL CMD"); + r_tgt_cmd_fsm = TGT_CMD_READ; + } + else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) + { + // check that the pktid is either : + // TYPE_CAS + // TYPE_SC + // ==> TYPE_CAS = X101 with the TSAR encoding + // ==> TYPE_SC = X111 with the TSAR encoding + // ==> mask = 0b0101 = 0x5 + assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) and + "The type specified in the pktid field is incompatible with the NOP CMD"); + + if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS; + else r_tgt_cmd_fsm = TGT_CMD_WRITE; + } + else + { + r_tgt_cmd_fsm = TGT_CMD_ERROR; + } + } + } + break; + + /////////////////// + case TGT_CMD_ERROR: // response error must be sent + + // wait if pending TGT_CMD request to TGT_RSP FSM + if(r_tgt_cmd_to_tgt_rsp_req.read()) break; + + // consume all the command packet flits before sending response error + if ( p_vci_tgt.cmdval and p_vci_tgt.eop ) + { + r_tgt_cmd_to_tgt_rsp_req = true; + r_tgt_cmd_to_tgt_rsp_error = 1; + r_tgt_cmd_fsm = TGT_CMD_IDLE; #if DEBUG_MEMC_TGT_CMD -if(m_debug_tgt_cmd_fsm) +if(m_debug) std::cout << " Segmentation violation:" @@ -993,48 +984,117 @@ << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; #endif - } - - break; - - ////////////////// - case TGT_CMD_READ: - // This test checks that the read does not cross a cache line limit. - // It must not be taken into account when dealing with an LL CMD. - if(((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) && + + } + break; + + //////////////////// + case TGT_CMD_CONFIG: // execute config request and return response + { + if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break; + + addr_t seg_base = m_seg[m_seg_config]->baseAddress(); + addr_t address = p_vci_tgt.address.read(); + size_t cell = (address - seg_base)/vci_param_int::B; + bool need_rsp = true; // default value + size_t error = 0; // default value + uint32_t rdata = 0; // default value + + if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock + and (cell == MEMC_LOCK) ) + { + rdata = (uint32_t)r_config_lock.read(); + r_config_lock = true; + } + else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock + and (cell == MEMC_LOCK) ) + { + r_config_lock = false; + } + else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type + and (cell == MEMC_CMD_TYPE) ) + { + r_config_cmd = p_vci_tgt.wdata.read(); + need_rsp = false; + } + else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo + and (cell == MEMC_ADDR_LO) ) + { + r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | + (addr_t)p_vci_tgt.wdata.read(); + } + else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi + and (cell == MEMC_ADDR_HI) ) + { + r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | + ((addr_t)p_vci_tgt.wdata.read())<<32; + } + else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines + and (cell == MEMC_BUF_LENGTH) ) + { + size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words*vci_param_int::B)); + if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++; + r_config_nlines = lines; + } + else + { + error = 1; + } + + if ( need_rsp ) + { + // blocked if previous pending request to TGT_RSP FSM + if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break; + + r_tgt_cmd_to_tgt_rsp_req = true; + r_tgt_cmd_to_tgt_rsp_error = error; + r_tgt_cmd_to_tgt_rsp_rdata = rdata; + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + else + { + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + +#if DEBUG_MEMC_TGT_CMD +if(m_debug) +std::cout << " Configuration request:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / wdata = " << p_vci_tgt.wdata.read() + << " / error = " << error << std::endl; +#endif + break; + } + ////////////////// + case TGT_CMD_READ: // Push a read request into read fifo + + // check that the read does not cross a cache line limit. + if ( ((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) and (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ)) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" - << std::endl; - std::cout - << " illegal address/plen combination for VCI read command" << std::endl; + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " illegal address/plen for VCI read command" << std::endl; exit(0); - } - if(!p_vci_tgt.eop.read()) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" - << std::endl; - std::cout - << " read or ll command packets must contain one single flit" - << std::endl; + } + // check single flit + if(!p_vci_tgt.eop.read()) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " read command packet must contain one single flit" << std::endl; exit(0); - } - if((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) && (p_vci_tgt.plen.read() != 8)) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" - << std::endl; - std::cout - << " ll command packets must have a plen of 8" - << std::endl; + } + // check plen for LL + if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and + (p_vci_tgt.plen.read() != 8) ) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " ll command packets must have a plen of 8" << std::endl; exit(0); - } - - if(p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok()) - { + } + + if ( p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok() ) + { #if DEBUG_MEMC_TGT_CMD -if(m_debug_tgt_cmd_fsm) +if(m_debug) std::cout << " Push into read_fifo:" << " address = " << std::hex << p_vci_tgt.address.read() @@ -1045,19 +1105,17 @@ #endif cmd_read_fifo_put = true; - if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) - m_cpt_ll++; - else - m_cpt_read++; + if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) m_cpt_ll++; + else m_cpt_read++; r_tgt_cmd_fsm = TGT_CMD_IDLE; - } - break; - - /////////////////// + } + break; + + /////////////////// case TGT_CMD_WRITE: - if(p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok()) - { + if(p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok()) + { #if DEBUG_MEMC_TGT_CMD -if(m_debug_tgt_cmd_fsm) +if(m_debug) std::cout << " Push into write_fifo:" << " address = " << std::hex << p_vci_tgt.address.read() @@ -1071,24 +1129,21 @@ cmd_write_fifo_put = true; if(p_vci_tgt.eop) r_tgt_cmd_fsm = TGT_CMD_IDLE; - } - break; - - //////////////////// + } + break; + + ///////////////// case TGT_CMD_CAS: - if((p_vci_tgt.plen.read() != 8) && (p_vci_tgt.plen.read() != 16)) - { - std::cout - << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" - << std::endl - << "illegal format for CAS command " << std::endl; - + if((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16)) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" + << "illegal format for CAS command " << std::endl; exit(0); - } - - if(p_vci_tgt.cmdval && m_cmd_cas_addr_fifo.wok()) - { + } + + if(p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok()) + { #if DEBUG_MEMC_TGT_CMD -if(m_debug_tgt_cmd_fsm) +if(m_debug) std::cout << " Pushing command into cmd_cas_fifo:" << " address = " << std::hex << p_vci_tgt.address.read() @@ -1102,6 +1157,6 @@ cmd_cas_fifo_put = true; if(p_vci_tgt.eop) r_tgt_cmd_fsm = TGT_CMD_IDLE; - } - break; + } + break; } // end switch tgt_cmd_fsm @@ -1115,5 +1170,4 @@ // It can be update or inval requests initiated by the WRITE or CAS FSM, // or inval requests initiated by the XRAM_RSP FSM. - // It can also be a direct request from the WRITE FSM. // // The FSM decrements the proper entry in UPT. @@ -1129,7 +1183,7 @@ switch(r_multi_ack_fsm.read()) { - /////////////////// + //////////////////// case MULTI_ACK_IDLE: - { + { bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok(); @@ -1165,23 +1219,19 @@ #if DEBUG_MEMC_MULTI_ACK - if(m_debug_multi_ack_fsm) - { - if (multi_ack_fifo_rok) - { - std::cout - << " Response for UPT entry " - << updt_index - << std::endl; - } - else - { - std::cout - << " Write FSM request to decrement UPT entry " - << updt_index - << std::endl; - } - } +if(m_debug) +{ + if (multi_ack_fifo_rok) + { + std::cout << " Response for UPT entry " + << updt_index << std::endl; + } + else + { + std::cout << " Write FSM request to decrement UPT entry " + << updt_index << std::endl; + } +} #endif break; @@ -1190,5 +1240,5 @@ //////////////////////// case MULTI_ACK_UPT_LOCK: - { + { // get lock to the UPDATE table if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break; @@ -1200,11 +1250,8 @@ if(not valid) { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " MULTI_ACK_UPT_LOCK state" << std::endl - << "unsuccessful access to decrement the UPT" - << std::endl; - - exit(0); + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " MULTI_ACK_UPT_LOCK state" << std::endl + << "unsuccessful access to decrement the UPT" << std::endl; + exit(0); } @@ -1219,29 +1266,22 @@ #if DEBUG_MEMC_MULTI_ACK - if(m_debug_multi_ack_fsm) - { - std::cout - << " Decrement the responses counter for UPT:" - << " entry = " << r_multi_ack_upt_index.read() - << " / rsp_count = " << std::dec << count - << std::endl; - } +if(m_debug) +std::cout << " Decrement the responses counter for UPT:" + << " entry = " << r_multi_ack_upt_index.read() + << " / rsp_count = " << std::dec << count << std::endl; #endif break; - } + } ///////////////////////// - case MULTI_ACK_UPT_CLEAR: - { + case MULTI_ACK_UPT_CLEAR: // Clear UPT entry / Test if rsp or ack required + { if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) { - std::cout - << "VCI_MEM_CACHE ERROR " << name() - << " MULTI_ACK_UPT_CLEAR state" - << " bad UPT allocation" - << std::endl; - - exit(0); + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " MULTI_ACK_UPT_CLEAR state" + << " bad UPT allocation" << std::endl; + exit(0); } @@ -1251,36 +1291,26 @@ r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); + bool need_ack = m_upt.need_ack(r_multi_ack_upt_index.read()); // clear the UPT entry m_upt.clear(r_multi_ack_upt_index.read()); - if(need_rsp) - { - r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; - } - else - { - r_multi_ack_fsm = MULTI_ACK_IDLE; - } + if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; + else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK; + else r_multi_ack_fsm = MULTI_ACK_IDLE; #if DEBUG_MEMC_MULTI_ACK - if(m_debug_multi_ack_fsm) - { - std::cout - << " Clear UPT entry " - << r_multi_ack_upt_index.read() - << std::endl; - } +if(m_debug) +std::cout << " Clear UPT entry " + << std::dec << r_multi_ack_upt_index.read() << std::endl; #endif break; - } - + } ///////////////////////// - case MULTI_ACK_WRITE_RSP: - { - // Post a request to TGT_RSP FSM - // Wait if pending request to the TGT_RSP FSM - if(r_multi_ack_to_tgt_rsp_req.read()) break; + case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM + // Wait if pending request + { + if ( r_multi_ack_to_tgt_rsp_req.read() ) break; r_multi_ack_to_tgt_rsp_req = true; @@ -1291,16 +1321,367 @@ #if DEBUG_MEMC_MULTI_ACK - if(m_debug_multi_ack_fsm) - { - std::cout - << " Request TGT_RSP FSM to send a response to srcid " - << r_multi_ack_srcid.read() - << std::endl; - } +if(m_debug) +std::cout << " " + << " Request TGT_RSP FSM to send a response to srcid " + << std::hex << r_multi_ack_srcid.read() << std::endl; #endif break; - } + } + ////////////////////////// + case MULTI_ACK_CONFIG_ACK: // Signals multi-inval completion to CONFIG FSM + // Wait if pending request + { + if ( r_multi_ack_to_config_ack.read() ) break; + + r_multi_ack_to_config_ack = true; + r_multi_ack_fsm = MULTI_ACK_IDLE; + +#if DEBUG_MEMC_MULTI_ACK +if(m_debug) +std::cout << " " + << " Signals inval completion to CONFIG FSM" << std::endl; +#endif + break; + } } // end switch r_multi_ack_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // CONFIG FSM + //////////////////////////////////////////////////////////////////////////////////// + // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC). + // The target buffer can have any size, and there is one single command for + // all cache lines covered by the target buffer. + // An INVAL or SYNC configuration request is defined by the followinf registers: + // - bool r_config_cmd : INVAL / SYNC / NOP) + // - uint64_t r_config_address : buffer base address + // - uint32_t r_config_nlines : number of lines covering buffer + // + // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling + // all cache lines covered by the target buffer. + // + // - INVAL request: + // For each line, it access to the DIR array. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // In case of hit, with no copies in L1 caches, the line is invalidated and + // a response is requested to TGT_RSP FSM. + // If there is copies, a multi-inval, or a broadcast-inval coherence transaction + // is launched and registered in UPT. The multi-inval transaction is signaled + // by the r_multi_ack_to config_ack or r_cleanup_to_config_ack flip-flops. + // The config inval response is sent only when the last line has been invalidated. + // + // - SYNC request: Not implemented yet + // + // From the software point of view, a configuration request is a sequence + // of 6 atomic accesses: + // - Read MEMC_LOCK : Get the lock + // - Write MEMC_ADDR_LO : Set the buffer address LSB + // - Write MEMC_ADDR_HI : Set the buffer address MSB + // - Write MEMC_BUF_LENGTH : set buffer length (bytes) + // - Write MEMC_CMD_TYPE : launch the actual operation + // - WRITE MEMC_LOCK : release the lock + //////////////////////////////////////////////////////////////////////////////////// + + switch( r_config_fsm.read() ) + { + ///////////////// + case CONFIG_IDLE: // waiting a config request + { + if ( r_config_cmd.read() != MEMC_CMD_NOP ) + { + r_config_fsm = CONFIG_LOOP; + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Config Request received" + << " address = " << std::hex << r_config_address.read() + << " / nlines = " << std::dec << r_config_nlines.read() + << " / type = " << r_config_cmd.read() << std::endl; +#endif + break; + } + ///////////////// + case CONFIG_LOOP: // test last line + { + if ( r_config_nlines.read() == 0 ) + { + r_config_cmd = MEMC_CMD_NOP; + r_config_fsm = CONFIG_RSP; + } + else + { + r_config_fsm = CONFIG_DIR_REQ; + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " + << " address = " << std::hex << r_config_address.read() + << " / nlines = " << std::dec << r_config_nlines.read() + << " / type = " << r_config_cmd.read() << std::endl; +#endif + break; + } + //////////////////// + case CONFIG_DIR_REQ: // Request directory lock + { + if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG ) + { + r_config_fsm = CONFIG_DIR_ACCESS; + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " + << " Request DIR access" << std::endl; +#endif + break; + } + /////////////////////// + case CONFIG_DIR_ACCESS: // Access directory and decode cmd + { + size_t way = 0; + DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way); + + if ( entry.valid and // hit & inval command + (r_config_cmd.read() == MEMC_CMD_INVAL) ) + { + r_config_way = way; + r_config_is_cnt = entry.is_cnt; + r_config_count = entry.count; + r_config_fsm = CONFIG_DIR_INVAL; + } + else if ( entry.valid and // hit & sync command + entry.dirty and + (r_config_cmd.read() == MEMC_CMD_SYNC) ) + { + std::cout << "VCI_MEM_CACHE ERROR: " + << "SYNC config request not implemented yet" << std::endl; + exit(0); + } + else // nothing to do : return to LOOP + { + r_config_nlines = r_config_nlines.read() - 1; + r_config_address = r_config_address.read() + (m_words*vci_param_int::B); + r_config_fsm = CONFIG_LOOP; + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Accessing directory: " + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / dirty = " < Inval directory entry" << std::endl; +#endif + break; + } + //////////////////////// + case CONFIG_BC_UPT_LOCK: // try to register BC transaction in UPT + { + if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_config_srcid.read(); + size_t trdid = r_config_trdid.read(); + size_t pktid = r_config_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_config_address.read())]; + size_t nb_copies = r_config_count.read(); + + wok = m_upt.set(false, // it's an inval transaction + true, // it's a broadcast + false, // no response required + true, // acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + if ( wok ) + { + r_config_fsm = CONFIG_BC_SEND; + r_config_upt_index = index; + +#if DEBUG_MEMC_CONFIG +if( m_debug ) +std::cout << " Register broadcast inval in UPT" << std::endl; +#endif + } + else + { + r_config_fsm = CONFIG_UPT_WAIT; + +#if DEBUG_MEMC_CONFIG +if( m_debug ) +std::cout << " " + << " UPT full" << std::endl; +#endif + } + } + break; + } + //////////////////// + case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM + { + if( not r_config_to_cc_send_multi_req.read() and + not r_config_to_cc_send_brdcast_req.read() ) + { + r_config_to_cc_send_multi_req = false; + r_config_to_cc_send_brdcast_req = true; + r_config_to_cc_send_trdid = r_config_upt_index.read(); + r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; + + r_cleanup_to_config_ack = false; + + r_config_fsm = CONFIG_BC_WAIT; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " + << " Post a broadcast inval request to CC_SEND FSM" + << " / address = " << r_config_address.read() <" + << " Waiting broadcast inval completion" << std::endl; +#endif + break; + } + ///////////////////// + case CONFIG_UPT_LOCK: // Try to register multi-update in UPT + { + if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_config_srcid.read(); + size_t trdid = r_config_trdid.read(); + size_t pktid = r_config_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_config_address.read())]; + size_t nb_copies = r_config_count.read(); + + wok = m_upt.set(false, // it's an inval transaction + false, // not a broadcast + false, // no response required + true, // acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + if ( wok ) + { + r_config_fsm = CONFIG_BC_SEND; + r_config_upt_index = index; + +#if DEBUG_MEMC_CONFIG +if( m_debug ) +std::cout << " Register broadcast inval in UPT" << std::endl; +#endif + } + else + { + r_config_fsm = CONFIG_UPT_WAIT; + +#if DEBUG_MEMC_CONFIG +if( m_debug ) +std::cout << " " + << " UPT full" << std::endl; +#endif + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Request access to UPT" << std::endl; +#endif + } + break; + } + ///////////////////// + case CONFIG_HEAP_REQ: // request access to the heap + { + break; + } + + //////////////// + case CONFIG_RSP: // request TGT_RSP FSM to return response + { + if ( not r_config_to_tgt_rsp_req ) + { + r_config_to_tgt_rsp_srcid = r_config_srcid.read(); + r_config_to_tgt_rsp_trdid = r_config_trdid.read(); + r_config_to_tgt_rsp_pktid = r_config_pktid.read(); + r_config_to_tgt_rsp_error = false; + r_config_to_tgt_rsp_req = true; + r_config_fsm = CONFIG_IDLE; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Request TGT_RSP FSM to return response:" + << " error = " << r_config_to_tgt_rsp_error.read() + << " / rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; +#endif + } + break; + + } + ///////////////////// + case CONFIG_UPT_WAIT: // release the lock on UPT for one cycle, and retry + { + if ( r_config_is_cnt.read() ) r_config_fsm = CONFIG_BC_UPT_LOCK; + else r_config_fsm = CONFIG_UPT_LOCK; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " + << " Release UPT lock" << std::endl; +#endif + break; + } + } // end switch r_config_fsm //////////////////////////////////////////////////////////////////////////////////// @@ -1329,13 +1710,12 @@ switch(r_read_fsm.read()) { - /////////////// - case READ_IDLE: - // waiting a read request - { + /////////////// + case READ_IDLE: // waiting a read request + { if(m_cmd_read_addr_fifo.rok()) { #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " Read request" << " : address = " << std::hex << m_cmd_read_addr_fifo.read() @@ -1350,23 +1730,21 @@ } + ////////////////// + case READ_DIR_REQ: // Get the lock to the directory + { + if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) + { + r_read_fsm = READ_DIR_LOCK; + } + +#if DEBUG_MEMC_READ +if(m_debug) +std::cout << " Requesting DIR lock " << std::endl; +#endif + break; + } + /////////////////// - case READ_DIR_REQ: - // Get the lock to the directory - { - if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { - r_read_fsm = READ_DIR_LOCK; - } - -#if DEBUG_MEMC_READ -if(m_debug_read_fsm) -std::cout << " Requesting DIR lock " << std::endl; -#endif - break; - } - - /////////////////// - case READ_DIR_LOCK: - // check directory for hit / miss + case READ_DIR_LOCK: // check directory for hit / miss { if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) @@ -1400,5 +1778,5 @@ { // test if we need to register a new copy in the heap - if(entry.is_cnt || (entry.count == 0) || !cached_read) + if(entry.is_cnt or (entry.count == 0) or !cached_read) { r_read_fsm = READ_DIR_HIT; @@ -1415,5 +1793,5 @@ #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) { std::cout << " Accessing directory: " @@ -1503,5 +1881,5 @@ #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " Update directory entry:" << " addr = " << std::hex << m_cmd_read_addr_fifo.read() @@ -1539,5 +1917,5 @@ #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " " << " Requesting HEAP lock " << std::endl; @@ -1553,5 +1931,5 @@ { // enter counter mode when we reach the limit of copies or the heap is full - bool go_cnt = (r_read_count.read() >= m_max_copies) || m_heap.is_full(); + bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); // read data in the cache @@ -1626,5 +2004,5 @@ #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " Update directory:" << " tag = " << std::hex << entry.tag @@ -1670,5 +2048,5 @@ #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " Add an entry in the heap:" << " owner_id = " << std::hex << heap_entry.owner.srcid @@ -1758,5 +2136,5 @@ #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " Request TGT_RSP FSM to return data:" << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() @@ -1778,8 +2156,8 @@ bool wok = !m_trt.full(index); - if(hit_read || !wok || hit_write) // missing line already requested or no space + if(hit_read or !wok or hit_write) // missing line already requested or no space { if(!wok) m_cpt_trt_full++; - if(hit_read || hit_write) m_cpt_trt_rb++; + if(hit_read or hit_write) m_cpt_trt_rb++; r_read_fsm = READ_IDLE; } @@ -1792,5 +2170,5 @@ #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " Check TRT:" << " hit_read = " << hit_read @@ -1820,8 +2198,8 @@ r_read_ll_key.read()); #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " Write in Transaction Table:" << " address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() << std::endl; + << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; #endif r_read_fsm = READ_TRT_REQ; @@ -1842,5 +2220,5 @@ #if DEBUG_MEMC_READ -if(m_debug_read_fsm) +if(m_debug) std::cout << " Request GET transaction for address " << std::hex << m_cmd_read_addr_fifo.read() << std::endl; @@ -1884,5 +2262,5 @@ switch(r_write_fsm.read()) { - //////////////// + //////////////// case WRITE_IDLE: // copy first word of a write burst in local buffer { @@ -1917,5 +2295,5 @@ } - if (m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)) + if (m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)) { r_write_fsm = WRITE_DIR_REQ; @@ -1927,5 +2305,5 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) + if(m_debug) { std::cout << " Write request " @@ -1946,5 +2324,5 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) + if(m_debug) { std::cout << " Check the directory: " @@ -2130,5 +2508,5 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) + if(m_debug) { std::cout << " Read the cache to complete local buffer" << std::endl; @@ -2172,5 +2550,6 @@ // no_update is true when there is no need for coherence transaction // (tests for sc requests) - bool no_update = ((r_write_count.read() ==0) || (owner && (r_write_count.read() ==1) && (r_write_pktid.read() != TYPE_SC))); + bool no_update = ( (r_write_count.read() == 0) or + (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC))); // write data in the cache if no coherence transaction @@ -2205,5 +2584,5 @@ // coherence update required { - if(!r_write_to_cc_send_multi_req.read() && + if(!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read()) { @@ -2217,20 +2596,20 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - if(no_update) - { - std::cout << " Write into cache / No coherence transaction" - << std::endl; - } - else - { - std::cout << " Coherence update required:" - << " is_cnt = " << r_write_is_cnt.read() - << " nb_copies = " << std::dec << r_write_count.read() << std::endl; - if(owner) - std::cout << " ... but the first copy is the writer" << std::endl; - } - } +if(m_debug) +{ + if(no_update) + { + std::cout << " Write into cache / No coherence transaction" + << std::endl; + } + else + { + std::cout << " Coherence update required:" + << " is_cnt = " << r_write_is_cnt.read() + << " nb_copies = " << std::dec << r_write_count.read() << std::endl; + if(owner) std::cout << " ... but the first copy is the writer" << std::endl; + } +} #endif break; @@ -2253,12 +2632,13 @@ wok = m_upt.set(true, // it's an update transaction - false, // it's not a broadcast - true, // it needs a response - srcid, - trdid, - pktid, - nline, - nb_copies, - index); + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); if(wok) // write data in cache { @@ -2282,12 +2662,13 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - if(wok) - { - std::cout << " Register the multicast update in UPT / " - << " nb_copies = " << r_write_count.read() << std::endl; - } - } +if(m_debug) +{ + if(wok) + { + std::cout << " Register the multicast update in UPT / " + << " nb_copies = " << r_write_count.read() << std::endl; + } +} #endif r_write_upt_index = index; @@ -2306,8 +2687,7 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) - { - std::cout << " Get acces to the HEAP" << std::endl; - } +if(m_debug) +std::cout << " Get acces to the HEAP" << std::endl; #endif r_write_fsm = WRITE_UPT_REQ; @@ -2317,10 +2697,8 @@ ////////////////// - case WRITE_UPT_REQ: - { - // prepare the coherence transaction for the CC_SEND FSM - // and write the first copy in the FIFO - // send the request if only one copy - + case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM + // and write the first copy in the FIFO + // send the request if only one copy + { assert(not r_write_to_cc_send_multi_req.read() and not r_write_to_cc_send_brdcast_req.read() and @@ -2373,5 +2751,5 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) + if(m_debug) { std::cout @@ -2404,5 +2782,5 @@ bool dec_upt_counter; - if(((entry.owner.srcid != r_write_srcid.read()) || (r_write_pktid.read() == TYPE_SC)) or + if(((entry.owner.srcid != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC)) or #if L1_MULTI_CACHE (entry.owner.cache_id != r_write_pktid.read()) or @@ -2419,5 +2797,5 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) + if(m_debug) { std::cout << " Post another request to CC_SEND FSM" @@ -2435,5 +2813,5 @@ #if DEBUG_MEMC_WRITE - if(m_debug_write_fsm) + if(m_debug) { std::cout << " Skip one entry in heap matching the writer" @@ -2533,5 +2911,5 @@ } - if(m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)) + if(m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)) { r_write_fsm = WRITE_DIR_REQ; @@ -2548,5 +2926,5 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) +if(m_debug) { std::cout << " Post a request to TGT_RSP FSM" @@ -2572,5 +2950,5 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) +if(m_debug) std::cout << " Check the TRT" << std::endl; #endif @@ -2588,5 +2966,5 @@ m_cpt_write_miss++; } - else if(wok && !hit_write) // set a new entry in TRT + else if(wok and !hit_write) // set a new entry in TRT { r_write_trt_index = wok_index; @@ -2608,5 +2986,5 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) +if(m_debug) std::cout << " Releases the locks before retry" << std::endl; #endif @@ -2643,5 +3021,5 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) +if(m_debug) std::cout << " Set a new entry in TRT" << std::endl; #endif @@ -2670,5 +3048,5 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) +if(m_debug) std::cout << " Modify an existing entry in TRT" << std::endl; #endif @@ -2689,5 +3067,5 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) +if(m_debug) std::cout << " Post a GET request to the IXR_CMD FSM" << std::endl; #endif @@ -2714,5 +3092,5 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) +if(m_debug) std::cout << " Check TRT" << " : wok = " << wok << " / index = " << wok_index << std::endl; @@ -2735,16 +3113,17 @@ size_t nb_copies = r_write_count.read(); - wok =m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // it needs a response - srcid, - trdid, - pktid, - nline, - nb_copies, - index); + wok = m_upt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); #if DEBUG_MEMC_WRITE -if( m_debug_write_fsm and wok ) +if( m_debug and wok ) std::cout << " Register broadcast inval in UPT" << " / nb_copies = " << r_write_count.read() << std::endl; @@ -2763,6 +3142,6 @@ // Register a put transaction to XRAM in TRT // and invalidate the line in directory - if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) || - (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) || + if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or + (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) { @@ -2805,5 +3184,5 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) +if(m_debug) std::cout << " Invalidate the directory entry: @ = " << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; @@ -2816,5 +3195,5 @@ case WRITE_BC_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM { - if(!r_write_to_cc_send_multi_req.read() && !r_write_to_cc_send_brdcast_req.read()) + if(!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read()) { r_write_to_cc_send_multi_req = false; @@ -2833,9 +3212,7 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) -{ - std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; -} +if(m_debug) +std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; #endif } @@ -2858,9 +3235,7 @@ #if DEBUG_MEMC_WRITE -if(m_debug_write_fsm) -{ - std::cout << " Post a put request to IXR_CMD FSM" << std::endl; -} +if(m_debug) +std::cout << " Post a put request to IXR_CMD FSM" << std::endl; #endif } @@ -2934,5 +3309,5 @@ #if DEBUG_MEMC_IXR_CMD -if(m_debug_ixr_cmd_fsm) +if(m_debug) std::cout << " " << " Send a get request to xram / address = " << std::hex @@ -2961,5 +3336,5 @@ #if DEBUG_MEMC_IXR_CMD -if(m_debug_ixr_cmd_fsm) +if(m_debug) std::cout << " " << " Send a put request to xram / address = " << std::hex @@ -2974,5 +3349,5 @@ #if DEBUG_MEMC_IXR_CMD -if(m_debug_ixr_cmd_fsm) +if(m_debug) std::cout << " " << " Send a get request to xram / address = " << std::hex @@ -3002,5 +3377,5 @@ #if DEBUG_MEMC_IXR_CMD -if(m_debug_ixr_cmd_fsm) +if(m_debug) std::cout << " " << " Send a put request to xram / address = " << std::hex @@ -3015,5 +3390,5 @@ #if DEBUG_MEMC_IXR_CMD -if(m_debug_ixr_cmd_fsm) +if(m_debug) std::cout << " " << " Send a get request to xram / address = " << std::hex @@ -3041,5 +3416,5 @@ #if DEBUG_MEMC_IXR_CMD -if(m_debug_ixr_cmd_fsm) +if(m_debug) std::cout << " " << " Send a put request to xram / address = " << std::hex @@ -3081,14 +3456,12 @@ r_ixr_rsp_cpt = 0; r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); - if(p_vci_ixr.reop.read() && !(p_vci_ixr.rerror.read() &0x1)) // PUT transaction + if(p_vci_ixr.reop.read() and !(p_vci_ixr.rerror.read() &0x1)) // PUT transaction { r_ixr_rsp_fsm = IXR_RSP_ACK; #if DEBUG_MEMC_IXR_RSP -if(m_debug_ixr_rsp_fsm) -{ - std::cout << " Response from XRAM to a put transaction" << std::endl; -} +if(m_debug) +std::cout << " Response from XRAM to a put transaction" << std::endl; #endif } @@ -3098,9 +3471,7 @@ #if DEBUG_MEMC_IXR_RSP -if(m_debug_ixr_rsp_fsm) -{ - std::cout << " Response from XRAM to a get transaction" << std::endl; -} +if(m_debug) +std::cout << " Response from XRAM to a get transaction" << std::endl; #endif } @@ -3114,8 +3485,6 @@ #if DEBUG_MEMC_IXR_RSP -if(m_debug_ixr_rsp_fsm) -{ - std::cout << " " << std::endl; -} +if(m_debug) +std::cout << " " << std::endl; #endif break; @@ -3130,9 +3499,7 @@ #if DEBUG_MEMC_IXR_RSP -if(m_debug_ixr_rsp_fsm) -{ - std::cout << " Erase TRT entry " - << r_ixr_rsp_trt_index.read() << std::endl; - } +if(m_debug) +std::cout << " Erase TRT entry " + << r_ixr_rsp_trt_index.read() << std::endl; #endif } @@ -3142,5 +3509,5 @@ case IXR_RSP_TRT_READ: // write a 64 bits data in the TRT { - if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) && p_vci_ixr.rspval) + if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) { size_t index = r_ixr_rsp_trt_index.read(); @@ -3149,5 +3516,5 @@ bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); - assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) || p_vci_ixr.rerror.read()) + assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) or p_vci_ixr.rerror.read()) and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); @@ -3166,11 +3533,9 @@ #if DEBUG_MEMC_IXR_RSP -if(m_debug_ixr_rsp_fsm) -{ - std::cout << " Writing a word in TRT : " - << " index = " << std::dec << index - << " / word = " << r_ixr_rsp_cpt.read() - << " / data = " << std::hex << data << std::endl; -} +if(m_debug) +std::cout << " Writing a word in TRT : " + << " index = " << std::dec << index + << " / word = " << r_ixr_rsp_cpt.read() + << " / data = " << std::hex << data << std::endl; #endif } @@ -3219,5 +3584,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Available cache line in TRT:" @@ -3233,5 +3598,5 @@ // Copy the TRT entry in a local buffer { - if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) && + if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) { @@ -3242,9 +3607,6 @@ r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; -// TransactionTabEntry trt_entry(m_trt.read(index)); -// r_xram_rsp_trt_buf.copy(trt_entry); // TRT entry local buffer - #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Get access to DIR and TRT" << std::endl; @@ -3266,5 +3628,5 @@ DirectoryEntry victim(m_cache_directory.select(set, way)); - bool inval = (victim.count && victim.valid) ; + bool inval = (victim.count and victim.valid) ; // copy the victim line in a local buffer @@ -3296,5 +3658,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Select a slot: " @@ -3323,5 +3685,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Get acces to UPT, but line invalidation registered" @@ -3331,10 +3693,10 @@ } - else if(m_upt.is_full() && r_xram_rsp_victim_inval.read()) // UPT full + else if(m_upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full { r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Get acces to UPT, but inval required and UPT full" << std::endl; @@ -3346,5 +3708,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Get acces to UPT" << std::endl; @@ -3359,5 +3721,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Release all locks and retry" << std::endl; @@ -3373,10 +3735,10 @@ // TYPE_READ_INS_UNC 0bX010 with TSAR encoding // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) && r_xram_rsp_trt_buf.proc_read; + bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read; // check if this is a cached read, this means pktid is either // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) && r_xram_rsp_trt_buf.proc_read; + bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read; bool dirty = false; @@ -3389,5 +3751,5 @@ m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]); - dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[word] != 0); + dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0); if(m_monitor_ok) @@ -3435,5 +3797,6 @@ bool wok = m_upt.set(false, // it's an inval transaction broadcast, // set broadcast bit - false, // it does not need a response + false, // no response required + false, // no acknowledge required 0, // srcid 0, // trdid @@ -3454,5 +3817,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) { std::cout << " " @@ -3500,5 +3863,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Set TRT entry for the put transaction" @@ -3534,5 +3897,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Request the TGT_RSP FSM to return data:" @@ -3547,10 +3910,10 @@ case XRAM_RSP_INVAL: // send invalidate request to CC_SEND FSM { - if(!r_xram_rsp_to_cc_send_multi_req.read() && + if(!r_xram_rsp_to_cc_send_multi_req.read() and !r_xram_rsp_to_cc_send_brdcast_req.read()) { bool multi_req = !r_xram_rsp_victim_is_cnt.read(); - bool last_multi_req = multi_req && (r_xram_rsp_victim_count.read() == 1); - bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1); + bool last_multi_req = multi_req and (r_xram_rsp_victim_count.read() == 1); + bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); r_xram_rsp_to_cc_send_multi_req = last_multi_req; @@ -3571,5 +3934,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Send an inval request to CC_SEND FSM" @@ -3593,6 +3956,6 @@ m_cpt_write_dirty++; - bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read(); - bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1); + bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read(); + bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; @@ -3600,5 +3963,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Send the put request to IXR_CMD FSM" @@ -3617,5 +3980,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Requesting HEAP lock" << std::endl; @@ -3655,8 +4018,8 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Erase copy:" - << " srcid = " << std::dec << entry.owner.srcid + << " srcid = " << std::hex << entry.owner.srcid << " / inst = " << std::dec << entry.owner.inst << std::endl; #endif @@ -3697,5 +4060,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Heap housekeeping" << std::endl; @@ -3713,5 +4076,5 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) +if(m_debug) std::cout << " " << " Error reported by XRAM / erase the TRT entry" << std::endl; @@ -3739,8 +4102,8 @@ #if DEBUG_MEMC_XRAM_RSP -if(m_debug_xram_rsp_fsm) - std::cout << " Request a response error to TGT_RSP FSM:" - << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; +if(m_debug) +std::cout << " Request a response error to TGT_RSP FSM:" + << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; #endif } @@ -3803,13 +4166,9 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Cleanup request:" << std::hex - << " / owner_id = " << srcid - << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) - << std::endl; - } +if(m_debug) +std::cout << " Cleanup request:" << std::hex + << " / owner_id = " << srcid + << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; #endif break; @@ -3831,13 +4190,8 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Cleanup request:" - << std::hex - << " / address = " << nline * m_words * 4 - << std::endl; - } +if(m_debug) +std::cout << " Cleanup request:" + << " / address = " << std::hex << nline * m_words * 4 << std::endl; #endif break; @@ -3845,7 +4199,6 @@ ///////////////////// - case CLEANUP_DIR_REQ: - { - // Get the lock to the directory + case CLEANUP_DIR_REQ: // Get the lock to the directory + { if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; @@ -3853,10 +4206,6 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Requesting DIR lock " - << std::endl; - } +if(m_debug) +std::cout << " Requesting DIR lock" << std::endl; #endif break; @@ -3895,10 +4244,8 @@ #endif - // hit : - // the copy must be cleared - if(entry.valid) + if(entry.valid) // hit : the copy must be cleared { assert( - (entry.count > 0) && + (entry.count > 0) and "VCI MEM CACHE ERROR: " "In CLEANUP_DIR_LOCK, CLEANUP command on a valid entry " @@ -3906,5 +4253,5 @@ // no access to the heap - if((entry.count == 1) || (entry.is_cnt)) + if((entry.count == 1) or (entry.is_cnt)) { r_cleanup_fsm = CLEANUP_DIR_WRITE; @@ -3916,8 +4263,5 @@ } } - // miss : - // we must check the update table for a pending - // invalidation transaction - else + else // miss : check UPT for a pending invalidation transaction { r_cleanup_fsm = CLEANUP_UPT_LOCK; @@ -3925,5 +4269,5 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) + if(m_debug) { std::cout @@ -3968,5 +4312,5 @@ bool match_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); - bool match = match_srcid && match_inst; + bool match = match_srcid and match_inst; if(not r_cleanup_is_cnt.read() and not match) @@ -3999,8 +4343,8 @@ m_cache_directory.write(set, way, entry); - r_cleanup_fsm = CLEANUP_SEND_ACK; + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) + if(m_debug) { std::cout @@ -4029,5 +4373,5 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) + if(m_debug) { std::cout @@ -4182,5 +4526,5 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) + if(m_debug) { std::cout @@ -4220,5 +4564,5 @@ bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); - bool match_heap = match_heap_srcid && match_heap_inst; + bool match_heap = match_heap_srcid and match_heap_inst; #if L1_MULTI_CACHE @@ -4260,5 +4604,5 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) + if(m_debug) { if(not match_heap) @@ -4289,8 +4633,7 @@ break; } - - case CLEANUP_HEAP_CLEAN: - { - // remove a copy in the linked list + //////////////////////// + case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list + { if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) { @@ -4329,19 +4672,14 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Remove the copy in the linked list" - << std::endl; - } -#endif - break; - } - - case CLEANUP_HEAP_FREE: - { - // The heap entry pointed by r_cleanup_next_ptr is freed - // and becomes the head of the list of free entries +if(m_debug) +std::cout << " " + << " Remove the copy in the linked list" << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed + // and becomes the head of the list of free entries + { if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) { @@ -4375,22 +4713,17 @@ m_heap.unset_full(); - r_cleanup_fsm = CLEANUP_SEND_ACK; + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Update the list of free entries" - << std::endl; - } -#endif - break; - } - - case CLEANUP_UPT_LOCK: - { - // search pending invalidate transaction matching the Cleanup NLINE in the UPDATE TABLE - // get the lock in the UPDATE_TABLE +if(m_debug) +std::cout << " " + << " Update the list of free entries" << std::endl; +#endif + break; + } + ////////////////////// + case CLEANUP_UPT_LOCK: // get the lock protecting the UPT to search a pending + // invalidate transaction matching the cleanup + { if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) break; @@ -4400,52 +4733,43 @@ match_inval = m_upt.search_inval(r_cleanup_nline.read(), index); - // no pending inval - if(not match_inval) - { - r_cleanup_fsm = CLEANUP_SEND_ACK; + if ( not match_inval ) // no pending inval + { + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Unexpected cleanup" - << " with no corresponding UPT entry:" - << " address = " << std::hex - << (r_cleanup_nline.read() *4*m_words) - << std::endl; - } -#endif - break; +if(m_debug) +std::cout << " Unexpected cleanup" + << " with no corresponding UPT entry:" + << " address = " << std::hex + << (r_cleanup_nline.read() *4*m_words) + << std::endl; +#endif + break; } // pending inval - r_cleanup_write_srcid = m_upt.srcid(index); - r_cleanup_write_trdid = m_upt.trdid(index); - r_cleanup_write_pktid = m_upt.pktid(index); - r_cleanup_write_need_rsp = m_upt.need_rsp(index); - r_cleanup_index = index; + r_cleanup_write_srcid = m_upt.srcid(index); + r_cleanup_write_trdid = m_upt.trdid(index); + r_cleanup_write_pktid = m_upt.pktid(index); + r_cleanup_need_rsp = m_upt.need_rsp(index); + r_cleanup_need_ack = m_upt.need_ack(index); + r_cleanup_index = index; r_cleanup_fsm = CLEANUP_UPT_DECREMENT; #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Cleanup matching pending" - << " invalidate transaction on UPT:" - << std::hex - << " address = " << r_cleanup_nline.read() * m_words * 4 - << " upt_entry = " << index - << std::endl; - } -#endif - break; - } - - case CLEANUP_UPT_DECREMENT: - { - // decrement response counter in UPT matching entry +if(m_debug) +std::cout << " Cleanup matching pending" + << " invalidate transaction on UPT:" + << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 + << " / upt_entry = " << index << std::endl; +#endif + break; + } + /////////////////////////// + case CLEANUP_UPT_DECREMENT: // decrement response counter in UPT matching entry + { if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) { @@ -4462,33 +4786,25 @@ m_upt.decrement(r_cleanup_index.read(), count); - // invalidation transaction finished - // (all acknowledgements received) - if(count == 0) + if(count == 0) // multi inval transaction completed { r_cleanup_fsm = CLEANUP_UPT_CLEAR; } - // invalidation transaction not finished - else - { - r_cleanup_fsm = CLEANUP_SEND_ACK ; + else // multi inval transaction not completed + { + r_cleanup_fsm = CLEANUP_SEND_CLACK ; } #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Decrement response counter in UPT:" +if(m_debug) +std::cout << " " + << " Decrement response counter in UPT:" << " UPT_index = " << r_cleanup_index.read() - << " rsp_count = " << count - << std::endl; - } -#endif - break; - } - - case CLEANUP_UPT_CLEAR: - { - // Clear UPT entry of finished invalidation transaction + << " / rsp_count = " << count << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_UPT_CLEAR: // Clear UPT entry + { if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) { @@ -4504,30 +4820,20 @@ m_upt.clear(r_cleanup_index.read()); - if(r_cleanup_write_need_rsp.read()) - { - r_cleanup_fsm = CLEANUP_WRITE_RSP; - } - else - { - r_cleanup_fsm = CLEANUP_SEND_ACK; - } + if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; + else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; + else r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Clear entry in UPT:" - << " UPT_index = " << r_cleanup_index.read() - << std::endl; - } -#endif - break; - } - - case CLEANUP_WRITE_RSP: - { - // response to a previous write on the direct network - // wait if pending request to the TGT_RSP FSM +if(m_debug) +std::cout << " Clear entry in UPT:" + << " UPT_index = " << r_cleanup_index.read() << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_WRITE_RSP: // response to a previous write on the direct network + // wait if pending request to the TGT_RSP FSM + { if(r_cleanup_to_tgt_rsp_req.read()) break; @@ -4538,26 +4844,37 @@ r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); - r_cleanup_fsm = CLEANUP_SEND_ACK; + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Send a response to a previous" - << " write request waiting for coherence transaction completion: " - << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() - << " / rtrdid = " << std::hex << r_cleanup_write_trdid.read() - << std::endl; - } -#endif - break; - } - - case CLEANUP_SEND_ACK: - { - // acknowledgement to a cleanup command - // on the coherence network (request to the CC_SEND FSM). - // wait if pending request to the CC_SEND FSM +if(m_debug) +std::cout << " " + << " Send a response to a previous write request: " + << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() + << " / rtrdid = " << r_cleanup_write_trdid.read() + << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; +#endif + break; + } + //////////////////////// + case CLEANUP_CONFIG_ACK: // signals inval completion to CONFIG FSM + // wait if pending request + { + if ( r_cleanup_to_config_ack.read() ) break; + + r_cleanup_to_config_ack = true; + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP +if(m_debug) +std::cout << " " + << " Acknowledge broacast inval completion" << std::endl; +#endif + break; + } + //////////////////////// + case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command + // on the coherence network (request to the CC_SEND FSM). + // wait if pending request to the CC_SEND FSM + { if(r_cleanup_to_cc_send_req.read()) break; @@ -4571,12 +4888,8 @@ #if DEBUG_MEMC_CLEANUP - if(m_debug_cleanup_fsm) - { - std::cout - << " Send the response to a cleanup request:" - << " srcid = " << std::dec << r_cleanup_srcid.read() - << std::endl; - } +if(m_debug) +std::cout << " Send the response to a cleanup request:" + << " srcid = " << std::dec << r_cleanup_srcid.read() << std::endl; #endif break; @@ -4618,5 +4931,5 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) + if(m_debug) { std::cout << " CAS command: " << std::hex @@ -4641,5 +4954,5 @@ r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); - if((r_cas_cpt.read() == 1) && m_cmd_cas_eop_fifo.read()) + if((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) r_cas_wdata = m_cmd_cas_wdata_fifo.read(); @@ -4668,5 +4981,5 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) + if(m_debug) { std::cout @@ -4702,5 +5015,5 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) + if(m_debug) { std::cout << " Directory acces" @@ -4754,5 +5067,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Read data from " << " cache and store it in buffer" << std::endl; @@ -4772,5 +5085,5 @@ // to avoid livelock, force the atomic access to fail pseudo-randomly - bool forced_fail = ((r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS); + bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS); r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001); @@ -4787,5 +5100,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Compare the old" << " and the new data" @@ -4810,5 +5123,5 @@ r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required } - else if(!r_cas_to_cc_send_multi_req.read() && + else if(!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read()) { @@ -4847,5 +5160,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Update cache:" << " way = " << std::dec << way @@ -4874,13 +5187,14 @@ size_t nb_copies = r_cas_count.read(); - wok = m_upt.set(true, // it's an update transaction - false, // it's not a broadcast - true, // it needs a response - srcid, - trdid, - pktid, - nline, - nb_copies, - index); + wok = m_upt.set(true, // it's an update transaction + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); if(wok) // coherence transaction registered in UPT { @@ -4916,5 +5230,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Register multi-update transaction in UPT" @@ -4931,5 +5245,5 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) + if(m_debug) { std::cout << " Send the first update request to CC_SEND FSM " @@ -5043,5 +5357,5 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) + if(m_debug) { std::cout << " Send the next update request to CC_SEND FSM " @@ -5069,5 +5383,5 @@ r_cas_to_ixr_cmd_data[i] = r_cas_wdata.read(); } - else if((i == word+1) && (r_cas_cpt.read() == 4)) // 64 bit CAS + else if((i == word+1) and (r_cas_cpt.read() == 4)) // 64 bit CAS { r_cas_to_ixr_cmd_data[i] = m_cmd_cas_wdata_fifo.read(); @@ -5113,12 +5427,13 @@ // register a broadcast inval transaction in UPT wok = m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // it needs a response - srcid, - trdid, - pktid, - nline, - nb_copies, - index); + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); if(wok) // UPT not full @@ -5148,5 +5463,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Register a broadcast inval transaction in UPT" @@ -5166,6 +5481,6 @@ case CAS_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry { - if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) && - (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) && + if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) { @@ -5204,5 +5519,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Register the PUT in TRT and invalidate DIR entry" @@ -5220,5 +5535,5 @@ case CAS_BC_CC_SEND: // Request the broadcast inval to CC_SEND FSM { - if(!r_cas_to_cc_send_multi_req.read() && + if(!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read()) { @@ -5248,5 +5563,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex @@ -5277,5 +5592,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Request TGT_RSP to send a failure response" << std::endl; @@ -5299,5 +5614,5 @@ #if DEBUG_MEMC_CAS -if(m_debug_cas_fsm) +if(m_debug) std::cout << " Request TGT_RSP to send a success response" << std::endl; @@ -5319,5 +5634,5 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) + if(m_debug) { std::cout << " Check TRT state" @@ -5329,5 +5644,5 @@ #endif - if(hit_read || !wok || hit_write) // missing line already requested or no space in TRT + if(hit_read or !wok or hit_write) // missing line already requested or no space in TRT { r_cas_fsm = CAS_WAIT; @@ -5370,5 +5685,5 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) + if(m_debug) { std::cout << " Register a GET transaction in TRT" << std::hex @@ -5392,5 +5707,5 @@ #if DEBUG_MEMC_CAS - if(m_debug_cas_fsm) + if(m_debug) { std::cout << " Request a GET transaction to IXR_CMD FSM" << std::hex @@ -5438,5 +5753,5 @@ { // XRAM_RSP FSM has highest priority - if(m_xram_rsp_to_cc_send_inst_fifo.rok() || + if(m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) { @@ -5453,5 +5768,5 @@ } - if(m_cas_to_cc_send_inst_fifo.rok() || + if(m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) { @@ -5474,5 +5789,5 @@ } - if(m_write_to_cc_send_inst_fifo.rok() || + if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) { @@ -5493,5 +5808,5 @@ { // CAS FSM has highest priority - if(m_cas_to_cc_send_inst_fifo.rok() || + if(m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) { @@ -5514,5 +5829,5 @@ } - if(m_write_to_cc_send_inst_fifo.rok() || + if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) { @@ -5529,5 +5844,5 @@ } - if(m_xram_rsp_to_cc_send_inst_fifo.rok() || + if(m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) { @@ -5555,5 +5870,5 @@ } - if(m_write_to_cc_send_inst_fifo.rok() || + if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) { @@ -5570,5 +5885,5 @@ } - if(m_xram_rsp_to_cc_send_inst_fifo.rok() || + if(m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) { @@ -5585,5 +5900,5 @@ } - if(m_cas_to_cc_send_inst_fifo.rok() || + if(m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) { @@ -5604,5 +5919,5 @@ { // WRITE FSM has highest priority - if(m_write_to_cc_send_inst_fifo.rok() || + if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) { @@ -5619,5 +5934,5 @@ } - if(m_xram_rsp_to_cc_send_inst_fifo.rok() || + if(m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) { @@ -5634,5 +5949,5 @@ } - if(m_cas_to_cc_send_inst_fifo.rok() || + if(m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) { @@ -5666,5 +5981,5 @@ #if DEBUG_MEMC_CC_SEND -if(m_debug_cc_send_fsm) +if(m_debug) std::cout << " Cleanup Ack for srcid " @@ -5705,5 +6020,5 @@ #if DEBUG_MEMC_CC_SEND -if(m_debug_cc_send_fsm) +if(m_debug) std::cout << " BC-Inval for line " @@ -5733,5 +6048,5 @@ #if DEBUG_MEMC_CC_SEND -if(m_debug_cc_send_fsm) +if(m_debug) std::cout << " BC-Inval for line " @@ -5761,5 +6076,5 @@ #if DEBUG_MEMC_CC_SEND -if(m_debug_cc_send_fsm) +if(m_debug) std::cout << " BC-Inval for line " @@ -5800,5 +6115,5 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug_cc_send_fsm) + if(m_debug) { std::cout @@ -5848,5 +6163,5 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug_cc_send_fsm) + if(m_debug) { std::cout @@ -5892,12 +6207,8 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug_cc_send_fsm) - { - std::cout - << " Multicast-Update for line " - << r_cas_to_cc_send_nline.read() - << std::endl; - } +if(m_debug) +std::cout << " Multicast-Update for line " + << r_cas_to_cc_send_nline.read() << std::endl; #endif break; @@ -5951,5 +6262,5 @@ DspinDhccpParam::FROM_L1_TYPE); - if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) || + if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or (type == DspinDhccpParam::TYPE_CLEANUP_INST)) { @@ -5964,5 +6275,5 @@ } - assert(false && + assert(false and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "Illegal type in coherence request"); @@ -6049,6 +6360,12 @@ r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); } - else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if(r_write_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_WRITE; + } + else if(r_cas_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_CAS ; + } else if(r_xram_rsp_to_tgt_rsp_req) { @@ -6056,7 +6373,16 @@ r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); } - else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if(r_multi_ack_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + } + else if(r_cleanup_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + } + else if(r_tgt_cmd_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + } break; } @@ -6185,4 +6511,5 @@ ///////////////////// case TGT_RSP_TGT_CMD: // send the response after a segmentation violation + // or after a config transaction { if ( p_vci_tgt.rspack ) @@ -6192,9 +6519,9 @@ #if DEBUG_MEMC_TGT_RSP -if( m_debug_tgt_rsp_fsm ) +if( m_debug ) { std::cout << " Segmentation violation from TGT_CMD response" + << " TGT_RSP_TGT_CMD> Segmentation violation ior config access response" << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() @@ -6214,5 +6541,5 @@ #if DEBUG_MEMC_TGT_RSP -if( m_debug_tgt_rsp_fsm ) +if( m_debug ) { std::cout @@ -6260,5 +6587,5 @@ #if DEBUG_MEMC_TGT_RSP -if(m_debug_tgt_rsp_fsm) +if(m_debug) std::cout << " Write response" << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() @@ -6271,5 +6598,5 @@ break; } - /////////////////// + ///////////////////// case TGT_RSP_CLEANUP: // pas clair pour moi (AG) { @@ -6278,5 +6605,5 @@ #if DEBUG_MEMC_TGT_RSP -if(m_debug_tgt_rsp_fsm) +if(m_debug) std::cout << " Cleanup response" << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read() @@ -6289,5 +6616,5 @@ break; } - ////////////////// + ///////////////// case TGT_RSP_CAS: // send one atomic word response { @@ -6296,5 +6623,5 @@ #if DEBUG_MEMC_TGT_RSP -if(m_debug_tgt_rsp_fsm) +if(m_debug) std::cout << " CAS response" << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() @@ -6308,5 +6635,5 @@ } - /////////////////////// + ////////////////// case TGT_RSP_XRAM: // send the response after XRAM access { @@ -6315,5 +6642,5 @@ #if DEBUG_MEMC_TGT_RSP -if( m_debug_tgt_rsp_fsm ) +if( m_debug ) std::cout << " Response following XRAM access" << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() @@ -6351,5 +6678,5 @@ break; } - ////////////////// + /////////////////////// case TGT_RSP_MULTI_ACK: // send the write response after coherence transaction { @@ -6358,5 +6685,5 @@ #if DEBUG_MEMC_TGT_RSP -if(m_debug_tgt_rsp_fsm) +if(m_debug) std::cout << " Write response after coherence transaction" << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() @@ -6374,10 +6701,13 @@ // ALLOC_UPT FSM //////////////////////////////////////////////////////////////////////////////////// - // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT). - // with a round robin priority between three FSMs : MULTI_ACK > WRITE > XRAM_RSP > CLEANUP - // - The WRITE FSM initiates update transactions and sets new entry in UPT. - // - The XRAM_RSP FSM initiates inval transactions and sets new entry in UPT. + // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT), + // with a round robin priority between six FSMs, with the following order: + // CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS + // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT. // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. + // - The WRITE FSM initiates update transaction and sets a new entry in UPT. + // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT. // - The CLEANUP FSM decrement an entry in UPT. + // - The CAS FSM does the same thing as the WRITE FSM. // The resource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// @@ -6385,11 +6715,34 @@ switch(r_alloc_upt_fsm.read()) { - - //////////////////////// - case ALLOC_UPT_MULTI_ACK: - if((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) && + ////////////////////// + case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM + if ( (r_config_fsm.read() != CONFIG_UPT_LOCK) and + (r_config_fsm.read() != CONFIG_BC_UPT_LOCK) ) + { + if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + + else if((r_write_fsm.read() == WRITE_UPT_LOCK) or + (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; + + else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; + + else if((r_cas_fsm.read() == CAS_UPT_LOCK) or + (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + } + break; + + ///////////////////////// + case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM + if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) { - if((r_write_fsm.read() == WRITE_UPT_LOCK) || + if((r_write_fsm.read() == WRITE_UPT_LOCK) or (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_WRITE; @@ -6401,13 +6754,17 @@ r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if((r_cas_fsm.read() == CAS_UPT_LOCK) || + else if((r_cas_fsm.read() == CAS_UPT_LOCK) or (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_CAS; + + else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or + (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + r_alloc_upt_fsm = ALLOC_UPT_CONFIG; } break; ///////////////////// - case ALLOC_UPT_WRITE: - if((r_write_fsm.read() != WRITE_UPT_LOCK) && + case ALLOC_UPT_WRITE: // allocated to WRITE FSM + if((r_write_fsm.read() != WRITE_UPT_LOCK) and (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) { @@ -6418,8 +6775,12 @@ r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if((r_cas_fsm.read() == CAS_UPT_LOCK) || + else if((r_cas_fsm.read() == CAS_UPT_LOCK) or (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_CAS; + else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or + (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + r_alloc_upt_fsm = ALLOC_UPT_CONFIG; + else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; @@ -6428,5 +6789,5 @@ //////////////////////// - case ALLOC_UPT_XRAM_RSP: + case ALLOC_UPT_XRAM_RSP: if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) { @@ -6434,12 +6795,16 @@ r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - else if((r_cas_fsm.read() == CAS_UPT_LOCK) || + else if((r_cas_fsm.read() == CAS_UPT_LOCK) or (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_CAS; + else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or + (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + r_alloc_upt_fsm = ALLOC_UPT_CONFIG; + else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - else if((r_write_fsm.read() == WRITE_UPT_LOCK) || + else if((r_write_fsm.read() == WRITE_UPT_LOCK) or (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_WRITE; @@ -6448,16 +6813,20 @@ ////////////////////////// - case ALLOC_UPT_CLEANUP: - if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) && + case ALLOC_UPT_CLEANUP: + if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) and (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT)) { - if((r_cas_fsm.read() == CAS_UPT_LOCK) || + if((r_cas_fsm.read() == CAS_UPT_LOCK) or (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_CAS; + else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or + (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + r_alloc_upt_fsm = ALLOC_UPT_CONFIG; + else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - else if((r_write_fsm.read() == WRITE_UPT_LOCK) || + else if((r_write_fsm.read() == WRITE_UPT_LOCK) or (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_WRITE; @@ -6469,12 +6838,16 @@ ////////////////////////// - case ALLOC_UPT_CAS: - if((r_cas_fsm.read() != CAS_UPT_LOCK) && + case ALLOC_UPT_CAS: + if((r_cas_fsm.read() != CAS_UPT_LOCK) and (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) { - if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + if((r_config_fsm.read() == CONFIG_UPT_LOCK) or + (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + r_alloc_upt_fsm = ALLOC_UPT_CONFIG; + + else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - else if((r_write_fsm.read() == WRITE_UPT_LOCK) || + else if((r_write_fsm.read() == WRITE_UPT_LOCK) or (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) r_alloc_upt_fsm = ALLOC_UPT_WRITE; @@ -6494,6 +6867,6 @@ //////////////////////////////////////////////////////////////////////////////////// // The ALLOC_DIR FSM allocates the access to the directory and - // the data cache with a round robin priority between 5 user FSMs : - // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP + // the data cache with a round robin priority between 6 user FSMs : + // The cyclic ordering is CONFIG > READ > WRITE > CAS > CLEANUP > XRAM_RSP // The ressource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// @@ -6501,4 +6874,5 @@ switch(r_alloc_dir_fsm.read()) { + ///////////////////// case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. // All the WAYS of a SET initialized in parallel @@ -6513,14 +6887,37 @@ break; + ////////////////////// + case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM + if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and + (r_config_fsm.read() != CONFIG_DIR_ACCESS) and + (r_config_fsm.read() != CONFIG_DIR_INVAL) ) + { + if(r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if(r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if(r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + } + break; + //////////////////// - case ALLOC_DIR_READ: - if(((r_read_fsm.read() != READ_DIR_REQ) && - (r_read_fsm.read() != READ_DIR_LOCK) && - (r_read_fsm.read() != READ_TRT_LOCK) && - (r_read_fsm.read() != READ_HEAP_REQ)) - || - ((r_read_fsm.read() == READ_TRT_LOCK) && - (r_alloc_trt_fsm.read() == ALLOC_TRT_READ))) - { + case ALLOC_DIR_READ: // allocated to READ FSM + if( ((r_read_fsm.read() != READ_DIR_REQ) and + (r_read_fsm.read() != READ_DIR_LOCK) and + (r_read_fsm.read() != READ_TRT_LOCK) and + (r_read_fsm.read() != READ_HEAP_REQ)) + or + ((r_read_fsm.read() == READ_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)) ) + { if(r_write_fsm.read() == WRITE_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_WRITE; @@ -6534,25 +6931,28 @@ else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; - } - break; - - ///////////////////// - case ALLOC_DIR_WRITE: - if(((r_write_fsm.read() != WRITE_DIR_REQ) && - (r_write_fsm.read() != WRITE_DIR_LOCK) && - (r_write_fsm.read() != WRITE_DIR_READ) && - (r_write_fsm.read() != WRITE_DIR_HIT) && - (r_write_fsm.read() != WRITE_BC_TRT_LOCK) && - (r_write_fsm.read() != WRITE_BC_UPT_LOCK) && - (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) && - (r_write_fsm.read() != WRITE_UPT_LOCK) && - (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) - || - ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) && - (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)) - || - ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) && - (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) - { + + else if(r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + } + break; + + ///////////////////// + case ALLOC_DIR_WRITE: // allocated to WRITE FSM + if(((r_write_fsm.read() != WRITE_DIR_REQ) and + (r_write_fsm.read() != WRITE_DIR_LOCK) and + (r_write_fsm.read() != WRITE_DIR_READ) and + (r_write_fsm.read() != WRITE_DIR_HIT) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_UPT_LOCK) and + (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_UPT_LOCK) and + (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) + or + ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) and + (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)) + or + ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) + { if(r_cas_fsm.read() == CAS_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_CAS; @@ -6564,28 +6964,31 @@ r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + else if(r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + else if(r_read_fsm.read() == READ_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_READ; - } - break; - - //////////////////// - case ALLOC_DIR_CAS: - if(((r_cas_fsm.read() != CAS_DIR_REQ) && - (r_cas_fsm.read() != CAS_DIR_LOCK) && - (r_cas_fsm.read() != CAS_DIR_HIT_READ) && - (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) && - (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) && - (r_cas_fsm.read() != CAS_BC_TRT_LOCK) && - (r_cas_fsm.read() != CAS_BC_UPT_LOCK) && - (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) && - (r_cas_fsm.read() != CAS_UPT_LOCK) && - (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK)) - || - ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) && - (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)) - || - ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) && - (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) - { + } + break; + + /////////////////// + case ALLOC_DIR_CAS: // allocated to CAS FSM + if(((r_cas_fsm.read() != CAS_DIR_REQ) and + (r_cas_fsm.read() != CAS_DIR_LOCK) and + (r_cas_fsm.read() != CAS_DIR_HIT_READ) and + (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and + (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_UPT_LOCK) and + (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_UPT_LOCK) and + (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK)) + or + ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) and + (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)) + or + ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) + { if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; @@ -6594,4 +6997,7 @@ r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + else if(r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + else if(r_read_fsm.read() == READ_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_READ; @@ -6599,17 +7005,20 @@ else if(r_write_fsm.read() == WRITE_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_WRITE; - } - break; - - /////////////////////// - case ALLOC_DIR_CLEANUP: - if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) && - (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) && - (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) && - (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) - { + } + break; + + /////////////////////// + case ALLOC_DIR_CLEANUP: // allocated to CLEANUP FSM + if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and + (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) + { if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + else if(r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + else if(r_read_fsm.read() == READ_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_READ; @@ -6620,14 +7029,17 @@ else if(r_cas_fsm.read() == CAS_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_CAS; - } - break; - - //////////////////////// - case ALLOC_DIR_XRAM_RSP: - if((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) && - (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) && - (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) - { - if(r_read_fsm.read() == READ_DIR_REQ) + } + break; + + //////////////////////// + case ALLOC_DIR_XRAM_RSP: // allocated to XRAM_RSP FSM + if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) + { + if(r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if(r_read_fsm.read() == READ_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_READ; @@ -6640,6 +7052,6 @@ else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; - } - break; + } + break; } // end switch alloc_dir_fsm @@ -6660,17 +7072,17 @@ if(r_read_fsm.read() != READ_TRT_LOCK) { - if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || + if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) || + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_CAS; - else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) && + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; @@ -6680,17 +7092,17 @@ ///////////////////// case ALLOC_TRT_WRITE: - if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) && - (r_write_fsm.read() != WRITE_BC_TRT_LOCK) && + if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) { - if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) || + if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_CAS; - else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) && + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; @@ -6703,13 +7115,13 @@ //////////////////// case ALLOC_TRT_CAS: - if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) && - (r_cas_fsm.read() != CAS_BC_TRT_LOCK) && + if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) { - if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) && + if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || + else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; @@ -6718,5 +7130,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_WRITE; @@ -6726,11 +7138,11 @@ //////////////////////// case ALLOC_TRT_XRAM_RSP: - if(((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) || - (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) && - (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) && - (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) && + if(((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or + (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) { - if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || + if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; @@ -6739,9 +7151,9 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) || + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_CAS; @@ -6751,5 +7163,5 @@ //////////////////////// case ALLOC_TRT_IXR_RSP: - if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) && + if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) { @@ -6757,13 +7169,13 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || + else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_WRITE; - else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) || + else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) r_alloc_trt_fsm = ALLOC_TRT_CAS; - else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) && + else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; @@ -6800,6 +7212,6 @@ //////////////////// case ALLOC_HEAP_READ: - if((r_read_fsm.read() != READ_HEAP_REQ) && - (r_read_fsm.read() != READ_HEAP_LOCK) && + if((r_read_fsm.read() != READ_HEAP_REQ) and + (r_read_fsm.read() != READ_HEAP_LOCK) and (r_read_fsm.read() != READ_HEAP_ERASE)) { @@ -6820,6 +7232,6 @@ ///////////////////// case ALLOC_HEAP_WRITE: - if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) && - (r_write_fsm.read() != WRITE_UPT_REQ) && + if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and + (r_write_fsm.read() != WRITE_UPT_REQ) and (r_write_fsm.read() != WRITE_UPT_NEXT)) { @@ -6840,6 +7252,6 @@ //////////////////// case ALLOC_HEAP_CAS: - if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) && - (r_cas_fsm.read() != CAS_UPT_REQ) && + if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and + (r_cas_fsm.read() != CAS_UPT_REQ) and (r_cas_fsm.read() != CAS_UPT_NEXT)) { @@ -6860,7 +7272,7 @@ /////////////////////// case ALLOC_HEAP_CLEANUP: - if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) && - (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) && - (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) && + if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)) { @@ -6881,5 +7293,5 @@ //////////////////////// case ALLOC_HEAP_XRAM_RSP: - if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) && + if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE)) { @@ -6901,39 +7313,19 @@ } // end switch alloc_heap_fsm - - //////////////////////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////// // TGT_CMD to READ FIFO - //////////////////////////////////////////////////////////////////////////////////// - - if(cmd_read_fifo_put) - { - if(cmd_read_fifo_get) - { - m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read())); - m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read() >>2); - m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read()); - m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read()); - m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read()); - } - else - { - m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read())); - m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read() >>2); - m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read()); - m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read()); - m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read()); - } - } - else - { - if(cmd_read_fifo_get) - { - m_cmd_read_addr_fifo.simple_get(); - m_cmd_read_length_fifo.simple_get(); - m_cmd_read_srcid_fifo.simple_get(); - m_cmd_read_trdid_fifo.simple_get(); - m_cmd_read_pktid_fifo.simple_get(); - } - } + ///////////////////////////////////////////////////////////////////// + + m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.address.read() ); + m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.plen.read()>>2 ); + m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.srcid.read() ); + m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.trdid.read() ); + m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.pktid.read() ); + ///////////////////////////////////////////////////////////////////// // TGT_CMD to WRITE FIFO @@ -7264,6 +7656,6 @@ //////////////////////////////////////////////////// - if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) && - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || + if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) or (r_ixr_rsp_fsm.read() == IXR_RSP_ACK)) @@ -7333,5 +7725,5 @@ p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read(); p_vci_tgt.rpktid = r_tgt_cmd_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0x1; + p_vci_tgt.rerror = r_tgt_cmd_to_tgt_rsp_error.read(); p_vci_tgt.reop = true; @@ -7368,5 +7760,5 @@ case TGT_RSP_WRITE: p_vci_tgt.rspval = true; - if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) && r_write_to_tgt_rsp_sc_fail.read()) + if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read()) p_vci_tgt.rdata = 1; else Index: trunk/modules/vci_mem_cache/include/soclib/mem_cache.h =================================================================== --- trunk/modules/vci_mem_cache/include/soclib/mem_cache.h (revision 434) +++ trunk/modules/vci_mem_cache/include/soclib/mem_cache.h (revision 434) @@ -0,0 +1,56 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * alain greiner + * + * Maintainers: alain + */ +#ifndef MEM_CACHE_REGS_H +#define MEM_CACHE_REGS_H + +enum SoclibMemCacheConfigRegs +{ + MEMC_LOCK, + MEMC_CMD_TYPE, + MEMC_ADDR_LO, + MEMC_ADDR_HI, + MEMC_BUF_LENGTH +}; + +enum SoclibMemCacheConfigCmd +{ + MEMC_CMD_NOP, + MEMC_CMD_INVAL, + MEMC_CMD_SYNC +}; + +#endif /* MEM_CACHE_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 +