Changeset 438
- Timestamp:
- Jul 12, 2013, 1:02:11 PM (11 years ago)
- Location:
- trunk/platforms/tsar_generic_xbar
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_xbar/top.cpp
r428 r438 45 45 // - CLUSTER_SIZE : size of the segment allocated to a cluster 46 46 // - NB_PROCS_MAX : number of processors per cluster (power of 2) 47 // - NB_DMA_CHANNELS 48 // - NB_TTY_CHANNELS 49 // - NB_NIC_CHANNELS 47 // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) 48 // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) 49 // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) 50 50 // 51 51 // Some other hardware parameters are not used when compiling the OS, … … 112 112 113 113 // cluster index (computed from x,y coordinates) 114 #define cluster(x,y) (y + CLUSTER_Y*x)114 #define cluster(x,y) (y + YMAX*x) 115 115 116 116 /////////////////////////////////////////////////////////// … … 125 125 /////////////////////////////////////////////////////////// 126 126 127 #define int_vci_cell_width 4 128 #define int_vci_plen_width 8 129 #define int_vci_address_width 40 130 #define int_vci_rerror_width 1 131 #define int_vci_clen_width 1 132 #define int_vci_rflag_width 1 133 #define int_vci_srcid_width 14 134 #define int_vci_pktid_width 4 135 #define int_vci_trdid_width 4 136 #define int_vci_wrplen_width 1 137 138 #define ext_vci_cell_width 8 139 #define ext_vci_plen_width 8 140 #define ext_vci_address_width 40 141 #define ext_vci_rerror_width 1 142 #define ext_vci_clen_width 1 143 #define ext_vci_rflag_width 1 144 #define ext_vci_srcid_width 14 145 #define ext_vci_pktid_width 4 146 #define ext_vci_trdid_width 4 147 #define ext_vci_wrplen_width 1 127 #define vci_cell_width_int 4 128 #define vci_cell_width_ext 8 129 130 #define vci_plen_width 8 131 #define vci_address_width 40 132 #define vci_rerror_width 1 133 #define vci_clen_width 1 134 #define vci_rflag_width 1 135 #define vci_srcid_width 14 136 #define vci_pktid_width 4 137 #define vci_trdid_width 4 138 #define vci_wrplen_width 1 148 139 149 140 //////////////////////////////////////////////////////////// … … 157 148 //////////////////////i///////////////////////////////////// 158 149 150 #define XMAX CLUSTER_X 151 #define YMAX CLUSTER_Y 152 159 153 #define XRAM_LATENCY 0 160 154 … … 178 172 #define NIC_TIMEOUT 10000 179 173 174 #define NORTH 0 175 #define SOUTH 1 176 #define EAST 2 177 #define WEST 3 178 180 179 //////////////////////////////////////////////////////////// 181 180 // Software to be loaded in ROM & RAM … … 189 188 190 189 #define MAX_FROZEN_CYCLES 10000 191 192 #define TRACE_MEMC_ID 1000000193 #define TRACE_PROC_ID 1000000194 190 195 191 ///////////////////////////////////////////////////////// … … 241 237 #define FBUF_TGTID 4 242 238 #define BDEV_TGTID 5 243 #define BROM_TGTID 6244 #define MNIC_TGTID 7239 #define MNIC_TGTID 6 240 #define BROM_TGTID 7 245 241 246 242 ///////////////////////////////// … … 250 246 using namespace soclib::caba; 251 247 using namespace soclib::common; 248 252 249 253 250 char soft_name[256] = SOFT_NAME; // pathname to binary code … … 259 256 bool debug_ok = false; // trace activated 260 257 size_t debug_period = 1; // trace period 261 size_t debug_memc_id = TRACE_MEMC_ID;// index of memc to be traced262 size_t debug_proc_id = TRACE_PROC_ID;// index of proc to be traced258 size_t debug_memc_id = 0; // index of memc to be traced 259 size_t debug_proc_id = 0; // index of proc to be traced 263 260 uint32_t debug_from = 0; // trace start cycle 264 261 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor … … 290 287 { 291 288 debug_memc_id = atoi(argv[n+1]); 292 assert( (debug_memc_id < ( CLUSTER_X*CLUSTER_Y) ) &&289 assert( (debug_memc_id < (XMAX*YMAX) ) && 293 290 "debug_memc_id larger than XMAX * YMAX" ); 294 291 } … … 296 293 { 297 294 debug_proc_id = atoi(argv[n+1]); 298 assert( (debug_proc_id < ( CLUSTER_X * CLUSTER_Y* NB_PROCS_MAX) ) &&295 assert( (debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX) ) && 299 296 "debug_proc_id larger than XMAX * YMAX * NB_PROCS" ); 300 297 } … … 332 329 333 330 // checking hardware parameters 334 assert( ( ( CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or335 ( CLUSTER_X == 8) or (CLUSTER_X == 16) ) and336 "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" );337 338 assert( ( ( CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y== 4) or339 ( CLUSTER_Y == 8) or (CLUSTER_Y== 16) ) and340 "The CLUSTER_Yparameter must be 1, 2, 4, 8 or 16" );331 assert( ( (XMAX == 1) or (XMAX == 2) or (XMAX == 4) or 332 (XMAX == 8) or (XMAX == 16) ) and 333 "The XMAX parameter must be 1, 2, 4, 8 or 16" ); 334 335 assert( ( (YMAX == 1) or (YMAX == 2) or (YMAX == 4) or 336 (YMAX == 8) or (YMAX == 16) ) and 337 "The YMAX parameter must be 1, 2, 4, 8 or 16" ); 341 338 342 339 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or … … 353 350 "The NB_NIC_CHANNELS parameter must be smaller than 9" ); 354 351 355 assert( ( int_vci_address_width == ext_vci_address_width) and352 assert( (vci_address_width == vci_address_width) and 356 353 "address widths must be equal on internal & external networks" ); 357 354 358 assert( ( int_vci_address_width == 40) and355 assert( (vci_address_width == 40) and 359 356 "VCI address width must be 40 bits" ); 360 357 361 358 std::cout << std::endl; 362 std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl;363 std::cout << " - CLUSTER_Y = " << CLUSTER_Y<< std::endl;364 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;359 std::cout << " - XMAX = " << XMAX << std::endl; 360 std::cout << " - YMAX = " << YMAX << std::endl; 361 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 365 362 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; 366 std::cout << " - NB_TTY_CHANNELS 367 std::cout << " - NB_NIC_CHANNELS 368 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;369 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;370 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;371 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;363 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; 364 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; 365 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 366 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; 367 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 368 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 372 369 373 370 std::cout << std::endl; 374 371 375 372 // Internal and External VCI parameters definition 376 typedef soclib::caba::VciParams< int_vci_cell_width,377 int_vci_plen_width,378 int_vci_address_width,379 int_vci_rerror_width,380 int_vci_clen_width,381 int_vci_rflag_width,382 int_vci_srcid_width,383 int_vci_pktid_width,384 int_vci_trdid_width,385 int_vci_wrplen_width> vci_param_int;386 387 typedef soclib::caba::VciParams< ext_vci_cell_width,388 ext_vci_plen_width,389 ext_vci_address_width,390 ext_vci_rerror_width,391 ext_vci_clen_width,392 ext_vci_rflag_width,393 ext_vci_srcid_width,394 ext_vci_pktid_width,395 ext_vci_trdid_width,396 ext_vci_wrplen_width> vci_param_ext;373 typedef soclib::caba::VciParams<vci_cell_width_int, 374 vci_plen_width, 375 vci_address_width, 376 vci_rerror_width, 377 vci_clen_width, 378 vci_rflag_width, 379 vci_srcid_width, 380 vci_pktid_width, 381 vci_trdid_width, 382 vci_wrplen_width> vci_param_int; 383 384 typedef soclib::caba::VciParams<vci_cell_width_ext, 385 vci_plen_width, 386 vci_address_width, 387 vci_rerror_width, 388 vci_clen_width, 389 vci_rflag_width, 390 vci_srcid_width, 391 vci_pktid_width, 392 vci_trdid_width, 393 vci_wrplen_width> vci_param_ext; 397 394 398 395 #if USE_OPENMP … … 406 403 size_t y_width; 407 404 408 if ( CLUSTER_X == 1) x_width = 0;409 else if ( CLUSTER_X == 2) x_width = 1;410 else if ( CLUSTER_X <= 4) x_width = 2;411 else if ( CLUSTER_X <= 8) x_width = 3;405 if (XMAX == 1) x_width = 0; 406 else if (XMAX == 2) x_width = 1; 407 else if (XMAX <= 4) x_width = 2; 408 else if (XMAX <= 8) x_width = 3; 412 409 else x_width = 4; 413 410 414 if ( CLUSTER_Y== 1) y_width = 0;415 else if ( CLUSTER_Y== 2) y_width = 1;416 else if ( CLUSTER_Y<= 4) y_width = 2;417 else if ( CLUSTER_Y<= 8) y_width = 3;411 if (YMAX == 1) y_width = 0; 412 else if (YMAX == 2) y_width = 1; 413 else if (YMAX <= 4) y_width = 2; 414 else if (YMAX <= 8) y_width = 3; 418 415 else y_width = 4; 419 416 … … 423 420 424 421 // internal network 425 MappingTable maptabd( int_vci_address_width,422 MappingTable maptabd(vci_address_width, 426 423 IntTab(x_width + y_width, 16 - x_width - y_width), 427 IntTab(x_width + y_width, int_vci_srcid_width - x_width - y_width),424 IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), 428 425 0x00FF000000); 429 426 430 for (size_t x = 0; x < CLUSTER_X; x++)427 for (size_t x = 0; x < XMAX; x++) 431 428 { 432 for (size_t y = 0; y < CLUSTER_Y; y++)429 for (size_t y = 0; y < YMAX; y++) 433 430 { 434 sc_uint< int_vci_address_width> offset;435 offset = (sc_uint< int_vci_address_width>)cluster(x,y)436 << ( int_vci_address_width-x_width-y_width);431 sc_uint<vci_address_width> offset; 432 offset = (sc_uint<vci_address_width>)cluster(x,y) 433 << (vci_address_width-x_width-y_width); 437 434 438 435 std::ostringstream sh; … … 469 466 470 467 // external network 471 MappingTable maptabx( ext_vci_address_width,468 MappingTable maptabx(vci_address_width, 472 469 IntTab(x_width+y_width), 473 470 IntTab(x_width+y_width), 474 471 0xFFFF000000ULL); 475 472 476 for (size_t x = 0; x < CLUSTER_X; x++)473 for (size_t x = 0; x < XMAX; x++) 477 474 { 478 for (size_t y = 0; y < CLUSTER_Y; y++)475 for (size_t y = 0; y < YMAX ; y++) 479 476 { 480 477 481 sc_uint< ext_vci_address_width> offset;482 offset = (sc_uint< ext_vci_address_width>)cluster(x,y)483 << ( ext_vci_address_width-x_width-y_width);478 sc_uint<vci_address_width> offset; 479 offset = (sc_uint<vci_address_width>)cluster(x,y) 480 << (vci_address_width-x_width-y_width); 484 481 485 482 std::ostringstream sh; … … 499 496 sc_signal<bool> signal_resetn("resetn"); 500 497 501 enum {502 NORTH = VirtualDspinRouter<dspin_cmd_width>::NORTH,503 SOUTH = VirtualDspinRouter<dspin_cmd_width>::SOUTH,504 EAST = VirtualDspinRouter<dspin_cmd_width>::EAST,505 WEST = VirtualDspinRouter<dspin_cmd_width>::WEST,506 LOCAL = VirtualDspinRouter<dspin_cmd_width>::LOCAL507 };508 509 498 // Horizontal inter-clusters DSPIN signals 510 499 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc = 511 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2);500 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 2); 512 501 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec = 513 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2);502 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 2); 514 503 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc = 515 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2);504 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2); 516 505 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec = 517 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2);506 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX, 2); 518 507 519 508 // Vertical inter-clusters DSPIN signals 520 509 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc = 521 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2);510 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 2); 522 511 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec = 523 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2);512 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 2); 524 513 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc = 525 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2);514 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2); 526 515 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec = 527 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2);516 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1, 2); 528 517 529 518 // Mesh boundaries DSPIN signals 530 519 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in = 531 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4);520 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in", XMAX, YMAX, 2, 4); 532 521 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out = 533 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4);522 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 2, 4); 534 523 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in = 535 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4);524 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in", XMAX, YMAX, 2, 4); 536 525 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out = 537 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4);526 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 2, 4); 538 527 539 528 … … 560 549 dspin_rsp_width, 561 550 vci_param_int, 562 vci_param_ext>* clusters[ CLUSTER_X][CLUSTER_Y];551 vci_param_ext>* clusters[XMAX][YMAX]; 563 552 564 553 #if USE_OPENMP … … 567 556 #pragma omp for 568 557 #endif 569 for(size_t i = 0; i < ( CLUSTER_X * CLUSTER_Y); i++)558 for(size_t i = 0; i < (XMAX * YMAX); i++) 570 559 { 571 size_t x = i / CLUSTER_Y;572 size_t y = i % CLUSTER_Y;560 size_t x = i / YMAX; 561 size_t y = i % YMAX; 573 562 574 563 #if USE_OPENMP … … 576 565 { 577 566 #endif 567 std::cout << std::endl; 568 std::cout << "Cluster_" << x << "_" << y << std::endl; 569 std::cout << std::endl; 578 570 579 571 std::ostringstream sc; … … 595 587 x_width, 596 588 y_width, 597 int_vci_srcid_width - x_width - y_width, // l_id width,589 vci_srcid_width - x_width - y_width, // l_id width, 598 590 MEMC_TGTID, 599 591 XICU_TGTID, … … 627 619 ); 628 620 629 std::cout << std::endl;630 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;631 std::cout << std::endl;632 633 621 #if USE_OPENMP 634 622 } // end critical … … 644 632 645 633 // Clock & RESET 646 for (size_t x = 0; x < ( CLUSTER_X); x++){647 for (size_t y = 0; y < CLUSTER_Y; y++){634 for (size_t x = 0; x < (XMAX); x++){ 635 for (size_t y = 0; y < YMAX; y++){ 648 636 clusters[x][y]->p_clk (signal_clk); 649 637 clusters[x][y]->p_resetn (signal_resetn); … … 652 640 653 641 // Inter Clusters horizontal connections 654 if ( CLUSTER_X > 1){655 for (size_t x = 0; x < ( CLUSTER_X-1); x++){656 for (size_t y = 0; y < CLUSTER_Y; y++){642 if (XMAX > 1){ 643 for (size_t x = 0; x < (XMAX-1); x++){ 644 for (size_t y = 0; y < YMAX; y++){ 657 645 for (size_t k = 0; k < 2; k++){ 658 clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]);659 clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]);660 clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]);661 clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]);662 clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]);663 clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]);664 clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]);665 clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]);646 clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); 647 clusters[x+1][y]->p_cmd_in[k][WEST] (signal_dspin_h_cmd_inc[x][y][k]); 648 clusters[x][y]->p_cmd_in[k][EAST] (signal_dspin_h_cmd_dec[x][y][k]); 649 clusters[x+1][y]->p_cmd_out[k][WEST] (signal_dspin_h_cmd_dec[x][y][k]); 650 clusters[x][y]->p_rsp_out[k][EAST] (signal_dspin_h_rsp_inc[x][y][k]); 651 clusters[x+1][y]->p_rsp_in[k][WEST] (signal_dspin_h_rsp_inc[x][y][k]); 652 clusters[x][y]->p_rsp_in[k][EAST] (signal_dspin_h_rsp_dec[x][y][k]); 653 clusters[x+1][y]->p_rsp_out[k][WEST] (signal_dspin_h_rsp_dec[x][y][k]); 666 654 } 667 655 } … … 671 659 672 660 // Inter Clusters vertical connections 673 if ( CLUSTER_Y> 1) {674 for (size_t y = 0; y < ( CLUSTER_Y-1); y++){675 for (size_t x = 0; x < CLUSTER_X; x++){661 if (YMAX > 1) { 662 for (size_t y = 0; y < (YMAX-1); y++){ 663 for (size_t x = 0; x < XMAX; x++){ 676 664 for (size_t k = 0; k < 2; k++){ 677 clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]);678 clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]);679 clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]);680 clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]);681 clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]);682 clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]);683 clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]);684 clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]);665 clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); 666 clusters[x][y+1]->p_cmd_in[k][SOUTH] (signal_dspin_v_cmd_inc[x][y][k]); 667 clusters[x][y]->p_cmd_in[k][NORTH] (signal_dspin_v_cmd_dec[x][y][k]); 668 clusters[x][y+1]->p_cmd_out[k][SOUTH] (signal_dspin_v_cmd_dec[x][y][k]); 669 clusters[x][y]->p_rsp_out[k][NORTH] (signal_dspin_v_rsp_inc[x][y][k]); 670 clusters[x][y+1]->p_rsp_in[k][SOUTH] (signal_dspin_v_rsp_inc[x][y][k]); 671 clusters[x][y]->p_rsp_in[k][NORTH] (signal_dspin_v_rsp_dec[x][y][k]); 672 clusters[x][y+1]->p_rsp_out[k][SOUTH] (signal_dspin_v_rsp_dec[x][y][k]); 685 673 } 686 674 } … … 690 678 691 679 // East & West boundary cluster connections 692 for (size_t y = 0; y < CLUSTER_Y; y++)680 for (size_t y = 0; y < YMAX; y++) 693 681 { 694 682 for (size_t k = 0; k < 2; k++) 695 683 { 696 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]);697 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]);698 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]);699 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]);700 701 clusters[ CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]);702 clusters[ CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]);703 clusters[ CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]);704 clusters[ CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]);684 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); 685 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); 686 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); 687 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); 688 689 clusters[XMAX-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[XMAX-1][y][k][EAST]); 690 clusters[XMAX-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[XMAX-1][y][k][EAST]); 691 clusters[XMAX-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[XMAX-1][y][k][EAST]); 692 clusters[XMAX-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[XMAX-1][y][k][EAST]); 705 693 } 706 694 } 707 695 708 696 // North & South boundary clusters connections 709 for (size_t x = 0; x < CLUSTER_X; x++)697 for (size_t x = 0; x < XMAX; x++) 710 698 { 711 699 for (size_t k = 0; k < 2; k++) … … 716 704 clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); 717 705 718 clusters[x][ CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]);719 clusters[x][ CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]);720 clusters[x][ CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]);721 clusters[x][ CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]);706 clusters[x][YMAX-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][YMAX-1][k][NORTH]); 707 clusters[x][YMAX-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][YMAX-1][k][NORTH]); 708 clusters[x][YMAX-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][YMAX-1][k][NORTH]); 709 clusters[x][YMAX-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][YMAX-1][k][NORTH]); 722 710 } 723 711 } … … 734 722 735 723 // network boundaries signals 736 for (size_t x = 0; x < CLUSTER_X ; x++){737 for (size_t y = 0; y < CLUSTER_Y; y++){724 for (size_t x = 0; x < XMAX ; x++){ 725 for (size_t y = 0; y < YMAX ; y++){ 738 726 for (size_t k = 0; k < 2; k++){ 739 727 for (size_t a = 0; a < 4; a++){ … … 767 755 768 756 // trace proc[debug_proc_id] 769 if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) 770 { 771 size_t l = debug_proc_id % NB_PROCS_MAX ; 772 size_t y = (debug_proc_id / NB_PROCS_MAX) % CLUSTER_Y ; 773 size_t x = debug_proc_id / (CLUSTER_Y * NB_PROCS_MAX) ; 774 775 std::ostringstream vci_signame; 776 vci_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 777 std::ostringstream p2m_signame; 778 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 779 std::ostringstream m2p_signame; 780 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 781 std::ostringstream cmd_signame; 782 cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; 783 std::ostringstream rsp_signame; 784 rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; 785 786 clusters[x][y]->proc[l]->print_trace(); 787 clusters[x][y]->wi_proc[l]->print_trace(); 788 clusters[x][y]->signal_vci_ini_proc[l].print_trace(vci_signame.str()); 789 clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 790 clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 791 clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(cmd_signame.str()); 792 clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(rsp_signame.str()); 793 794 clusters[x][y]->xbar_rsp_d->print_trace(); 795 clusters[x][y]->xbar_cmd_d->print_trace(); 796 clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); 797 clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); 798 clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); 799 clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); 800 } 757 size_t l = debug_proc_id % NB_PROCS_MAX ; 758 size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ; 759 size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ; 760 761 std::ostringstream proc_signame; 762 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 763 std::ostringstream p2m_signame; 764 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 765 std::ostringstream m2p_signame; 766 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 767 std::ostringstream p_cmd_signame; 768 p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; 769 std::ostringstream p_rsp_signame; 770 p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; 771 772 clusters[x][y]->proc[l]->print_trace(); 773 clusters[x][y]->wi_proc[l]->print_trace(); 774 clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); 775 clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 776 clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 777 clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); 778 clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); 779 780 clusters[x][y]->xbar_rsp_d->print_trace(); 781 clusters[x][y]->xbar_cmd_d->print_trace(); 782 clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); 783 clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); 784 clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); 785 clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); 801 786 802 787 // trace memc[debug_memc_id] 803 if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) 804 { 805 size_t x = debug_memc_id / CLUSTER_Y; 806 size_t y = debug_memc_id % CLUSTER_Y; 807 808 std::ostringstream smemc; 809 smemc << "[SIG]MEMC_" << x << "_" << y; 810 std::ostringstream sxram; 811 sxram << "[SIG]XRAM_" << x << "_" << y; 812 std::ostringstream sm2p; 813 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; 814 std::ostringstream sp2m; 815 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; 816 std::ostringstream cmd_signame; 817 cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; 818 std::ostringstream rsp_signame; 819 rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; 820 821 clusters[x][y]->memc->print_trace(); 822 clusters[x][y]->wt_memc->print_trace(); 823 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 824 clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 825 clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); 826 clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); 827 clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(cmd_signame.str()); 828 clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(rsp_signame.str()); 829 } 788 x = debug_memc_id / YMAX; 789 y = debug_memc_id % YMAX; 790 791 std::ostringstream smemc; 792 smemc << "[SIG]MEMC_" << x << "_" << y; 793 std::ostringstream sxram; 794 sxram << "[SIG]XRAM_" << x << "_" << y; 795 std::ostringstream sm2p; 796 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; 797 std::ostringstream sp2m; 798 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; 799 std::ostringstream m_cmd_signame; 800 m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; 801 std::ostringstream m_rsp_signame; 802 m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; 803 804 clusters[x][y]->memc->print_trace(); 805 clusters[x][y]->wt_memc->print_trace(); 806 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 807 clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 808 clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); 809 clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); 810 clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str()); 811 clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str()); 830 812 831 813 // trace replicated peripherals … … 836 818 837 819 // trace external peripherals 838 size_t io_x = cluster_io_id / CLUSTER_Y;839 size_t io_y = cluster_io_id % CLUSTER_Y;820 size_t io_x = cluster_io_id / YMAX; 821 size_t io_y = cluster_io_id % YMAX; 840 822 841 823 clusters[io_x][io_y]->brom->print_trace(); -
trunk/platforms/tsar_generic_xbar/top.desc
r428 r438 3 3 4 4 # internal VCI parameters values 5 int_vci_cell_size = 4 6 int_vci_plen_size = 8 7 int_vci_addr_size = 40 8 int_vci_rerror_size = 1 9 int_vci_clen_size = 1 10 int_vci_rflag_size = 1 11 int_vci_srcid_size = 14 12 int_vci_pktid_size = 4 13 int_vci_trdid_size = 4 14 int_vci_wrplen_size = 1 5 vci_cell_size_int = 4 6 vci_cell_size_ext = 8 15 7 16 # external VCI parameters values 17 ext_vci_cell_size = 8 18 ext_vci_plen_size = 8 19 ext_vci_addr_size = 40 20 ext_vci_rerror_size = 1 21 ext_vci_clen_size = 1 22 ext_vci_rflag_size = 1 23 ext_vci_srcid_size = 14 24 ext_vci_pktid_size = 4 25 ext_vci_trdid_size = 4 26 ext_vci_wrplen_size = 1 8 vci_plen_size = 8 9 vci_addr_size = 40 10 vci_rerror_size = 1 11 vci_clen_size = 1 12 vci_rflag_size = 1 13 vci_srcid_size = 14 14 vci_pktid_size = 4 15 vci_trdid_size = 4 16 vci_wrplen_size = 1 27 17 28 18 # DSPIN network parameters values … … 31 21 32 22 todo = Platform('caba', 'top.cpp', 33 uses = [34 Uses('caba:tsar_xbar_cluster',35 dspin_cmd_width = dspin_cmd_flit_size,36 dspin_rsp_width = dspin_rsp_flit_size,37 23 38 vci_param_int = 'caba:vci_param', 24 uses = [ 25 Uses('caba:tsar_xbar_cluster', 26 vci_data_width_int = vci_cell_size_int, 27 vci_data_width_ext = vci_cell_size_ext, 28 dspin_cmd_width = dspin_cmd_flit_size, 29 dspin_rsp_width = dspin_rsp_flit_size), 39 30 40 cell_size = int_vci_cell_size, 41 plen_size = int_vci_plen_size, 42 addr_size = int_vci_addr_size, 43 rerror_size = int_vci_rerror_size, 44 clen_size = int_vci_clen_size, 45 rflag_size = int_vci_rflag_size, 46 srcid_size = int_vci_srcid_size, 47 pktid_size = int_vci_pktid_size, 48 trdid_size = int_vci_trdid_size, 49 wrplen_size = int_vci_wrplen_size, 31 Uses('common:elf_file_loader'), 32 Uses('common:plain_file_loader'), 33 ], 50 34 51 vci_param_ext = 'caba:vci_param', 52 53 cell_size_ext = ext_vci_cell_size, 54 ), 55 56 Uses('common:elf_file_loader'), 57 Uses('common:plain_file_loader'), 58 ], 35 # default VCI parameters (global variables) 36 cell_size = vci_cell_size_int, 37 plen_size = vci_plen_size, 38 addr_size = vci_addr_size, 39 rerror_size = vci_rerror_size, 40 clen_size = vci_clen_size, 41 rflag_size = vci_rflag_size, 42 srcid_size = vci_srcid_size, 43 pktid_size = vci_pktid_size, 44 trdid_size = vci_trdid_size, 45 wrplen_size = vci_wrplen_size, 59 46 ) 60
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