Index: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 434) +++ trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 439) @@ -90,4 +90,5 @@ enum tgt_rsp_fsm_state_e { + TGT_RSP_CONFIG_IDLE, TGT_RSP_TGT_CMD_IDLE, TGT_RSP_READ_IDLE, @@ -97,4 +98,5 @@ TGT_RSP_MULTI_ACK_IDLE, TGT_RSP_CLEANUP_IDLE, + TGT_RSP_CONFIG, TGT_RSP_TGT_CMD, TGT_RSP_READ, @@ -118,8 +120,13 @@ enum cc_send_fsm_state_e { + CC_SEND_CONFIG_IDLE, CC_SEND_XRAM_RSP_IDLE, CC_SEND_WRITE_IDLE, CC_SEND_CAS_IDLE, CC_SEND_CLEANUP_IDLE, + CC_SEND_CONFIG_INVAL_HEADER, + CC_SEND_CONFIG_INVAL_NLINE, + CC_SEND_CONFIG_BRDCAST_HEADER, + CC_SEND_CONFIG_BRDCAST_NLINE, CC_SEND_CLEANUP_ACK, CC_SEND_XRAM_RSP_BRDCAST_HEADER, @@ -158,14 +165,12 @@ CONFIG_DIR_REQ, CONFIG_DIR_ACCESS, - CONFIG_DIR_INVAL, - CONFIG_BC_UPT_LOCK, + CONFIG_DIR_UPT_LOCK, CONFIG_BC_SEND, CONFIG_BC_WAIT, - - CONFIG_UPT_WAIT, - - CONFIG_UPT_LOCK, - - CONFIG_HEAP_REQ + CONFIG_INV_SEND, + CONFIG_HEAP_REQ, + CONFIG_HEAP_SCAN, + CONFIG_HEAP_LAST, + CONFIG_INV_WAIT }; @@ -345,5 +350,6 @@ ALLOC_HEAP_CAS, ALLOC_HEAP_CLEANUP, - ALLOC_HEAP_XRAM_RSP + ALLOC_HEAP_XRAM_RSP, + ALLOC_HEAP_CONFIG }; @@ -568,16 +574,21 @@ /////////////////////////////////////////////////////// - sc_signal r_config_fsm; // FSM state - sc_signal r_config_lock; // lock protecting exclusive access - sc_signal r_config_cmd; // config request status - sc_signal r_config_address; // target buffer physical address - sc_signal r_config_srcid; // config request srcid - sc_signal r_config_trdid; // config request trdid - sc_signal r_config_pktid; // config request pktid - sc_signal r_config_nlines; // number of lines covering the buffer - sc_signal r_config_way; // selected way - sc_signal r_config_count; // number of copies + sc_signal r_config_fsm; // FSM state + sc_signal r_config_lock; // lock protecting exclusive access + sc_signal r_config_cmd; // config request status + sc_signal r_config_address; // target buffer physical address + sc_signal r_config_srcid; // config request srcid + sc_signal r_config_trdid; // config request trdid + sc_signal r_config_pktid; // config request pktid + sc_signal r_config_nlines; // number of lines covering the buffer + sc_signal r_config_dir_way; // DIR: selected way + sc_signal r_config_dir_count; // DIR: number of copies + sc_signal r_config_dir_is_cnt; // DIR: counter mode (broadcast required) + sc_signal r_config_dir_copy_srcid; // DIR: first copy SRCID + sc_signal r_config_dir_copy_inst; // DIR: first copy L1 type + sc_signal r_config_dir_next_ptr; // DIR: index of next copy in HEAP + sc_signal r_config_heap_next; // current pointer to scan HEAP + sc_signal r_config_upt_index; // UPT index - sc_signal r_config_is_cnt; // counter mode (broadcast required) // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) @@ -591,6 +602,12 @@ sc_signal r_config_to_cc_send_multi_req; // multi-inval request sc_signal r_config_to_cc_send_brdcast_req; // broadcast-inval request - sc_signal r_config_to_cc_send_nline; // line index + sc_signal r_config_to_cc_send_nline; // line index sc_signal r_config_to_cc_send_trdid; // UPT index + GenericFifo m_config_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_config_to_cc_send_srcid_fifo; // fifo for owners srcid + +#if L1_MULTI_CACHE + GenericFifo m_config_to_cc_send_cache_id_fifo; // fifo for cache_id +#endif /////////////////////////////////////////////////////// Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 434) +++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 439) @@ -69,4 +69,5 @@ const char *tgt_rsp_fsm_str[] = { + "TGT_RSP_CONFIG_IDLE", "TGT_RSP_TGT_CMD_IDLE", "TGT_RSP_READ_IDLE", @@ -76,4 +77,5 @@ "TGT_RSP_MULTI_ACK_IDLE", "TGT_RSP_CLEANUP_IDLE", + "TGT_RSP_CONFIG", "TGT_RSP_TGT_CMD", "TGT_RSP_READ", @@ -93,8 +95,13 @@ const char *cc_send_fsm_str[] = { + "CC_SEND_CONFIG_IDLE", "CC_SEND_XRAM_RSP_IDLE", "CC_SEND_WRITE_IDLE", "CC_SEND_CAS_IDLE", "CC_SEND_CLEANUP_IDLE", + "CC_SEND_CONFIG_INVAL_HEADER", + "CC_SEND_CONFIG_INVAL_NLINE", + "CC_SEND_CONFIG_BRDCAST_HEADER", + "CC_SEND_CONFIG_BRDCAST_NLINE", "CC_SEND_CLEANUP_ACK", "CC_SEND_XRAM_RSP_BRDCAST_HEADER", @@ -121,4 +128,20 @@ "MULTI_ACK_WRITE_RSP", "MULTI_ACK_CONFIG_ACK" +}; +const char *config_fsm_str[] = +{ + "CONFIG_IDLE", + "CONFIG_LOOP", + "CONFIG_RSP", + "CONFIG_DIR_REQ", + "CONFIG_DIR_ACCESS", + "CONFIG_DIR_UPT_LOCK", + "CONFIG_BC_SEND", + "CONFIG_BC_WAIT", + "CONFIG_INV_SEND", + "CONFIG_HEAP_REQ", + "CONFIG_HEAP_SCAN", + "CONFIG_HEAP_LAST", + "CONFIG_INV_WAIT" }; const char *read_fsm_str[] = @@ -274,5 +297,6 @@ "ALLOC_HEAP_CAS", "ALLOC_HEAP_CLEANUP", - "ALLOC_HEAP_XRAM_RSP" + "ALLOC_HEAP_XRAM_RSP", + "ALLOC_HEAP_CONFIG" }; @@ -375,7 +399,12 @@ m_cc_receive_to_multi_ack_fifo("m_cc_receive_to_multi_ack_fifo", 4), - r_read_fsm("r_read_fsm"), - - r_write_fsm("r_write_fsm"), + r_config_fsm( "r_config_fsm" ), + + m_config_to_cc_send_inst_fifo( "m_config_to_cc_send_inst_fifo", 8 ), + m_config_to_cc_send_srcid_fifo( "m_config_to_cc_send_srcid_fifo", 8 ), + + r_read_fsm( "r_read_fsm" ), + + r_write_fsm( "r_write_fsm" ), m_write_to_cc_send_inst_fifo("m_write_to_cc_send_inst_fifo",8), @@ -563,4 +592,5 @@ << " | " << write_fsm_str[r_write_fsm.read()] << " | " << cas_fsm_str[r_cas_fsm.read()] + << " | " << config_fsm_str[r_config_fsm.read()] << " | " << cleanup_fsm_str[r_cleanup_fsm.read()] << std::endl; std::cout << " " << cc_send_fsm_str[r_cc_send_fsm.read()] @@ -686,4 +716,10 @@ r_config_lock = false; + m_config_to_cc_send_inst_fifo.init(); + m_config_to_cc_send_srcid_fifo.init(); +#if L1_MULTI_CACHE + m_config_to_cc_send_cache_id_fifo.init(); +#endif + r_tgt_cmd_to_tgt_rsp_req = false; @@ -802,4 +838,9 @@ size_t xram_rsp_to_cc_send_fifo_cache_id = 0; #endif + + bool config_to_cc_send_fifo_put = false; + bool config_to_cc_send_fifo_get = false; + bool config_to_cc_send_fifo_inst = false; + size_t config_to_cc_send_fifo_srcid = 0; bool cas_to_cc_send_fifo_put = false; @@ -856,5 +897,5 @@ // acces key, second flit the data to write => WRITE FSM. // - // The READ/WRITE commands accepted in the configuration segment are targeting, + // The READ/WRITE commands accepted in the configuration segment are targeting // configuration or status registers. They must contain one single flit. // - For almost all addressable registers, the response is returned immediately. @@ -873,5 +914,5 @@ std::cout << " Receive command from srcid " - << std::dec << p_vci_tgt.srcid.read() + << std::hex << p_vci_tgt.srcid.read() << " / address " << std::hex << p_vci_tgt.address.read() << std::endl; #endif @@ -991,52 +1032,66 @@ case TGT_CMD_CONFIG: // execute config request and return response { - if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break; - addr_t seg_base = m_seg[m_seg_config]->baseAddress(); addr_t address = p_vci_tgt.address.read(); size_t cell = (address - seg_base)/vci_param_int::B; - bool need_rsp = true; // default value - size_t error = 0; // default value - uint32_t rdata = 0; // default value + + bool need_rsp; + size_t error; + uint32_t rdata = 0; // default value if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock and (cell == MEMC_LOCK) ) { - rdata = (uint32_t)r_config_lock.read(); - r_config_lock = true; + rdata = (uint32_t)r_config_lock.read(); + need_rsp = true; + error = 0; + r_config_lock = true; } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock and (cell == MEMC_LOCK) ) { - r_config_lock = false; + need_rsp = true; + error = 0; + r_config_lock = false; + } + else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo + and (cell == MEMC_ADDR_LO) ) + { + need_rsp = true; + error = 0; + r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | + (addr_t)p_vci_tgt.wdata.read(); + } + else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi + and (cell == MEMC_ADDR_HI) ) + { + need_rsp = true; + error = 0; + r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | + ((addr_t)p_vci_tgt.wdata.read())<<32; + } + else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines + and (cell == MEMC_BUF_LENGTH) ) + { + need_rsp = true; + error = 0; + size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words<<2)); + if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++; + r_config_nlines = lines; } else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type and (cell == MEMC_CMD_TYPE) ) { - r_config_cmd = p_vci_tgt.wdata.read(); - need_rsp = false; - } - else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo - and (cell == MEMC_ADDR_LO) ) - { - r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | - (addr_t)p_vci_tgt.wdata.read(); - } - else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi - and (cell == MEMC_ADDR_HI) ) - { - r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | - ((addr_t)p_vci_tgt.wdata.read())<<32; - } - else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines - and (cell == MEMC_BUF_LENGTH) ) - { - size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words*vci_param_int::B)); - if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++; - r_config_nlines = lines; + need_rsp = false; + error = 0; + r_config_cmd = p_vci_tgt.wdata.read(); + r_config_srcid = p_vci_tgt.srcid.read(); + r_config_trdid = p_vci_tgt.trdid.read(); + r_config_pktid = p_vci_tgt.pktid.read(); } else { - error = 1; + need_rsp = true; + error = 1; } @@ -1168,15 +1223,13 @@ // update the UPT. // - // It can be update or inval requests initiated by the WRITE or CAS FSM, - // or inval requests initiated by the XRAM_RSP FSM. + // - The FSM decrements the proper entry in UPT, + // and clear the UPT entry when all responses have been received. + // - If required, it sends a request to the TGT_RSP FSM to complete + // a pending write transaction. + // - If required, it sends an acknowledge to the CONFIG FSM to signal + // completion of a line inval. // - // The FSM decrements the proper entry in UPT. - // It sends a request to the TGT_RSP FSM to complete the pending - // write transaction (acknowledge response to the writer processor), - // and clear the UPT entry when all responses have been received. - // - // All those response packets are one flit packet. - // The index in the Table is defined in the UPDT_TABLE INDEX field, and - // the transaction type is defined in the UPT entry. + // All those multi-ack packets are one flit packet. + // The index in the UPT is defined in the UPDTID field. //////////////////////////////////////////////////////////////////////// @@ -1225,5 +1278,5 @@ std::cout << " Response for UPT entry " - << updt_index << std::endl; + << (size_t)updt_index << std::endl; } else @@ -1370,5 +1423,7 @@ // The config inval response is sent only when the last line has been invalidated. // - // - SYNC request: Not implemented yet + // - SYNC request: + // + // ... Not implemented yet ... // // From the software point of view, a configuration request is a sequence @@ -1390,5 +1445,4 @@ { r_config_fsm = CONFIG_LOOP; - } #if DEBUG_MEMC_CONFIG @@ -1399,4 +1453,5 @@ << " / type = " << r_config_cmd.read() << std::endl; #endif + } break; } @@ -1416,8 +1471,8 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " address = " << std::hex << r_config_address.read() << " / nlines = " << std::dec << r_config_nlines.read() - << " / type = " << r_config_cmd.read() << std::endl; + << " / command = " << r_config_cmd.read() << std::endl; #endif break; @@ -1433,5 +1488,5 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " Request DIR access" << std::endl; #endif @@ -1439,5 +1494,5 @@ } /////////////////////// - case CONFIG_DIR_ACCESS: // Access directory and decode cmd + case CONFIG_DIR_ACCESS: // Access directory and decode config command { size_t way = 0; @@ -1447,8 +1502,12 @@ (r_config_cmd.read() == MEMC_CMD_INVAL) ) { - r_config_way = way; - r_config_is_cnt = entry.is_cnt; - r_config_count = entry.count; - r_config_fsm = CONFIG_DIR_INVAL; + r_config_dir_way = way; + r_config_dir_copy_inst = entry.owner.inst; + r_config_dir_copy_srcid = entry.owner.srcid; + r_config_dir_is_cnt = entry.is_cnt; + r_config_dir_count = entry.count; + r_config_dir_next_ptr = entry.ptr; + + r_config_fsm = CONFIG_DIR_UPT_LOCK; } else if ( entry.valid and // hit & sync command @@ -1460,8 +1519,8 @@ exit(0); } - else // nothing to do : return to LOOP + else // return to LOOP { r_config_nlines = r_config_nlines.read() - 1; - r_config_address = r_config_address.read() + (m_words*vci_param_int::B); + r_config_address = r_config_address.read() + (m_words<<2); r_config_fsm = CONFIG_LOOP; } @@ -1470,84 +1529,83 @@ if(m_debug) std::cout << " Accessing directory: " - << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " address = " << std::hex << r_config_address.read() << " / hit = " << std::dec << entry.valid - << " / dirty = " < Inval directory entry" << std::endl; -#endif - break; - } - //////////////////////// - case CONFIG_BC_UPT_LOCK: // try to register BC transaction in UPT + ///////////////////////// + case CONFIG_DIR_UPT_LOCK: // enter this state in case of INVAL command + // Try to get both DIR & UPT locks, and return + // to LOOP state if UPT full. + // Register inval in UPT, and invalidate the + // directory if UPT not full. { if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) { - bool wok = false; - size_t index = 0; - size_t srcid = r_config_srcid.read(); - size_t trdid = r_config_trdid.read(); - size_t pktid = r_config_pktid.read(); - addr_t nline = m_nline[(addr_t)(r_config_address.read())]; - size_t nb_copies = r_config_count.read(); - - wok = m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - false, // no response required - true, // acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - if ( wok ) + size_t set = m_y[(addr_t)(r_config_address.read())]; + size_t way = r_config_dir_way.read(); + + if ( r_config_dir_count.read() == 0 ) // inval DIR and return to LOOP { - r_config_fsm = CONFIG_BC_SEND; - r_config_upt_index = index; + m_cache_directory.inval( way, set ); + r_config_nlines = r_config_nlines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG -if( m_debug ) -std::cout << " Register broadcast inval in UPT" << std::endl; +if(m_debug) +std::cout << " " + << " No copies in L1 : inval DIR entry" << std::endl; #endif } - else + else // try to register inval in UPT { - r_config_fsm = CONFIG_UPT_WAIT; - + bool wok = false; + size_t index = 0; + bool broadcast = r_config_dir_is_cnt.read(); + size_t srcid = r_config_srcid.read(); + size_t trdid = r_config_trdid.read(); + size_t pktid = r_config_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_config_address.read())]; + size_t nb_copies = r_config_dir_count.read(); + + wok = m_upt.set(false, // it's an inval transaction + broadcast, + false, // no response required + true, // acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + if ( wok ) // UPT success => inval DIR slot + { + m_cache_directory.inval( way, set ); + r_config_upt_index = index; + if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; + else r_config_fsm = CONFIG_INV_SEND; + #if DEBUG_MEMC_CONFIG -if( m_debug ) -std::cout << " " - << " UPT full" << std::endl; -#endif +if(m_debug) +std::cout << " " + << " Inval DIR entry and register inval in UPT" + << " : index = " << std::dec << index + << " / broadcast = " << broadcast << std::endl; +#endif + } + else // UPT full => release both DIR and UPT locks + { + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " + << " UPT full : release DIR & UPT locks and retry" << std::endl; +#endif + } } } @@ -1564,7 +1622,5 @@ r_config_to_cc_send_trdid = r_config_upt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; - r_cleanup_to_config_ack = false; - r_config_fsm = CONFIG_BC_WAIT; @@ -1581,69 +1637,138 @@ case CONFIG_BC_WAIT: // wait broadcast completion to return to LOOP { - if ( r_cleanup_to_config_ack.read() ) r_config_fsm = CONFIG_LOOP; + if ( r_cleanup_to_config_ack.read() ) + { + r_config_fsm = CONFIG_LOOP; + r_config_nlines = r_config_nlines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + } #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " - << " Waiting broadcast inval completion" << std::endl; +std::cout << " Waiting BC completion " + << " done = " << r_cleanup_to_config_ack.read() + << std::endl; #endif break; } ///////////////////// - case CONFIG_UPT_LOCK: // Try to register multi-update in UPT - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) + case CONFIG_INV_SEND: // Post a multi inval request to CC_SEND FSM + { + if( not r_config_to_cc_send_multi_req.read() and + not r_config_to_cc_send_brdcast_req.read() ) { - bool wok = false; - size_t index = 0; - size_t srcid = r_config_srcid.read(); - size_t trdid = r_config_trdid.read(); - size_t pktid = r_config_pktid.read(); - addr_t nline = m_nline[(addr_t)(r_config_address.read())]; - size_t nb_copies = r_config_count.read(); - - wok = m_upt.set(false, // it's an inval transaction - false, // not a broadcast - false, // no response required - true, // acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - if ( wok ) - { - r_config_fsm = CONFIG_BC_SEND; - r_config_upt_index = index; + r_config_to_cc_send_multi_req = true; + r_config_to_cc_send_brdcast_req = false; + r_config_to_cc_send_trdid = r_config_upt_index.read(); + r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; + r_multi_ack_to_config_ack = false; + + config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); + config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); + config_to_cc_send_fifo_put = true; + + if ( r_config_dir_count.read() == 1 ) r_config_fsm = CONFIG_INV_WAIT; + else r_config_fsm = CONFIG_HEAP_REQ; #if DEBUG_MEMC_CONFIG -if( m_debug ) -std::cout << " Register broadcast inval in UPT" << std::endl; -#endif - } - else - { - r_config_fsm = CONFIG_UPT_WAIT; +if(m_debug) +std::cout << " " + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << r_config_dir_copy_srcid.read() + << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; +#endif + } + break; + } + ///////////////////// + case CONFIG_HEAP_REQ: // Try to get access to Heap + { + if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG ) + { + r_config_fsm = CONFIG_HEAP_SCAN; + r_config_heap_next = r_config_dir_next_ptr.read(); + } + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " " + << " Requesting HEAP lock" << std::endl; +#endif + break; + } + ////////////////////// + case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM + { + HeapEntry entry = m_heap.read( r_config_heap_next.read() ); + bool last_copy = (entry.next == r_config_heap_next.read()); + + config_to_cc_send_fifo_srcid = entry.owner.srcid; + config_to_cc_send_fifo_inst = entry.owner.inst; + // config_to_cc_send_fifo_last = last_copy; + config_to_cc_send_fifo_put = true; + + if ( m_config_to_cc_send_inst_fifo.wok() ) // inval request accepted + { + r_config_heap_next = entry.next; + if ( last_copy ) r_config_fsm = CONFIG_HEAP_LAST; + } #if DEBUG_MEMC_CONFIG -if( m_debug ) -std::cout << " " - << " UPT full" << std::endl; -#endif - } +if(m_debug) +std::cout << " " + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; +#endif + break; + } + ////////////////////// + case CONFIG_HEAP_LAST: // HEAP housekeeping + { + size_t free_pointer = m_heap.next_free_ptr(); + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + + if ( m_heap.is_full() ) + { + last_entry.next = r_config_dir_next_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = free_pointer; + } + + m_heap.write_free_ptr( r_config_dir_next_ptr.read() ); + m_heap.write( r_config_heap_next.read(), last_entry ); + r_config_fsm = CONFIG_INV_WAIT; #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " Request access to UPT" << std::endl; -#endif +std::cout << " " + << " Heap housekeeping" << std::endl; +#endif + break; + } + ///////////////////// + case CONFIG_INV_WAIT: // wait inval completion to return to LOOP + { + if ( r_multi_ack_to_config_ack.read() ) + { + r_config_fsm = CONFIG_LOOP; + r_config_nlines = r_config_nlines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); } - break; - } - ///////////////////// - case CONFIG_HEAP_REQ: // request access to the heap - { - break; + +#if DEBUG_MEMC_CONFIG +if(m_debug) +std::cout << " Waiting inval completion " + << " done = " << r_multi_ack_to_config_ack.read() + << std::endl; +#endif + break; } @@ -1651,5 +1776,5 @@ case CONFIG_RSP: // request TGT_RSP FSM to return response { - if ( not r_config_to_tgt_rsp_req ) + if ( not r_config_to_tgt_rsp_req.read() ) { r_config_to_tgt_rsp_srcid = r_config_srcid.read(); @@ -1664,22 +1789,9 @@ std::cout << " Request TGT_RSP FSM to return response:" << " error = " << r_config_to_tgt_rsp_error.read() - << " / rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; + << " / rsrcid = " << std::hex << r_config_srcid.read() << std::endl; #endif } break; - } - ///////////////////// - case CONFIG_UPT_WAIT: // release the lock on UPT for one cycle, and retry - { - if ( r_config_is_cnt.read() ) r_config_fsm = CONFIG_BC_UPT_LOCK; - else r_config_fsm = CONFIG_UPT_LOCK; - -#if DEBUG_MEMC_CONFIG -if(m_debug) -std::cout << " " - << " Release UPT lock" << std::endl; -#endif - break; } } // end switch r_config_fsm @@ -5729,6 +5841,8 @@ // the CLEANUP fsm. // - // It implements a round-robin priority between the four possible client FSMs - // XRAM_RSP, WRITE, CAS and CLEANUP. Each FSM can request the next services: + // It implements a round-robin priority between the five possible client FSMs + // XRAM_RSP > CAS > CLEANUP > WRITE > CONFIG + // + // Each FSM can request the next services: // - r_xram_rsp_to_cc_send_multi_req : multi-inval // r_xram_rsp_to_cc_send_brdcast_req : broadcast-inval @@ -5737,4 +5851,7 @@ // - r_cas_to_cc_send_multi_req : multi-update // r_cas_to_cc_send_brdcast_req : broadcast-inval + // - r_config_to_cc_send_multi_req : multi-inval + // r_config_to_cc_send_brdcast_req : broadcast-inval + // // - r_cleanup_to_cc_send_req : cleanup acknowledgement // @@ -5750,7 +5867,8 @@ switch(r_cc_send_fsm.read()) { - case CC_SEND_WRITE_IDLE: - { - // XRAM_RSP FSM has highest priority + ///////////////////////// + case CC_SEND_CONFIG_IDLE: // XRAM_RSP FSM has highest priority + { + // XRAM_RSP if(m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) @@ -5760,5 +5878,4 @@ break; } - if(r_xram_rsp_to_cc_send_brdcast_req.read()) { @@ -5767,5 +5884,5 @@ break; } - + // CAS if(m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) @@ -5775,5 +5892,4 @@ break; } - if(r_cas_to_cc_send_brdcast_req.read()) { @@ -5782,5 +5898,5 @@ break; } - + // CLEANUP if (r_cleanup_to_cc_send_req.read()) { @@ -5788,5 +5904,5 @@ break; } - + // WRITE if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -5796,16 +5912,56 @@ break; } - if(r_write_to_cc_send_brdcast_req.read()) { r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; m_cpt_inval++; + break; + } + // CONFIG + if(r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + m_cpt_inval++; + break; + } + if(r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + m_cpt_inval++; + break; } break; } - - case CC_SEND_XRAM_RSP_IDLE: - { - // CAS FSM has highest priority + //////////////////////// + case CC_SEND_WRITE_IDLE: // CONFIG FSM has highest priority + { + // CONFIG + if(r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + m_cpt_inval++; + break; + } + if(r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + m_cpt_inval++; + break; + } + // XRAM_RSP + if(m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + m_cpt_inval++; + break; + } + if(r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + m_cpt_inval++; + break; + } + // CAS if(m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) @@ -5815,5 +5971,4 @@ break; } - if(r_cas_to_cc_send_brdcast_req.read()) { @@ -5822,11 +5977,11 @@ break; } - - if(r_cleanup_to_cc_send_req.read()) + // CLEANUP + if (r_cleanup_to_cc_send_req.read()) { r_cc_send_fsm = CC_SEND_CLEANUP_ACK; break; } - + // WRITE if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -5836,5 +5991,4 @@ break; } - if(r_write_to_cc_send_brdcast_req.read()) { @@ -5843,5 +5997,58 @@ break; } - + break; + } + /////////////////////////// + case CC_SEND_XRAM_RSP_IDLE: // CAS FSM has highest priority + { + // CAS + if(m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + m_cpt_update++; + break; + } + if(r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + m_cpt_inval++; + break; + } + // CLEANUP + if(r_cleanup_to_cc_send_req.read()) + { + r_cc_send_fsm = CC_SEND_CLEANUP_ACK; + break; + } + // WRITE + if(m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + m_cpt_update++; + break; + } + + if(r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + m_cpt_inval++; + break; + } + // CONFIG + if(r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + m_cpt_inval++; + break; + } + if(r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + m_cpt_inval++; + break; + } + // XRAM_RSP if(m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) @@ -5851,17 +6058,15 @@ break; } - if(r_xram_rsp_to_cc_send_brdcast_req.read()) { r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; m_cpt_inval++; - } - + break; + } break; } - - case CC_SEND_CAS_IDLE: - { - // CLEANUP FSM has highest priority + ////////////////////// + case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority + { if(r_cleanup_to_cc_send_req.read()) { @@ -5869,5 +6074,4 @@ break; } - if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -5877,5 +6081,4 @@ break; } - if(r_write_to_cc_send_brdcast_req.read()) { @@ -5884,5 +6087,17 @@ break; } - + // CONFIG + if(r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + m_cpt_inval++; + break; + } + if(r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + m_cpt_inval++; + break; + } if(m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) @@ -5892,5 +6107,4 @@ break; } - if(r_xram_rsp_to_cc_send_brdcast_req.read()) { @@ -5899,5 +6113,4 @@ break; } - if(m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) @@ -5907,16 +6120,16 @@ break; } - if(r_cas_to_cc_send_brdcast_req.read()) { r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; m_cpt_inval++; + break; } break; } - - case CC_SEND_CLEANUP_IDLE: - { - // WRITE FSM has highest priority + ////////////////////////// + case CC_SEND_CLEANUP_IDLE: // WRITE FSM has highest priority + { + // WRITE if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -5926,5 +6139,4 @@ break; } - if(r_write_to_cc_send_brdcast_req.read()) { @@ -5933,5 +6145,18 @@ break; } - + // CONFIG + if(r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + m_cpt_inval++; + break; + } + if(r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + m_cpt_inval++; + break; + } + // XRAM_RSP if(m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) @@ -5941,5 +6166,4 @@ break; } - if(r_xram_rsp_to_cc_send_brdcast_req.read()) { @@ -5948,5 +6172,5 @@ break; } - + // CAS if(m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) @@ -5956,5 +6180,4 @@ break; } - if(r_cas_to_cc_send_brdcast_req.read()) { @@ -5963,16 +6186,67 @@ break; } - + // CLEANUP if(r_cleanup_to_cc_send_req.read()) { r_cc_send_fsm = CC_SEND_CLEANUP_ACK; - } - + break; + } break; } - - case CC_SEND_CLEANUP_ACK: - { - // send only flit for a cleanup acknowledgement (from CLEANUP FSM) + ///////////////////////////////// + case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) + { + if(m_config_to_cc_send_inst_fifo.rok()) + { + if(not p_dspin_out.read) break; + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; + break; + } + if(r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false; + r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) + { + if(not p_dspin_out.read) break; + m_cpt_inval_mult++; + config_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + +#if DEBUG_MEMC_CC_SEND +if(m_debug) +std::cout << " multi-inval for line " + << std::hex << r_config_to_cc_send_nline.read() << std::endl; +#endif + break; + } + /////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) + { + if(not p_dspin_out.read) break; + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; + break; + } + ////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) + { + if(not p_dspin_out.read) break; + m_cpt_inval_brdcast++; + r_config_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + +#if DEBUG_MEMC_CC_SEND +if(m_debug) +std::cout << " BC-Inval for line " + << std::hex << r_config_to_cc_send_nline.read() << std::endl; +#endif + break; + } + ///////////////////////// + case CC_SEND_CLEANUP_ACK: // send one flit for a cleanup acknowledgement + { if(not p_dspin_out.read) break; @@ -5988,34 +6262,24 @@ break; } - - case CC_SEND_XRAM_RSP_INVAL_HEADER: - { - // send first flit multi-inval (from XRAM_RSP FSM) + /////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) + { if(m_xram_rsp_to_cc_send_inst_fifo.rok()) { if(not p_dspin_out.read) break; - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; break; } - - if(r_xram_rsp_to_cc_send_multi_req.read()) - { - r_xram_rsp_to_cc_send_multi_req = false; - } - + if(r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false; r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; break; } - - case CC_SEND_XRAM_RSP_INVAL_NLINE: - { - // send second flit multi-inval (from XRAM_RSP FSM) + ////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) + { if(not p_dspin_out.read) break; - m_cpt_inval_mult++; - xram_rsp_to_cc_send_fifo_get = true; - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; #if DEBUG_MEMC_CC_SEND @@ -6027,21 +6291,16 @@ break; } - - case CC_SEND_XRAM_RSP_BRDCAST_HEADER: - { - // send first flit broadcast-inval (from XRAM_RSP FSM) + ///////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) + { if(not p_dspin_out.read) break; - r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; break; } - - case CC_SEND_XRAM_RSP_BRDCAST_NLINE: - { - // send second flit broadcast-inval (from XRAM_RSP FSM) + //////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) + { if(not p_dspin_out.read) break; - m_cpt_inval_brdcast++; - r_xram_rsp_to_cc_send_brdcast_req = false; r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; @@ -6055,17 +6314,14 @@ break; } - - case CC_SEND_WRITE_BRDCAST_HEADER: - { - // send first flit broadcast-inval (from WRITE FSM) + ////////////////////////////////// + case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) + { if(not p_dspin_out.read) break; - r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; break; } - - case CC_SEND_WRITE_BRDCAST_NLINE: - { - // send second flit broadcast-inval (from WRITE FSM) + ///////////////////////////////// + case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) + { if(not p_dspin_out.read) break; @@ -6083,8 +6339,7 @@ break; } - - case CC_SEND_WRITE_UPDT_HEADER: - { - // send first flit for a multi-update (from WRITE FSM) + /////////////////////////////// + case CC_SEND_WRITE_UPDT_HEADER: // send first flit for a multi-update (from WRITE FSM) + { if(m_write_to_cc_send_inst_fifo.rok()) { @@ -6103,10 +6358,8 @@ break; } - - case CC_SEND_WRITE_UPDT_NLINE: - { - // send second flit for a multi-update (from WRITE FSM) + ////////////////////////////// + case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) + { if(not p_dspin_out.read) break; - m_cpt_update_mult++; @@ -6115,21 +6368,15 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug) - { - std::cout - << " Multicast-Update for line " - << r_write_to_cc_send_nline.read() - << std::endl; - } +if(m_debug) +std::cout << " Multicast-Update for line " + << r_write_to_cc_send_nline.read() << std::endl; #endif break; } - - case CC_SEND_WRITE_UPDT_DATA: - { - // send N data flits for a multi-update (from WRITE FSM) + ///////////////////////////// + case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) + { if(not p_dspin_out.read) break; - if(r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)) { @@ -6142,19 +6389,15 @@ break; } - - case CC_SEND_CAS_BRDCAST_HEADER: - { - // send first flit for a broadcast-inval (from CAS FSM) + //////////////////////////////// + case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) + { if(not p_dspin_out.read) break; - r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; break; } - - case CC_SEND_CAS_BRDCAST_NLINE: - { - // send second flit broadcast-inval (from CAS FSM) + /////////////////////////////// + case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) + { if(not p_dspin_out.read) break; - m_cpt_inval_brdcast++; @@ -6163,19 +6406,14 @@ #if DEBUG_MEMC_CC_SEND - if(m_debug) - { - std::cout - << " Broadcast-Inval for line " - << r_cas_to_cc_send_nline.read() - << std::endl; - } +if(m_debug) +std::cout << " Broadcast-Inval for line " + << r_cas_to_cc_send_nline.read() << std::endl; #endif break; } - - case CC_SEND_CAS_UPDT_HEADER: - { - // send first flit for a multi-update (from CAS FSM) + ///////////////////////////// + case CC_SEND_CAS_UPDT_HEADER: // send first flit for a multi-update (from CAS FSM) + { if(m_cas_to_cc_send_inst_fifo.rok()) { @@ -6195,8 +6433,7 @@ break; } - - case CC_SEND_CAS_UPDT_NLINE: - { - // send second flit for a multi-update (from CAS FSM) + //////////////////////////// + case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) + { if(not p_dspin_out.read) break; @@ -6214,8 +6451,7 @@ break; } - - case CC_SEND_CAS_UPDT_DATA: - { - // send first data for a multi-update (from CAS FSM) + /////////////////////////// + case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) + { if(not p_dspin_out.read) break; @@ -6230,10 +6466,8 @@ break; } - - case CC_SEND_CAS_UPDT_DATA_HIGH: - { - // send second data for a multi-update (from CAS FSM) + //////////////////////////////// + case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) + { if(not p_dspin_out.read) break; - cas_to_cc_send_fifo_get = true; r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; @@ -6334,9 +6568,10 @@ } } - ///////////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////////////////// // TGT_RSP FSM - ///////////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////////////////// // The TGT_RSP fsm sends the responses on the VCI target port - // with a round robin priority between seven requests : + // with a round robin priority between eigth requests : + // - r_config_to_tgt_rsp_req // - r_tgt_cmd_to_tgt_rsp_req // - r_read_to_tgt_rsp_req @@ -6348,24 +6583,20 @@ // // The ordering is : - // tgt_cmd > read > write > cas > xram > multi_ack > cleanup - ///////////////////////////////////////////////////////////////////// + // config >tgt_cmd > read > write > cas > xram > multi_ack > cleanup + ////////////////////////////////////////////////////////////////////////// switch(r_tgt_rsp_fsm.read()) { - case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority - { - if(r_read_to_tgt_rsp_req) + ///////////////////////// + case TGT_RSP_CONFIG_IDLE: // tgt_cmd requests have the highest priority + { + if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if(r_read_to_tgt_rsp_req) { r_tgt_rsp_fsm = TGT_RSP_READ; r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); } - else if(r_write_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_WRITE; - } - else if(r_cas_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_CAS ; - } + else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; else if(r_xram_rsp_to_tgt_rsp_req) { @@ -6373,16 +6604,28 @@ r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); } - else if(r_multi_ack_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - } - else if(r_cleanup_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - } - else if(r_tgt_cmd_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - } + else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + break; + } + ////////////////////////// + case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority + { + if(r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if(r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; break; } @@ -6390,6 +6633,6 @@ case TGT_RSP_READ_IDLE: // write requests have the highest priority { - if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; else if(r_xram_rsp_to_tgt_rsp_req) { @@ -6398,6 +6641,7 @@ } else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; else if(r_read_to_tgt_rsp_req) { @@ -6410,5 +6654,5 @@ case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority { - if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; else if(r_xram_rsp_to_tgt_rsp_req) { @@ -6417,6 +6661,7 @@ } else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; else if(r_read_to_tgt_rsp_req) { @@ -6424,6 +6669,5 @@ r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); } - - else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; break; } @@ -6437,6 +6681,7 @@ } else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; - else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; else if(r_read_to_tgt_rsp_req) { @@ -6444,6 +6689,6 @@ r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); } - else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; break; } @@ -6452,7 +6697,8 @@ { - if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; - else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; else if(r_read_to_tgt_rsp_req) { @@ -6460,6 +6706,6 @@ r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); } - else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; else if(r_xram_rsp_to_tgt_rsp_req) { @@ -6469,9 +6715,10 @@ break; } - /////////////////////// + //////////////////////////// case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority { - if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; else if(r_read_to_tgt_rsp_req) { @@ -6479,6 +6726,6 @@ r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); } - else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; else if(r_xram_rsp_to_tgt_rsp_req) { @@ -6489,8 +6736,9 @@ break; } - /////////////////////// + ////////////////////////// case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority { - if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; else if(r_read_to_tgt_rsp_req) { @@ -6498,6 +6746,6 @@ r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); } - else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; else if(r_xram_rsp_to_tgt_rsp_req) { @@ -6506,15 +6754,14 @@ } else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; - else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - break; - } - ///////////////////// - case TGT_RSP_TGT_CMD: // send the response after a segmentation violation - // or after a config transaction + else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + break; + } + //////////////////// + case TGT_RSP_CONFIG: // send the response for a config transaction { if ( p_vci_tgt.rspack ) { - r_tgt_cmd_to_tgt_rsp_req = false; - r_tgt_rsp_fsm = TGT_RSP_TGT_CMD_IDLE; + r_config_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_CONFIG_IDLE; #if DEBUG_MEMC_TGT_RSP @@ -6523,5 +6770,28 @@ std::cout << " Segmentation violation ior config access response" + << " TGT_RSP_CONFIG> Config transaction completed response" + << " / rsrcid = " << std::hex << r_config_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_config_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_config_to_tgt_rsp_pktid.read() + << std::endl; +} +#endif + } + break; + } + ///////////////////// + case TGT_RSP_TGT_CMD: // send the response for a segmentation violation + { + if ( p_vci_tgt.rspack ) + { + r_tgt_cmd_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_TGT_CMD_IDLE; + +#if DEBUG_MEMC_TGT_RSP +if( m_debug ) +{ + std::cout + << " Segmentation violation response" << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() @@ -6531,7 +6801,6 @@ #endif } - } - break; - + break; + } ////////////////// case TGT_RSP_READ: // send the response to a read @@ -6634,5 +6903,4 @@ break; } - ////////////////// case TGT_RSP_XRAM: // send the response after XRAM access @@ -6717,6 +6985,5 @@ ////////////////////// case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM - if ( (r_config_fsm.read() != CONFIG_UPT_LOCK) and - (r_config_fsm.read() != CONFIG_BC_UPT_LOCK) ) + if (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK) { if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) @@ -6758,6 +7025,5 @@ r_alloc_upt_fsm = ALLOC_UPT_CAS; - else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or - (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CONFIG; } @@ -6779,6 +7045,5 @@ r_alloc_upt_fsm = ALLOC_UPT_CAS; - else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or - (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CONFIG; @@ -6799,6 +7064,5 @@ r_alloc_upt_fsm = ALLOC_UPT_CAS; - else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or - (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CONFIG; @@ -6821,6 +7085,5 @@ r_alloc_upt_fsm = ALLOC_UPT_CAS; - else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or - (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CONFIG; @@ -6842,6 +7105,5 @@ (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) { - if((r_config_fsm.read() == CONFIG_UPT_LOCK) or - (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) + if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_CONFIG; @@ -6891,5 +7153,5 @@ if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and (r_config_fsm.read() != CONFIG_DIR_ACCESS) and - (r_config_fsm.read() != CONFIG_DIR_INVAL) ) + (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK) ) { if(r_read_fsm.read() == READ_DIR_REQ) @@ -7189,6 +7451,6 @@ //////////////////////////////////////////////////////////////////////////////////// // The ALLOC_HEAP FSM allocates the access to the heap - // with a round robin priority between 5 user FSMs : - // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP + // with a round robin priority between 6 user FSMs : + // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP > CONFIG // The ressource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// @@ -7197,5 +7459,5 @@ { //////////////////// - case ALLOC_HEAP_RESET: + case ALLOC_HEAP_RESET: // Initializes the heap one ENTRY each cycle. @@ -7211,5 +7473,5 @@ //////////////////// - case ALLOC_HEAP_READ: + case ALLOC_HEAP_READ: if((r_read_fsm.read() != READ_HEAP_REQ) and (r_read_fsm.read() != READ_HEAP_LOCK) and @@ -7227,9 +7489,12 @@ else if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if(r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; } break; ///////////////////// - case ALLOC_HEAP_WRITE: + case ALLOC_HEAP_WRITE: if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and (r_write_fsm.read() != WRITE_UPT_REQ) and @@ -7245,4 +7510,7 @@ r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + else if(r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + else if(r_read_fsm.read() == READ_HEAP_REQ) r_alloc_heap_fsm = ALLOC_HEAP_READ; @@ -7251,5 +7519,5 @@ //////////////////// - case ALLOC_HEAP_CAS: + case ALLOC_HEAP_CAS: if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and (r_cas_fsm.read() != CAS_UPT_REQ) and @@ -7262,4 +7530,7 @@ r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + else if(r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + else if(r_read_fsm.read() == READ_HEAP_REQ) r_alloc_heap_fsm = ALLOC_HEAP_READ; @@ -7271,5 +7542,5 @@ /////////////////////// - case ALLOC_HEAP_CLEANUP: + case ALLOC_HEAP_CLEANUP: if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and @@ -7280,4 +7551,7 @@ r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + else if(r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + else if(r_read_fsm.read() == READ_HEAP_REQ) r_alloc_heap_fsm = ALLOC_HEAP_READ; @@ -7292,8 +7566,31 @@ //////////////////////// - case ALLOC_HEAP_XRAM_RSP: + case ALLOC_HEAP_XRAM_RSP: if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE)) { + if(r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if(r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if(r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + } + break; + + /////////////////////// + case ALLOC_HEAP_CONFIG: + if((r_config_fsm.read() != CONFIG_HEAP_REQ) and + (r_config_fsm.read() != CONFIG_HEAP_SCAN)) + { if(r_read_fsm.read() == READ_HEAP_REQ) r_alloc_heap_fsm = ALLOC_HEAP_READ; @@ -7308,4 +7605,6 @@ r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; } break; @@ -7332,99 +7631,43 @@ ///////////////////////////////////////////////////////////////////// - if(cmd_write_fifo_put) - { - if(cmd_write_fifo_get) - { - m_cmd_write_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read())); - m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read()); - m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read()); - m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read()); - m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read()); - m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read()); - m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read()); - } - else - { - m_cmd_write_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read())); - m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read()); - m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read()); - m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read()); - m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read()); - m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read()); - m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read()); - } - } - else - { - if(cmd_write_fifo_get) - { - m_cmd_write_addr_fifo.simple_get(); - m_cmd_write_eop_fifo.simple_get(); - m_cmd_write_srcid_fifo.simple_get(); - m_cmd_write_trdid_fifo.simple_get(); - m_cmd_write_pktid_fifo.simple_get(); - m_cmd_write_data_fifo.simple_get(); - m_cmd_write_be_fifo.simple_get(); - } - } + m_cmd_write_addr_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + (addr_t)p_vci_tgt.address.read() ); + m_cmd_write_eop_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.eop.read() ); + m_cmd_write_srcid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.srcid.read() ); + m_cmd_write_trdid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.trdid.read() ); + m_cmd_write_pktid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.pktid.read() ); + m_cmd_write_data_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.wdata.read() ); + m_cmd_write_be_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.be.read() ); + //////////////////////////////////////////////////////////////////////////////////// // TGT_CMD to CAS FIFO //////////////////////////////////////////////////////////////////////////////////// - if(cmd_cas_fifo_put) - { - if(cmd_cas_fifo_get) - { - m_cmd_cas_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read())); - m_cmd_cas_eop_fifo.put_and_get(p_vci_tgt.eop.read()); - m_cmd_cas_srcid_fifo.put_and_get(p_vci_tgt.srcid.read()); - m_cmd_cas_trdid_fifo.put_and_get(p_vci_tgt.trdid.read()); - m_cmd_cas_pktid_fifo.put_and_get(p_vci_tgt.pktid.read()); - m_cmd_cas_wdata_fifo.put_and_get(p_vci_tgt.wdata.read()); - } - else - { - m_cmd_cas_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read())); - m_cmd_cas_eop_fifo.simple_put(p_vci_tgt.eop.read()); - m_cmd_cas_srcid_fifo.simple_put(p_vci_tgt.srcid.read()); - m_cmd_cas_trdid_fifo.simple_put(p_vci_tgt.trdid.read()); - m_cmd_cas_pktid_fifo.simple_put(p_vci_tgt.pktid.read()); - m_cmd_cas_wdata_fifo.simple_put(p_vci_tgt.wdata.read()); - } - } - else - { - if(cmd_cas_fifo_get) - { - m_cmd_cas_addr_fifo.simple_get(); - m_cmd_cas_eop_fifo.simple_get(); - m_cmd_cas_srcid_fifo.simple_get(); - m_cmd_cas_trdid_fifo.simple_get(); - m_cmd_cas_pktid_fifo.simple_get(); - m_cmd_cas_wdata_fifo.simple_get(); - } - } + m_cmd_cas_addr_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + (addr_t)p_vci_tgt.address.read() ); + m_cmd_cas_eop_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.eop.read() ); + m_cmd_cas_srcid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.srcid.read() ); + m_cmd_cas_trdid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.trdid.read() ); + m_cmd_cas_pktid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.pktid.read() ); + m_cmd_cas_wdata_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.wdata.read() ); + //////////////////////////////////////////////////////////////////////////////////// // CC_RECEIVE to CLEANUP FIFO //////////////////////////////////////////////////////////////////////////////////// - if(cc_receive_to_cleanup_fifo_put) - { - if(cc_receive_to_cleanup_fifo_get) - { - m_cc_receive_to_cleanup_fifo.put_and_get(p_dspin_in.data.read()); - } - else - { - m_cc_receive_to_cleanup_fifo.simple_put(p_dspin_in.data.read()); - } - } - else - { - if(cc_receive_to_cleanup_fifo_get) - { - m_cc_receive_to_cleanup_fifo.simple_get(); - } - } + m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, + cc_receive_to_cleanup_fifo_put, + p_dspin_in.data.read() ); //////////////////////////////////////////////////////////////////////////////////// @@ -7432,22 +7675,7 @@ //////////////////////////////////////////////////////////////////////////////////// - if(cc_receive_to_multi_ack_fifo_put) - { - if(cc_receive_to_multi_ack_fifo_get) - { - m_cc_receive_to_multi_ack_fifo.put_and_get(p_dspin_in.data.read()); - } - else - { - m_cc_receive_to_multi_ack_fifo.simple_put(p_dspin_in.data.read()); - } - } - else - { - if(cc_receive_to_multi_ack_fifo_get) - { - m_cc_receive_to_multi_ack_fifo.simple_get(); - } - } + m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, + cc_receive_to_multi_ack_fifo_put, + p_dspin_in.data.read() ); //////////////////////////////////////////////////////////////////////////////////// @@ -7455,102 +7683,51 @@ //////////////////////////////////////////////////////////////////////////////////// - if(write_to_cc_send_fifo_put) - { - if(write_to_cc_send_fifo_get) - { - m_write_to_cc_send_inst_fifo.put_and_get(write_to_cc_send_fifo_inst); - m_write_to_cc_send_srcid_fifo.put_and_get(write_to_cc_send_fifo_srcid); + m_write_to_cc_send_inst_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, + write_to_cc_send_fifo_inst ); + m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, + write_to_cc_send_fifo_srcid ); #if L1_MULTI_CACHE - m_write_to_cc_send_cache_id_fifo.put_and_get(write_to_cc_send_fifo_cache_id); -#endif - } - else - { - m_write_to_cc_send_inst_fifo.simple_put(write_to_cc_send_fifo_inst); - m_write_to_cc_send_srcid_fifo.simple_put(write_to_cc_send_fifo_srcid); + m_write_to_cc_send_cache_id_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, + write_to_cc_send_fifo_cache_id ); +#endif + + //////////////////////////////////////////////////////////////////////////////////// + // CONFIG to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_config_to_cc_send_inst_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, + config_to_cc_send_fifo_inst ); + m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, + config_to_cc_send_fifo_srcid ); #if L1_MULTI_CACHE - m_write_to_cc_send_cache_id_fifo.simple_put(write_to_cc_send_fifo_cache_id); -#endif - } - } - else - { - if(write_to_cc_send_fifo_get) - { - m_write_to_cc_send_inst_fifo.simple_get(); - m_write_to_cc_send_srcid_fifo.simple_get(); -#if L1_MULTI_CACHE - m_write_to_cc_send_cache_id_fifo.simple_get(); -#endif - } - } + m_config_to_cc_send_cache_id_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, + config_to_cc_send_fifo_cache_id ); +#endif + //////////////////////////////////////////////////////////////////////////////////// // XRAM_RSP to CC_SEND FIFO //////////////////////////////////////////////////////////////////////////////////// - if(xram_rsp_to_cc_send_fifo_put) - { - if(xram_rsp_to_cc_send_fifo_get) - { - m_xram_rsp_to_cc_send_inst_fifo.put_and_get(xram_rsp_to_cc_send_fifo_inst); - m_xram_rsp_to_cc_send_srcid_fifo.put_and_get(xram_rsp_to_cc_send_fifo_srcid); + m_xram_rsp_to_cc_send_inst_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, + xram_rsp_to_cc_send_fifo_inst ); + m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, + xram_rsp_to_cc_send_fifo_srcid ); #if L1_MULTI_CACHE - m_xram_rsp_to_cc_send_cache_id_fifo.put_and_get(xram_rsp_to_cc_send_fifo_cache_id); -#endif - } - else - { - m_xram_rsp_to_cc_send_inst_fifo.simple_put(xram_rsp_to_cc_send_fifo_inst); - m_xram_rsp_to_cc_send_srcid_fifo.simple_put(xram_rsp_to_cc_send_fifo_srcid); -#if L1_MULTI_CACHE - m_xram_rsp_to_cc_send_cache_id_fifo.simple_put(xram_rsp_to_cc_send_fifo_cache_id); -#endif - } - } - else - { - if(xram_rsp_to_cc_send_fifo_get) - { - m_xram_rsp_to_cc_send_inst_fifo.simple_get(); - m_xram_rsp_to_cc_send_srcid_fifo.simple_get(); -#if L1_MULTI_CACHE - m_xram_rsp_to_cc_send_cache_id_fifo.simple_get(); -#endif - } - } + m_xram_rsp_to_cc_send_cache_id_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, + xram_rsp_to_cc_send_fifo_cache_id ); +#endif + //////////////////////////////////////////////////////////////////////////////////// // CAS to CC_SEND FIFO //////////////////////////////////////////////////////////////////////////////////// - if(cas_to_cc_send_fifo_put) - { - if(cas_to_cc_send_fifo_get) - { - m_cas_to_cc_send_inst_fifo.put_and_get(cas_to_cc_send_fifo_inst); - m_cas_to_cc_send_srcid_fifo.put_and_get(cas_to_cc_send_fifo_srcid); + m_cas_to_cc_send_inst_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, + cas_to_cc_send_fifo_inst ); + m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, + cas_to_cc_send_fifo_srcid ); #if L1_MULTI_CACHE - m_cas_to_cc_send_cache_id_fifo.put_and_get(cas_to_cc_send_fifo_cache_id); -#endif - } - else - { - m_cas_to_cc_send_inst_fifo.simple_put(cas_to_cc_send_fifo_inst); - m_cas_to_cc_send_srcid_fifo.simple_put(cas_to_cc_send_fifo_srcid); -#if L1_MULTI_CACHE - m_cas_to_cc_send_cache_id_fifo.simple_put(cas_to_cc_send_fifo_cache_id); -#endif - } - } - else - { - if(cas_to_cc_send_fifo_get) - { - m_cas_to_cc_send_inst_fifo.simple_get(); - m_cas_to_cc_send_srcid_fifo.simple_get(); -#if L1_MULTI_CACHE - m_cas_to_cc_send_cache_id_fifo.simple_get(); -#endif - } - } + m_cas_to_cc_send_cache_id_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, + cas_to_cc_send_fifo_cache_id ); +#endif m_cpt_cycles++; @@ -7675,4 +7852,5 @@ break; + case TGT_CMD_CONFIG: case TGT_CMD_ERROR: p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); @@ -7689,8 +7867,4 @@ case TGT_CMD_CAS: p_vci_tgt.cmdack = m_cmd_cas_addr_fifo.wok(); - break; - - default: - p_vci_tgt.cmdack = false; break; } @@ -7702,4 +7876,5 @@ switch(r_tgt_rsp_fsm.read()) { + case TGT_RSP_CONFIG_IDLE: case TGT_RSP_TGT_CMD_IDLE: case TGT_RSP_READ_IDLE: @@ -7709,4 +7884,5 @@ case TGT_RSP_MULTI_ACK_IDLE: case TGT_RSP_CLEANUP_IDLE: + { p_vci_tgt.rspval = false; p_vci_tgt.rsrcid = 0; @@ -7717,4 +7893,17 @@ p_vci_tgt.reop = false; break; + } + case TGT_RSP_CONFIG: + { + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_config_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_config_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_config_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = r_config_to_tgt_rsp_error.read(); + p_vci_tgt.reop = true; + + break; + } case TGT_RSP_TGT_CMD: @@ -7840,10 +8029,60 @@ { /////////////////////////// + case CC_SEND_CONFIG_IDLE: case CC_SEND_XRAM_RSP_IDLE: case CC_SEND_WRITE_IDLE: case CC_SEND_CAS_IDLE: case CC_SEND_CLEANUP_IDLE: + { break; - + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_HEADER: + { + uint8_t multi_inval_type; + if(m_config_to_cc_send_inst_fifo.read()) + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; + } + else + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; + } + + uint64_t flit = 0; + uint64_t dest = m_config_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( flit, + dest, + DspinDhccpParam::MULTI_INVAL_DEST); + + DspinDhccpParam::dspin_set( flit, + m_cc_global_id, + DspinDhccpParam::MULTI_INVAL_SRCID); + + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); + + DspinDhccpParam::dspin_set( flit, + multi_inval_type, + DspinDhccpParam::FROM_MC_TYPE); + p_dspin_out.write = true; + p_dspin_out.data = flit; + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_INVAL_NLINE); + p_dspin_out.eop = true; + p_dspin_out.write = true; + p_dspin_out.data = flit; + break; + } //////////////////////// case CC_SEND_CLEANUP_ACK: @@ -7889,9 +8128,9 @@ break; - } + } /////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_HEADER: - { + { if(not m_xram_rsp_to_cc_send_inst_fifo.rok()) break; @@ -7907,130 +8146,115 @@ uint64_t flit = 0; - uint64_t dest = - m_xram_rsp_to_cc_send_srcid_fifo.read() << - (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); - - DspinDhccpParam::dspin_set( - flit, - dest, - DspinDhccpParam::MULTI_INVAL_DEST); - - DspinDhccpParam::dspin_set( - flit, - m_cc_global_id, - DspinDhccpParam::MULTI_INVAL_SRCID); - - DspinDhccpParam::dspin_set( - flit, - r_xram_rsp_to_cc_send_trdid.read(), - DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); - - DspinDhccpParam::dspin_set( - flit, - multi_inval_type, - DspinDhccpParam::FROM_MC_TYPE); - + uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( flit, + dest, + DspinDhccpParam::MULTI_INVAL_DEST); + + DspinDhccpParam::dspin_set( flit, + m_cc_global_id, + DspinDhccpParam::MULTI_INVAL_SRCID); + + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); + + DspinDhccpParam::dspin_set( flit, + multi_inval_type, + DspinDhccpParam::FROM_MC_TYPE); p_dspin_out.write = true; p_dspin_out.data = flit; - break; - } + } ////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_NLINE: - { + { uint64_t flit = 0; - DspinDhccpParam::dspin_set( - flit, - r_xram_rsp_to_cc_send_nline.read(), - DspinDhccpParam::MULTI_INVAL_NLINE); - - + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_INVAL_NLINE); p_dspin_out.eop = true; p_dspin_out.write = true; p_dspin_out.data = flit; - break; - } + } ///////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_HEADER: case CC_SEND_XRAM_RSP_BRDCAST_HEADER: case CC_SEND_WRITE_BRDCAST_HEADER: case CC_SEND_CAS_BRDCAST_HEADER: - { + { uint64_t flit = 0; - DspinDhccpParam::dspin_set( - flit, - m_broadcast_boundaries, - DspinDhccpParam::BROADCAST_BOX); - - DspinDhccpParam::dspin_set( - flit, - m_cc_global_id, - DspinDhccpParam::BROADCAST_SRCID); - - DspinDhccpParam::dspin_set( - flit, - 1ULL, - DspinDhccpParam::FROM_MC_BC); - + DspinDhccpParam::dspin_set( flit, + m_broadcast_boundaries, + DspinDhccpParam::BROADCAST_BOX); + + DspinDhccpParam::dspin_set( flit, + m_cc_global_id, + DspinDhccpParam::BROADCAST_SRCID); + + DspinDhccpParam::dspin_set( flit, + 1ULL, + DspinDhccpParam::FROM_MC_BC); p_dspin_out.write = true; p_dspin_out.data = flit; - break; - } + } //////////////////////////////////// case CC_SEND_XRAM_RSP_BRDCAST_NLINE: - { + { uint64_t flit = 0; - - DspinDhccpParam::dspin_set( - flit, - r_xram_rsp_to_cc_send_nline.read(), - DspinDhccpParam::BROADCAST_NLINE); - + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); p_dspin_out.write = true; p_dspin_out.eop = true; p_dspin_out.data = flit; - break; - } - ///////////////////////////////// - case CC_SEND_WRITE_BRDCAST_NLINE: - { + } + ////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_NLINE: + { uint64_t flit = 0; - - DspinDhccpParam::dspin_set( - flit, - r_write_to_cc_send_nline.read(), - DspinDhccpParam::BROADCAST_NLINE); - + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); p_dspin_out.write = true; p_dspin_out.eop = true; p_dspin_out.data = flit; - break; - } - /////////////////////////////// - case CC_SEND_CAS_BRDCAST_NLINE: - { + } + ///////////////////////////////// + case CC_SEND_WRITE_BRDCAST_NLINE: + { uint64_t flit = 0; - - DspinDhccpParam::dspin_set( - flit, - r_cas_to_cc_send_nline.read(), - DspinDhccpParam::BROADCAST_NLINE); - + DspinDhccpParam::dspin_set( flit, + r_write_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); p_dspin_out.write = true; p_dspin_out.eop = true; p_dspin_out.data = flit; - break; - } + } + /////////////////////////////// + case CC_SEND_CAS_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_cas_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_out.write = true; + p_dspin_out.eop = true; + p_dspin_out.data = flit; + break; + } /////////////////////////////// case CC_SEND_WRITE_UPDT_HEADER: - { + { if(not m_write_to_cc_send_inst_fifo.rok()) break; @@ -8074,8 +8298,8 @@ break; - } + } ////////////////////////////// case CC_SEND_WRITE_UPDT_NLINE: - { + { uint64_t flit = 0; @@ -8094,8 +8318,8 @@ break; - } + } ///////////////////////////// case CC_SEND_WRITE_UPDT_DATA: - { + { uint8_t multi_updt_cpt = @@ -8122,8 +8346,8 @@ break; - } + } //////////////////////////// case CC_SEND_CAS_UPDT_HEADER: - { + { if (not m_cas_to_cc_send_inst_fifo.rok()) break; @@ -8167,8 +8391,8 @@ break; - } + } //////////////////////////// case CC_SEND_CAS_UPDT_NLINE: - { + { uint64_t flit = 0; @@ -8187,8 +8411,8 @@ break; - } + } /////////////////////////// case CC_SEND_CAS_UPDT_DATA: - { + { uint64_t flit = 0; @@ -8208,8 +8432,8 @@ break; - } + } //////////////////////////////// case CC_SEND_CAS_UPDT_DATA_HIGH: - { + { uint64_t flit = 0; @@ -8229,5 +8453,5 @@ break; - } + } }