Index: branches/v5/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd	(revision 367)
+++ branches/v5/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd	(revision 440)
@@ -9,6 +9,13 @@
 
         tmpl_parameters = [
-			parameter.Module('vci_param'  , default = 'caba:vci_param')
-		],
+            parameter.Module('vci_param_int', default = 'caba:vci_param',
+                cell_size = parameter.Reference('memc_cell_size_int')
+            ),
+            parameter.Module('vci_param_ext', default = 'caba:vci_param',
+                cell_size = parameter.Reference('memc_cell_size_ext')
+            ),
+            parameter.Int('dspin_in_width'),
+            parameter.Int('dspin_out_width'),
+        ],
 
         header_files = [
@@ -19,5 +26,11 @@
         ],
 
-        implementation_files = [ '../source/src/vci_mem_cache.cpp' ],
+        interface_files = [
+            '../../include/soclib/mem_cache.h', 
+        ],
+
+        implementation_files = [
+            '../source/src/vci_mem_cache.cpp'
+        ],
 
         uses = [
@@ -27,45 +40,34 @@
             Uses('caba:generic_fifo'),
             Uses('caba:generic_llsc_global_table'),
-			Uses('caba:dspin_dhccp_param')
+            Uses('caba:dspin_dhccp_param')
         ],
 
         ports = [
-            Port( 'caba:vci_target'   , 'p_vci_tgt' ),
-            Port(
-				'caba:dspin_input',
-				'p_dspin_in',
-				dspin_data_size = 33,
-			),
-			Port(
-				'caba:dspin_output',
-				'p_dspin_out',
-				dspin_data_size = 40,
-			),
-            Port( 'caba:vci_initiator', 'p_vci_ixr' ),
-            Port( 'caba:bit_in'       , 'p_resetn'  , auto = 'resetn' ),
-            Port( 'caba:clock_in'     , 'p_clk'     , auto = 'clock'  ),
+            Port('caba:clock_in'     , 'p_clk'      , auto = 'clock' ),
+            Port('caba:bit_in'       , 'p_resetn'   , auto = 'resetn'),
+            Port('caba:vci_target'   , 'p_vci_tgt'),
+            Port('caba:vci_initiator', 'p_vci_ixr'),
+            Port('caba:dspin_input',
+                'p_dspin_in',
+                dspin_data_size = parameter.Reference('dspin_in_width')
+            ),
+            Port('caba:dspin_output',
+                'p_dspin_out',
+                dspin_data_size = parameter.Reference('dspin_out_width')
+            ),
         ],
 
         instance_parameters = [
-            parameter.Module( 'mtp', 'common:mapping_table' ),
-            parameter.Module( 'mtc', 'common:mapping_table' ),
-            parameter.Module( 'mtx', 'common:mapping_table' ),
-            parameter.IntTab( 'vci_ixr_index' ),
-            parameter.IntTab( 'vci_ini_index' ),
-            parameter.IntTab( 'vci_tgt_index' ),
-            parameter.IntTab( 'vci_tgt_index_cleanup '),
-            parameter.Int   ( 'nways' ),
-            parameter.Int   ( 'nsets' ),
-            parameter.Int   ( 'nwords' ),
-            parameter.Int   ( 'heap_size' ),
-        ],
-
-        extensions = [
-            'dsx:get_ident='
-            'vci_ini_index:p_vci_ini:mtc,'
-            'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
-            'vci_tgt_index:p_vci_tgt:mtp,'
-            'vci_ixr_index:p_vci_ixr:mtx',
-            'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
+            parameter.Module('mtp', 'common:mapping_table'),
+            parameter.Module('mtc', 'common:mapping_table'),
+            parameter.Module('mtx', 'common:mapping_table'),
+            parameter.IntTab('vci_ixr_index'),
+            parameter.IntTab('vci_ini_index'),
+            parameter.IntTab('vci_tgt_index'),
+            parameter.IntTab('vci_tgt_index_cleanup'),
+            parameter.Int   ('nways'),
+            parameter.Int   ('nsets'),
+            parameter.Int   ('nwords'),
+            parameter.Int   ('heap_size'),
         ],
 )
Index: branches/v5/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 367)
+++ branches/v5/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 440)
@@ -40,5 +40,4 @@
   ////////////////////////////////////////////////////////////////////////
   class Owner{
-    typedef uint32_t size_t;
     
     public:
@@ -92,5 +91,4 @@
 
     typedef uint32_t tag_t;
-    typedef uint32_t size_t;
 
     public:
@@ -165,6 +163,8 @@
     void print()
     {
-      std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 
-                << lock 
+      std::cout << "Valid = " << valid 
+                << " ; IS COUNT = " << is_cnt 
+                << " ; Dirty = " << dirty 
+                << " ; Lock = " << lock 
                 << " ; Tag = " << std::hex << tag << std::dec 
                 << " ; Count = " << count 
@@ -187,5 +187,4 @@
     typedef uint32_t data_t;
     typedef uint32_t tag_t;
-    typedef uint32_t size_t;
 
     private:
@@ -275,4 +274,13 @@
 
     /////////////////////////////////////////////////////////////////////
+    // The inval function invalidate an entry defined by the set and
+    // way arguments. 
+    /////////////////////////////////////////////////////////////////////
+    void inval( const size_t &set, const size_t &way )
+    {
+        m_dir_tab[set][way].init();
+    }
+
+    /////////////////////////////////////////////////////////////////////
     // The read_neutral() function reads a directory entry, without
     // changing the LRU
@@ -321,11 +329,15 @@
       // update LRU bits
       bool all_recent = true;
-      for ( size_t i=0 ; i<m_ways ; i++ ) {
-        if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
-      }
-      if ( all_recent ) {
-        for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
-      } else {
-        m_lru_tab[set][way].recent = true;
+      for ( size_t i=0 ; i<m_ways ; i++ ) 
+      {
+          if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
+      }
+      if ( all_recent ) 
+      {
+          for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
+      } 
+      else 
+      {
+          m_lru_tab[set][way].recent = true;
       }
     } // end write()
@@ -408,5 +420,4 @@
   ///////////////////////////////////////////////////////////////////////
   class HeapEntry{
-    typedef uint32_t size_t;
 
     public:
@@ -472,5 +483,4 @@
   ////////////////////////////////////////////////////////////////////////
   class HeapDirectory{
-    typedef uint32_t size_t;
     
     private:
Index: branches/v5/modules/vci_mem_cache/caba/source/include/update_tab.h
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/source/include/update_tab.h	(revision 367)
+++ branches/v5/modules/vci_mem_cache/caba/source/include/update_tab.h	(revision 440)
@@ -11,12 +11,15 @@
 ////////////////////////////////////////////////////////////////////////
 class UpdateTabEntry {
+
   typedef uint32_t size_t;
   typedef sc_dt::sc_uint<40> addr_t;
 
   public:
+
   bool 	    valid;      // It is a valid pending transaction
   bool	    update;     // It is an update transaction
   bool      brdcast;    // It is a broadcast invalidate
-  bool      rsp;        // It needs a response to the initiator
+  bool      rsp;        // Response to the initiator required
+  bool      ack;        // Acknowledge to the CONFIG FSM required
   size_t 	srcid;      // The srcid of the initiator which wrote the data
   size_t 	trdid;      // The trdid of the initiator which wrote the data
@@ -25,9 +28,11 @@
   size_t 	count;      // The number of acknowledge responses to receive
 
-  UpdateTabEntry(){
+  UpdateTabEntry()
+  {
     valid	= false;
     update  = false;
     brdcast = false;
     rsp     = false;
+    ack     = false;
     srcid	= 0;
     trdid	= 0;
@@ -38,12 +43,13 @@
 
   UpdateTabEntry(bool   i_valid, 
-      bool   i_update,
-      bool   i_brdcast,
-      bool   i_rsp,
-      size_t i_srcid, 
-      size_t i_trdid, 
-      size_t i_pktid, 
-      addr_t i_nline,
-      size_t i_count) 
+                 bool   i_update,
+                 bool   i_brdcast,
+                 bool   i_rsp,
+                 bool   i_ack,
+                 size_t i_srcid, 
+                 size_t i_trdid, 
+                 size_t i_pktid, 
+                 addr_t i_nline,
+                 size_t i_count) 
   {
     valid	= i_valid;
@@ -51,4 +57,5 @@
     brdcast = i_brdcast;
     rsp     = i_rsp;
+    ack     = i_ack;
     srcid	= i_srcid;
     trdid	= i_trdid;
@@ -64,4 +71,5 @@
     brdcast = source.brdcast;
     rsp     = source.rsp;
+    ack     = source.ack;
     srcid   = source.srcid;
     trdid   = source.trdid;
@@ -80,4 +88,5 @@
     brdcast= false;
     rsp    = false;
+    ack    = false;
     srcid  = 0;
     trdid  = 0;
@@ -98,4 +107,5 @@
     brdcast= source.brdcast;
     rsp    = source.rsp;
+    ack    = source.ack  ;
     srcid  = source.srcid;
     trdid  = source.trdid;
@@ -108,14 +118,16 @@
   // The print() function prints the entry  
   ////////////////////////////////////////////////////////////////////
-  void print(){
-    std::cout << std::dec << "valid  = " << valid  << std::endl;
-    std::cout << "update = " << update << std::endl;
-    std::cout << "brdcast= " << brdcast<< std::endl;
-    std::cout << "rsp    = " << rsp    << std::endl;
-    std::cout << "srcid  = " << srcid  << std::endl; 
-    std::cout << "trdid  = " << trdid  << std::endl; 
-    std::cout << "pktid  = " << pktid  << std::endl; 
-    std::cout << std::hex << "nline  = " << nline  << std::endl;
-    std::cout << std::dec << "count  = " << count  << std::endl;
+  void print()
+  {
+    std::cout << " val = " << std::dec << valid 
+              << " / updt = " << update 
+              << " / bc = " << brdcast
+              << " / rsp = " << rsp 
+              << " / ack = " << ack   
+              << " / count = " << count
+              << " / srcid = " << std::hex << srcid 
+              << " / trdid = " << trdid   
+              << " / pktid = " << pktid
+              << " / nline = " << nline  << std::endl;
   }
 };
@@ -126,9 +138,8 @@
 class UpdateTab{
 
-  typedef uint32_t size_t;
-  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint64_t addr_t;
 
   private:
-  size_t size_tab;
+  size_t                      size_tab;
   std::vector<UpdateTabEntry> tab;
 
@@ -150,15 +161,18 @@
   // The size() function returns the size of the tab  
   ////////////////////////////////////////////////////////////////////
-  const size_t size(){
+  const size_t size()
+  {
     return size_tab;
   }
 
-
   ////////////////////////////////////////////////////////////////////
   // The print() function diplays the tab content 
   ////////////////////////////////////////////////////////////////////
-  void print(){
-    for(size_t i=0; i<size_tab; i++) {
-      std::cout << "UPDATE TAB ENTRY " << std::dec << i << "--------" << std::endl;
+  void print()
+  {
+    std::cout << "UPDATE TABLE Content" << std::endl;
+    for(size_t i=0; i<size_tab; i++) 
+    {
+      std::cout << "[" << std::dec << i << "] ";
       tab[i].print();
     }
@@ -166,14 +180,11 @@
   }
 
-
   /////////////////////////////////////////////////////////////////////
   // The init() function initializes the tab 
   /////////////////////////////////////////////////////////////////////
-  void init(){
-    for ( size_t i=0; i<size_tab; i++) {
-      tab[i].init();
-    }
-  }
-
+  void init()
+  {
+    for ( size_t i=0; i<size_tab; i++) tab[i].init();
+  }
 
   /////////////////////////////////////////////////////////////////////
@@ -201,19 +212,23 @@
   ///////////////////////////////////////////////////////////////////////////
   bool set(const bool	update,
-      const bool   brdcast,
-      const bool   rsp,
-      const size_t srcid,
-      const size_t trdid,
-      const size_t pktid,
-      const addr_t nline,
-      const size_t count,
-      size_t &index)
-  {
-    for ( size_t i=0 ; i<size_tab ; i++ ) {
-      if( !tab[i].valid ) {
+           const bool   brdcast,
+           const bool   rsp,
+           const bool   ack,
+           const size_t srcid,
+           const size_t trdid,
+           const size_t pktid,
+           const addr_t nline,
+           const size_t count,
+           size_t       &index)
+  {
+    for ( size_t i=0 ; i<size_tab ; i++ ) 
+    {
+      if( !tab[i].valid ) 
+      {
         tab[i].valid		= true;
         tab[i].update		= update;
         tab[i].brdcast      = brdcast;
         tab[i].rsp          = rsp;
+        tab[i].ack          = ack;
         tab[i].srcid		= (size_t) srcid;
         tab[i].trdid		= (size_t) trdid;
@@ -236,12 +251,15 @@
   /////////////////////////////////////////////////////////////////////
   bool decrement( const size_t index,
-      size_t &counter ) 
+                  size_t &counter ) 
   {
     assert((index<size_tab) && "Bad Update Tab Entry");
-    if ( tab[index].valid ) {
+    if ( tab[index].valid ) 
+    {
       tab[index].count--;
       counter = tab[index].count;
       return true;
-    } else {
+    } 
+    else 
+    {
       return false;
     }
@@ -253,8 +271,7 @@
   bool is_full()
   {
-    for(size_t i = 0 ; i < size_tab ; i++){
-      if(!tab[i].valid){
-        return false;
-      }
+    for(size_t i = 0 ; i < size_tab ; i++)
+    {
+      if(!tab[i].valid) return false;
     }
     return true;
@@ -266,6 +283,113 @@
   bool is_not_empty()
   {
-    for(size_t i = 0 ; i < size_tab ; i++){
-      if(tab[i].valid){
+    for(size_t i = 0 ; i < size_tab ; i++)
+    {
+      if(tab[i].valid) return true;
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The need_rsp() function returns the need of a response
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool need_rsp(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].rsp;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The need_ack() function returns the need of an acknowledge
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool need_ack(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].ack;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_brdcast() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_brdcast(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].brdcast;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_update(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].update;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The srcid() function returns the srcid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t srcid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].srcid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The trdid() function returns the trdid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t trdid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].trdid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The pktid() function returns the pktid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t pktid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].pktid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The nline() function returns the nline value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  addr_t nline(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].nline;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The search_inval() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool search_inval(const addr_t nline,size_t &index)
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++)
+    {
+      if ( (tab[i].nline == nline) and tab[i].valid and not tab[i].update )
+      {
+        index = i ;
         return true;
       }
@@ -275,111 +399,16 @@
 
   /////////////////////////////////////////////////////////////////////
-  // The need_rsp() function returns the need of a response
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  bool need_rsp(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].rsp;	
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The is_update() function returns the transaction type
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  bool is_brdcast(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].brdcast;	
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The is_update() function returns the transaction type
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  bool is_update(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].update;	
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The srcid() function returns the srcid value
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  size_t srcid(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].srcid;	
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The trdid() function returns the trdid value
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  size_t trdid(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].trdid;	
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The pktid() function returns the pktid value
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  size_t pktid(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].pktid;	
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The nline() function returns the nline value
-  // Arguments :
-  // - index : the index of the entry
-  /////////////////////////////////////////////////////////////////////
-  addr_t nline(const size_t index)
-  {
-    assert(index<size_tab && "Bad Update Tab Entry");
-    return tab[index].nline;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The search_inval() function returns the index of the entry in UPT
+  // The read_nline() function returns the index of the entry in UPT
   // Arguments :
   // - nline : the line number of the entry in the directory
   /////////////////////////////////////////////////////////////////////
-  bool search_inval(const addr_t nline,size_t &index)
+  bool read_nline(const addr_t nline,size_t &index) 
   {
     size_t i ;
 
-    for (i = 0 ; i < size_tab ; i++){
-      if((tab[i].nline == nline) && tab[i].valid){
-        if(!tab[i].update){
-          index = i ;
-          return true;
-        }
-      }
-    }
-    return false;
-  }
-
-  /////////////////////////////////////////////////////////////////////
-  // The read_nline() function returns the index of the entry in UPT
-  // Arguments :
-  // - nline : the line number of the entry in the directory
-  /////////////////////////////////////////////////////////////////////
-  bool read_nline(const addr_t nline,size_t &index) 
-  {
-    size_t i ;
-
-    for (i = 0 ; i < size_tab ; i++){
-      if((tab[i].nline == nline) && tab[i].valid){
+    for (i = 0 ; i < size_tab ; i++)
+    {
+      if ( (tab[i].nline == nline) and tab[i].valid )
+      {
         index = i ;
         return true;
Index: branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 367)
+++ branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 440)
@@ -52,59 +52,81 @@
 #include "dspin_dhccp_param.h"
 
-#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
-#define UPDATE_TAB_LINES      4 // Number of lines in the update tab
+#define TRT_ENTRIES      4      // Number of entries in TRT
+#define UPT_ENTRIES      4      // Number of entries in UPT
+#define HEAP_ENTRIES     1024   // Number of entries in HEAP
 
 namespace soclib {  namespace caba {
+
   using namespace sc_core;
 
-  template<typename vci_param>
+  template<typename vci_param_int, 
+           typename vci_param_ext,
+           size_t   dspin_in_width,
+           size_t   dspin_out_width>
     class VciMemCache
     : public soclib::caba::BaseModule
     {
-      typedef sc_dt::sc_uint<40> addr_t;
-      typedef typename vci_param::fast_addr_t vci_addr_t;
+      typedef typename vci_param_int::fast_addr_t  addr_t;
+
+      typedef typename sc_dt::sc_uint<64>          wide_data_t;
+
       typedef uint32_t data_t;
       typedef uint32_t tag_t;
-      typedef uint32_t size_t;
       typedef uint32_t be_t;
       typedef uint32_t copy_t;
 
       /* States of the TGT_CMD fsm */
-      enum tgt_cmd_fsm_state_e{
+      enum tgt_cmd_fsm_state_e
+      {
         TGT_CMD_IDLE,
+        TGT_CMD_ERROR,
         TGT_CMD_READ,
         TGT_CMD_WRITE,
-        TGT_CMD_CAS
+        TGT_CMD_CAS,
+        TGT_CMD_CONFIG
       };
 
       /* States of the TGT_RSP fsm */
-      enum tgt_rsp_fsm_state_e{
+      enum tgt_rsp_fsm_state_e
+      {
+        TGT_RSP_CONFIG_IDLE,
+        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_READ_IDLE,
         TGT_RSP_WRITE_IDLE,
         TGT_RSP_CAS_IDLE,
         TGT_RSP_XRAM_IDLE,
-        TGT_RSP_INIT_IDLE,
+        TGT_RSP_MULTI_ACK_IDLE,
         TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_CONFIG,
+        TGT_RSP_TGT_CMD,
         TGT_RSP_READ,
         TGT_RSP_WRITE,
         TGT_RSP_CAS,
         TGT_RSP_XRAM,
-        TGT_RSP_INIT,
+        TGT_RSP_MULTI_ACK,
         TGT_RSP_CLEANUP
       };
 
       /* States of the DSPIN_TGT fsm */
-      enum cc_receive_fsm_state_e{
+      enum cc_receive_fsm_state_e
+      {
         CC_RECEIVE_IDLE,
         CC_RECEIVE_CLEANUP,
+        CC_RECEIVE_CLEANUP_EOP,
         CC_RECEIVE_MULTI_ACK
       };
 
       /* States of the CC_SEND fsm */
-      enum cc_send_fsm_state_e{
+      enum cc_send_fsm_state_e
+      {
+        CC_SEND_CONFIG_IDLE,
         CC_SEND_XRAM_RSP_IDLE,
         CC_SEND_WRITE_IDLE,
         CC_SEND_CAS_IDLE,
         CC_SEND_CLEANUP_IDLE,
+        CC_SEND_CONFIG_INVAL_HEADER,
+        CC_SEND_CONFIG_INVAL_NLINE,
+        CC_SEND_CONFIG_BRDCAST_HEADER,
+        CC_SEND_CONFIG_BRDCAST_NLINE,
         CC_SEND_CLEANUP_ACK,
         CC_SEND_XRAM_RSP_BRDCAST_HEADER,
@@ -126,13 +148,34 @@
 
       /* States of the MULTI_ACK fsm */
-      enum multi_ack_fsm_state_e{
+      enum multi_ack_fsm_state_e
+      {
         MULTI_ACK_IDLE,
         MULTI_ACK_UPT_LOCK,
         MULTI_ACK_UPT_CLEAR,
-        MULTI_ACK_WRITE_RSP
+        MULTI_ACK_WRITE_RSP,
+        MULTI_ACK_CONFIG_ACK
+      };
+
+      /* States of the CONFIG fsm */
+      enum config_fsm_state_e
+      {
+        CONFIG_IDLE,
+        CONFIG_LOOP,
+        CONFIG_RSP,
+        CONFIG_DIR_REQ,
+        CONFIG_DIR_ACCESS,
+        CONFIG_DIR_UPT_LOCK,
+        CONFIG_BC_SEND,
+        CONFIG_BC_WAIT,
+        CONFIG_INV_SEND,
+        CONFIG_HEAP_REQ,
+        CONFIG_HEAP_SCAN,
+        CONFIG_HEAP_LAST,
+        CONFIG_INV_WAIT
       };
 
       /* States of the READ fsm */
-      enum read_fsm_state_e{
+      enum read_fsm_state_e
+      {
         READ_IDLE,
         READ_DIR_REQ,
@@ -151,5 +194,6 @@
 
       /* States of the WRITE fsm */
-      enum write_fsm_state_e{
+      enum write_fsm_state_e
+      {
         WRITE_IDLE,
         WRITE_NEXT,
@@ -177,5 +221,6 @@
 
       /* States of the IXR_RSP fsm */
-      enum ixr_rsp_fsm_state_e{
+      enum ixr_rsp_fsm_state_e
+      {
         IXR_RSP_IDLE,
         IXR_RSP_ACK,
@@ -185,5 +230,6 @@
 
       /* States of the XRAM_RSP fsm */
-      enum xram_rsp_fsm_state_e{
+      enum xram_rsp_fsm_state_e
+      {
         XRAM_RSP_IDLE,
         XRAM_RSP_TRT_COPY,
@@ -204,17 +250,19 @@
 
       /* States of the IXR_CMD fsm */
-      enum ixr_cmd_fsm_state_e{
+      enum ixr_cmd_fsm_state_e
+      {
         IXR_CMD_READ_IDLE,
         IXR_CMD_WRITE_IDLE,
         IXR_CMD_CAS_IDLE,
         IXR_CMD_XRAM_IDLE,
-        IXR_CMD_READ_NLINE,
-        IXR_CMD_WRITE_NLINE,
-        IXR_CMD_CAS_NLINE,
-        IXR_CMD_XRAM_DATA
+        IXR_CMD_READ,
+        IXR_CMD_WRITE,
+        IXR_CMD_CAS,
+        IXR_CMD_XRAM
       };
 
       /* States of the CAS fsm */
-      enum cas_fsm_state_e{
+      enum cas_fsm_state_e
+      {
         CAS_IDLE,
         CAS_DIR_REQ,
@@ -241,5 +289,6 @@
 
       /* States of the CLEANUP fsm */
-      enum cleanup_fsm_state_e{
+      enum cleanup_fsm_state_e
+      {
         CLEANUP_IDLE,
         CLEANUP_GET_NLINE,
@@ -256,10 +305,13 @@
         CLEANUP_UPT_CLEAR,
         CLEANUP_WRITE_RSP,
-        CLEANUP_SEND_ACK
+        CLEANUP_CONFIG_ACK,
+        CLEANUP_SEND_CLACK
       };
 
       /* States of the ALLOC_DIR fsm */
-      enum alloc_dir_fsm_state_e{
+      enum alloc_dir_fsm_state_e
+      {
         ALLOC_DIR_RESET,
+        ALLOC_DIR_CONFIG,
         ALLOC_DIR_READ,
         ALLOC_DIR_WRITE,
@@ -270,5 +322,6 @@
 
       /* States of the ALLOC_TRT fsm */
-      enum alloc_trt_fsm_state_e{
+      enum alloc_trt_fsm_state_e
+      {
         ALLOC_TRT_READ,
         ALLOC_TRT_WRITE,
@@ -279,5 +332,7 @@
 
       /* States of the ALLOC_UPT fsm */
-      enum alloc_upt_fsm_state_e{
+      enum alloc_upt_fsm_state_e
+      {
+        ALLOC_UPT_CONFIG,
         ALLOC_UPT_WRITE,
         ALLOC_UPT_XRAM_RSP,
@@ -288,5 +343,6 @@
 
       /* States of the ALLOC_HEAP fsm */
-      enum alloc_heap_fsm_state_e{
+      enum alloc_heap_fsm_state_e
+      {
         ALLOC_HEAP_RESET,
         ALLOC_HEAP_READ,
@@ -294,5 +350,6 @@
         ALLOC_HEAP_CAS,
         ALLOC_HEAP_CLEANUP,
-        ALLOC_HEAP_XRAM_RSP
+        ALLOC_HEAP_XRAM_RSP,
+        ALLOC_HEAP_CONFIG
       };
 
@@ -325,30 +382,35 @@
       };
 
+      /* Configuration commands */
+      enum cmd_config_type_e
+      {
+          CMD_CONFIG_INVAL = 0,
+          CMD_CONFIG_SYNC  = 1
+      };
+
       // debug variables (for each FSM)
-      bool         m_debug_global;
-      bool         m_debug_tgt_cmd_fsm;
-      bool         m_debug_tgt_rsp_fsm;
-      bool         m_debug_cc_send_fsm;
-      bool         m_debug_cc_receive_fsm;
-      bool         m_debug_multi_ack_fsm;
-      bool         m_debug_read_fsm;
-      bool         m_debug_write_fsm;
-      bool         m_debug_cas_fsm;
-      bool         m_debug_cleanup_fsm;
-      bool         m_debug_ixr_cmd_fsm;
-      bool         m_debug_ixr_rsp_fsm;
-      bool         m_debug_xram_rsp_fsm;
+      bool         m_debug;
       bool         m_debug_previous_hit;
       size_t       m_debug_previous_count;
 
       bool         m_monitor_ok;
-      vci_addr_t   m_monitor_base;
-      vci_addr_t   m_monitor_length;
+      addr_t       m_monitor_base;
+      addr_t       m_monitor_length;
 
       // instrumentation counters
       uint32_t     m_cpt_cycles;        // Counter of cycles
+
       uint32_t     m_cpt_read;          // Number of READ transactions
+      uint32_t     m_cpt_read_remote;   // number of remote READ transactions
+      uint32_t     m_cpt_read_flits;    // number of flits for READs
+      uint32_t     m_cpt_read_cost;     // Number of (flits * distance) for READs
+
       uint32_t     m_cpt_read_miss;     // Number of MISS READ
+
       uint32_t     m_cpt_write;         // Number of WRITE transactions
+      uint32_t     m_cpt_write_remote;  // number of remote WRITE transactions
+      uint32_t     m_cpt_write_flits;   // number of flits for WRITEs
+      uint32_t     m_cpt_write_cost;    // Number of (flits * distance) for WRITEs
+
       uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
       uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
@@ -366,4 +428,15 @@
       uint32_t     m_cpt_cas;           // Number of CAS transactions
 
+      uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
+
+      uint32_t     m_cpt_update_flits;  // Number of flits for UPDATEs
+      uint32_t     m_cpt_update_cost;   // Number of (flits * distance) for UPDATEs
+
+      uint32_t     m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
+
+      uint32_t     m_cpt_get;
+
+      uint32_t     m_cpt_put;
+
       size_t       m_prev_count;
 
@@ -373,25 +446,25 @@
 
       public:
-      sc_in<bool>                           p_clk;
-      sc_in<bool>                           p_resetn;
-      soclib::caba::VciTarget<vci_param>    p_vci_tgt;
-      soclib::caba::VciInitiator<vci_param> p_vci_ixr;
-      soclib::caba::DspinInput<33>          p_dspin_in;
-      soclib::caba::DspinOutput<40>         p_dspin_out;
+      sc_in<bool>                                 p_clk;
+      sc_in<bool>                                 p_resetn;
+      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
+      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
+      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
+      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
 
       VciMemCache(
           sc_module_name name,                                // Instance Name
-          const soclib::common::MappingTable &mtp,            // Mapping table for direct network
-          const soclib::common::MappingTable &mtx,            // Mapping table for external network
-          const soclib::common::IntTab       &srcid_x,        // global index on external network
-          const soclib::common::IntTab       &tgtid_d,        // global index on direct network
-          const size_t                       cc_global_id,    // global index on cc network
+          const soclib::common::MappingTable &mtp,            // Mapping table INT network
+          const soclib::common::MappingTable &mtx,            // Mapping table RAM network
+          const soclib::common::IntTab       &srcid_x,        // global index RAM network
+          const soclib::common::IntTab       &tgtid_d,        // global index INT network
+          const size_t                       cc_global_id,    // global index CC network
           const size_t                       nways,           // Number of ways per set
           const size_t                       nsets,           // Number of sets
           const size_t                       nwords,          // Number of words per line
-          const size_t                       max_copies,      // max number of copies in heap
-          const size_t                       heap_size=1024,  // number of heap entries
-          const size_t                       trt_lines=TRANSACTION_TAB_LINES, 
-          const size_t                       upt_lines=UPDATE_TAB_LINES,       
+          const size_t                       max_copies,      // max number of copies
+          const size_t                       heap_size=HEAP_ENTRIES,
+          const size_t                       trt_lines=TRT_ENTRIES, 
+          const size_t                       upt_lines=UPT_ENTRIES,     
           const size_t                       debug_start_cycle=0,
           const bool                         debug_ok=false );
@@ -401,6 +474,6 @@
       void print_stats();
       void print_trace();
-      void copies_monitor(vci_addr_t addr);
-      void start_monitor(vci_addr_t addr, vci_addr_t length);
+      void copies_monitor(addr_t addr);
+      void start_monitor(addr_t addr, addr_t length);
       void stop_monitor();
 
@@ -409,12 +482,12 @@
       void transition();
       void genMoore();
-      void check_monitor( const char *buf, vci_addr_t addr, data_t data);
-      void check_monitor_read( const char *buf, vci_addr_t addr);
+      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
 
       // Component attributes
-      std::list<soclib::common::Segment> m_seglist;          // segments allocated to memcache
+      std::list<soclib::common::Segment> m_seglist;          // segments allocated 
       size_t                             m_nseg;             // number of segments
       soclib::common::Segment            **m_seg;            // array of segments pointers
-      const size_t                       m_srcid_x;          // global index on external network
+      size_t                             m_seg_config;       // config segment index
+      const size_t                       m_srcid_x;          // global index on RAM network
       const size_t                       m_initiators;       // Number of initiators
       const size_t                       m_heap_size;        // Size of the heap
@@ -434,18 +507,17 @@
       size_t                             m_max_copies;       // max number of copies in heap
       GenericLLSCGlobalTable
-      < 32  ,                              // number of slots
-        4096,                              // number of processors in the system
-        8000,                              // registratioÃ§n life span (in # of LL operations)
-        typename vci_param::fast_addr_t >  // address type
-                                         m_llsc_table;       // ll/sc global registration table
+      < 32  ,    // number of slots
+        4096,    // number of processors in the system
+        8000,    // registration life (# of LL operations)
+        addr_t >                         m_llsc_table;       // ll/sc registration table
 
       // adress masks
-      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
-      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
-      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
-      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline;
+      const soclib::common::AddressMaskingTable<addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
 
       // broadcast address
-      uint32_t                                                m_broadcast_address;
+      uint32_t                           m_broadcast_boundaries;
 
       //////////////////////////////////////////////////
@@ -453,6 +525,8 @@
       //////////////////////////////////////////////////
 
+      sc_signal<int>         r_tgt_cmd_fsm;
+
       // Fifo between TGT_CMD fsm and READ fsm
-      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
+      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
       GenericFifo<size_t>    m_cmd_read_length_fifo;
       GenericFifo<size_t>    m_cmd_read_srcid_fifo;
@@ -461,5 +535,5 @@
 
       // Fifo between TGT_CMD fsm and WRITE fsm
-      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
+      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
       GenericFifo<bool>      m_cmd_write_eop_fifo;
       GenericFifo<size_t>    m_cmd_write_srcid_fifo;
@@ -470,5 +544,5 @@
 
       // Fifo between TGT_CMD fsm and CAS fsm
-      GenericFifo<uint64_t>  m_cmd_cas_addr_fifo;
+      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
       GenericFifo<bool>      m_cmd_cas_eop_fifo;
       GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
@@ -477,11 +551,63 @@
       GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
 
-      // Fifo between INIT_RSP fsm and CLEANUP fsm
+      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
       GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
       
-      // Fifo between INIT_RSP fsm and MULTI_ACK fsm
+      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
       GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
 
-      sc_signal<int>         r_tgt_cmd_fsm;
+      // Buffer between TGT_CMD fsm and TGT_RSP fsm
+      // (segmentation violation response request)
+      sc_signal<bool>     r_tgt_cmd_to_tgt_rsp_req;
+
+      sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
+      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_error;
+      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_srcid;
+      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_trdid;
+      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_pktid;
+
+      sc_signal<addr_t>   r_tgt_cmd_config_addr;
+      sc_signal<size_t>   r_tgt_cmd_config_cmd;
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by the CONFIG fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>      r_config_fsm;            // FSM state
+      sc_signal<bool>     r_config_lock;           // lock protecting exclusive access
+      sc_signal<int>      r_config_cmd;            // config request status
+      sc_signal<addr_t>   r_config_address;        // target buffer physical address
+      sc_signal<size_t>   r_config_srcid;          // config request srcid
+      sc_signal<size_t>   r_config_trdid;          // config request trdid
+      sc_signal<size_t>   r_config_pktid;          // config request pktid
+      sc_signal<size_t>   r_config_nlines;         // number of lines covering the buffer
+      sc_signal<size_t>   r_config_dir_way;        // DIR: selected way
+      sc_signal<size_t>   r_config_dir_count;      // DIR: number of copies
+      sc_signal<bool>     r_config_dir_is_cnt;     // DIR: counter mode (broadcast required)
+      sc_signal<size_t>   r_config_dir_copy_srcid; // DIR: first copy SRCID
+      sc_signal<bool>     r_config_dir_copy_inst;  // DIR: first copy L1 type
+      sc_signal<size_t>   r_config_dir_next_ptr;   // DIR: index of next copy in HEAP
+      sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
+
+      sc_signal<size_t>   r_config_upt_index;  // UPT index
+
+      // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
+      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
+      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
+      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
+      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
+      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
+
+      // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
+      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
+      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
+      sc_signal<addr_t>   r_config_to_cc_send_nline;        // line index
+      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
+      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;    // fifo for the L1 type
+      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
+
+#if L1_MULTI_CACHE
+      GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
+#endif
 
       ///////////////////////////////////////////////////////
@@ -489,21 +615,20 @@
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_read_fsm;        // FSM state
-      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
-      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
-      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
-      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
-      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
-      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
-      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
-      sc_signal<size_t>   r_read_count;      // number of copies
-      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
-      sc_signal<data_t> * r_read_data;       // data (one cache line)
-      sc_signal<size_t>   r_read_way;        // associative way (in cache)
-      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
-      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
-      sc_signal<bool>     r_read_last_free;  // Last free entry
-      sc_signal<typename vci_param::fast_addr_t>
-                          r_read_ll_key;     // LL key returned by the llsc_global_table
+      sc_signal<int>      r_read_fsm;          // FSM state
+      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
+      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
+      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
+      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
+      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
+      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
+      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
+      sc_signal<size_t>   r_read_count;        // number of copies
+      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
+      sc_signal<data_t> * r_read_data;         // data (one cache line)
+      sc_signal<size_t>   r_read_way;          // associative way (in cache)
+      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
+      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
+      sc_signal<bool>     r_read_last_free;    // Last free entry
+      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
 
       // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
@@ -520,6 +645,5 @@
       sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
       sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
-      sc_signal<typename vci_param::fast_addr_t>
-                          r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
+      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
 
       ///////////////////////////////////////////////////////////////
@@ -578,4 +702,5 @@
       GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
       GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
+
 #if L1_MULTI_CACHE
       GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
@@ -596,4 +721,7 @@
       sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
       sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
+
+      // signaling completion of multi-inval to CONFIG fsm
+      sc_signal<bool>     r_multi_ack_to_config_ack; 
 
       // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
@@ -633,11 +761,16 @@
       sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
 
-      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write response
+      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write rsp
       sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
       sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
-      sc_signal<bool>     r_cleanup_write_need_rsp;// needs a write rsp
+
+      sc_signal<bool>     r_cleanup_need_rsp;      // write response required
+      sc_signal<bool>     r_cleanup_need_ack;      // config acknowledge required
 
       sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
 
+      // signaling completion of broadcast-inval to CONFIG fsm
+      sc_signal<bool>     r_cleanup_to_config_ack;  
+       
       // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
       sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
@@ -703,4 +836,5 @@
       GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
       GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
+
 #if L1_MULTI_CACHE
       GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
@@ -749,6 +883,5 @@
       sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
       sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
-      sc_signal<typename vci_param::fast_addr_t>
-                          r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
+      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
 
       // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
@@ -759,4 +892,5 @@
       GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
       GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
+
 #if L1_MULTI_CACHE
       GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
Index: branches/v5/modules/vci_mem_cache/caba/source/include/xram_transaction.h
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/source/include/xram_transaction.h	(revision 367)
+++ branches/v5/modules/vci_mem_cache/caba/source/include/xram_transaction.h	(revision 440)
@@ -13,8 +13,9 @@
 ////////////////////////////////////////////////////////////////////////
 
-class TransactionTabEntry {
-    typedef uint32_t              size_t;
+class TransactionTabEntry 
+{
+    typedef sc_dt::sc_uint<64>    wide_data_t;
+    typedef sc_dt::sc_uint<40>    addr_t;
     typedef uint32_t              data_t;
-    typedef sc_dt::sc_uint<40>    addr_t;
     typedef uint32_t              be_t;
 
@@ -84,5 +85,6 @@
     // The print() function prints the entry 
     ////////////////////////////////////////////////////////////////////
-    void print(){
+    void print()
+    {
         std::cout << "valid       = " << valid        << std::endl;
         std::cout << "xram_read   = " << xram_read    << std::endl;
@@ -137,12 +139,14 @@
 //                  The transaction tab                              
 ////////////////////////////////////////////////////////////////////////
-class TransactionTab{
-    typedef uint32_t size_t;
-    typedef uint32_t data_t;
-    typedef sc_dt::sc_uint<40> addr_t;
-    typedef uint32_t be_t;
+class TransactionTab
+{
+    typedef sc_dt::sc_uint<64>    wide_data_t;
+    typedef sc_dt::sc_uint<40>    addr_t;
+    typedef uint32_t              data_t;
+    typedef uint32_t              be_t;
 
     private:
-    size_t size_tab;                // The size of the tab
+    const std::string tab_name;                // the name for logs
+    size_t            size_tab;                // the size of the tab
 
     data_t be_to_mask(be_t be)
@@ -176,9 +180,13 @@
     }
 
-    TransactionTab(size_t n_entries, size_t n_words)
-    {
-        size_tab = n_entries;
+    TransactionTab(const std::string &name,
+                   size_t            n_entries, 
+                   size_t            n_words )
+    : tab_name( name ),
+      size_tab( n_entries ) 
+    {
         tab = new TransactionTabEntry[size_tab];
-        for ( size_t i=0; i<size_tab; i++) {
+        for ( size_t i=0; i<size_tab; i++) 
+        {
             tab[i].alloc(n_words);
         }
@@ -368,29 +376,57 @@
 
     /////////////////////////////////////////////////////////////////////
-    // The write_rsp() function writes a word of the response to an 
-    // XRAM read transaction.
+    // The write_rsp() function writes two 32 bits words of the response 
+    // to a XRAM read transaction.
     // The BE field in TRT is taken into account.
     // Arguments :
     // - index : the index of the transaction in the transaction tab
     // - word_index : the index of the data in the line
-    // - data : the data to write
+    // - data : a 64 bits value
     // - error : invalid data
     /////////////////////////////////////////////////////////////////////
-    void write_rsp(const size_t index,
-            const size_t word,
-            const data_t data,
-            const bool   rerror)
-    {
-        assert( (index < size_tab) 
-                && "Selected entry  out of range in write_rsp() Transaction Tab");
-        assert( (word <= tab[index].wdata_be.size()) 
-                && "Bad word_index in write_rsp() in TransactionTab");
-        assert( tab[index].valid 
-                && "Transaction Tab Entry invalid in write_rsp()");
-        assert( tab[index].xram_read 
-                && "Selected entry is not an XRAM read transaction in write_rsp()");
-
-        data_t mask = be_to_mask(tab[index].wdata_be[word]);
-        tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+    void write_rsp(const size_t      index,
+                   const size_t      word,
+                   const wide_data_t data,
+                   const bool        rerror)
+    {
+        data_t  value;
+        data_t  mask;
+
+        if ( index >= size_tab )
+        { 
+            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
+                      <<  " TRT entry  out of range in write_rsp()" << std::endl;
+            exit(0);
+        }
+        if ( word > tab[index].wdata_be.size() ) 
+        { 
+            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
+                      <<  " Bad word_index in write_rsp() in TRT" << std::endl;
+            exit(0);
+        }
+        if ( not tab[index].valid )
+        { 
+            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
+                      <<  " TRT Entry invalid in write_rsp()" << std::endl;
+            exit(0);
+        }
+        if ( not tab[index].xram_read )
+        { 
+            std::cout << "VCI_MEM_CACHE ERRROR " << tab_name
+                      <<  " TRT entry is not an XRAM GET in write_rsp()" << std::endl;
+            exit(0);
+        }
+
+        // first 32 bits word
+        value = (data_t)data;
+        mask  = be_to_mask(tab[index].wdata_be[word]);
+        tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (value & ~mask);
+
+        // second 32 bits word
+        value = (data_t)(data>>32);
+        mask  = be_to_mask(tab[index].wdata_be[word+1]);
+        tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask);
+
+        // error update
         tab[index].rerror |= rerror;
     }
Index: branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 367)
+++ branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 440)
@@ -26,5 +26,6 @@
 * SOCLIB_LGPL_HEADER_END
 *
-* Maintainers: alain eric.guthmuller@polytechnique.edu
+* Maintainers: alain.greiner@lip6.fr
+*              eric.guthmuller@polytechnique.edu
 *              cesar.fuguet-tortolero@lip6.fr
 *              alexandre.joannou@lip6.fr
@@ -33,51 +34,54 @@
 #include "../include/vci_mem_cache.h"
 
-//////   debug services   ///////////////////////////////////////////////////////
+//////   debug services   /////////////////////////////////////////////////////////////
 // All debug messages are conditionned by two variables:
 // - compile time   : DEBUG_MEMC_*** : defined below
-// - execution time : m_debug_***    : defined by constructor arguments
-//    m_debug_* = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle)
-/////////////////////////////////////////////////////////////////////////////////
-
-#define DEBUG_MEMC_GLOBAL   0 // synthetic trace of all FSMs
-#define DEBUG_MEMC_READ     1 // detailed trace of READ FSM
-#define DEBUG_MEMC_WRITE    1 // detailed trace of WRITE FSM
-#define DEBUG_MEMC_CAS      1 // detailed trace of CAS FSM
-#define DEBUG_MEMC_IXR_CMD  1 // detailed trace of IXR_RSP FSM
-#define DEBUG_MEMC_IXR_RSP  1 // detailed trace of IXR_RSP FSM
-#define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM
-#define DEBUG_MEMC_CC_SEND 1 // detailed trace of CC_SEND FSM
+// - execution time : m_debug  = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle)
+///////////////////////////////////////////////////////////////////////////////////////
+
+#define DEBUG_MEMC_GLOBAL    0 // synthetic trace of all FSMs
+#define DEBUG_MEMC_CONFIG    1 // detailed trace of CONFIG FSM
+#define DEBUG_MEMC_READ      1 // detailed trace of READ FSM
+#define DEBUG_MEMC_WRITE     1 // detailed trace of WRITE FSM
+#define DEBUG_MEMC_CAS       1 // detailed trace of CAS FSM
+#define DEBUG_MEMC_IXR_CMD   1 // detailed trace of IXR_RSP FSM
+#define DEBUG_MEMC_IXR_RSP   1 // detailed trace of IXR_RSP FSM
+#define DEBUG_MEMC_XRAM_RSP  1 // detailed trace of XRAM_RSP FSM
+#define DEBUG_MEMC_CC_SEND   1 // detailed trace of CC_SEND FSM
 #define DEBUG_MEMC_MULTI_ACK 1 // detailed trace of MULTI_ACK FSM
-#define DEBUG_MEMC_TGT_CMD  1 // detailed trace of TGT_CMD FSM
-#define DEBUG_MEMC_TGT_RSP  1 // detailed trace of TGT_RSP FSM
-#define DEBUG_MEMC_CLEANUP  1 // detailed trace of CLEANUP FSM
-
-#define RANDOMIZE_CAS       1
-
-namespace soclib
-{
-namespace caba
-{
+#define DEBUG_MEMC_TGT_CMD   1 // detailed trace of TGT_CMD FSM
+#define DEBUG_MEMC_TGT_RSP   1 // detailed trace of TGT_RSP FSM
+#define DEBUG_MEMC_CLEANUP   1 // detailed trace of CLEANUP FSM
+
+#define RANDOMIZE_CAS        1
+
+namespace soclib { namespace caba {
 
 const char *tgt_cmd_fsm_str[] =
 {
   "TGT_CMD_IDLE",
+  "TGT_CMD_ERROR",
   "TGT_CMD_READ",
   "TGT_CMD_WRITE",
-  "TGT_CMD_CAS"
+  "TGT_CMD_CAS",
+  "TGT_CMD_CONFIG"
 };
 const char *tgt_rsp_fsm_str[] =
 {
+  "TGT_RSP_CONFIG_IDLE",
+  "TGT_RSP_TGT_CMD_IDLE",
   "TGT_RSP_READ_IDLE",
   "TGT_RSP_WRITE_IDLE",
   "TGT_RSP_CAS_IDLE",
   "TGT_RSP_XRAM_IDLE",
-  "TGT_RSP_INIT_IDLE",
+  "TGT_RSP_MULTI_ACK_IDLE",
   "TGT_RSP_CLEANUP_IDLE",
+  "TGT_RSP_CONFIG",
+  "TGT_RSP_TGT_CMD",
   "TGT_RSP_READ",
   "TGT_RSP_WRITE",
   "TGT_RSP_CAS",
   "TGT_RSP_XRAM",
-  "TGT_RSP_INIT",
+  "TGT_RSP_MULTI_ACK",
   "TGT_RSP_CLEANUP"
 };
@@ -86,12 +90,18 @@
   "CC_RECEIVE_IDLE",
   "CC_RECEIVE_CLEANUP",
+  "CC_RECEIVE_CLEANUP_EOP",
   "CC_RECEIVE_MULTI_ACK"
 };
 const char *cc_send_fsm_str[] =
 {
+  "CC_SEND_CONFIG_IDLE",
   "CC_SEND_XRAM_RSP_IDLE",
   "CC_SEND_WRITE_IDLE",
   "CC_SEND_CAS_IDLE",
   "CC_SEND_CLEANUP_IDLE",
+  "CC_SEND_CONFIG_INVAL_HEADER",
+  "CC_SEND_CONFIG_INVAL_NLINE",
+  "CC_SEND_CONFIG_BRDCAST_HEADER",
+  "CC_SEND_CONFIG_BRDCAST_NLINE",
   "CC_SEND_CLEANUP_ACK",
   "CC_SEND_XRAM_RSP_BRDCAST_HEADER",
@@ -116,5 +126,22 @@
   "MULTI_ACK_UPT_LOCK",
   "MULTI_ACK_UPT_CLEAR",
-  "MULTI_ACK_WRITE_RSP"
+  "MULTI_ACK_WRITE_RSP",
+  "MULTI_ACK_CONFIG_ACK"
+};
+const char *config_fsm_str[] =
+{
+  "CONFIG_IDLE",
+  "CONFIG_LOOP",
+  "CONFIG_RSP",
+  "CONFIG_DIR_REQ",
+  "CONFIG_DIR_ACCESS",
+  "CONFIG_DIR_UPT_LOCK",
+  "CONFIG_BC_SEND",
+  "CONFIG_BC_WAIT",
+  "CONFIG_INV_SEND",
+  "CONFIG_HEAP_REQ",
+  "CONFIG_HEAP_SCAN",
+  "CONFIG_HEAP_LAST",
+  "CONFIG_INV_WAIT"
 };
 const char *read_fsm_str[] =
@@ -190,8 +217,8 @@
   "IXR_CMD_CAS_IDLE",
   "IXR_CMD_XRAM_IDLE",
-  "IXR_CMD_READ_NLINE",
-  "IXR_CMD_WRITE_NLINE",
-  "IXR_CMD_CAS_NLINE",
-  "IXR_CMD_XRAM_DATA"
+  "IXR_CMD_READ",
+  "IXR_CMD_WRITE",
+  "IXR_CMD_CAS",
+  "IXR_CMD_XRAM"
 };
 const char *cas_fsm_str[] =
@@ -235,5 +262,6 @@
   "CLEANUP_UPT_CLEAR",
   "CLEANUP_WRITE_RSP",
-  "CLEANUP_SEND_ACK"
+  "CLEANUP_CONFIG_ACK",
+  "CLEANUP_SEND_CLACK"
 };
 const char *alloc_dir_fsm_str[] =
@@ -269,10 +297,14 @@
   "ALLOC_HEAP_CAS",
   "ALLOC_HEAP_CLEANUP",
-  "ALLOC_HEAP_XRAM_RSP"
+  "ALLOC_HEAP_XRAM_RSP",
+  "ALLOC_HEAP_CONFIG"
 };
 
 #define tmpl(x) \
-  template<typename vci_param> x \
-  VciMemCache<vci_param>
+  template<typename vci_param_int, \
+           typename vci_param_ext, \
+           size_t dspin_in_width,  \
+           size_t dspin_out_width> x \
+  VciMemCache<vci_param_int, vci_param_ext, dspin_in_width, dspin_out_width>
 
 using namespace soclib::common;
@@ -288,7 +320,7 @@
   const IntTab        &srcid_x,          // global index on external network
   const IntTab        &tgtid_d,          // global index on direct network
-  const size_t        cc_global_id,      // global index on cc network 
+  const size_t        cc_global_id,      // global index on cc network
   const size_t        nways,             // number of ways per set
-  const size_t        nsets,             // number of associative sets 
+  const size_t        nsets,             // number of associative sets
   const size_t        nwords,            // number of words in cache line
   const size_t        max_copies,        // max number of copies in heap
@@ -311,5 +343,5 @@
     m_nseg( 0 ),
     m_srcid_x( mtx.indexForId(srcid_x) ),
-    m_initiators( 1 << vci_param::S ),
+    m_initiators( 1 << vci_param_int::S ),
     m_heap_size( heap_size ),
     m_ways( nways ),
@@ -320,8 +352,8 @@
     m_debug_ok( debug_ok ),
     m_trt_lines(trt_lines),
-    m_trt(trt_lines, nwords),
+    m_trt(this->name(), trt_lines, nwords),
     m_upt_lines(upt_lines),
     m_upt(upt_lines),
-    m_cache_directory(nways, nsets, nwords, vci_param::N),
+    m_cache_directory(nways, nsets, nwords, vci_param_int::N),
     m_cache_data(nways, nsets, nwords),
     m_heap(m_heap_size),
@@ -332,11 +364,13 @@
     m_x(L2(m_words), 2),
     m_y(L2(m_sets), L2(m_words) + 2),
-    m_z(vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
-    m_nline(vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+    m_z(vci_param_int::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline(vci_param_int::N - L2(m_words) - 2, L2(m_words) + 2),
 #undef L2
 
     // XMIN(5 bits) / XMAX(5 bits) / YMIN(5 bits) / YMAX(5 bits)
     //   0b00000    /   0b11111    /   0b00000    /   0b11111
-    m_broadcast_address(0x7C1F),
+    m_broadcast_boundaries(0x7C1F),
+
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
 
     //  FIFOs
@@ -365,9 +399,12 @@
     m_cc_receive_to_multi_ack_fifo("m_cc_receive_to_multi_ack_fifo", 4),
 
-    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
-
-    r_read_fsm("r_read_fsm"),
-
-    r_write_fsm("r_write_fsm"),
+    r_config_fsm( "r_config_fsm" ),
+
+    m_config_to_cc_send_inst_fifo( "m_config_to_cc_send_inst_fifo", 8 ),
+    m_config_to_cc_send_srcid_fifo( "m_config_to_cc_send_srcid_fifo", 8 ),
+
+    r_read_fsm( "r_read_fsm" ),
+
+    r_write_fsm( "r_write_fsm" ),
 
     m_write_to_cc_send_inst_fifo("m_write_to_cc_send_inst_fifo",8),
@@ -412,4 +449,6 @@
     r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt")
 {
+    std::cout << "  - Building VciMemCache : " << name << std::endl;
+
     assert(IS_POW_OF_2(nsets));
     assert(IS_POW_OF_2(nwords));
@@ -420,6 +459,17 @@
 
     // check Transaction table size
-    assert((uint32_log2(trt_lines) <= vci_param::T) and
-         "Need more bits for VCI TRDID field");
+    assert((uint32_log2(trt_lines) <= vci_param_ext::T) and
+    "MEMC ERROR : Need more bits for VCI TRDID field");
+
+    // check internal and external data width
+    assert( (vci_param_int::B == 4 ) and
+    "MEMC ERROR : VCI internal data width must be 32 bits");
+
+    assert( (vci_param_ext::B == 8) and
+    "MEMC ERROR : VCI external data width must be 64 bits");
+
+    // Check coherence between internal & external addresses
+    assert( (vci_param_int::N == vci_param_ext::N) and
+    "MEMC ERROR : VCI internal & external addresses must have the same width");
 
     // Get the segments associated to the MemCache
@@ -429,4 +479,7 @@
     for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++)
     {
+        std::cout << "    => segment " << seg->name()
+                  << " / base = " << std::hex << seg->baseAddress()
+                  << " / size = " << seg->size() << std::endl;
         m_nseg++;
     }
@@ -436,4 +489,5 @@
     for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++)
     {
+        if ( seg->special() ) m_seg_config = i;
         m_seg[i] = & (*seg);
         i++;
@@ -475,5 +529,5 @@
 
 ///////////////////////////////////////////////////////////////////////
-tmpl(void) ::start_monitor(vci_addr_t addr, vci_addr_t length)
+tmpl(void) ::start_monitor(addr_t addr, addr_t length)
 ///////////////////////////////////////////////////////////////////////
 {
@@ -490,38 +544,34 @@
 }
 
-///////////////////////////////////////////////////////////////////////
-tmpl(void) ::check_monitor(const char *buf, vci_addr_t addr, data_t data)
-///////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////
+tmpl(void) ::check_monitor( const char  *buf,
+                            addr_t      addr,
+                            data_t      data,
+                            bool        read )
+////////////////////////////////////////////////
 {
   if((addr >= m_monitor_base) and
       (addr < m_monitor_base + m_monitor_length))
   {
-    std::cout << " MEMC Write Monitor : " << buf << " Address = " << std::hex << addr
-              << " / Data = " << data << " at cycle " << std::dec << m_cpt_cycles << std::endl;
+    if ( read ) std::cout << " Monitor MEMC Read  ";
+    else        std::cout << " Monitor MEMC Write ";
+    std::cout << buf
+              << " / Address = " << std::hex << addr
+              << " / Data = " << data
+              << " at cycle " << std::dec << m_cpt_cycles << std::endl;
   }
 }
 
-///////////////////////////////////////////////////////////////////////
-tmpl(void) ::check_monitor_read(const char *buf, vci_addr_t addr)
-///////////////////////////////////////////////////////////////////////
-{
-  if((addr >= m_monitor_base) and
-      (addr < m_monitor_base + m_monitor_length))
-  {
-    std::cout << " MEMC Read Monitor : " << buf << " Address = " << std::hex << addr
-              << std::endl;
-  }
-}
-
 /////////////////////////////////////////////////////
-tmpl(void) ::copies_monitor(vci_addr_t addr)
+tmpl(void) ::copies_monitor(addr_t addr)
 /////////////////////////////////////////////////////
 {
   DirectoryEntry entry = m_cache_directory.read_neutral(addr);
+
   if((entry.count != m_debug_previous_count) or
       (entry.valid != m_debug_previous_hit))
   {
-    std::cout << " MEMC " << name()
-              << " cache change at cycle " << std::dec << m_cpt_cycles
+    std::cout << "Monitor MEMC " << name()
+              << " at cycle " << std::dec << m_cpt_cycles
               << " for address " << std::hex << addr
               << " / HIT = " << entry.valid
@@ -537,19 +587,21 @@
 {
   std::cout << "MEMC " << name() << std::endl;
-  std::cout << "  "  << tgt_cmd_fsm_str[r_tgt_cmd_fsm]
-            << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm]
-            << " | " << read_fsm_str[r_read_fsm]
-            << " | " << write_fsm_str[r_write_fsm]
-            << " | " << cas_fsm_str[r_cas_fsm]
-            << " | " << cleanup_fsm_str[r_cleanup_fsm] << std::endl;
-  std::cout << "  "  << cc_send_fsm_str[r_cc_send_fsm]
-            << " | " << cc_receive_fsm_str[r_cc_receive_fsm]
-            << " | " << multi_ack_fsm_str[r_multi_ack_fsm]
-            << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm]
-            << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm]
+  std::cout << "  "  << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()]
+            << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()]
+            << " | " << read_fsm_str[r_read_fsm.read()]
+            << " | " << write_fsm_str[r_write_fsm.read()]
+            << " | " << cas_fsm_str[r_cas_fsm.read()]
+            << " | " << config_fsm_str[r_config_fsm.read()]
+            << " | " << cleanup_fsm_str[r_cleanup_fsm.read()] << std::endl;
+  std::cout << "  "  << cc_send_fsm_str[r_cc_send_fsm.read()]
+            << " | " << cc_receive_fsm_str[r_cc_receive_fsm.read()]
+            << " | " << multi_ack_fsm_str[r_multi_ack_fsm.read()]
+            << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()]
+            << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()]
             << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl;
-
-  //m_llsc_table.print_trace();
-
+  std::cout << "  "  << alloc_dir_fsm_str[r_alloc_dir_fsm.read()]
+            << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()]
+            << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()]
+            << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl;
 }
 
@@ -613,5 +665,6 @@
     // Initializing FSMs
     r_tgt_cmd_fsm    = TGT_CMD_IDLE;
-    r_tgt_rsp_fsm    = TGT_RSP_READ_IDLE;
+    r_config_fsm     = CONFIG_IDLE;
+    r_tgt_rsp_fsm    = TGT_RSP_TGT_CMD_IDLE;
     r_cc_send_fsm    = CC_SEND_XRAM_RSP_IDLE;
     r_cc_receive_fsm = CC_RECEIVE_IDLE;
@@ -629,17 +682,5 @@
     r_ixr_cmd_fsm    = IXR_CMD_READ_IDLE;
 
-    m_debug_global         = false;
-    m_debug_tgt_cmd_fsm    = false;
-    m_debug_tgt_rsp_fsm    = false;
-    m_debug_cc_send_fsm  = false;
-    m_debug_cc_receive_fsm  = false;
-    m_debug_multi_ack_fsm  = false;
-    m_debug_read_fsm       = false;
-    m_debug_write_fsm      = false;
-    m_debug_cas_fsm        = false;
-    m_debug_cleanup_fsm    = false;
-    m_debug_ixr_cmd_fsm    = false;
-    m_debug_ixr_rsp_fsm    = false;
-    m_debug_xram_rsp_fsm   = false;
+    m_debug                = false;
     m_debug_previous_hit   = false;
     m_debug_previous_count = 0;
@@ -672,4 +713,15 @@
     m_cmd_cas_eop_fifo.init()   ;
 
+    r_config_cmd  = MEMC_CMD_NOP;
+    r_config_lock = false;
+
+    m_config_to_cc_send_inst_fifo.init();
+    m_config_to_cc_send_srcid_fifo.init();
+#if L1_MULTI_CACHE
+    m_config_to_cc_send_cache_id_fifo.init();
+#endif
+
+    r_tgt_cmd_to_tgt_rsp_req = false;
+
     r_read_to_tgt_rsp_req = false;
     r_read_to_ixr_cmd_req = false;
@@ -677,6 +729,6 @@
     r_write_to_tgt_rsp_req          = false;
     r_write_to_ixr_cmd_req          = false;
-    r_write_to_cc_send_multi_req   = false;
-    r_write_to_cc_send_brdcast_req = false;
+    r_write_to_cc_send_multi_req    = false;
+    r_write_to_cc_send_brdcast_req  = false;
     r_write_to_multi_ack_req        = false;
 
@@ -765,5 +817,5 @@
   bool    cc_receive_to_cleanup_fifo_get = false;
   bool    cc_receive_to_cleanup_fifo_put = false;
-   
+
   bool    cc_receive_to_multi_ack_fifo_get = false;
   bool    cc_receive_to_multi_ack_fifo_put = false;
@@ -787,4 +839,9 @@
 #endif
 
+  bool    config_to_cc_send_fifo_put   = false;
+  bool    config_to_cc_send_fifo_get   = false;
+  bool    config_to_cc_send_fifo_inst  = false;
+  size_t  config_to_cc_send_fifo_srcid = 0;
+
   bool    cas_to_cc_send_fifo_put   = false;
   bool    cas_to_cc_send_fifo_get   = false;
@@ -796,24 +853,12 @@
 #endif
 
-  m_debug_global         = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_tgt_cmd_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_tgt_rsp_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_cc_send_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_cc_receive_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_multi_ack_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_read_fsm       = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_write_fsm      = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_cas_fsm        = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_cleanup_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_ixr_cmd_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_ixr_rsp_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
-  m_debug_xram_rsp_fsm   = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
 
 #if DEBUG_MEMC_GLOBAL
-  if(m_debug_global)
-  {
+if(m_debug)
+{
     std::cout
         << "---------------------------------------------"           << std::dec << std::endl
-        << "MEM_CACHE "            << name() 
+        << "MEM_CACHE "            << name()
         << " ; Time = "            << m_cpt_cycles                                << std::endl
         << " - TGT_CMD FSM    = "  << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()]       << std::endl
@@ -833,5 +878,5 @@
         << " - ALLOC_UPT FSM  = "  << alloc_upt_fsm_str[r_alloc_upt_fsm.read()]   << std::endl
         << " - ALLOC_HEAP FSM = "  << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl;
-  }
+}
 #endif
 
@@ -839,227 +884,334 @@
   //    TGT_CMD FSM
   ////////////////////////////////////////////////////////////////////////////////////
-  // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+  // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors,
+  // and dispatch these commands to the proper FSM through dedicated FIFOs.
   //
-  // There are 5 types of accepted commands :
-  // - READ   : A READ request has a length of 1 VCI cell. It can be a single word
-  //            or an entire cache line, depending on the PLEN value.
-  // - WRITE  : A WRITE request has a maximum length of 16 cells, and can only
-  //            concern words in a same line.
-  // - CAS    : A CAS request has a length of 2 cells or 4 cells.
-  // - LL     : An LL request has a length of 1 cell.
-  // - SC     : An SC request has a length of 2 cells. First cell contains the
-  //            acces key, second cell the data to write in case of success.
+  // There are 5 types of commands accepted in the XRAM segment:
+  // - READ   : A READ request has a length of 1 VCI flit. It can be a single word
+  //            or an entire cache line, depending on the PLEN value => READ FSM
+  // - WRITE  : A WRITE request has a maximum length of 16 flits, and can only
+  //            concern words in a same line => WRITE FSM
+  // - CAS    : A CAS request has a length of 2 flits or 4 flits => CAS FSM
+  // - LL     : An LL request has a length of 1 flit => READ FSM
+  // - SC     : An SC request has a length of 2 flits. First flit contains the
+  //            acces key, second flit the data to write => WRITE FSM.
+  //
+  // The READ/WRITE commands accepted in the configuration segment are targeting
+  // configuration or status registers. They must contain one single flit.
+  // - For almost all addressable registers, the response is returned immediately. 
+  // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed.
   ////////////////////////////////////////////////////////////////////////////////////
 
   switch(r_tgt_cmd_fsm.read())
   {
-      //////////////////
-    case TGT_CMD_IDLE:
-      if(p_vci_tgt.cmdval)
-      {
+    //////////////////
+    case TGT_CMD_IDLE:     // waiting a VCI command (RAM or CONFIG)
+    if(p_vci_tgt.cmdval)
+    {
 
 #if DEBUG_MEMC_TGT_CMD
-        if(m_debug_tgt_cmd_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name()
-              << ".TGT_CMD_IDLE> Receive command from srcid "
-              << std::dec << p_vci_tgt.srcid.read()
-              << " / for address "
-              << std::hex << p_vci_tgt.address.read()
-              << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " TGT_CMD_IDLE> Receive command from srcid "
+          << std::hex << p_vci_tgt.srcid.read()
+          << " / address " << std::hex << p_vci_tgt.address.read() << std::endl;
 #endif
         // checking segmentation violation
-        vci_addr_t  address = p_vci_tgt.address.read();
-        uint32_t    plen    = p_vci_tgt.plen.read();
-        bool found = false;
-        for(size_t seg_id = 0 ; seg_id < m_nseg ; seg_id++)
-        {
-          if(m_seg[seg_id]->contains(address) &&
-              m_seg[seg_id]->contains(address + plen - vci_param::B))
-          {
-            found = true;
-          }
-        }
-        if(not found)
-        {
-          std::cout << "VCI_MEM_CACHE ERROR " << name() << std::endl;
-          std::cout
-              << "Out of segment VCI address in TGT_CMD_IDLE state (address = "
-              << std::hex << address << ", srcid = " << p_vci_tgt.srcid.read()
-              << std::dec << ", cycle = " << m_cpt_cycles << ")" << std::endl;
-          exit(0);
-        }
-
-        if(p_vci_tgt.cmd.read() == vci_param::CMD_READ)
-        {
-          // check that the pktid is either :
-          // TYPE_READ_DATA_UNC
-          // TYPE_READ_DATA_MISS
-          // TYPE_READ_INS_UNC
-          // TYPE_READ_INS_MISS
-          // ==> bit2 must be zero with the TSAR encoding
-          // ==> mask = 0b0100 = 0x4
-          assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) &&
-                 "The type specified in the pktid field is incompatible with the READ CMD");
-          r_tgt_cmd_fsm = TGT_CMD_READ;
-        }
-        else if(p_vci_tgt.cmd.read() == vci_param::CMD_WRITE)
-        {
-          // check that the pktid is TYPE_WRITE
-          // ==> TYPE_WRITE = X100 with the TSAR encoding
-          // ==> mask = 0b0111 = 0x7
-          assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) &&
-                 "The type specified in the pktid field is incompatible with the WRITE CMD");
-          r_tgt_cmd_fsm = TGT_CMD_WRITE;
-        }
-        else if(p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ)
-        {
-          // check that the pktid is TYPE_LL
-          // ==> TYPE_LL = X110 with the TSAR encoding
-          // ==> mask = 0b0111 = 0x7
-          assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) &&
-                 "The type specified in the pktid field is incompatible with the LL CMD");
-          r_tgt_cmd_fsm = TGT_CMD_READ;
-        }
-        else if(p_vci_tgt.cmd.read() == vci_param::CMD_NOP)
-        {
-          // check that the pktid is either :
-          // TYPE_CAS
-          // TYPE_SC
-          // ==> TYPE_CAS = X101 with the TSAR encoding
-          // ==> TYPE_SC  = X111 with the TSAR encoding
-          // ==> mask = 0b0101 = 0x5
-          assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) &&
-                 "The type specified in the pktid field is incompatible with the NOP CMD");
-
-          if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS)
-            r_tgt_cmd_fsm = TGT_CMD_CAS;
-          else // TYPE_SC
-            r_tgt_cmd_fsm = TGT_CMD_WRITE;
+        addr_t      address  = p_vci_tgt.address.read();
+        uint32_t    plen     = p_vci_tgt.plen.read();
+        bool        found    = false;
+        bool        config   = false;
+
+        // register arguments for response (segmentation violation or config)
+        r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read();
+        r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read();
+        r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read();
+
+        for(size_t seg_id = 0 ; (seg_id < m_nseg) and not found ; seg_id++)
+        {
+            if( m_seg[seg_id]->contains(address) and
+                m_seg[seg_id]->contains(address + plen - vci_param_int::B) )
+            {
+                found = true;
+                if ( m_seg[seg_id]->special() ) config = true;
+            }
+        }
+
+        if ( not found )                /////////// out of segment error
+        {
+            r_tgt_cmd_fsm   = TGT_CMD_ERROR;
+        }
+        else if ( config )              /////////// configuration command
+        {
+            if ( not p_vci_tgt.eop.read() ) r_tgt_cmd_fsm = TGT_CMD_ERROR;
+            else                            r_tgt_cmd_fsm = TGT_CMD_CONFIG;
+        }
+        else                            //////////// memory access 
+        {
+            if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ )
+            {
+                // check that the pktid is either :
+                // TYPE_READ_DATA_UNC
+                // TYPE_READ_DATA_MISS
+                // TYPE_READ_INS_UNC
+                // TYPE_READ_INS_MISS
+                // ==> bit2 must be zero with the TSAR encoding
+                // ==> mask = 0b0100 = 0x4
+                assert( ((p_vci_tgt.pktid.read() & 0x4) == 0x0) and
+                "The type specified in the pktid field is incompatible with the READ CMD");
+                r_tgt_cmd_fsm = TGT_CMD_READ;
+            }
+            else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
+            {
+                // check that the pktid is TYPE_WRITE
+                // ==> TYPE_WRITE = X100 with the TSAR encoding
+                // ==> mask = 0b0111 = 0x7
+                assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) and
+                "The type specified in the pktid field is incompatible with the WRITE CMD");
+                r_tgt_cmd_fsm = TGT_CMD_WRITE;
+            }
+            else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)
+            {
+                // check that the pktid is TYPE_LL
+                // ==> TYPE_LL = X110 with the TSAR encoding
+                // ==> mask = 0b0111 = 0x7
+                assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) and
+                "The type specified in the pktid field is incompatible with the LL CMD");
+                r_tgt_cmd_fsm = TGT_CMD_READ;
+            }
+            else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)
+            {
+                // check that the pktid is either :
+                // TYPE_CAS
+                // TYPE_SC
+                // ==> TYPE_CAS = X101 with the TSAR encoding
+                // ==> TYPE_SC  = X111 with the TSAR encoding
+                // ==> mask = 0b0101 = 0x5
+                assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) and
+                "The type specified in the pktid field is incompatible with the NOP CMD");
+
+                if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS;
+                else                                           r_tgt_cmd_fsm = TGT_CMD_WRITE; 
+            }
+            else
+            {
+                r_tgt_cmd_fsm = TGT_CMD_ERROR;
+            }
+        }
+    }
+    break;
+
+    ///////////////////
+    case TGT_CMD_ERROR:  // response error must be sent
+
+    // wait if pending TGT_CMD request to TGT_RSP FSM
+    if(r_tgt_cmd_to_tgt_rsp_req.read()) break;
+
+    // consume all the command packet flits before sending response error
+    if ( p_vci_tgt.cmdval and p_vci_tgt.eop )
+    {
+        r_tgt_cmd_to_tgt_rsp_req   = true;
+        r_tgt_cmd_to_tgt_rsp_error = 1;
+        r_tgt_cmd_fsm              = TGT_CMD_IDLE;
+
+#if DEBUG_MEMC_TGT_CMD
+if(m_debug)
+  std::cout << "  <MEMC " << name()
+    << " TGT_CMD_ERROR> Segmentation violation:"
+    << " address = " << std::hex << p_vci_tgt.address.read()
+    << " / srcid = " << p_vci_tgt.srcid.read()
+    << " / trdid = " << p_vci_tgt.trdid.read()
+    << " / pktid = " << p_vci_tgt.pktid.read()
+    << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
+#endif
+
+    }
+    break;
+
+    ////////////////////
+    case TGT_CMD_CONFIG:    // execute config request and return response
+    {
+        addr_t   seg_base = m_seg[m_seg_config]->baseAddress();
+        addr_t   address  = p_vci_tgt.address.read();
+        size_t   cell     = (address - seg_base)/vci_param_int::B;
+      
+        bool     need_rsp; 
+        size_t   error;  
+        uint32_t rdata = 0;         // default value
+
+        if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
+             and (cell == MEMC_LOCK) )
+        {
+            rdata            = (uint32_t)r_config_lock.read();
+            need_rsp         = true;
+            error            = 0;
+            r_config_lock    = true;
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
+                   and (cell == MEMC_LOCK) )
+        {
+            need_rsp         = true;
+            error            = 0;
+            r_config_lock    = false;
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
+                   and (cell == MEMC_ADDR_LO) )
+        {
+            need_rsp         = true;
+            error            = 0;
+            r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) |
+                               (addr_t)p_vci_tgt.wdata.read();
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_hi
+                   and (cell == MEMC_ADDR_HI) )
+        {
+            need_rsp         = true;
+            error            = 0;
+            r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) |
+                               ((addr_t)p_vci_tgt.wdata.read())<<32;
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
+                   and (cell == MEMC_BUF_LENGTH) )
+        {
+            need_rsp         = true;
+            error            = 0;
+            size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words<<2));
+            if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++;
+            r_config_nlines  = lines;
+        }
+        else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
+                   and (cell == MEMC_CMD_TYPE) )
+        {
+            need_rsp         = false;
+            error            = 0;
+            r_config_cmd     = p_vci_tgt.wdata.read();
+            r_config_srcid   = p_vci_tgt.srcid.read();
+            r_config_trdid   = p_vci_tgt.trdid.read();
+            r_config_pktid   = p_vci_tgt.pktid.read();
         }
         else
         {
-          std::cout << "VCI_MEM_CACHE ERROR " << name()
-                    << " TGT_CMD_IDLE state" << std::endl;
-          std::cout << " illegal VCI command type" << std::endl;
-          exit(0);
-        }
-      }
-      break;
-
-      //////////////////
-    case TGT_CMD_READ:
-      // This test checks that the read does not cross a cache line limit.
-      // It must not be taken into account when dealing with an LL CMD.
-      if(((m_x[(vci_addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) && (p_vci_tgt.cmd.read() != vci_param::CMD_LOCKED_READ))
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
-            << std::endl;
-        std::cout
-            << " illegal address/plen combination for VCI read command" << std::endl;
+            need_rsp         = true;
+            error            = 1;
+        }
+
+        if ( need_rsp )
+        {
+            // blocked if previous pending request to TGT_RSP FSM
+            if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break;
+
+            r_tgt_cmd_to_tgt_rsp_req   = true;
+            r_tgt_cmd_to_tgt_rsp_error = error;
+            r_tgt_cmd_to_tgt_rsp_rdata = rdata;
+            r_tgt_cmd_fsm              = TGT_CMD_IDLE;
+        }
+        else
+        {
+            r_tgt_cmd_fsm              = TGT_CMD_IDLE;
+        }
+
+#if DEBUG_MEMC_TGT_CMD
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:"
+          << " address = " << std::hex << p_vci_tgt.address.read()
+          << " / wdata = " << p_vci_tgt.wdata.read()
+          << " / error = " << error << std::endl;
+#endif
+        break;
+    }
+    //////////////////
+    case TGT_CMD_READ:    // Push a read request into read fifo
+
+    // check that the read does not cross a cache line limit.
+    if ( ((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) and
+          (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ))
+    {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+                  << " illegal address/plen for VCI read command" << std::endl;
         exit(0);
-      }
-      if(!p_vci_tgt.eop.read())
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
-            << std::endl;
-        std::cout
-            << " read or ll command packets must contain one single flit"
-            << std::endl;
+    }
+    // check single flit
+    if(!p_vci_tgt.eop.read())
+    {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+                  << " read command packet must contain one single flit" << std::endl;
         exit(0);
-      }
-      if((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) && (p_vci_tgt.plen.read() != 8))
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
-            << std::endl;
-        std::cout
-            << " ll command packets must have a plen of 8"
-            << std::endl;
+    } 
+    // check plen for LL
+    if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 
+         (p_vci_tgt.plen.read() != 8) )
+    {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+                  << " ll command packets must have a plen of 8" << std::endl;
         exit(0);
-      }
-
-      if(p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok())
-      {
+    }
+
+    if ( p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok() )
+    {
 
 #if DEBUG_MEMC_TGT_CMD
-        if(m_debug_tgt_cmd_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".TGT_CMD_READ> Push into read_fifo:"
-                    << " address = " << std::hex << p_vci_tgt.address.read()
-                    << " srcid = " << std::dec << p_vci_tgt.srcid.read()
-                    << " trdid = " << p_vci_tgt.trdid.read()
-                    << " pktid = " << p_vci_tgt.pktid.read()
-                    << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:"
+          << " address = " << std::hex << p_vci_tgt.address.read()
+          << " / srcid = " << p_vci_tgt.srcid.read()
+          << " / trdid = " << p_vci_tgt.trdid.read()
+          << " / pktid = " << p_vci_tgt.pktid.read()
+          << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
 #endif
         cmd_read_fifo_put = true;
-        if(p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ)
-          m_cpt_ll++;
-        else
-          m_cpt_read++;
+        if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) m_cpt_ll++;
+        else                                                       m_cpt_read++;
         r_tgt_cmd_fsm = TGT_CMD_IDLE;
-      }
-      break;
-
-      ///////////////////
+    }
+    break;
+
+    ///////////////////
     case TGT_CMD_WRITE:
-      if(p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok())
-      {
+    if(p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok())
+    {
 
 #if DEBUG_MEMC_TGT_CMD
-        if(m_debug_tgt_cmd_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".TGT_CMD_WRITE> Push into write_fifo:"
-                    << " address = " << std::hex << p_vci_tgt.address.read()
-                    << " srcid = " << std::dec << p_vci_tgt.srcid.read()
-                    << " trdid = " << p_vci_tgt.trdid.read()
-                    << " pktid = " << p_vci_tgt.pktid.read()
-                    << " wdata = " << std::hex << p_vci_tgt.wdata.read()
-                    << " be = " << p_vci_tgt.be.read()
-                    << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:"
+          << " address = " << std::hex << p_vci_tgt.address.read()
+          << " / srcid = " << p_vci_tgt.srcid.read()
+          << " / trdid = " << p_vci_tgt.trdid.read()
+          << " / pktid = " << p_vci_tgt.pktid.read()
+          << " / wdata = " << p_vci_tgt.wdata.read()
+          << " / be = " << p_vci_tgt.be.read()
+          << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
 #endif
         cmd_write_fifo_put = true;
         if(p_vci_tgt.eop)  r_tgt_cmd_fsm = TGT_CMD_IDLE;
-      }
-      break;
-
-      ////////////////////
+    }
+    break;
+
+    /////////////////
     case TGT_CMD_CAS:
-      if((p_vci_tgt.plen.read() != 8) && (p_vci_tgt.plen.read() != 16))
-      {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state"
-            << std::endl
-            << "illegal format for CAS command " << std::endl;
-
+    if((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16))
+    {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state"
+                  << "illegal format for CAS command " << std::endl;
         exit(0);
-      }
-
-      if(p_vci_tgt.cmdval && m_cmd_cas_addr_fifo.wok())
-      {
+    }
+
+    if(p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok())
+    {
 
 #if DEBUG_MEMC_TGT_CMD
-        if(m_debug_tgt_cmd_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
-                    << " address = " << std::hex << p_vci_tgt.address.read()
-                    << " srcid = " << std::dec << p_vci_tgt.srcid.read()
-                    << " trdid = " << p_vci_tgt.trdid.read()
-                    << " pktid = " << p_vci_tgt.pktid.read()
-                    << " wdata = " << std::hex << p_vci_tgt.wdata.read()
-                    << " be = " << p_vci_tgt.be.read()
-                    << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
+          << " address = " << std::hex << p_vci_tgt.address.read()
+          << " srcid = " << p_vci_tgt.srcid.read()
+          << " trdid = " << p_vci_tgt.trdid.read()
+          << " pktid = " << p_vci_tgt.pktid.read()
+          << " wdata = " << p_vci_tgt.wdata.read()
+          << " be = " << p_vci_tgt.be.read()
+          << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
 #endif
         cmd_cas_fifo_put = true;
         if(p_vci_tgt.eop) r_tgt_cmd_fsm = TGT_CMD_IDLE;
-      }
-      break;
+    }
+    break;
   } // end switch tgt_cmd_fsm
 
@@ -1071,96 +1223,75 @@
   // update the UPT.
   //
-  // It can be update or inval requests initiated by the WRITE or CAS FSM,
-  // or inval requests initiated by the XRAM_RSP FSM.
-  // It can also be a direct request from the WRITE FSM.
+  // - The FSM decrements the proper entry in UPT,
+  //   and clear the UPT entry when all responses have been received.
+  // - If required, it sends a request to the TGT_RSP FSM to complete
+  //   a pending  write transaction.
+  // - If required, it sends an acknowledge to the CONFIG FSM to signal 
+  //   completion of a line inval.
   //
-  // The FSM decrements the proper entry in UPT.
-  // It sends a request to the TGT_RSP FSM to complete the pending
-  // write transaction (acknowledge response to the writer processor),
-  // and clear the UPT entry when all responses have been received.
-  //
-  // All those response packets are one flit packet.
-  // The index in the Table is defined in the UPDT_TABLE INDEX field, and
-  // the transaction type is defined in the UPT entry.
+  // All those multi-ack packets are one flit packet.
+  // The index in the UPT is defined in the UPDTID field.
   ////////////////////////////////////////////////////////////////////////
 
   switch(r_multi_ack_fsm.read())
   {
+    ////////////////////
     case MULTI_ACK_IDLE:
-      {
+    {
         bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok();
 
-        // None Multicast Acknowledgement received and
-        // none WRITE FSM UPT decrement request
-        if( not multi_ack_fifo_rok and
-            not r_write_to_multi_ack_req.read())
-        {
+        // No CC_RECEIVE FSM request and no WRITE FSM request
+        if( not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read())
           break;
-        }
-
-        // WRITE FSM request to decrement update table response counter
-        // Priority to Multicast Acknowledgement priority
+
+        uint8_t updt_index;
+
+        // handling WRITE FSM request to decrement update table response
+        // counter if no CC_RECEIVE FSM request
         if(not multi_ack_fifo_rok)
         {
+          updt_index               = r_write_to_multi_ack_upt_index.read();
           r_write_to_multi_ack_req = false;
-          r_multi_ack_upt_index    = r_write_to_multi_ack_upt_index.read();
-          r_multi_ack_fsm          = MULTI_ACK_UPT_LOCK;
-
-          break;
-        }
-
-        // Multicast Acknowledgement received 
-        uint64_t flit = m_cc_receive_to_multi_ack_fifo.read();
-
-        uint8_t updt_index = 
-          DspinDhccpParam::dspin_get(flit, DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
-
-        bool eop =
-          (DspinDhccpParam::dspin_get(flit, DspinDhccpParam::FROM_L1_EOP) == 0x1);
-
-        if(updt_index >= m_upt.size())
-        {
-          std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " MULTI_ACK_IDLE state" << std::endl
-            << "index too large for UPT: "
-            << std::dec
-            << " / UPT index = " << updt_index
-            << " / UPT size = "  << m_upt.size()
-            << std::endl;
-
-          exit(0);
-        }
-
-        if(not eop)
-        {
-          std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " MULTI_ACK_IDLE state" << std::endl
-            << "A Multicast Acknowledgement must be an one flit packet"
-            << std::endl;
-
-          exit(0);
-        }
-
-        cc_receive_to_multi_ack_fifo_get = true;
-        r_multi_ack_upt_index           = updt_index;
-        r_multi_ack_fsm                 = MULTI_ACK_UPT_LOCK;
+        }
+        // Handling CC_RECEIVE FSM request
+        else
+        {
+          uint64_t flit = m_cc_receive_to_multi_ack_fifo.read();
+          updt_index    = DspinDhccpParam::dspin_get(flit,
+                            DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
+
+          cc_receive_to_multi_ack_fifo_get = true;
+        }
+
+        assert((updt_index < m_upt.size()) and
+               "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : "
+               "index too large for UPT");
+
+        r_multi_ack_upt_index = updt_index;
+        r_multi_ack_fsm       = MULTI_ACK_UPT_LOCK;
 
 #if DEBUG_MEMC_MULTI_ACK
-        if(m_debug_multi_ack_fsm)
-        {
-          std::cout
-            <<  "  <MEMC " << name()
-            << ".MULTI_ACK_IDLE> Response for UPT entry "
-            << updt_index
-            << std::endl;
-        }
+if(m_debug)
+{
+    if (multi_ack_fifo_rok)
+    {
+        std::cout << "  <MEMC " << name()
+                  << " MULTI_ACK_IDLE> Response for UPT entry "
+                  << (size_t)updt_index << std::endl;
+    }
+    else
+    {
+        std::cout << "  <MEMC " << name()
+                  << " MULTI_ACK_IDLE> Write FSM request to decrement UPT entry "
+                  << updt_index << std::endl;
+    }
+}
 #endif
         break;
       }
 
+    ////////////////////////
     case MULTI_ACK_UPT_LOCK:
-      {
+    {
         // get lock to the UPDATE table
         if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break;
@@ -1172,11 +1303,8 @@
         if(not valid)
         {
-          std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " MULTI_ACK_UPT_LOCK state" << std::endl
-            << "unsuccessful access to decrement the UPT"
-            << std::endl;
-
-          exit(0);
+            std::cout << "VCI_MEM_CACHE ERROR " << name()
+                      << " MULTI_ACK_UPT_LOCK state" << std::endl
+                      << "unsuccessful access to decrement the UPT" << std::endl;
+            exit(0);
         }
 
@@ -1191,28 +1319,22 @@
 
 #if DEBUG_MEMC_MULTI_ACK
-        if(m_debug_multi_ack_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:"
-            << " entry = "       << r_multi_ack_upt_index.read()
-            << " / rsp_count = " << std::dec << count
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:"
+          << " entry = "       << r_multi_ack_upt_index.read()
+          << " / rsp_count = " << std::dec << count << std::endl;
 #endif
         break;
-      }
-
-    case MULTI_ACK_UPT_CLEAR:
-      {
+    }
+
+    /////////////////////////
+    case MULTI_ACK_UPT_CLEAR:   // Clear UPT entry / Test if rsp or ack required
+    {
         if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK)
         {
-          std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " MULTI_ACK_UPT_CLEAR state"
-            << " bad UPT allocation"
-            << std::endl;
-
-          exit(0);
+            std::cout << "VCI_MEM_CACHE ERROR " << name()
+                      << " MULTI_ACK_UPT_CLEAR state"
+                      << " bad UPT allocation" << std::endl;
+            exit(0);
         }
 
@@ -1222,35 +1344,26 @@
         r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read());
         bool need_rsp     = m_upt.need_rsp(r_multi_ack_upt_index.read());
+        bool need_ack     = m_upt.need_ack(r_multi_ack_upt_index.read());
 
         // clear the UPT entry
         m_upt.clear(r_multi_ack_upt_index.read());
 
-        if(need_rsp)
-        {
-          r_multi_ack_fsm = MULTI_ACK_WRITE_RSP;
-        }
-        else
-        {
-          r_multi_ack_fsm = MULTI_ACK_IDLE;
-        }
+        if      ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP;
+        else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK;
+        else                 r_multi_ack_fsm = MULTI_ACK_IDLE;
 
 #if DEBUG_MEMC_MULTI_ACK
-        if(m_debug_multi_ack_fsm)
-        {
-          std::cout
-            <<  "  <MEMC " << name()
-            << ".MULTI_ACK_UPT_CLEAR> Clear UPT entry "
-            << r_multi_ack_upt_index.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout <<  "  <MEMC " << name()
+          << " MULTI_ACK_UPT_CLEAR> Clear UPT entry "
+          << std::dec << r_multi_ack_upt_index.read() << std::endl;
 #endif
         break;
-      }
-
-    case MULTI_ACK_WRITE_RSP:
-      {
-        // Post a request to TGT_RSP FSM
-        // Wait if pending request to the TGT_RSP FSM
-        if(r_multi_ack_to_tgt_rsp_req.read()) break;
+    }
+    /////////////////////////
+    case MULTI_ACK_WRITE_RSP:     // Post a response request to TGT_RSP FSM
+                                  // Wait if pending request 
+    {
+        if ( r_multi_ack_to_tgt_rsp_req.read() ) break;
 
         r_multi_ack_to_tgt_rsp_req   = true;
@@ -1261,16 +1374,426 @@
 
 #if DEBUG_MEMC_MULTI_ACK
-        if(m_debug_multi_ack_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".MULTI_ACK_WRITE_RSP> Request TGT_RSP FSM to send a response to srcid "
-            << r_multi_ack_srcid.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " MULTI_ACK_WRITE_RSP>"
+          << " Request TGT_RSP FSM to send a response to srcid "
+          << std::hex << r_multi_ack_srcid.read() << std::endl;
 #endif
         break;
-      }
+    }
+    //////////////////////////
+    case MULTI_ACK_CONFIG_ACK:    // Signals multi-inval completion to CONFIG FSM
+                                  // Wait if pending request 
+    {
+        if ( r_multi_ack_to_config_ack.read() ) break;
+
+        r_multi_ack_to_config_ack   = true;
+        r_multi_ack_fsm              = MULTI_ACK_IDLE;
+
+#if DEBUG_MEMC_MULTI_ACK
+if(m_debug)
+std::cout << "  <MEMC " << name() << " MULTI_ACK_CONFIG_ACK>"
+          << " Signals inval completion to CONFIG FSM" << std::endl;
+#endif
+        break;
+    }
   } // end switch r_multi_ack_fsm
+
+  ////////////////////////////////////////////////////////////////////////////////////
+  //    CONFIG FSM
+  ////////////////////////////////////////////////////////////////////////////////////
+  // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC).
+  // The target buffer can have any size, and there is one single command for
+  // all cache lines covered by the target buffer. 
+  // An INVAL or SYNC configuration request is defined by the followinf registers:
+  // - bool      r_config_cmd        : INVAL / SYNC / NOP)
+  // - uint64_t  r_config_address    : buffer base address
+  // - uint32_t  r_config_nlines     : number of lines covering buffer
+  //
+  // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 
+  // all cache lines covered by the target buffer.
+  //
+  // - INVAL request:
+  //   For each line, it access to the DIR array. 
+  //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
+  //   In case of hit, with no copies in L1 caches, the line is invalidated and
+  //   a response is requested to TGT_RSP FSM.
+  //   If there is copies, a multi-inval, or a broadcast-inval coherence transaction
+  //   is launched and registered in UPT. The multi-inval transaction is signaled
+  //   by the r_multi_ack_to config_ack or r_cleanup_to_config_ack flip-flops.
+  //   The config inval response is sent only when the last line has been invalidated.
+  //
+  // - SYNC request:
+  //
+  //  ...  Not implemented yet ...
+  //
+  // From the software point of view, a configuration request is a sequence
+  // of 6 atomic accesses:
+  // - Read  MEMC_LOCK       : Get the lock
+  // - Write MEMC_ADDR_LO    : Set the buffer address LSB
+  // - Write MEMC_ADDR_HI    : Set the buffer address MSB
+  // - Write MEMC_BUF_LENGTH : set buffer length (bytes)
+  // - Write MEMC_CMD_TYPE   : launch the actual operation
+  // - WRITE MEMC_LOCK       : release the lock
+  ////////////////////////////////////////////////////////////////////////////////////
+
+  switch( r_config_fsm.read() )
+  {
+      /////////////////
+      case CONFIG_IDLE:  // waiting a config request 
+      {
+          if ( r_config_cmd.read() != MEMC_CMD_NOP )  
+          {
+              r_config_fsm    = CONFIG_LOOP;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received" 
+          << " address = " << std::hex << r_config_address.read()
+          << " / nlines = " << std::dec << r_config_nlines.read()
+          << " / type = " << r_config_cmd.read() << std::endl;
+#endif
+          }
+          break;
+      }
+      /////////////////
+      case CONFIG_LOOP:   // test last line 
+      {
+          if ( r_config_nlines.read() == 0 )
+          {
+              r_config_cmd = MEMC_CMD_NOP;
+              r_config_fsm = CONFIG_RSP;
+          }
+          else
+          {
+              r_config_fsm = CONFIG_DIR_REQ;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_LOOP>" 
+          << " address = " << std::hex << r_config_address.read()    
+          << " / nlines = " << std::dec << r_config_nlines.read() 
+          << " / command = " << r_config_cmd.read() << std::endl;
+#endif
+          break;
+      }
+      ////////////////////
+      case CONFIG_DIR_REQ:  // Request directory lock
+      {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG )
+          {
+              r_config_fsm = CONFIG_DIR_ACCESS;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_DIR_REQ>"
+          << " Request DIR access" << std::endl;
+#endif
+          break;
+      }
+      ///////////////////////
+      case CONFIG_DIR_ACCESS:   // Access directory and decode config command
+      {
+          size_t way = 0;
+          DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way);
+
+          if ( entry.valid and                            // hit & inval command
+               (r_config_cmd.read() == MEMC_CMD_INVAL) ) 
+          {
+              r_config_dir_way        = way;
+              r_config_dir_copy_inst  = entry.owner.inst;
+              r_config_dir_copy_srcid = entry.owner.srcid;
+              r_config_dir_is_cnt     = entry.is_cnt;
+              r_config_dir_count      = entry.count;
+              r_config_dir_next_ptr   = entry.ptr;
+
+              r_config_fsm    = CONFIG_DIR_UPT_LOCK;
+          }
+          else if ( entry.valid and                       // hit & sync command
+                    entry.dirty and
+                    (r_config_cmd.read() == MEMC_CMD_SYNC) )
+          { 
+              std::cout << "VCI_MEM_CACHE ERROR: "
+                        << "SYNC config request not implemented yet" << std::endl;
+              exit(0);
+          }
+          else                                            // return to LOOP 
+          {
+              r_config_nlines  = r_config_nlines.read() - 1;
+              r_config_address = r_config_address.read() + (m_words<<2);
+              r_config_fsm     = CONFIG_LOOP;
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: "
+          << " address = " << std::hex << r_config_address.read()
+          << " / hit = " << std::dec << entry.valid
+          << " / dirty = " << entry.dirty
+          << " / count = " << entry.count
+          << " / is_cnt = " << entry.is_cnt << std::endl;
+#endif
+          break;
+      }
+      /////////////////////////
+      case CONFIG_DIR_UPT_LOCK:  // enter this state in case of INVAL command
+                                 // Try to get both DIR & UPT locks, and return
+                                 // to LOOP state if UPT full.
+                                 // Register inval in UPT, and invalidate the
+                                 // directory if UPT not full. 
+      {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG )
+          {
+              size_t set        = m_y[(addr_t)(r_config_address.read())];
+              size_t way        = r_config_dir_way.read();
+
+              if ( r_config_dir_count.read() == 0 )     // inval DIR and return to LOOP
+              {
+                  m_cache_directory.inval( way, set );
+                  r_config_nlines  = r_config_nlines.read() - 1;
+                  r_config_address = r_config_address.read() + (m_words<<2);
+                  r_config_fsm     = CONFIG_LOOP;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_DIR_UPT_LOCK>"
+          << " No copies in L1 : inval DIR entry"  << std::endl;
+#endif
+              }
+              else    // try to register inval in UPT
+              {
+                  bool        wok       = false;
+                  size_t      index     = 0;
+                  bool        broadcast = r_config_dir_is_cnt.read();
+                  size_t      srcid     = r_config_srcid.read();
+                  size_t      trdid     = r_config_trdid.read();
+                  size_t      pktid     = r_config_pktid.read();
+                  addr_t      nline     = m_nline[(addr_t)(r_config_address.read())];
+                  size_t      nb_copies = r_config_dir_count.read();
+
+                  wok = m_upt.set(false,       // it's an inval transaction
+                                  broadcast,   
+                                  false,       // no response required
+                                  true,        // acknowledge required
+                                  srcid,
+                                  trdid,
+                                  pktid,
+                                  nline,
+                                  nb_copies,
+                                  index);
+                  if ( wok )  // UPT success => inval DIR slot
+                  {
+                      m_cache_directory.inval( way, set );
+                      r_config_upt_index = index;
+                      if ( broadcast )  r_config_fsm = CONFIG_BC_SEND;
+                      else              r_config_fsm = CONFIG_INV_SEND;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_DIR_UPT_LOCK>"
+          << " Inval DIR entry and register inval in UPT"
+          << " : index = " << std::dec << index
+          << " / broadcast = " << broadcast << std::endl;
+#endif
+                  }
+                  else       // UPT full => release both DIR and UPT locks
+                  {
+                      r_config_fsm = CONFIG_LOOP;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_DIR_UPT_LOCK>"
+          << " UPT full : release DIR & UPT locks and retry" << std::endl;
+#endif
+                  }
+              }
+          }
+          break;
+      }
+      ////////////////////
+      case CONFIG_BC_SEND:    // Post a broadcast inval request to CC_SEND FSM
+      {
+          if( not r_config_to_cc_send_multi_req.read() and 
+              not r_config_to_cc_send_brdcast_req.read() )
+          {
+              r_config_to_cc_send_multi_req   = false;
+              r_config_to_cc_send_brdcast_req = true;
+              r_config_to_cc_send_trdid       = r_config_upt_index.read();
+              r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
+              r_cleanup_to_config_ack         = false;
+              r_config_fsm                    = CONFIG_BC_WAIT;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_BC_SEND>"
+          << " Post a broadcast inval request to CC_SEND FSM" 
+          << " / address = " << r_config_address.read() <<std::endl;
+#endif
+          }
+          break;
+      }
+      ////////////////////
+      case CONFIG_BC_WAIT:      // wait broadcast completion to return to LOOP
+      {
+          if ( r_cleanup_to_config_ack.read() ) 
+          {
+              r_config_fsm     = CONFIG_LOOP;
+              r_config_nlines  = r_config_nlines.read() - 1;
+              r_config_address = r_config_address.read() + (m_words<<2);
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_BC_WAIT> Waiting BC completion " 
+          << " done = " << r_cleanup_to_config_ack.read() 
+          << std::endl; 
+#endif
+          break;
+      }
+      /////////////////////
+      case CONFIG_INV_SEND:    // Post a multi inval request to CC_SEND FSM
+      {
+          if( not r_config_to_cc_send_multi_req.read() and 
+              not r_config_to_cc_send_brdcast_req.read() )
+          {
+              r_config_to_cc_send_multi_req   = true;
+              r_config_to_cc_send_brdcast_req = false;
+              r_config_to_cc_send_trdid       = r_config_upt_index.read();
+              r_config_to_cc_send_nline       = m_nline[(addr_t)(r_config_address.read())];
+              r_multi_ack_to_config_ack       = false;
+
+              config_to_cc_send_fifo_srcid    = r_config_dir_copy_srcid.read();
+              config_to_cc_send_fifo_inst     = r_config_dir_copy_inst.read();
+              config_to_cc_send_fifo_put      = true;
+
+              if ( r_config_dir_count.read() == 1 )  r_config_fsm = CONFIG_INV_WAIT;
+              else                                   r_config_fsm = CONFIG_HEAP_REQ;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_INV_SEND>"
+          << " Post multi inval request to CC_SEND FSM" 
+          << " / address = " << std::hex << r_config_address.read() 
+          << " / copy = " << r_config_dir_copy_srcid.read() 
+          << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl;
+#endif
+          }
+          break;
+      }
+      /////////////////////
+      case CONFIG_HEAP_REQ:  // Try to get access to Heap
+      {
+          if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG )
+          {
+              r_config_fsm       = CONFIG_HEAP_SCAN;
+              r_config_heap_next = r_config_dir_next_ptr.read();
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_HEAP_REQ>"
+          << " Requesting HEAP lock" << std::endl;
+#endif
+          break;
+      }
+      //////////////////////
+      case CONFIG_HEAP_SCAN:      // scan HEAP and send inval to CC_SEND FSM
+      {
+          HeapEntry entry = m_heap.read( r_config_heap_next.read() );
+          bool last_copy  = (entry.next == r_config_heap_next.read()); 
+
+          config_to_cc_send_fifo_srcid = entry.owner.srcid;
+          config_to_cc_send_fifo_inst  = entry.owner.inst;
+          // config_to_cc_send_fifo_last  = last_copy;
+          config_to_cc_send_fifo_put   = true;
+
+          if ( m_config_to_cc_send_inst_fifo.wok() ) // inval request accepted
+          {
+              r_config_heap_next = entry.next;
+              if ( last_copy ) r_config_fsm = CONFIG_HEAP_LAST;
+          }
+          
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_HEAP_SCAN>"
+          << " Post multi inval request to CC_SEND FSM" 
+          << " / address = " << std::hex << r_config_address.read() 
+          << " / copy = " << entry.owner.srcid 
+          << " / inst = " << std::dec << entry.owner.inst << std::endl;
+#endif
+          break;
+      }
+      //////////////////////
+      case CONFIG_HEAP_LAST:      // HEAP housekeeping
+      {
+          size_t free_pointer = m_heap.next_free_ptr();
+          HeapEntry last_entry;
+          last_entry.owner.srcid = 0;
+          last_entry.owner.inst  = false;
+
+          if ( m_heap.is_full() )
+          {
+              last_entry.next = r_config_dir_next_ptr.read();
+              m_heap.unset_full();
+          }
+          else
+          { 
+              last_entry.next = free_pointer;
+          }
+
+          m_heap.write_free_ptr( r_config_dir_next_ptr.read() );
+          m_heap.write( r_config_heap_next.read(), last_entry );
+          r_config_fsm = CONFIG_INV_WAIT;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_HEAP_LAST>"
+          << " Heap housekeeping" << std::endl;
+#endif
+          break;
+      }
+      /////////////////////
+      case CONFIG_INV_WAIT:      // wait inval completion to return to LOOP
+      {
+          if ( r_multi_ack_to_config_ack.read() )
+          {
+              r_config_fsm     = CONFIG_LOOP;
+              r_config_nlines  = r_config_nlines.read() - 1;
+              r_config_address = r_config_address.read() + (m_words<<2);
+          }
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_INV_WAIT> Waiting inval completion " 
+          << " done = " << r_multi_ack_to_config_ack.read() 
+          << std::endl; 
+#endif
+          break;
+      }
+
+      ////////////////
+      case CONFIG_RSP:  // request TGT_RSP FSM to return response 
+      {
+          if ( not r_config_to_tgt_rsp_req.read() )
+          {
+              r_config_to_tgt_rsp_srcid  = r_config_srcid.read();
+              r_config_to_tgt_rsp_trdid  = r_config_trdid.read();
+              r_config_to_tgt_rsp_pktid  = r_config_pktid.read();
+              r_config_to_tgt_rsp_error  = false;
+              r_config_to_tgt_rsp_req    = true;
+              r_config_fsm               = CONFIG_IDLE;
+
+#if DEBUG_MEMC_CONFIG
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:"
+          << " error = " << r_config_to_tgt_rsp_error.read()
+          << " / rsrcid = " << std::hex << r_config_srcid.read() << std::endl;
+#endif
+          }
+          break;
+
+      }
+  }  // end switch r_config_fsm
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -1300,19 +1823,17 @@
   {
       ///////////////
-    case READ_IDLE:
-      // waiting a read request
-    {
+      case READ_IDLE:  // waiting a read request
+      {
       if(m_cmd_read_addr_fifo.rok())
       {
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".READ_IDLE> Read request:"
-                    << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
-                    << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
-                    << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read()
-                    << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
+          << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / srcid = " << m_cmd_read_srcid_fifo.read()
+          << " / trdid = " << m_cmd_read_trdid_fifo.read()
+          << " / pktid = " << m_cmd_read_pktid_fifo.read()
+          << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
 #endif
         r_read_fsm = READ_DIR_REQ;
@@ -1321,27 +1842,21 @@
     }
 
+    //////////////////
+    case READ_DIR_REQ:  // Get the lock to the directory
+    {
+      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
+      {
+        r_read_fsm = READ_DIR_LOCK;
+      }
+
+#if DEBUG_MEMC_READ
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl;
+#endif
+      break;
+    }
+
     ///////////////////
-    case READ_DIR_REQ:
-      // Get the lock to the directory
-    {
-      if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
-      {
-        r_read_fsm = READ_DIR_LOCK;
-      }
-
-#if DEBUG_MEMC_READ
-      if(m_debug_read_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name() << ".READ_DIR_REQ> Requesting DIR lock "
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    ///////////////////
-    case READ_DIR_LOCK:
-      // check directory for hit / miss
+    case READ_DIR_LOCK:  // check directory for hit / miss
     {
       if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
@@ -1375,5 +1890,5 @@
         {
           // test if we need to register a new copy in the heap
-          if(entry.is_cnt || (entry.count == 0) || !cached_read)
+          if(entry.is_cnt or (entry.count == 0) or !cached_read)
           {
             r_read_fsm = READ_DIR_HIT;
@@ -1390,27 +1905,20 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name() << ".READ_DIR_LOCK> Accessing directory: "
-              << " address = " << std::hex << m_cmd_read_addr_fifo.read()
-              << " / hit = " << std::dec << entry.valid
-              << " / count = " <<std::dec << entry.count
-              << " / is_cnt = " << entry.is_cnt << std::endl;
-          if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)
-          {
-            std::cout
-                << "  <MEMC " << name() << ".READ_DIR_LOCK> global_llsc_table LL access" << std::endl;
-          }
-        }
+if(m_debug)
+{
+std::cout << "  <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: "
+          << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / hit = " << std::dec << entry.valid
+          << " / count = " <<std::dec << entry.count
+          << " / is_cnt = " << entry.is_cnt;
+if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl;
+else                                                std::cout << std::endl;
+}
 #endif
       }
       else
       {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " READ_DIR_LOCK state" << std::endl
-            << "Bad DIR allocation"   << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state"
+                  << "Bad DIR allocation"   << std::endl;
         exit(0);
       }
@@ -1429,5 +1937,4 @@
       if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
       {
-        // signals generation
         // check if this is an instruction read, this means pktid is either
         // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
@@ -1441,5 +1948,5 @@
 
         // read data in the cache
-        size_t set        = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        size_t set        = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
         size_t way        = r_read_way.read();
 
@@ -1451,5 +1958,5 @@
         entry.is_cnt  = is_cnt;
         entry.dirty   = r_read_dirty.read();
-        entry.tag   = r_read_tag.read();
+        entry.tag     = r_read_tag.read();
         entry.lock    = r_read_lock.read();
         entry.ptr     = r_read_ptr.read();
@@ -1486,25 +1993,24 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name() << ".READ_DIR_HIT> Update directory entry:"
-              << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
-              << " / set = " << std::dec << set
-              << " / way = " << way
-              << " / owner_id = " << entry.owner.srcid
-              << " / owner_ins = " << entry.owner.inst
-              << " / count = " << entry.count
-              << " / is_cnt = " << entry.is_cnt << std::endl;
-        }
-#endif
-/**/
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
+          << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / set = " << std::dec << set
+          << " / way = " << way
+          << " / owner_id = " << std::hex << entry.owner.srcid
+          << " / owner_ins = " << std::dec << entry.owner.inst
+          << " / count = " << entry.count
+          << " / is_cnt = " << entry.is_cnt << std::endl;
+#endif
+
           if(m_monitor_ok)
           {
             char buf[80];
-            snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", m_cmd_read_srcid_fifo.read(), ((m_cmd_read_pktid_fifo.read()&0x2)!=0));
-            check_monitor_read(buf, m_cmd_read_addr_fifo.read());
+            snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d",
+                     (int)m_cmd_read_srcid_fifo.read(),
+                     (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0));
+            check_monitor(buf, m_cmd_read_addr_fifo.read(), r_read_data[0], true);
           }
-/**/
+
 
         m_cache_directory.write(set, way, entry);
@@ -1514,44 +2020,31 @@
     }
 
+    ///////////////////
+    case READ_HEAP_REQ:    // Get the lock to the HEAP directory
+    {
+      if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
+      {
+        r_read_fsm = READ_HEAP_LOCK;
+      }
+
+#if DEBUG_MEMC_READ
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_HEAP_REQ>"
+          << " Requesting HEAP lock " << std::endl;
+#endif
+      break;
+    }
+
     ////////////////////
-    case READ_HEAP_REQ:
-      // Get the lock to the HEAP directory
-    {
-/**/
-          if(m_monitor_ok)
-          {
-            char buf[80];
-            snprintf(buf, 80, "READ_HEAP_REQ srcid %d, ins %d", m_cmd_read_srcid_fifo.read(), ((m_cmd_read_pktid_fifo.read()&0x2)!=0));
-            check_monitor_read(buf, m_cmd_read_addr_fifo.read());
-          }
-/**/
+    case READ_HEAP_LOCK:   // read data in cache, update the directory
+                           // and prepare the HEAP update
+    {
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
       {
-        r_read_fsm = READ_HEAP_LOCK;
-      }
-
-#if DEBUG_MEMC_READ
-      if(m_debug_read_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name() << ".READ_HEAP_REQ> Requesting HEAP lock "
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    ////////////////////
-    case READ_HEAP_LOCK:
-      // read data in cache, update the directory
-      // and prepare the HEAP update
-    {
-      if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
-      {
         // enter counter mode when we reach the limit of copies or the heap is full
-        bool go_cnt = (r_read_count.read() >= m_max_copies) || m_heap.is_full();
+        bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full();
 
         // read data in the cache
-        size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
         size_t way = r_read_way.read();
 
@@ -1623,30 +2116,23 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".READ_HEAP_LOCK> Update directory:"
-                    << " tag = " << std::hex << entry.tag
-                    << " set = " << std::dec << set
-                    << " way = " << way
-                    << " count = " << entry.count
-                    << " is_cnt = " << entry.is_cnt << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_HEAP_LOCK> Update directory:"
+          << " tag = " << std::hex << entry.tag
+          << " set = " << std::dec << set
+          << " way = " << way
+          << " count = " << entry.count
+          << " is_cnt = " << entry.is_cnt << std::endl;
 #endif
       }
       else
       {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " READ_HEAP_LOCK state" << std::endl
-            << "Bad HEAP allocation"   << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK"
+                  << "Bad HEAP allocation"   << std::endl;
         exit(0);
       }
-
-      break;
-    }
-
+      break;
+    }
     /////////////////////
-    case READ_HEAP_WRITE:       // add a entry in the heap
+    case READ_HEAP_WRITE:       // add an entry in the heap
     {
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
@@ -1674,25 +2160,18 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name() << ".READ_HEAP_WRITE> Add an entry in the heap:"
-              << " owner_id = " << heap_entry.owner.srcid
-              << " owner_ins = " << heap_entry.owner.inst << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:"
+          << " owner_id = " << std::hex << heap_entry.owner.srcid
+          << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl;
 #endif
       }
       else
       {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " READ_HEAP_WRITE state" << std::endl
-            << "Bad HEAP allocation" << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE"
+                  << "Bad HEAP allocation" << std::endl;
         exit(0);
       }
       break;
     }
-
     /////////////////////
     case READ_HEAP_ERASE:
@@ -1713,9 +2192,6 @@
       else
       {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " READ_HEAP_ERASE state" << std::endl
-            << "Bad HEAP allocation" << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE"
+                  << "Bad HEAP allocation" << std::endl;
         exit(0);
       }
@@ -1749,12 +2225,10 @@
       else
       {
-        std::cout << "VCI_MEM_CACHE ERROR " << name()
-                  << " READ_HEAP_LAST state" << std::endl;
-        std::cout << "Bad HEAP allocation" << std::endl;
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST"
+                  << "Bad HEAP allocation" << std::endl;
         exit(0);
       }
       break;
     }
-
     //////////////
     case READ_RSP:    //  request the TGT_RSP FSM to return data
@@ -1763,5 +2237,5 @@
       {
         for(size_t i=0 ; i<m_words ; i++)  r_read_to_tgt_rsp_data[i] = r_read_data[i];
-        r_read_to_tgt_rsp_word   = m_x[(vci_addr_t) m_cmd_read_addr_fifo.read()];
+        r_read_to_tgt_rsp_word   = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
         r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
         r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
@@ -1774,16 +2248,13 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".READ_RSP> Request the TGT_RSP FSM to return data:"
-                    << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read()
-                    << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
-                    << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
-        }
-#endif
-      }
-      break;
-    }
-
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:"
+          << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read()
+          << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
+#endif
+      }
+      break;
+    }
     ///////////////////
     case READ_TRT_LOCK: // read miss : check the Transaction Table
@@ -1792,13 +2263,13 @@
       {
         size_t      index     = 0;
-        vci_addr_t  addr      = (vci_addr_t) m_cmd_read_addr_fifo.read();
+        addr_t      addr      = (addr_t) m_cmd_read_addr_fifo.read();
         bool        hit_read  = m_trt.hit_read(m_nline[addr], index);
         bool        hit_write = m_trt.hit_write(m_nline[addr]);
         bool        wok       = !m_trt.full(index);
 
-        if(hit_read || !wok || hit_write)    // missing line already requested or no space
+        if(hit_read or !wok or hit_write)    // missing line already requested or no space
         {
           if(!wok)      m_cpt_trt_full++;
-          if(hit_read || hit_write)   m_cpt_trt_rb++;
+          if(hit_read or hit_write)   m_cpt_trt_rb++;
           r_read_fsm = READ_IDLE;
         }
@@ -1811,11 +2282,9 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".READ_TRT_LOCK> Check TRT:"
-                    << " hit_read = " << hit_read
-                    << " / hit_write = " << hit_write
-                    << " / full = " << !wok << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_TRT_LOCK> Check TRT:"
+          << " hit_read = " << hit_read
+          << " / hit_write = " << hit_write
+          << " / full = " << !wok << std::endl;
 #endif
       }
@@ -1830,5 +2299,5 @@
         m_trt.set(r_read_trt_index.read(),
                               true,
-                              m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                              m_nline[(addr_t)(m_cmd_read_addr_fifo.read())],
                               m_cmd_read_srcid_fifo.read(),
                               m_cmd_read_trdid_fifo.read(),
@@ -1836,16 +2305,13 @@
                               true,
                               m_cmd_read_length_fifo.read(),
-                              m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                              m_x[(addr_t)(m_cmd_read_addr_fifo.read())],
                               std::vector<be_t> (m_words,0),
                               std::vector<data_t> (m_words,0),
                               r_read_ll_key.read());
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".READ_TRT_SET> Write in Transaction Table: " << std::hex
-                    << " address = " << std::hex << m_cmd_read_addr_fifo.read()
-                    << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
-                    << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table:"
+          << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl;
 #endif
         r_read_fsm = READ_TRT_REQ;
@@ -1855,24 +2321,18 @@
 
     //////////////////
-    case READ_TRT_REQ:
-    {
-      // consume the read request in the FIFO,
-      // and send it to the ixr_cmd_fsm
-
+    case READ_TRT_REQ:   // consume the read request in FIFO and send it to IXR_CMD_FSM
+    {
       if(not r_read_to_ixr_cmd_req)
       {
         cmd_read_fifo_get       = true;
         r_read_to_ixr_cmd_req   = true;
-        r_read_to_ixr_cmd_nline = m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        r_read_to_ixr_cmd_nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
         r_read_to_ixr_cmd_trdid = r_read_trt_index.read();
         r_read_fsm              = READ_IDLE;
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name() << ".READ_TRT_REQ> Request GET transaction for address "
-              << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address "
+          << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
 #endif
       }
@@ -1914,5 +2374,5 @@
   switch(r_write_fsm.read())
   {
-      ////////////////
+    ////////////////
     case WRITE_IDLE:  // copy first word of a write burst in local buffer
     {
@@ -1929,5 +2389,5 @@
         // consume a word in the FIFO & write it in the local buffer
         cmd_write_fifo_get  = true;
-        size_t index        = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+        size_t index        = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
 
         r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
@@ -1947,5 +2407,5 @@
         }
 
-        if (m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))
+        if (m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))
         {
           r_write_fsm = WRITE_DIR_REQ;
@@ -1957,7 +2417,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_IDLE> Write request "
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
                     << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
                     << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
@@ -1976,8 +2436,8 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name()
-                    << ".WRITE_NEXT> Write another word in local buffer"
+                    << " WRITE_NEXT> Write another word in local buffer"
                     << std::endl;
         }
@@ -1986,6 +2446,6 @@
 
         // check that the next word is in the same cache line
-        if((m_nline[(vci_addr_t)(r_write_address.read())]       !=
-            m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())]))
+        if((m_nline[(addr_t)(r_write_address.read())]       !=
+            m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]))
         {
           std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_NEXT state" << std::endl
@@ -2029,5 +2489,5 @@
           if(not m_cmd_write_addr_fifo.rok()) break;
 
-          assert(m_cmd_write_eop_fifo.read() &&
+          assert(m_cmd_write_eop_fifo.read() and
                  "Error in VCI_MEM_CACHE : "
                  "invalid packet format for SC command");
@@ -2060,8 +2520,8 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
+      if(m_debug)
       {
         std::cout
-            << "  <MEMC " << name() << ".WRITE_DIR_REQ> Requesting DIR lock "
+            << "  <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "
             << std::endl;
       }
@@ -2095,5 +2555,5 @@
           r_write_way        = way;
 
-          if(entry.is_cnt && entry.count)
+          if(entry.is_cnt and entry.count)
           {
             r_write_fsm = WRITE_DIR_READ;
@@ -2110,7 +2570,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> Check the directory: "
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
                     << " address = " << std::hex << r_write_address.read()
                     << " hit = " << std::dec << entry.valid
@@ -2118,7 +2578,7 @@
                     << " is_cnt = " << entry.is_cnt << std::endl;
           if((r_write_pktid.read() & 0x7) == TYPE_SC)
-            std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> global_llsc_table SC access" << std::endl;
+            std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_table SC access" << std::endl;
           else
-            std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> global_llsc_table SW access" << std::endl;
+            std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_table SW access" << std::endl;
         }
 #endif
@@ -2140,5 +2600,5 @@
     {
       // update local buffer
-      size_t set  = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t set  = m_y[(addr_t)(r_write_address.read())];
       size_t way  = r_write_way.read();
       for(size_t word=0 ; word<m_words ; word++)
@@ -2160,7 +2620,7 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
+      if(m_debug)
+      {
+        std::cout << "  <MEMC " << name() << " WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
       }
 #endif
@@ -2187,5 +2647,5 @@
       entry.ptr            = r_write_ptr.read();
 
-      size_t set           = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t set           = m_y[(addr_t)(r_write_address.read())];
       size_t way           = r_write_way.read();
 
@@ -2202,5 +2662,6 @@
       // no_update is true when there is no need for coherence transaction
       // (tests for sc requests)
-      bool no_update = ((r_write_count.read() ==0) || (owner && (r_write_count.read() ==1) && (r_write_pktid.read() != TYPE_SC)));
+      bool no_update = ( (r_write_count.read() == 0) or
+                         (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC)));
 
       // write data in the cache if no coherence transaction
@@ -2213,8 +2674,9 @@
           if(m_monitor_ok)
           {
-            vci_addr_t address = (r_write_address.read() & ~(vci_addr_t) 0x3F) | word<<2;
+            addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
             char buf[80];
-            snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", r_write_srcid.read());
-            check_monitor(buf, address, r_write_data[word].read());
+            snprintf(buf, 80, "WRITE_DIR_HIT srcid %d",
+                     (int)r_write_srcid.read());
+            check_monitor(buf, address, r_write_data[word].read(), false);
           }
         }
@@ -2234,6 +2696,6 @@
       // coherence update required
       {
-        if(!r_write_to_cc_send_multi_req.read()   &&
-            !r_write_to_cc_send_brdcast_req.read())
+        if(!r_write_to_cc_send_multi_req.read() and
+           !r_write_to_cc_send_brdcast_req.read())
         {
           r_write_fsm = WRITE_UPT_LOCK;
@@ -2246,20 +2708,20 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
-      {
-        if(no_update)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Write into cache / No coherence transaction"
-                    << std::endl;
-        }
-        else
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Coherence update required:"
-                    << " is_cnt = " << r_write_is_cnt.read()
-                    << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
-          if(owner)
-            std::cout << "       ... but the first copy is the writer" << std::endl;
-        }
-      }
+if(m_debug)
+{
+    if(no_update)
+    {
+        std::cout << "  <MEMC " << name() 
+                  << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
+                  << std::endl;
+    }
+    else
+    {
+        std::cout << "  <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"
+                  << " is_cnt = " << r_write_is_cnt.read()
+                  << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
+        if(owner) std::cout << "       ... but the first copy is the writer" << std::endl;
+    }
+}
 #endif
       break;
@@ -2276,30 +2738,35 @@
         size_t      trdid      = r_write_trdid.read();
         size_t      pktid      = r_write_pktid.read();
-        addr_t      nline      = m_nline[(vci_addr_t)(r_write_address.read())];
+        addr_t      nline      = m_nline[(addr_t)(r_write_address.read())];
         size_t      nb_copies  = r_write_count.read();
-        size_t      set        = m_y[(vci_addr_t)(r_write_address.read())];
+        size_t      set        = m_y[(addr_t)(r_write_address.read())];
         size_t      way        = r_write_way.read();
 
         wok = m_upt.set(true,  // it's an update transaction
-                               false,    // it's not a broadcast
-                               true,     // it needs a response
-                               srcid,
-                               trdid,
-                               pktid,
-                               nline,
-                               nb_copies,
-                               index);
+                        false,    // it's not a broadcast
+                        true,     // response required
+                        false,    // no acknowledge required
+                        srcid,    
+                        trdid,
+                        pktid,
+                        nline,
+                        nb_copies,
+                        index);
         if(wok)       // write data in cache
         {
           for(size_t word=0 ; word<m_words ; word++)
           {
-            m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
+            m_cache_data.write(way,
+                               set,
+                               word,
+                               r_write_data[word].read(),
+                               r_write_be[word].read());
 
             if(m_monitor_ok)
             {
-              vci_addr_t address = (r_write_address.read() & ~(vci_addr_t) 0x3F) | word<<2;
+              addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
               char buf[80];
-              snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", srcid);
-              check_monitor(buf, address, r_write_data[word].read());
+              snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", (int)srcid);
+              check_monitor(buf, address, r_write_data[word].read(), false);
             }
           }
@@ -2307,12 +2774,13 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          if(wok)
-          {
-            std::cout << "  <MEMC " << name() << ".WRITE_UPT_LOCK> Register the multicast update in UPT / "
-                      << " nb_copies = " << r_write_count.read() << std::endl;
-          }
-        }
+if(m_debug)
+{
+    if(wok)
+    {
+        std::cout << "  <MEMC " << name() 
+                  << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
+                  << " nb_copies = " << r_write_count.read() << std::endl;
+    }
+}
 #endif
         r_write_upt_index = index;
@@ -2331,8 +2799,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() 
+          << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
 #endif
         r_write_fsm = WRITE_UPT_REQ;
@@ -2342,49 +2809,43 @@
 
     //////////////////
-    case WRITE_UPT_REQ:
-    {
-      // prepare the coherence transaction for the CC_SEND FSM
-      // and write the first copy in the FIFO
-      // send the request if only one copy
-
-      if(!r_write_to_cc_send_multi_req.read() &&
-          !r_write_to_cc_send_brdcast_req.read())    // no pending coherence request
-      {
-        r_write_to_cc_send_brdcast_req  = false;
-        r_write_to_cc_send_trdid        = r_write_upt_index.read();
-        r_write_to_cc_send_nline        = m_nline[(vci_addr_t)(r_write_address.read())];
-        r_write_to_cc_send_index        = r_write_word_index.read();
-        r_write_to_cc_send_count        = r_write_word_count.read();
-
-        for(size_t i=0; i<m_words ; i++) r_write_to_cc_send_be[i]=r_write_be[i].read();
-
-        size_t min = r_write_word_index.read();
-        size_t max = r_write_word_index.read() + r_write_word_count.read();
-        for(size_t i=min ; i<max ; i++) r_write_to_cc_send_data[i] = r_write_data[i];
-
-        if((r_write_copy.read() != r_write_srcid.read()) or(r_write_pktid.read() == TYPE_SC) or
+    case WRITE_UPT_REQ:    // prepare the coherence transaction for the CC_SEND FSM
+                           // and write the first copy in the FIFO
+                           // send the request if only one copy
+    {
+      assert(not r_write_to_cc_send_multi_req.read()   and
+             not r_write_to_cc_send_brdcast_req.read() and
+             "Error in VCI_MEM_CACHE : pending multicast or broadcast\n"
+             "transaction in WRITE_UPT_REQ state"
+            );
+
+      r_write_to_cc_send_brdcast_req  = false;
+      r_write_to_cc_send_trdid        = r_write_upt_index.read();
+      r_write_to_cc_send_nline        = m_nline[(addr_t)(r_write_address.read())];
+      r_write_to_cc_send_index        = r_write_word_index.read();
+      r_write_to_cc_send_count        = r_write_word_count.read();
+
+      for(size_t i=0; i<m_words ; i++) r_write_to_cc_send_be[i]=r_write_be[i].read();
+
+      size_t min = r_write_word_index.read();
+      size_t max = r_write_word_index.read() + r_write_word_count.read();
+      for(size_t i=min ; i<max ; i++) r_write_to_cc_send_data[i] = r_write_data[i];
+
+      if((r_write_copy.read() != r_write_srcid.read()) or(r_write_pktid.read() == TYPE_SC) or
 #if L1_MULTI_CACHE
-            (r_write_copy_cache.read() != r_write_pktid.read()) or
-#endif
-            r_write_copy_inst.read())
-        {
-          // put the first srcid in the fifo
-          write_to_cc_send_fifo_put     = true;
-          write_to_cc_send_fifo_inst    = r_write_copy_inst.read();
-          write_to_cc_send_fifo_srcid   = r_write_copy.read();
+          (r_write_copy_cache.read() != r_write_pktid.read()) or
+#endif
+          r_write_copy_inst.read())
+      {
+        // put the first srcid in the fifo
+        write_to_cc_send_fifo_put     = true;
+        write_to_cc_send_fifo_inst    = r_write_copy_inst.read();
+        write_to_cc_send_fifo_srcid   = r_write_copy.read();
 #if L1_MULTI_CACHE
-          write_to_cc_send_fifo_cache_id= r_write_copy_cache.read();
-#endif
-          if(r_write_count.read() == 1)
-          {
-            r_write_fsm = WRITE_IDLE;
-            r_write_to_cc_send_multi_req = true;
-          }
-          else
-          {
-            r_write_fsm = WRITE_UPT_NEXT;
-            r_write_to_dec = false;
-
-          }
+        write_to_cc_send_fifo_cache_id= r_write_copy_cache.read();
+#endif
+        if(r_write_count.read() == 1)
+        {
+          r_write_fsm = WRITE_IDLE;
+          r_write_to_cc_send_multi_req = true;
         }
         else
@@ -2392,17 +2853,26 @@
           r_write_fsm = WRITE_UPT_NEXT;
           r_write_to_dec = false;
-        }
+
+        }
+      }
+      else
+      {
+        r_write_fsm = WRITE_UPT_NEXT;
+        r_write_to_dec = false;
+      }
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_UPT_REQ> Post first request to CC_SEND FSM"
-                    << " / srcid = " << std::dec << r_write_copy.read()
-                    << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
-          if(r_write_count.read() == 1)
-            std::cout << "         ... and this is the last" << std::endl;
-        }
-#endif
-      }
+      if(m_debug)
+      {
+        std::cout
+          << "  <MEMC "    << name()
+          << " WRITE_UPT_REQ> Post first request to CC_SEND FSM"
+          << " / srcid = " << std::dec << r_write_copy.read()
+          << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
+
+        if(r_write_count.read() == 1)
+          std::cout << "         ... and this is the last" << std::endl;
+      }
+#endif
       break;
     }
@@ -2424,5 +2894,5 @@
       bool dec_upt_counter;
 
-      if(((entry.owner.srcid != r_write_srcid.read()) || (r_write_pktid.read() == TYPE_SC)) or
+      if(((entry.owner.srcid != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC)) or
 #if L1_MULTI_CACHE
           (entry.owner.cache_id != r_write_pktid.read()) or
@@ -2439,7 +2909,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Post another request to CC_SEND FSM"
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM"
                     << " / heap_index = " << std::dec << r_write_ptr.read()
                     << " / srcid = " << std::dec << r_write_copy.read()
@@ -2455,7 +2925,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
                     << " / heap_index = " << std::dec << r_write_ptr.read()
                     << " / srcid = " << std::dec << r_write_copy.read()
@@ -2535,5 +3005,5 @@
           // consume a word in the FIFO & write it in the local buffer
           cmd_write_fifo_get  = true;
-          size_t index        = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+          size_t index        = m_x[(addr_t)(m_cmd_write_addr_fifo.read())];
 
           r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
@@ -2553,5 +3023,5 @@
           }
 
-          if(m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7)  == TYPE_SC))
+          if(m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7)  == TYPE_SC))
           {
             r_write_fsm = WRITE_DIR_REQ;
@@ -2568,16 +3038,16 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
-                    << std::dec << r_write_srcid.read() << std::endl;
-          if(m_cmd_write_addr_fifo.rok())
-          {
-            std::cout << "                    New Write request: "
-                      << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
-                      << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
-                      << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
-          }
-        }
+if(m_debug)
+{
+    std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM"
+              << " : rsrcid = " << std::hex << r_write_srcid.read() << std::endl;
+    if(m_cmd_write_addr_fifo.rok())
+    {
+        std::cout << "                    New Write request: "
+                  << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
+                  << " / address = " << m_cmd_write_addr_fifo.read()
+                  << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
+    }
+}
 #endif
       }
@@ -2592,12 +3062,10 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
 #endif
         size_t  hit_index = 0;
         size_t  wok_index = 0;
-        vci_addr_t  addr  = (vci_addr_t) r_write_address.read();
+        addr_t  addr  = (addr_t) r_write_address.read();
         bool    hit_read  = m_trt.hit_read(m_nline[addr], hit_index);
         bool    hit_write = m_trt.hit_write(m_nline[addr]);
@@ -2610,5 +3078,5 @@
           m_cpt_write_miss++;
         }
-        else if(wok && !hit_write)      // set a new entry in TRT
+        else if(wok and !hit_write)      // set a new entry in TRT
         {
           r_write_trt_index = wok_index;
@@ -2628,9 +3096,8 @@
     case WRITE_WAIT:  // release the locks protecting the shared ressources
     {
+
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".WRITE_WAIT> Releases the locks before retry" << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl;
 #endif
       r_write_fsm = WRITE_DIR_REQ;
@@ -2654,5 +3121,5 @@
         m_trt.set(r_write_trt_index.read(),
                               true,     // read request to XRAM
-                              m_nline[(vci_addr_t)(r_write_address.read())],
+                              m_nline[(addr_t)(r_write_address.read())],
                               r_write_srcid.read(),
                               r_write_trdid.read(),
@@ -2666,8 +3133,6 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
 #endif
       }
@@ -2695,9 +3160,6 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
-          m_trt.print(r_write_trt_index.read());
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
 #endif
       }
@@ -2712,13 +3174,11 @@
         r_write_to_ixr_cmd_req   = true;
         r_write_to_ixr_cmd_write = false;
-        r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_ixr_cmd_nline = m_nline[(addr_t)(r_write_address.read())];
         r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
         r_write_fsm              = WRITE_RSP;
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
 #endif
       }
@@ -2744,9 +3204,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_BC_TRT_LOCK> Check TRT : wok = "
-                    << wok << " / index = " << wok_index << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT"
+          << " : wok = " << wok << " / index = " << wok_index << std::endl;
 #endif
       }
@@ -2764,26 +3222,22 @@
         size_t      trdid     = r_write_trdid.read();
         size_t      pktid     = r_write_pktid.read();
-        addr_t      nline     = m_nline[(vci_addr_t)(r_write_address.read())];
+        addr_t      nline     = m_nline[(addr_t)(r_write_address.read())];
         size_t      nb_copies = r_write_count.read();
 
-        wok =m_upt.set(false,  // it's an inval transaction
-                              true,     // it's a broadcast
-                              true,     // it needs a response
-                              srcid,
-                              trdid,
-                              pktid,
-                              nline,
-                              nb_copies,
-                              index);
+        wok = m_upt.set(false,  // it's an inval transaction
+                        true,     // it's a broadcast
+                        true,     // response required
+                        false,    // no acknowledge required
+                        srcid,
+                        trdid,
+                        pktid,
+                        nline,
+                        nb_copies,
+                        index);
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          if(wok)
-          {
-            std::cout << "  <MEMC " << name() << ".WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "
-                      << " nb_copies = " << r_write_count.read() << std::endl;
-          }
-        }
+if( m_debug and wok )
+std::cout << "  <MEMC " << name() << " WRITE_BC_UPT_LOCK> Register broadcast inval in UPT"
+          << " / nb_copies = " << r_write_count.read() << std::endl;
 #endif
         r_write_upt_index = index;
@@ -2800,6 +3254,6 @@
       // Register a put transaction to XRAM in TRT
       // and invalidate the line in directory
-      if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) ||
-          (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) ||
+      if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or
+          (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or
           (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE))
       {
@@ -2812,5 +3266,5 @@
       m_trt.set(r_write_trt_index.read(),
                             false,    // write request to XRAM
-                            m_nline[(vci_addr_t)(r_write_address.read())],
+                            m_nline[(addr_t)(r_write_address.read())],
                             0,
                             0,
@@ -2836,5 +3290,5 @@
       entry.ptr           = 0;
       entry.count         = 0;
-      size_t set          = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t set          = m_y[(addr_t)(r_write_address.read())];
       size_t way          = r_write_way.read();
 
@@ -2842,9 +3296,7 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug_write_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
-                  << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
+          << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
 #endif
       r_write_fsm = WRITE_BC_CC_SEND;
@@ -2855,10 +3307,10 @@
     case WRITE_BC_CC_SEND:    // Post a coherence broadcast request to CC_SEND FSM
     {
-      if(!r_write_to_cc_send_multi_req.read() && !r_write_to_cc_send_brdcast_req.read())
+      if(!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read())
       {
         r_write_to_cc_send_multi_req   = false;
         r_write_to_cc_send_brdcast_req = true;
         r_write_to_cc_send_trdid       = r_write_upt_index.read();
-        r_write_to_cc_send_nline       = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_cc_send_nline       = m_nline[(addr_t)(r_write_address.read())];
         r_write_to_cc_send_index       = 0;
         r_write_to_cc_send_count       = 0;
@@ -2872,8 +3324,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl;
 #endif
       }
@@ -2888,5 +3339,5 @@
         r_write_to_ixr_cmd_req     = true;
         r_write_to_ixr_cmd_write   = true;
-        r_write_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_ixr_cmd_nline   = m_nline[(addr_t)(r_write_address.read())];
         r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
 
@@ -2896,8 +3347,7 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug_write_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
 #endif
       }
@@ -2910,48 +3360,59 @@
   ///////////////////////////////////////////////////////////////////////
   // The IXR_CMD fsm controls the command packets to the XRAM :
-  // - It sends a single cell VCI read request to the XRAM in case of MISS
+  // It handles requests from the READ, WRITE, CAS, XRAM_RSP FSMs
+  // with a round-robin priority.
+  //
+  // - It sends a single flit VCI read request to the XRAM in case of MISS
   // posted by the READ, WRITE or CAS FSMs : the TRDID field contains
   // the Transaction Tab index.
-  // The VCI response is a multi-cell packet : the N cells contain
+  // The VCI response is a multi-flit packet : the N cells contain
   // the N data words.
-  // - It sends a multi-cell VCI write when the XRAM_RSP FSM, WRITE FSM
+  //
+  // - It sends a multi-flit VCI write when the XRAM_RSP FSM, WRITE FSM
   // or CAS FSM request to save a dirty line to the XRAM.
-  // The VCI response is a single cell packet.
-  // This FSM handles requests from the READ, WRITE, CAS & XRAM_RSP FSMs
-  // with a round-robin priority.
+  // The VCI response is a single flit packet.
   ////////////////////////////////////////////////////////////////////////
 
   switch(r_ixr_cmd_fsm.read())
   {
-      ////////////////////////
+    ////////////////////////
     case IXR_CMD_READ_IDLE:
-      if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      break;
-      ////////////////////////
+    {
+      if     (r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      break;
+    }
+    ////////////////////////
     case IXR_CMD_WRITE_IDLE:
-      if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
-      break;
-      ////////////////////////
+    {
+      if     (r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      break;
+    }
+    ////////////////////////
     case IXR_CMD_CAS_IDLE:
-      if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
-      break;
-      ////////////////////////
+    {
+      if     (r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      break;
+    }
+    ////////////////////////
     case IXR_CMD_XRAM_IDLE:
-      if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
-      break;
-      /////////////////////////       // send a get request to XRAM
-    case IXR_CMD_READ_NLINE:
+    {
+      if     (r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      break;
+    }
+    //////////////////       // send a get from READ FSM
+    case IXR_CMD_READ:
+    {
       if(p_vci_ixr.cmdack)
       {
@@ -2960,18 +3421,20 @@
 
 #if DEBUG_MEMC_IXR_CMD
-        if(m_debug_ixr_cmd_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
-        }
-#endif
-      }
-      break;
-      //////////////////////////
-    case IXR_CMD_WRITE_NLINE:     // send a put or get command to XRAM
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_READ>"
+          << " Send a get request to xram / address = " << std::hex
+          << (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
+#endif
+      }
+      break;
+    }
+    ///////////////////
+    case IXR_CMD_WRITE:     // send a put or get from WRITE FSM
+    {
       if(p_vci_ixr.cmdack)
       {
-        if(r_write_to_ixr_cmd_write.read())
-        {
-          if(r_ixr_cmd_cpt.read() == (m_words - 1))
+        if(r_write_to_ixr_cmd_write.read())   // PUT
+        {
+          if(r_ixr_cmd_cpt.read() == (m_words - 2))
           {
             r_ixr_cmd_cpt = 0;
@@ -2981,15 +3444,16 @@
           else
           {
-            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
           }
 
 #if DEBUG_MEMC_IXR_CMD
-          if(m_debug_ixr_cmd_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
-          }
-#endif
-        }
-        else
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
+          << " Send a put request to xram / address = " << std::hex
+          << (addr_t)((r_write_to_ixr_cmd_nline.read() * m_words +
+                      r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
+#endif
+        }
+        else                                  // GET
         {
           r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
@@ -2997,19 +3461,21 @@
 
 #if DEBUG_MEMC_IXR_CMD
-          if(m_debug_ixr_cmd_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
-          }
-#endif
-        }
-      }
-      break;
-      //////////////////////
-    case IXR_CMD_CAS_NLINE:      // send a put or get command to XRAM
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
+          << " Send a get request to xram / address = " << std::hex
+          << (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
+#endif
+        }
+      }
+      break;
+    }
+    /////////////////
+    case IXR_CMD_CAS:      // send a put or get command from CAS FSM
+    {
       if(p_vci_ixr.cmdack)
       {
-        if(r_cas_to_ixr_cmd_write.read())
-        {
-          if(r_ixr_cmd_cpt.read() == (m_words - 1))
+        if(r_cas_to_ixr_cmd_write.read()) // PUT
+        {
+          if(r_ixr_cmd_cpt.read() == (m_words - 2))
           {
             r_ixr_cmd_cpt = 0;
@@ -3019,15 +3485,16 @@
           else
           {
-            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
           }
 
 #if DEBUG_MEMC_IXR_CMD
-          if(m_debug_ixr_cmd_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_CMD_CAS_NLINE> Send a put request to xram" << std::endl;
-          }
-#endif
-        }
-        else
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
+          << " Send a put request to xram / address = " << std::hex
+          << (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words +
+                      r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
+#endif
+        }
+        else                            // GET
         {
           r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE;
@@ -3035,17 +3502,19 @@
 
 #if DEBUG_MEMC_IXR_CMD
-          if(m_debug_ixr_cmd_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_CMD_CAS_NLINE> Send a get request to xram" << std::endl;
-          }
-#endif
-        }
-      }
-      break;
-      ////////////////////////
-    case IXR_CMD_XRAM_DATA:     // send a put command to XRAM
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
+          << " Send a get request to xram / address = " << std::hex
+          << (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
+#endif
+        }
+      }
+      break;
+    }
+    //////////////////
+    case IXR_CMD_XRAM:     // send a put from XRAM_RSP FSM
+    {
       if(p_vci_ixr.cmdack)
       {
-        if(r_ixr_cmd_cpt.read() == (m_words - 1))
+        if(r_ixr_cmd_cpt.read() == (m_words - 2))
         {
           r_ixr_cmd_cpt = 0;
@@ -3055,15 +3524,17 @@
         else
         {
-          r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+          r_ixr_cmd_cpt = r_ixr_cmd_cpt + 2;
         }
 
 #if DEBUG_MEMC_IXR_CMD
-        if(m_debug_ixr_cmd_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
-        }
-#endif
-      }
-      break;
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM>"
+          << " Send a put request to xram / address = " << std::hex
+          << (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words +
+                       r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
+#endif
+      }
+      break;
+    }
 
   } // end switch r_ixr_cmd_fsm
@@ -3090,6 +3561,6 @@
   switch(r_ixr_rsp_fsm.read())
   {
-      //////////////////
-    case IXR_RSP_IDLE:  // test if it's a get or a put transaction
+    //////////////////
+    case IXR_RSP_IDLE:  // test transaction type: PUT/GET
     {
       if(p_vci_ixr.rspval.read())
@@ -3097,39 +3568,35 @@
         r_ixr_rsp_cpt   = 0;
         r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
-        if(p_vci_ixr.reop.read() && !(p_vci_ixr.rerror.read() &0x1))   // put transaction
+        if(p_vci_ixr.reop.read() and !(p_vci_ixr.rerror.read() &0x1))   // PUT transaction
         {
           r_ixr_rsp_fsm = IXR_RSP_ACK;
 
 #if DEBUG_MEMC_IXR_RSP
-          if(m_debug_ixr_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
-          }
-#endif
-        }
-        else                     // get transaction
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
+#endif
+        }
+        else                                                         // GET transaction
         {
           r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
 
 #if DEBUG_MEMC_IXR_RSP
-          if(m_debug_ixr_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
-          }
-#endif
-        }
-      }
-      break;
-    }
-    ////////////////////////
-    case IXR_RSP_ACK:        // Aknowledge the VCI response
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
+#endif
+        }
+      }
+      break;
+    }
+    /////////////////
+    case IXR_RSP_ACK:        // Aknowledge the VCI response for a PUT
     {
       if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
 
 #if DEBUG_MEMC_IXR_RSP
-      if(m_debug_ixr_rsp_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".IXR_RSP_ACK>" << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_RSP_ACK>" << std::endl;
 #endif
       break;
@@ -3144,29 +3611,31 @@
 
 #if DEBUG_MEMC_IXR_RSP
-        if(m_debug_ixr_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_ERASE> Erase TRT entry "
-                    << r_ixr_rsp_trt_index.read() << std::endl;
-        }
-#endif
-      }
-      break;
-    }
-    ///////////////////////
-    case IXR_RSP_TRT_READ:    // write data in the TRT
-    {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval)
-      {
-        size_t index    = r_ixr_rsp_trt_index.read();
-        bool   eop    = p_vci_ixr.reop.read();
-        data_t data   = p_vci_ixr.rdata.read();
-        bool   error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
-        assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || p_vci_ixr.rerror.read())
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry "
+          << r_ixr_rsp_trt_index.read() << std::endl;
+#endif
+      }
+      break;
+    }
+    //////////////////////
+    case IXR_RSP_TRT_READ:    // write a 64 bits data in the TRT
+    {
+      if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and  p_vci_ixr.rspval)
+      {
+        size_t      index    = r_ixr_rsp_trt_index.read();
+        bool        eop      = p_vci_ixr.reop.read();
+        wide_data_t data     = p_vci_ixr.rdata.read();
+        bool        error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
+
+        assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) or p_vci_ixr.rerror.read())
                and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
-        m_trt.write_rsp(index,
-                                    r_ixr_rsp_cpt.read(),
-                                    data,
-                                    error);
-        r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+
+        m_trt.write_rsp( index,
+                         r_ixr_rsp_cpt.read(),
+                         data,
+                         error);
+
+        r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 2;
+
         if(eop)
         {
@@ -3176,11 +3645,9 @@
 
 #if DEBUG_MEMC_IXR_RSP
-        if(m_debug_ixr_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_READ> Writing a word in TRT : "
-                    << " index = " << std::dec << index
-                    << " / word = " << r_ixr_rsp_cpt.read()
-                    << " / data = " << std::hex << data << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : "
+          << " index = " << std::dec << index
+          << " / word = " << r_ixr_rsp_cpt.read()
+          << " / data = " << std::hex << data << std::endl;
 #endif
       }
@@ -3200,5 +3667,5 @@
   //
   // When a response is available, the corresponding TRT entry
-  // must be copied in a local buffer to be written in the cache.
+  // is copied in a local buffer to be written in the cache.
   // The FSM takes the lock protecting the TRT, and the lock protecting the DIR.
   // It selects a cache slot and writes the line in the cache.
@@ -3214,6 +3681,6 @@
   switch(r_xram_rsp_fsm.read())
   {
-      ///////////////////
-    case XRAM_RSP_IDLE: // scan the XRAM responses to get the TRT index (round robin)
+    ///////////////////
+    case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin)
     {
       size_t ptr   = r_xram_rsp_trt_index.read();
@@ -3221,5 +3688,5 @@
       for(size_t i=0 ; i<lines ; i++)
       {
-        size_t index= (i+ptr+1) %lines;
+        size_t index = (i+ptr+1) %lines;
         if(r_ixr_rsp_to_xram_rsp_rok[index])
         {
@@ -3229,9 +3696,8 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-          if(m_debug_xram_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".XRAM_RSP_IDLE> Available cache line in TRT:"
-                      << " index = " << std::dec << index << std::endl;
-          }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_IDLE>"
+          << " Available cache line in TRT:"
+          << " index = " << std::dec << index << std::endl;
 #endif
           break;
@@ -3241,25 +3707,20 @@
     }
     ///////////////////////
-    case XRAM_RSP_DIR_LOCK:
-      // Takes the lock on the directory
-      // Takes the lock on TRT
-      // Copy the TRT entry in a local buffer
-    {
-      if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) &&
+    case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock
+                            // Copy the TRT entry in a local buffer
+    {
+      if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and
           (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP))
       {
         // copy the TRT entry in the r_xram_rsp_trt_buf local buffer
         size_t  index = r_xram_rsp_trt_index.read();
-
-        TransactionTabEntry trt_entry(m_trt.read(index));
-        r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+        r_xram_rsp_trt_buf.copy( m_trt.read(index) );
 
         r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_LOCK>"
+          << " Get access to DIR and TRT" << std::endl;
 #endif
       }
@@ -3267,16 +3728,17 @@
     }
     ///////////////////////
-    case XRAM_RSP_TRT_COPY:
-      // Select a victim cache line
-    {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP))
+    case XRAM_RSP_TRT_COPY: // Select a victim cache line
+                            // and copy it in a local buffer
+    {
+      if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+           (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) )
       {
         // selects & extracts a victim line from cache
         size_t way = 0;
-        size_t set = m_y[(vci_addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)];
+        size_t set = m_y[(addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)];
 
         DirectoryEntry victim(m_cache_directory.select(set, way));
 
-        bool inval = (victim.count && victim.valid) ;
+        bool inval = (victim.count and victim.valid) ;
 
         // copy the victim line in a local buffer
@@ -3284,4 +3746,5 @@
 
         r_xram_rsp_victim_copy      = victim.owner.srcid;
+
 #if L1_MULTI_CACHE
         r_xram_rsp_victim_copy_cache= victim.owner.cache_id;
@@ -3307,19 +3770,16 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_COPY> Select a slot: "
-                    << " way = " << std::dec << way
-                    << " / set = " << set
-                    << " / inval_required = " << inval << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
+          << " Select a slot: "
+          << " way = " << std::dec << way
+          << " / set = " << set
+          << " / inval_required = " << inval << std::endl;
 #endif
       }
       else
       {
-        std::cout << "VCI_MEM_CACHE ERROR "     << name()
-                  << " XRAM_RSP_TRT_COPY state" << std::endl
-                  << "bad TRT allocation"       << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY"
+                  << " bad TRT or DIR allocation" << std::endl;
         exit(0);
       }
@@ -3327,34 +3787,30 @@
     }
     /////////////////////////
-    case XRAM_RSP_INVAL_LOCK: // check a possible pending inval
+    case XRAM_RSP_INVAL_LOCK: // Take the UPT lock to check a possible pending inval
     {
       if(r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP)
       {
-        size_t index;
-        if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index))
+        size_t index = 0;
+        if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index))  // pending inval
         {
           r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
-          if(m_debug_xram_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
-                      << " but an invalidation is already registered at this address" << std::endl;
-            m_upt.print();
-          }
-#endif
-
-        }
-        else if(m_upt.is_full() && r_xram_rsp_victim_inval.read())
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+          << " Get acces to UPT, but line invalidation registered"
+          << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline
+          << " / index = " << std::dec << index << std::endl;
+#endif
+
+        }
+        else if(m_upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full
         {
           r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
-          if(m_debug_xram_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
-                      << " but the table is full" << std::endl;
-            m_upt.print();
-          }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+          << " Get acces to UPT, but inval required and UPT full" << std::endl;
 #endif
         }
@@ -3364,8 +3820,7 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-          if(m_debug_xram_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
-          }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+          << " Get acces to UPT" << std::endl;
 #endif
         }
@@ -3374,6 +3829,12 @@
     }
     /////////////////////////
-    case XRAM_RSP_INVAL_WAIT: // returns to DIR_LOCK to retry
-    {
+    case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry
+    {
+
+#if DEBUG_MEMC_XRAM_RSP
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>"
+          << " Release all locks and retry" << std::endl;
+#endif
       r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
       break;
@@ -3381,17 +3842,19 @@
     ///////////////////////
     case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory)
-      // and possibly set an inval request in UPT
-    {
-      // signals generation
+                              // and possibly set an inval request in UPT
+    {
       // check if this is an instruction read, this means pktid is either
       // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
       // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-      bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) && r_xram_rsp_trt_buf.proc_read;
+      bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read;
+
       // check if this is a cached read, this means pktid is either
       // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
       // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
-      bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) && r_xram_rsp_trt_buf.proc_read;
-
-      // update data
+      bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read;
+
+      bool dirty = false;
+
+      // update cache data
       size_t set   = r_xram_rsp_victim_set.read();
       size_t way   = r_xram_rsp_victim_way.read();
@@ -3400,14 +3863,14 @@
         m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
 
+        dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0);
+
         if(m_monitor_ok)
         {
-          vci_addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
-          check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word]);
-        }
-      }
-      // compute dirty
-      bool dirty = false;
-      for(size_t i=0; i<m_words; i++) dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
-      // update directory
+          addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
+          check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word], false);
+        }
+      }
+
+      // update cache directory
       DirectoryEntry entry;
       entry.valid   = true;
@@ -3437,25 +3900,28 @@
       m_cache_directory.write(set, way, entry);
 
+      // request an invalidattion request in UPT for victim line
       if(r_xram_rsp_victim_inval.read())
       {
-        bool   brdcast    = r_xram_rsp_victim_is_cnt.read();
-        size_t index    = 0;
-        size_t count_copies   = r_xram_rsp_victim_count.read();
+        bool   broadcast    = r_xram_rsp_victim_is_cnt.read();
+        size_t index        = 0;
+        size_t count_copies = r_xram_rsp_victim_count.read();
 
         bool   wok = m_upt.set(false,      // it's an inval transaction
-                                      brdcast,  // set brdcast bit
-                                      false,    // it does not need a response
-                                      0,    // srcid
-                                      0,    // trdid
-                                      0,    // pktid
-                                      r_xram_rsp_victim_nline.read(),
-                                      count_copies,
-                                      index);
+                               broadcast,  // set broadcast bit
+                               false,      // no response required 
+                               false,      // no acknowledge required 
+                               0,          // srcid
+                               0,          // trdid
+                               0,          // pktid
+                               r_xram_rsp_victim_nline.read(),
+                               count_copies,
+                               index);
+
         r_xram_rsp_upt_index = index;
 
         if(!wok)
         {
-          std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST state" << std::endl;
-          std::cout << "an update_tab entry was free but write is unsuccessful" << std::endl;
+          std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT"
+                    << " update_tab entry free but write unsuccessful" << std::endl;
           exit(0);
         }
@@ -3463,33 +3929,34 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-      if(m_debug_xram_rsp_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_UPDT> Directory update: "
-                  << " way = " << std::dec << way
-                  << " / set = " << set
-                  << " / owner_id = " << entry.owner.srcid
-                  << " / owner_ins = " << entry.owner.inst
-                  << " / count = " << entry.count
-                  << " / is_cnt = " << entry.is_cnt << std::endl;
-        if(r_xram_rsp_victim_inval.read())
-          std::cout << "                           Invalidation request for victim line "
-                    << std::hex << r_xram_rsp_victim_nline.read()
-                    << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl;
-      }
-#endif
-
-      // If the victim is not dirty, we don't need another XRAM  put transaction,
-      // and we canwe erase the TRT entry
+if(m_debug)
+{
+std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_UPDT>"
+          << " Cache update: "
+          << " way = " << std::dec << way
+          << " / set = " << set
+          << " / owner_id = " << std::hex << entry.owner.srcid
+          << " / owner_ins = " << std::dec << entry.owner.inst
+          << " / count = " << entry.count
+          << " / is_cnt = " << entry.is_cnt << std::endl;
+if(r_xram_rsp_victim_inval.read())
+std::cout << "                           Invalidation request for victim line "
+          << std::hex << r_xram_rsp_victim_nline.read()
+          << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl;
+}
+#endif
+
+      // If the victim is not dirty, we don't need another XRAM put transaction,
+      // and we can erase the TRT entry
       if(!r_xram_rsp_victim_dirty.read())  m_trt.erase(r_xram_rsp_trt_index.read());
 
       // Next state
       if(r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
-      else if(r_xram_rsp_trt_buf.proc_read)       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
-      else if(r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
-      else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+      else if(r_xram_rsp_trt_buf.proc_read)    r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+      else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
+      else                                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
       break;
     }
     ////////////////////////
-    case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (write to XRAM) if the victim is dirty
+    case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (PUT to XRAM) if the victim is dirty
     {
       if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
@@ -3508,13 +3975,12 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
-                    << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-        }
-#endif
-        if(r_xram_rsp_trt_buf.proc_read)       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
-        else if(r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
-        else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
+          << " Set TRT entry for the put transaction"
+          << " / dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+#endif
+        if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+        else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
+        else                                     r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
       }
       break;
@@ -3528,5 +3994,8 @@
         r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
         r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
-        for(size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+        for(size_t i=0; i < m_words; i++)
+        {
+            r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+        }
         r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
         r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
@@ -3535,17 +4004,15 @@
         r_xram_rsp_to_tgt_rsp_req    = true;
 
-        if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+        if(r_xram_rsp_victim_inval)      r_xram_rsp_fsm = XRAM_RSP_INVAL;
         else if(r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-        else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
-
+        else                             r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:"
-                    << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid
-                    << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
-                    << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_RSP>"
+          << " Request the TGT_RSP FSM to return data:"
+          << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid
+          << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
+          << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
 #endif
       }
@@ -3555,10 +4022,10 @@
     case XRAM_RSP_INVAL:  // send invalidate request to CC_SEND FSM
     {
-      if(!r_xram_rsp_to_cc_send_multi_req.read() &&
+      if(!r_xram_rsp_to_cc_send_multi_req.read() and
           !r_xram_rsp_to_cc_send_brdcast_req.read())
       {
         bool multi_req = !r_xram_rsp_victim_is_cnt.read();
-        bool last_multi_req  = multi_req && (r_xram_rsp_victim_count.read() == 1);
-        bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+        bool last_multi_req  = multi_req and (r_xram_rsp_victim_count.read() == 1);
+        bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
 
         r_xram_rsp_to_cc_send_multi_req    = last_multi_req;
@@ -3575,13 +4042,12 @@
 
         if(r_xram_rsp_victim_dirty)  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-        else if(not_last_multi_req)    r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
-        else                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+        else if(not_last_multi_req)  r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
+        else                         r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL> Send an inval request to CC_SEND FSM:"
-                    << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL>"
+          << " Send an inval request to CC_SEND FSM"
+          << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
 #endif
       }
@@ -3596,26 +4062,27 @@
         r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
         r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
-        for(size_t i=0; i<m_words ; i++) r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+        for(size_t i=0; i<m_words ; i++)
+        {
+            r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+        }
         m_cpt_write_dirty++;
 
-        bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read();
-        bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+        bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read();
+        bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
+
         if(not_last_multi_req)   r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
-        else                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
+        else                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:"
-                    << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-        }
-#endif
-      }
-      break;
-    }
-
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>"
+          << " Send the put request to IXR_CMD FSM"
+          << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+#endif
+      }
+      break;
+    }
     /////////////////////////
-    case XRAM_RSP_HEAP_REQ:
-      // Get the lock to the HEAP directory
+    case XRAM_RSP_HEAP_REQ:    // Get the lock to the HEAP
     {
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
@@ -3625,16 +4092,12 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-      if(m_debug_xram_rsp_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name() << ".XRAM_RSP_HEAP_REQ> Requesting HEAP lock "
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_REQ>"
+          << " Requesting HEAP lock" << std::endl;
+#endif
+      break;
+    }
     /////////////////////////
-    case XRAM_RSP_HEAP_ERASE: // erase the list of copies and sent invalidations
+    case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations
     {
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
@@ -3667,10 +4130,9 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_ERASE> Erase the list of copies:"
-                    << " srcid = " << std::dec << entry.owner.srcid
-                    << " / inst = " << std::dec << entry.owner.inst << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_ERASE>"
+          << " Erase copy:"
+          << " srcid = " << std::hex << entry.owner.srcid
+          << " / inst = " << std::dec << entry.owner.inst << std::endl;
 #endif
       }
@@ -3678,10 +4140,10 @@
     }
     /////////////////////////
-    case XRAM_RSP_HEAP_LAST:  // last member of the list
+    case XRAM_RSP_HEAP_LAST:  // last copy
     {
       if(r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP)
       {
-        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST state" << std::endl;
-        std::cout << "bad HEAP allocation" << std::endl;
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST"
+                   << " bad HEAP allocation" << std::endl;
         exit(0);
       }
@@ -3710,8 +4172,7 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-      if(m_debug_xram_rsp_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_LAST>"
+          << " Heap housekeeping" << std::endl;
 #endif
       break;
@@ -3724,11 +4185,10 @@
       // Next state
       if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP;
-      else                                 r_xram_rsp_fsm = XRAM_RSP_IDLE;
+      else                             r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-      if(m_debug_xram_rsp_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
+          << " Error reported by XRAM / erase the TRT entry" << std::endl;
 #endif
       break;
@@ -3742,5 +4202,8 @@
         r_xram_rsp_to_tgt_rsp_trdid  = r_xram_rsp_trt_buf.trdid;
         r_xram_rsp_to_tgt_rsp_pktid  = r_xram_rsp_trt_buf.pktid;
-        for(size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+        for(size_t i=0; i < m_words; i++)
+        {
+            r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+        }
         r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
         r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
@@ -3751,9 +4214,8 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
-                    << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
+          << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
 #endif
       }
@@ -3771,7 +4233,7 @@
   switch(r_cleanup_fsm.read())
   {
-    case CLEANUP_IDLE:
-    {
-      // Get first DSPIN flit of the CLEANUP command
+    //////////////////
+    case CLEANUP_IDLE:     // Get first DSPIN flit of the CLEANUP command
+    {
       if(not m_cc_receive_to_cleanup_fifo.rok()) break;
 
@@ -3796,6 +4258,5 @@
         DspinDhccpParam::dspin_get(
             flit,
-            DspinDhccpParam::CLEANUP_NLINE_MSB) 
-        << 32;
+            DspinDhccpParam::CLEANUP_NLINE_MSB) << 32;
 
       r_cleanup_inst  = (type == DspinDhccpParam::TYPE_CLEANUP_INST);
@@ -3814,60 +4275,42 @@
       m_cpt_cleanup++;
       cc_receive_to_cleanup_fifo_get = true;
-      r_cleanup_fsm                 = CLEANUP_GET_NLINE;
+      r_cleanup_fsm                  = CLEANUP_GET_NLINE;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC "         << name()
-            << ".CLEANUP_IDLE> Cleanup request:" << std::hex
-            << " / owner_id = "   << srcid
-            << " / owner_ins = "  << (type == DspinDhccpParam::TYPE_CLEANUP_INST)
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_GET_NLINE:
-    {
-      // Get second flit of cleanup command
+if(m_debug)
+std::cout << "  <MEMC "         << name()
+          << " CLEANUP_IDLE> Cleanup request:" << std::hex
+          << " / owner_id = "   << srcid
+          << " / owner_ins = "  << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl;
+#endif
+      break;
+    }
+
+    ///////////////////////
+    case CLEANUP_GET_NLINE:  // GET second DSPIN flit of the cleanup command
+    {
       if(not m_cc_receive_to_cleanup_fifo.rok()) break;
 
       uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
 
-      addr_t nline =
-        r_cleanup_nline.read() |
+      addr_t nline = r_cleanup_nline.read() |
         DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB);
 
-      bool eop =
-        DspinDhccpParam::dspin_get(flit, DspinDhccpParam::FROM_L1_EOP) == 0x1;
-
-      assert(
-          eop &&
-          "VCI_MEM_CACHE ERROR: "
-          "CLEANUP command must have exactly two flits");
-
       cc_receive_to_cleanup_fifo_get = true;
-      r_cleanup_nline               = nline;
-      r_cleanup_fsm                 = CLEANUP_DIR_REQ;
+      r_cleanup_nline                = nline;
+      r_cleanup_fsm                  = CLEANUP_DIR_REQ;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC "         << name()
-            << ".CLEANUP_GET_NLINE> Cleanup request:"
-            << std::hex
-            << " / address = "    << nline * m_words * 4
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_DIR_REQ:
-    {
-      // Get the lock to the directory
+if(m_debug)
+std::cout << "  <MEMC "         << name()
+          << " CLEANUP_GET_NLINE> Cleanup request:"
+          << " / address = " << std::hex << nline * m_words * 4 << std::endl;
+#endif
+      break;
+    }
+
+    /////////////////////
+    case CLEANUP_DIR_REQ:   // Get the lock to the directory
+    {
       if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break;
 
@@ -3875,14 +4318,11 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name() << ".CLEANUP_DIR_REQ> Requesting DIR lock "
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl;
+#endif
+      break;
+    }
+
+    //////////////////////
     case CLEANUP_DIR_LOCK:
     {
@@ -3916,10 +4356,8 @@
 #endif
 
-      // hit :
-      // the copy must be cleared
-      if(entry.valid)
+      if(entry.valid)      // hit : the copy must be cleared
       {
         assert(
-            (entry.count > 0) &&
+            (entry.count > 0) and
             "VCI MEM CACHE ERROR: "
             "In CLEANUP_DIR_LOCK, CLEANUP command on a valid entry "
@@ -3927,5 +4365,5 @@
 
         // no access to the heap
-        if((entry.count == 1) || (entry.is_cnt))
+        if((entry.count == 1) or (entry.is_cnt))
         {
           r_cleanup_fsm = CLEANUP_DIR_WRITE;
@@ -3937,8 +4375,5 @@
         }
       }
-      // miss :
-      // we must check the update table for a pending
-      // invalidation transaction
-      else
+      else                // miss : check UPT for a pending invalidation transaction
       {
         r_cleanup_fsm = CLEANUP_UPT_LOCK;
@@ -3946,9 +4381,9 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_DIR_LOCK> Test directory status: "
+            << " CLEANUP_DIR_LOCK> Test directory status: "
             << std::hex
             << " line = "         << cleanup_address
@@ -3966,4 +4401,5 @@
     }
 
+    ///////////////////////
     case CLEANUP_DIR_WRITE:
     {
@@ -3980,5 +4416,5 @@
 
       size_t way         = r_cleanup_way.read();
-      size_t set         = m_y[(vci_addr_t)(r_cleanup_nline.read()*m_words*4)];
+      size_t set         = m_y[(addr_t)(r_cleanup_nline.read()*m_words*4)];
       bool   match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read());
 
@@ -3988,5 +4424,5 @@
 
       bool   match_inst  = (r_cleanup_copy_inst.read() == r_cleanup_inst.read());
-      bool   match       = match_srcid && match_inst;
+      bool   match       = match_srcid and match_inst;
 
       if(not r_cleanup_is_cnt.read() and not match)
@@ -4019,12 +4455,12 @@
       m_cache_directory.write(set, way, entry);
 
-      r_cleanup_fsm = CLEANUP_SEND_ACK;
+      r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_DIR_WRITE> Update directory:"
+            << " CLEANUP_DIR_WRITE> Update directory:"
             << std::hex
             << " address = "   << r_cleanup_nline.read() * m_words * 4
@@ -4040,4 +4476,5 @@
     }
 
+    //////////////////////
     case CLEANUP_HEAP_REQ:
     {
@@ -4048,9 +4485,9 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_HEAP_REQ> HEAP lock acquired "
+            << " CLEANUP_HEAP_REQ> HEAP lock acquired "
             << std::endl;
       }
@@ -4059,4 +4496,5 @@
     }
 
+    //////////////////////
     case CLEANUP_HEAP_LOCK:
     {
@@ -4075,5 +4513,5 @@
 
       size_t way            = r_cleanup_way.read();
-      size_t set            = m_y[(vci_addr_t)(r_cleanup_nline.read() *m_words*4)];
+      size_t set            = m_y[(addr_t)(r_cleanup_nline.read() *m_words*4)];
 
       HeapEntry heap_entry  = m_heap.read(r_cleanup_ptr.read());
@@ -4200,9 +4638,9 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         std::cout
             << "  <MEMC " << name()
-            << ".CLEANUP_HEAP_LOCK> Checks matching:"
+            << " CLEANUP_HEAP_LOCK> Checks matching:"
             << " address = "      << r_cleanup_nline.read() * m_words * 4
             << " / dir_id = "     << r_cleanup_copy.read()
@@ -4218,4 +4656,5 @@
     }
 
+    ////////////////////////
     case CLEANUP_HEAP_SEARCH:
     {
@@ -4237,5 +4676,5 @@
       bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read());
       bool match_heap_inst  = (heap_entry.owner.inst  == r_cleanup_inst.read());
-      bool match_heap       = match_heap_srcid && match_heap_inst;
+      bool match_heap       = match_heap_srcid and match_heap_inst;
 
 #if L1_MULTI_CACHE
@@ -4277,5 +4716,5 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
+      if(m_debug)
       {
         if(not match_heap)
@@ -4283,5 +4722,5 @@
           std::cout
               << "  <MEMC " << name()
-              << ".CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
+              << " CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
               << std::endl;
         }
@@ -4290,5 +4729,5 @@
           std::cout
               << "  <MEMC " << name()
-              << ".CLEANUP_HEAP_SEARCH> Matching copy found:"
+              << " CLEANUP_HEAP_SEARCH> Matching copy found:"
               << std::endl;
         }
@@ -4306,8 +4745,7 @@
       break;
     }
-
-    case CLEANUP_HEAP_CLEAN:
-    {
-      // remove a copy in the linked list
+    ////////////////////////
+    case CLEANUP_HEAP_CLEAN:    // remove a copy in the linked list
+    {
       if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP)
       {
@@ -4346,19 +4784,14 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << ".CLEANUP_HEAP_SEARCH> Remove the copy in the linked list"
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_HEAP_FREE:
-    {
-      // The heap entry pointed by r_cleanup_next_ptr is freed
-      // and becomes the head of the list of free entries
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_HEAP_SEARCH>"
+          << " Remove the copy in the linked list" << std::endl;
+#endif
+      break;
+    }
+    ///////////////////////
+    case CLEANUP_HEAP_FREE:   // The heap entry pointed by r_cleanup_next_ptr is freed
+                              // and becomes the head of the list of free entries
+    {
       if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP)
       {
@@ -4392,22 +4825,17 @@
       m_heap.unset_full();
 
-      r_cleanup_fsm = CLEANUP_SEND_ACK;
+      r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << ".CLEANUP_HEAP_SEARCH> Update the list of free entries"
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_UPT_LOCK:
-    {
-      // search pending invalidate transaction matching the Cleanup NLINE in the UPDATE TABLE
-      // get the lock in the UPDATE_TABLE
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_HEAP_FREE>"
+          << " Update the list of free entries" << std::endl;
+#endif
+      break;
+    }
+    //////////////////////
+    case CLEANUP_UPT_LOCK:   // get the lock protecting the UPT to search a pending
+                             // invalidate transaction matching the cleanup 
+    {
       if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) break;
 
@@ -4417,52 +4845,43 @@
       match_inval = m_upt.search_inval(r_cleanup_nline.read(), index);
 
-      // no pending inval
-      if(not match_inval)
-      {
-        r_cleanup_fsm = CLEANUP_SEND_ACK;
+      if ( not match_inval )     // no pending inval
+      {
+          r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-        if(m_debug_cleanup_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name()
-              << ".CLEANUP_UPT_LOCK> Unexpected cleanup"
-              << " with no corresponding UPT entry:"
-              << " address = " << std::hex
-              << (r_cleanup_nline.read() *4*m_words)
-              << std::endl;
-        }
-#endif
-        break;
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CLEANUP_UPT_LOCK> Unexpected cleanup"
+          << " with no corresponding UPT entry:"
+          << " address = " << std::hex
+          << (r_cleanup_nline.read() *4*m_words)
+          << std::endl;
+#endif
+          break;
       }
 
       // pending inval
-      r_cleanup_write_srcid    = m_upt.srcid(index);
-      r_cleanup_write_trdid    = m_upt.trdid(index);
-      r_cleanup_write_pktid    = m_upt.pktid(index);
-      r_cleanup_write_need_rsp = m_upt.need_rsp(index);
-      r_cleanup_index          = index;
+      r_cleanup_write_srcid = m_upt.srcid(index);
+      r_cleanup_write_trdid = m_upt.trdid(index);
+      r_cleanup_write_pktid = m_upt.pktid(index);
+      r_cleanup_need_rsp    = m_upt.need_rsp(index);
+      r_cleanup_need_ack    = m_upt.need_ack(index);
+      r_cleanup_index       = index;
 
       r_cleanup_fsm         = CLEANUP_UPT_DECREMENT;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << ".CLEANUP_UPT_LOCK> Cleanup matching pending"
-            << " invalidate transaction on UPT:"
-            << std::hex
-            << " address = "   << r_cleanup_nline.read() * m_words * 4
-            << " upt_entry = " << index
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_UPT_DECREMENT:
-    {
-      // decrement response counter in UPT matching entry
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CLEANUP_UPT_LOCK> Cleanup matching pending"
+          << " invalidate transaction on UPT:"
+          << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4
+          << " / upt_entry = " << index << std::endl;
+#endif
+      break;
+    }
+    ///////////////////////////
+    case CLEANUP_UPT_DECREMENT:   // decrement response counter in UPT matching entry
+    {
       if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP)
       {
@@ -4479,33 +4898,25 @@
       m_upt.decrement(r_cleanup_index.read(), count);
 
-      // invalidation transaction finished
-      // (all acknowledgements received)
-      if(count == 0)
+      if(count == 0)   // multi inval transaction completed
       {
         r_cleanup_fsm = CLEANUP_UPT_CLEAR;
       }
-      // invalidation transaction not finished
-      else
-      {
-        r_cleanup_fsm = CLEANUP_SEND_ACK ;
+      else             // multi inval transaction not completed
+      {
+        r_cleanup_fsm = CLEANUP_SEND_CLACK ;
       }
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC "      << name()
-            << ".CLEANUP_UPT_DECREMENT> Decrement response counter in UPT:"
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_UPT_DECREMENT>"
+          << " Decrement response counter in UPT:"
             << " UPT_index = " << r_cleanup_index.read()
-            << " rsp_count = " << count
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_UPT_CLEAR:
-    {
-      // Clear UPT entry of finished invalidation transaction
+            << " / rsp_count = " << count << std::endl;
+#endif
+      break;
+    }
+    ///////////////////////
+    case CLEANUP_UPT_CLEAR:    // Clear UPT entry 
+    {
       if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP)
       {
@@ -4521,30 +4932,20 @@
       m_upt.clear(r_cleanup_index.read());
 
-      if(r_cleanup_write_need_rsp.read())
-      {
-        r_cleanup_fsm = CLEANUP_WRITE_RSP;
-      }
-      else
-      {
-        r_cleanup_fsm = CLEANUP_SEND_ACK;
-      }
+      if      ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP;
+      else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK;
+      else                                  r_cleanup_fsm = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC "      << name()
-            << ".CLEANUP_UPT_CLEAR> Clear entry in UPT:"
-            << " UPT_index = " << r_cleanup_index.read()
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_WRITE_RSP:
-    {
-      // response to a previous write on the direct network
-      // wait if pending request to the TGT_RSP FSM
+if(m_debug)
+std::cout << "  <MEMC "      << name()
+          << " CLEANUP_UPT_CLEAR> Clear entry in UPT:"
+          << " UPT_index = " << r_cleanup_index.read() << std::endl;
+#endif
+      break;
+    }
+    ///////////////////////
+    case CLEANUP_WRITE_RSP:    // response to a previous write on the direct network
+                               // wait if pending request to the TGT_RSP FSM
+    {
       if(r_cleanup_to_tgt_rsp_req.read()) break;
 
@@ -4555,26 +4956,37 @@
       r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
 
-      r_cleanup_fsm                = CLEANUP_SEND_ACK;
+      r_cleanup_fsm                = CLEANUP_SEND_CLACK;
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << ".CLEANUP_WRITE_RSP> Send a response to a previous"
-            << " write request waiting for coherence transaction completion: "
-            << " rsrcid = "   << std::dec << r_cleanup_write_srcid.read()
-            << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read()
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    case CLEANUP_SEND_ACK:
-    {
-      // acknowledgement to a cleanup command
-      // on the coherence network (request to the CC_SEND FSM).
-      // wait if pending request to the CC_SEND FSM
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_WRITE_RSP>"
+          << " Send a response to a previous write request: "
+          << " rsrcid = "   << std::hex << r_cleanup_write_srcid.read()
+          << " / rtrdid = " << r_cleanup_write_trdid.read()
+          << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl;
+#endif
+      break;
+    }
+    ////////////////////////
+    case CLEANUP_CONFIG_ACK:   // signals inval completion to CONFIG FSM
+                               // wait if pending request
+    {
+      if ( r_cleanup_to_config_ack.read() ) break;
+
+      r_cleanup_to_config_ack      = true;
+      r_cleanup_fsm                = CLEANUP_SEND_CLACK;
+
+#if DEBUG_MEMC_CLEANUP
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CLEANUP_CONFIG_ACK>"
+          << " Acknowledge broacast inval completion" << std::endl;
+#endif
+      break;
+    }
+    ////////////////////////
+    case CLEANUP_SEND_CLACK:    // acknowledgement to a cleanup command
+                              // on the coherence network (request to the CC_SEND FSM).
+                              // wait if pending request to the CC_SEND FSM
+    {
       if(r_cleanup_to_cc_send_req.read()) break;
 
@@ -4588,12 +5000,8 @@
 
 #if DEBUG_MEMC_CLEANUP
-      if(m_debug_cleanup_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name()
-            << ".CLEANUP_SEND_ACK> Send the response to a cleanup request:"
-            << " srcid = " << std::dec << r_cleanup_srcid.read()
-            << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:"
+          << " srcid = " << std::dec << r_cleanup_srcid.read() << std::endl;
 #endif
       break;
@@ -4635,7 +5043,7 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_IDLE> CAS command: " << std::hex
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " CAS_IDLE> CAS command: " << std::hex
                     << " srcid = " <<  std::dec << m_cmd_cas_srcid_fifo.read()
                     << " addr = " << std::hex << m_cmd_cas_addr_fifo.read()
@@ -4658,5 +5066,5 @@
           r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read();
 
-        if((r_cas_cpt.read() == 1) && m_cmd_cas_eop_fifo.read())
+        if((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read())
           r_cas_wdata = m_cmd_cas_wdata_fifo.read();
 
@@ -4685,8 +5093,8 @@
 
 #if DEBUG_MEMC_CAS
-      if(m_debug_cas_fsm)
+      if(m_debug)
       {
         std::cout
-            << "  <MEMC " << name() << ".CAS_DIR_REQ> Requesting DIR lock "
+            << "  <MEMC " << name() << " CAS_DIR_REQ> Requesting DIR lock "
             << std::endl;
       }
@@ -4719,7 +5127,7 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_DIR_LOCK> Directory acces"
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " CAS_DIR_LOCK> Directory acces"
                     << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
                     << " / hit = " << std::dec << entry.valid
@@ -4746,5 +5154,5 @@
     {
       size_t way  = r_cas_way.read();
-      size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+      size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
       // update directory (lock & dirty bits)
@@ -4771,11 +5179,7 @@
 
 #if DEBUG_MEMC_CAS
-      if(m_debug_cas_fsm)
-      {
-        std::cout
-          << "  <MEMC " << name() << ".CAS_DIR_HIT_READ> Read data from "
-          << " cache and store it in buffer"
-          << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from "
+          << " cache and store it in buffer" << std::endl;
 #endif
       break;
@@ -4784,5 +5188,5 @@
     case CAS_DIR_HIT_COMPARE:
     {
-      size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+      size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
       // Read data in buffer & check data change
@@ -4793,5 +5197,5 @@
 
       // to avoid livelock, force the atomic access to fail pseudo-randomly
-      bool forced_fail = ((r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS);
+      bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS);
       r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001);
 
@@ -4808,12 +5212,10 @@
 
 #if DEBUG_MEMC_CAS
-      if(m_debug_cas_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_COMPARE> Compare the old"
-                  << " and the new data"
-                  << " / expected value = " << r_cas_rdata[0].read()
-                  << " / actual value = "   << r_cas_data[word].read()
-                  << " / forced_fail = "    << forced_fail << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old"
+          << " and the new data"
+          << " / expected value = " << r_cas_rdata[0].read()
+          << " / actual value = "   << r_cas_data[word].read()
+          << " / forced_fail = "    << forced_fail << std::endl;
 #endif
       break;
@@ -4833,5 +5235,5 @@
           r_cas_fsm = CAS_BC_TRT_LOCK;    // broadcast invalidate required
         }
-        else if(!r_cas_to_cc_send_multi_req.read() &&
+        else if(!r_cas_to_cc_send_multi_req.read() and
                 !r_cas_to_cc_send_brdcast_req.read())
         {
@@ -4846,6 +5248,6 @@
       {
         size_t way  = r_cas_way.read();
-        size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-        size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
+        size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
         // cache update
@@ -4859,25 +5261,23 @@
         if(m_monitor_ok)
         {
-          vci_addr_t address = m_cmd_cas_addr_fifo.read();
+          addr_t address = m_cmd_cas_addr_fifo.read();
           char buf[80];
-          snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
-          check_monitor(buf, address, r_cas_wdata.read());
+          snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
+                   (int)m_cmd_cas_srcid_fifo.read());
+          check_monitor(buf, address, r_cas_wdata.read(), false);
 
           if(r_cas_cpt.read() == 4)
-            check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read());
+            check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
         }
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_WRITE> Update cache:"
-                    << " way = " << std::dec << way
-                    << " / set = " << set
-                    << " / word = " << word
-                    << " / value = " << r_cas_wdata.read()
-                    << " / count = " << r_cas_count.read() << std::endl;
-          std::cout << "  <MEMC "
-                    << name() << ".CAS_DIR_HIT_WRITE> global_llsc_table SW access" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:"
+          << " way = " << std::dec << way
+          << " / set = " << set
+          << " / word = " << word
+          << " / value = " << r_cas_wdata.read()
+          << " / count = " << r_cas_count.read()
+          << " / global_llsc_table access" << std::endl;
 #endif
       }
@@ -4896,22 +5296,23 @@
         size_t      trdid      = m_cmd_cas_trdid_fifo.read();
         size_t      pktid      = m_cmd_cas_pktid_fifo.read();
-        addr_t      nline      = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        addr_t      nline      = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
         size_t      nb_copies  = r_cas_count.read();
 
-        wok = m_upt.set(true,  // it's an update transaction
-                               false,   // it's not a broadcast
-                               true,    // it needs a response
-                               srcid,
-                               trdid,
-                               pktid,
-                               nline,
-                               nb_copies,
-                               index);
+        wok = m_upt.set(true,    // it's an update transaction
+                        false,   // it's not a broadcast
+                        true,    // response required  
+                        false,   // no acknowledge required
+                        srcid,
+                        trdid,
+                        pktid,
+                        nline,
+                        nb_copies,
+                        index);
         if(wok)   // coherence transaction registered in UPT
         {
           // cache update
           size_t way  = r_cas_way.read();
-          size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-          size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
           m_cache_data.write(way, set, word, r_cas_wdata.read());
@@ -4925,11 +5326,12 @@
           if(m_monitor_ok)
           {
-            vci_addr_t address = m_cmd_cas_addr_fifo.read();
+            addr_t address = m_cmd_cas_addr_fifo.read();
             char buf[80];
-            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
-            check_monitor(buf, address, r_cas_wdata.read());
+            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
+                     (int)m_cmd_cas_srcid_fifo.read());
+            check_monitor(buf, address, r_cas_wdata.read(), false);
 
             if(r_cas_cpt.read() ==4)
-              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read());
+              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
           }
         }
@@ -4940,12 +5342,10 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name()
-                    << ".CAS_UPT_LOCK> Register multi-update transaction in UPT"
-                    << " / wok = " << wok
-                    << " / nline  = " << std::hex << nline
-                    << " / count = " << nb_copies << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CAS_UPT_LOCK> Register multi-update transaction in UPT"
+          << " / wok = " << wok
+          << " / nline  = " << std::hex << nline
+          << " / count = " << nb_copies << std::endl;
 #endif
       }
@@ -4957,8 +5357,8 @@
 
 #if DEBUG_MEMC_CAS
-      if(m_debug_cas_fsm)
+      if(m_debug)
       {
         std::cout << "  <MEMC " << name()
-                  << ".CAS_WAIT> Release all locks" << std::endl;
+                  << " CAS_WAIT> Release all locks" << std::endl;
       }
 #endif
@@ -4973,8 +5373,8 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
+        if(m_debug)
         {
           std::cout << "  <MEMC " << name()
-                    << ".CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
+                    << " CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
         }
 #endif
@@ -4989,10 +5389,10 @@
              "VCI_MEM_CACHE ERROR : bad HEAP allocation");
 
-      if(!r_cas_to_cc_send_multi_req.read() && !r_cas_to_cc_send_brdcast_req.read())
+      if(!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read())
       {
         r_cas_to_cc_send_brdcast_req  = false;
         r_cas_to_cc_send_trdid        = r_cas_upt_index.read();
-        r_cas_to_cc_send_nline        = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-        r_cas_to_cc_send_index        = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        r_cas_to_cc_send_nline        = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
+        r_cas_to_cc_send_index        = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
         r_cas_to_cc_send_wdata        = r_cas_wdata.read();
 
@@ -5029,7 +5429,7 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_UPT_REQ> Send the first update request to CC_SEND FSM "
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " CAS_UPT_REQ> Send the first update request to CC_SEND FSM "
                     << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
                     << " / wdata = " << std::hex << r_cas_wdata.read()
@@ -5069,7 +5469,7 @@
 
 #if DEBUG_MEMC_CAS
-      if(m_debug_cas_fsm)
-      {
-        std::cout << "  <MEMC " << name() << ".CAS_UPT_NEXT> Send the next update request to CC_SEND FSM "
+      if(m_debug)
+      {
+        std::cout << "  <MEMC " << name() << " CAS_UPT_NEXT> Send the next update request to CC_SEND FSM "
                   << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
                   << " / wdata = " << std::hex << r_cas_wdata.read()
@@ -5088,5 +5488,5 @@
         {
           // fill the data buffer
-          size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
           for(size_t i = 0; i<m_words; i++)
           {
@@ -5095,5 +5495,5 @@
               r_cas_to_ixr_cmd_data[i] = r_cas_wdata.read();
             }
-            else if((i == word+1) && (r_cas_cpt.read() == 4))   // 64 bit CAS
+            else if((i == word+1) and (r_cas_cpt.read() == 4))   // 64 bit CAS
             {
               r_cas_to_ixr_cmd_data[i] = m_cmd_cas_wdata_fifo.read();
@@ -5123,7 +5523,7 @@
       break;
     }
-    ///////////////////
+    /////////////////////
     case CAS_BC_UPT_LOCK:  // register a broadcast inval transaction in UPT
-      // write data in cache in case of successful registration
+                           // write data in cache in case of successful registration
     {
       if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS)
@@ -5134,17 +5534,18 @@
         size_t      trdid     = m_cmd_cas_trdid_fifo.read();
         size_t      pktid     = m_cmd_cas_pktid_fifo.read();
-        addr_t      nline     = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        addr_t      nline     = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
         size_t      nb_copies = r_cas_count.read();
 
         // register a broadcast inval transaction in UPT
         wok = m_upt.set(false,  // it's an inval transaction
-                               true,    // it's a broadcast
-                               true,    // it needs a response
-                               srcid,
-                               trdid,
-                               pktid,
-                               nline,
-                               nb_copies,
-                               index);
+                        true,    // it's a broadcast
+                        true,    // response required
+                        false,   // no acknowledge required
+                        srcid,
+                        trdid,
+                        pktid,
+                        nline,
+                        nb_copies,
+                        index);
 
         if(wok)     // UPT not full
@@ -5152,6 +5553,6 @@
           // cache update
           size_t way  = r_cas_way.read();
-          size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
-          size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t set  = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
+          size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];
 
           m_cache_data.write(way, set, word, r_cas_wdata.read());
@@ -5162,21 +5563,22 @@
           if(m_monitor_ok)
           {
-            vci_addr_t address = m_cmd_cas_addr_fifo.read();
+            addr_t address = m_cmd_cas_addr_fifo.read();
             char buf[80];
-            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
-            check_monitor(buf, address, r_cas_wdata.read());
+            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
+                     (int)m_cmd_cas_srcid_fifo.read());
+            check_monitor(buf, address, r_cas_wdata.read(), false);
             if(r_cas_cpt.read() ==4)
-              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read());
+              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
           }
           r_cas_upt_index = index;
           r_cas_fsm = CAS_BC_DIR_INVAL;
+
 #if DEBUG_MEMC_CAS
-          if(m_debug_cas_fsm)
-          {
-            std::cout << "  <MEMC " << name() << ".CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
-                      << " / nline = " << nline
-                      << " / count = " << nb_copies
-                      << " / upt_index = " << index << std::endl;
-          }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
+          << " / nline = " << std::hex << nline
+          << " / count = " << std::dec << nb_copies
+          << " / upt_index = " << index << std::endl;
 #endif
         }
@@ -5188,9 +5590,9 @@
       break;
     }
-    //////////////////
+    //////////////////////
     case CAS_BC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
     {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) &&
-          (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) &&
+      if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and
+          (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and
           (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS))
       {
@@ -5198,5 +5600,5 @@
         m_trt.set(r_cas_trt_index.read(),
                               false,    // PUT request to XRAM
-                              m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())],
+                              m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],
                               0,
                               0,
@@ -5222,5 +5624,5 @@
         entry.owner.inst    = false;
         entry.ptr           = 0;
-        size_t set          = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        size_t set          = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];
         size_t way          = r_cas_way.read();
         m_cache_directory.write(set, way, entry);
@@ -5229,10 +5631,9 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
-                    << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]
-                    << " / set = " << std::dec << set << " / way = " << way << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
+          << " / nline = " << std::hex << m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]
+          << " / set = " << std::dec << set << " / way = " << way << std::endl;
 #endif
       }
@@ -5246,5 +5647,5 @@
     case CAS_BC_CC_SEND:  // Request the broadcast inval to CC_SEND FSM
     {
-      if(!r_cas_to_cc_send_multi_req.read() &&
+      if(!r_cas_to_cc_send_multi_req.read() and
           !r_cas_to_cc_send_brdcast_req.read())
       {
@@ -5252,5 +5653,5 @@
         r_cas_to_cc_send_brdcast_req  = true;
         r_cas_to_cc_send_trdid        = r_cas_upt_index.read();
-        r_cas_to_cc_send_nline        = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        r_cas_to_cc_send_nline        = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
         r_cas_to_cc_send_index        = 0;
         r_cas_to_cc_send_wdata        = 0;
@@ -5267,5 +5668,5 @@
         r_cas_to_ixr_cmd_req     = true;
         r_cas_to_ixr_cmd_write   = true;
-        r_cas_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+        r_cas_to_ixr_cmd_nline   = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];
         r_cas_to_ixr_cmd_trdid   = r_cas_trt_index.read();
         r_cas_fsm                = CAS_IDLE;
@@ -5274,16 +5675,15 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
-                    << " / nline = " << m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]
-                    << " / trt_index = " << r_cas_trt_index.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
+          << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
+          << " / trt_index = " << r_cas_trt_index.read() << std::endl;
 #endif
       }
       else
       {
-        std::cout << "MEM_CACHE, CAS_BC_XRAM_REQ state : request should not have been previously set"
-                  << std::endl;
+        std::cout << "ERROR in MEM_CACHE / CAS_BC_XRAM_REQ state"
+                  << " : request should not have been previously set" << std::endl;
       }
       break;
@@ -5304,8 +5704,7 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
 #endif
       }
@@ -5327,8 +5726,7 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
 #endif
       }
@@ -5342,13 +5740,13 @@
         size_t   index = 0;
         bool hit_read = m_trt.hit_read(
-                          m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()],index);
+                          m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index);
         bool hit_write = m_trt.hit_write(
-                           m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]);
+                           m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]);
         bool wok = !m_trt.full(index);
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_MISS_TRT_LOCK> Check TRT state"
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_LOCK> Check TRT state"
                     << " / hit_read = "  << hit_read
                     << " / hit_write = " << hit_write
@@ -5358,5 +5756,5 @@
 #endif
 
-        if(hit_read || !wok || hit_write)    // missing line already requested or no space in TRT
+        if(hit_read or !wok or hit_write)    // missing line already requested or no space in TRT
         {
           r_cas_fsm = CAS_WAIT;
@@ -5387,5 +5785,5 @@
         m_trt.set(r_cas_trt_index.read(),
                               true,   // read request
-                              m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()],
+                              m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],
                               m_cmd_cas_srcid_fifo.read(),
                               m_cmd_cas_trdid_fifo.read(),
@@ -5399,8 +5797,8 @@
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
-                    << " / nline = " << m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
+                    << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
                     << " / trt_index = " << r_cas_trt_index.read() << std::endl;
         }
@@ -5417,12 +5815,12 @@
         r_cas_to_ixr_cmd_write      = false;
         r_cas_to_ixr_cmd_trdid      = r_cas_trt_index.read();
-        r_cas_to_ixr_cmd_nline      = m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()];
+        r_cas_to_ixr_cmd_nline      = m_nline[(addr_t) m_cmd_cas_addr_fifo.read()];
         r_cas_fsm                   = CAS_WAIT;
 
 #if DEBUG_MEMC_CAS
-        if(m_debug_cas_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
-                    << " / nline = " << m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]
+        if(m_debug)
+        {
+          std::cout << "  <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
+                    << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
                     << " / trt_index = " << r_cas_trt_index.read() << std::endl;
         }
@@ -5443,6 +5841,8 @@
   // the CLEANUP fsm.
   //
-  // It implements a round-robin priority between the four possible client FSMs
-  // XRAM_RSP, WRITE, CAS and CLEANUP. Each FSM can request the next services:
+  // It implements a round-robin priority between the five possible client FSMs
+  //     XRAM_RSP > CAS > CLEANUP > WRITE > CONFIG 
+  //
+  // Each FSM can request the next services:
   // - r_xram_rsp_to_cc_send_multi_req : multi-inval
   //   r_xram_rsp_to_cc_send_brdcast_req : broadcast-inval
@@ -5451,4 +5851,7 @@
   // - r_cas_to_cc_send_multi_req : multi-update
   //   r_cas_to_cc_send_brdcast_req : broadcast-inval
+  // - r_config_to_cc_send_multi_req : multi-inval
+  //   r_config_to_cc_send_brdcast_req : broadcast-inval
+  //   
   // - r_cleanup_to_cc_send_req : cleanup acknowledgement
   //
@@ -5464,8 +5867,9 @@
   switch(r_cc_send_fsm.read())
   {
-    case CC_SEND_WRITE_IDLE:
-      {
-        // XRAM_RSP FSM has highest priority
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||
+      /////////////////////////
+      case CC_SEND_CONFIG_IDLE:    // XRAM_RSP FSM has highest priority
+      {
+        // XRAM_RSP
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
             r_xram_rsp_to_cc_send_multi_req.read())
         {
@@ -5474,5 +5878,4 @@
           break;
         }
-
         if(r_xram_rsp_to_cc_send_brdcast_req.read())
         {
@@ -5481,6 +5884,6 @@
           break;
         }
-
-        if(m_cas_to_cc_send_inst_fifo.rok() ||
+        // CAS
+        if(m_cas_to_cc_send_inst_fifo.rok() or
             r_cas_to_cc_send_multi_req.read())
         {
@@ -5489,5 +5892,4 @@
           break;
         }
-
         if(r_cas_to_cc_send_brdcast_req.read())
         {
@@ -5496,5 +5898,5 @@
           break;
         }
-
+        // CLEANUP
         if (r_cleanup_to_cc_send_req.read())
         {
@@ -5502,6 +5904,6 @@
           break;
         }
-
-        if(m_write_to_cc_send_inst_fifo.rok() ||
+        // WRITE
+        if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
         {
@@ -5510,17 +5912,57 @@
           break;
         }
-
         if(r_write_to_cc_send_brdcast_req.read())
         {
           r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
           m_cpt_inval++;
+          break;
+        }
+        // CONFIG
+        if(r_config_to_cc_send_multi_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        if(r_config_to_cc_send_brdcast_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+          m_cpt_inval++;
+          break;
         }
         break;
       }
-
-    case CC_SEND_XRAM_RSP_IDLE:
-      {
-        // CAS FSM has highest priority
-        if(m_cas_to_cc_send_inst_fifo.rok() ||
+      ////////////////////////
+      case CC_SEND_WRITE_IDLE:     // CONFIG FSM has highest priority
+      {
+        // CONFIG
+        if(r_config_to_cc_send_multi_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        if(r_config_to_cc_send_brdcast_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        // XRAM_RSP
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
+            r_xram_rsp_to_cc_send_multi_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        if(r_xram_rsp_to_cc_send_brdcast_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        // CAS
+        if(m_cas_to_cc_send_inst_fifo.rok() or
             r_cas_to_cc_send_multi_req.read())
         {
@@ -5529,5 +5971,4 @@
           break;
         }
-
         if(r_cas_to_cc_send_brdcast_req.read())
         {
@@ -5536,12 +5977,12 @@
           break;
         }
-
-        if(r_cleanup_to_cc_send_req.read())
+        // CLEANUP
+        if (r_cleanup_to_cc_send_req.read())
         {
           r_cc_send_fsm = CC_SEND_CLEANUP_ACK;
           break;
         }
-
-        if(m_write_to_cc_send_inst_fifo.rok() ||
+        // WRITE
+        if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
         {
@@ -5550,5 +5991,4 @@
           break;
         }
-
         if(r_write_to_cc_send_brdcast_req.read())
         {
@@ -5557,6 +5997,59 @@
           break;
         }
-
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||
+        break;
+      }
+      ///////////////////////////
+      case CC_SEND_XRAM_RSP_IDLE:   // CAS FSM has highest priority
+      {
+        // CAS
+        if(m_cas_to_cc_send_inst_fifo.rok() or
+            r_cas_to_cc_send_multi_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
+          m_cpt_update++;
+          break;
+        }
+        if(r_cas_to_cc_send_brdcast_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        // CLEANUP
+        if(r_cleanup_to_cc_send_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CLEANUP_ACK;
+          break;
+        }
+        // WRITE
+        if(m_write_to_cc_send_inst_fifo.rok() or
+            r_write_to_cc_send_multi_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
+          m_cpt_update++;
+          break;
+        }
+
+        if(r_write_to_cc_send_brdcast_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        // CONFIG
+        if(r_config_to_cc_send_multi_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        if(r_config_to_cc_send_brdcast_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        // XRAM_RSP
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
             r_xram_rsp_to_cc_send_multi_req.read())
         {
@@ -5565,17 +6058,15 @@
           break;
         }
-
         if(r_xram_rsp_to_cc_send_brdcast_req.read())
         {
           r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
           m_cpt_inval++;
-        }
-
+          break;
+        }
         break;
       }
-
-    case CC_SEND_CAS_IDLE:
-      {
-        // CLEANUP FSM has highest priority
+      //////////////////////
+      case CC_SEND_CAS_IDLE:   // CLEANUP FSM has highest priority
+      {
         if(r_cleanup_to_cc_send_req.read())
         {
@@ -5583,6 +6074,5 @@
           break;
         }
-
-        if(m_write_to_cc_send_inst_fifo.rok() ||
+        if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
         {
@@ -5591,5 +6081,4 @@
           break;
         }
-
         if(r_write_to_cc_send_brdcast_req.read())
         {
@@ -5598,6 +6087,18 @@
           break;
         }
-
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||
+        // CONFIG
+        if(r_config_to_cc_send_multi_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        if(r_config_to_cc_send_brdcast_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
             r_xram_rsp_to_cc_send_multi_req.read())
         {
@@ -5606,5 +6107,4 @@
           break;
         }
-
         if(r_xram_rsp_to_cc_send_brdcast_req.read())
         {
@@ -5613,6 +6113,5 @@
           break;
         }
-
-        if(m_cas_to_cc_send_inst_fifo.rok() ||
+        if(m_cas_to_cc_send_inst_fifo.rok() or
             r_cas_to_cc_send_multi_req.read())
         {
@@ -5621,17 +6120,17 @@
           break;
         }
-
         if(r_cas_to_cc_send_brdcast_req.read())
         {
           r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
           m_cpt_inval++;
+          break;
         }
         break;
       }
-
-    case CC_SEND_CLEANUP_IDLE:
-      {
-        // WRITE FSM has highest priority
-        if(m_write_to_cc_send_inst_fifo.rok() ||
+      //////////////////////////
+      case CC_SEND_CLEANUP_IDLE:   // WRITE FSM has highest priority
+      {
+        // WRITE
+        if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
         {
@@ -5640,5 +6139,4 @@
           break;
         }
-
         if(r_write_to_cc_send_brdcast_req.read())
         {
@@ -5647,6 +6145,19 @@
           break;
         }
-
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||
+        // CONFIG
+        if(r_config_to_cc_send_multi_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        if(r_config_to_cc_send_brdcast_req.read())
+        {
+          r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+          m_cpt_inval++;
+          break;
+        }
+        // XRAM_RSP
+        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
             r_xram_rsp_to_cc_send_multi_req.read())
         {
@@ -5655,5 +6166,4 @@
           break;
         }
-
         if(r_xram_rsp_to_cc_send_brdcast_req.read())
         {
@@ -5662,6 +6172,6 @@
           break;
         }
-
-        if(m_cas_to_cc_send_inst_fifo.rok() ||
+        // CAS
+        if(m_cas_to_cc_send_inst_fifo.rok() or
             r_cas_to_cc_send_multi_req.read())
         {
@@ -5670,5 +6180,4 @@
           break;
         }
-
         if(r_cas_to_cc_send_brdcast_req.read())
         {
@@ -5677,16 +6186,67 @@
           break;
         }
-
+        // CLEANUP
         if(r_cleanup_to_cc_send_req.read())
         {
           r_cc_send_fsm = CC_SEND_CLEANUP_ACK;
-        }
-
+          break;
+        }
         break;
       }
-
-    case CC_SEND_CLEANUP_ACK:
-      {
-        // send only flit for a cleanup acknowledgement (from CLEANUP FSM)
+      /////////////////////////////////
+      case CC_SEND_CONFIG_INVAL_HEADER:   // send first flit multi-inval (from CONFIG FSM)
+      {
+        if(m_config_to_cc_send_inst_fifo.rok())
+        {
+          if(not p_dspin_out.read) break;
+          r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE;
+          break;
+        }
+        if(r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false;
+        r_cc_send_fsm = CC_SEND_CONFIG_IDLE;
+        break;
+      }
+      ////////////////////////////////
+      case CC_SEND_CONFIG_INVAL_NLINE:    // send second flit multi-inval (from CONFIG FSM)
+      {
+        if(not p_dspin_out.read) break;
+        m_cpt_inval_mult++;
+        config_to_cc_send_fifo_get = true;
+        r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+
+#if DEBUG_MEMC_CC_SEND
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_CONFIG_INVAL_NLINE> multi-inval for line "
+          << std::hex << r_config_to_cc_send_nline.read() << std::endl;
+#endif
+        break;
+      }
+      ///////////////////////////////////
+      case CC_SEND_CONFIG_BRDCAST_HEADER:   // send first flit BC-inval (from CONFIG FSM)
+      {
+        if(not p_dspin_out.read) break;
+        r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE;
+        break;
+      }
+      //////////////////////////////////
+      case CC_SEND_CONFIG_BRDCAST_NLINE:    // send second flit BC-inval (from CONFIG FSM)
+      {
+        if(not p_dspin_out.read) break;
+        m_cpt_inval_brdcast++;
+        r_config_to_cc_send_brdcast_req = false;
+        r_cc_send_fsm = CC_SEND_CONFIG_IDLE;
+
+#if DEBUG_MEMC_CC_SEND
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_CONFIG_BRDCAST_NLINE> BC-Inval for line "
+          << std::hex << r_config_to_cc_send_nline.read() << std::endl;
+#endif
+        break;
+      }
+      /////////////////////////
+      case CC_SEND_CLEANUP_ACK:   // send one flit for a cleanup acknowledgement 
+      {
         if(not p_dspin_out.read) break;
 
@@ -5695,103 +6255,73 @@
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid "
-            << r_cleanup_to_cc_send_srcid.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_CLEANUP_ACK> Cleanup Ack for srcid "
+          << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl;
 #endif
         break;
       }
-
-    case CC_SEND_XRAM_RSP_INVAL_HEADER:
-      {
-        // send first flit multi-inval (from XRAM_RSP FSM)
+      ///////////////////////////////////
+      case CC_SEND_XRAM_RSP_INVAL_HEADER:   // send first flit multi-inval (from XRAM_RSP FSM)
+      {
         if(m_xram_rsp_to_cc_send_inst_fifo.rok())
         {
           if(not p_dspin_out.read) break;
-
           r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE;
           break;
         }
-
-        if(r_xram_rsp_to_cc_send_multi_req.read())
-        {
-          r_xram_rsp_to_cc_send_multi_req = false;
-        }
-
+        if(r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false;
         r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE;
         break;
       }
-
-    case CC_SEND_XRAM_RSP_INVAL_NLINE:
-      {
-        // send second flit multi-inval (from XRAM_RSP FSM)
+      //////////////////////////////////
+      case CC_SEND_XRAM_RSP_INVAL_NLINE:   // send second flit multi-inval (from XRAM_RSP FSM)
+      {
         if(not p_dspin_out.read) break;
-
         m_cpt_inval_mult++;
-
         xram_rsp_to_cc_send_fifo_get = true;
-        r_cc_send_fsm                = CC_SEND_XRAM_RSP_INVAL_HEADER;
+        r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".CC_SEND_XRAM_RSP_INVAL_NLINE> Broadcast-Inval for line "
-            << r_xram_rsp_to_cc_send_nline.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_XRAM_RSP_INVAL_NLINE> BC-Inval for line "
+          << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl;
 #endif
         break;
       }
-
-    case CC_SEND_XRAM_RSP_BRDCAST_HEADER:
-      {
-        // send first flit broadcast-inval (from XRAM_RSP FSM)
+      /////////////////////////////////////
+      case CC_SEND_XRAM_RSP_BRDCAST_HEADER:  // send first flit broadcast-inval (from XRAM_RSP FSM)
+      {
         if(not p_dspin_out.read) break;
-
         r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE;
         break;
       }
-
-    case CC_SEND_XRAM_RSP_BRDCAST_NLINE:
-      {
-        // send second flit broadcast-inval (from XRAM_RSP FSM)
+      ////////////////////////////////////
+      case CC_SEND_XRAM_RSP_BRDCAST_NLINE:   // send second flit broadcast-inval (from XRAM_RSP FSM)
+      {
         if(not p_dspin_out.read) break;
-
         m_cpt_inval_brdcast++;
-
         r_xram_rsp_to_cc_send_brdcast_req = false;
         r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".CC_SEND_XRAM_RSP_BRDCAST_NLINE> Broadcast-Inval for line "
-            << r_xram_rsp_to_cc_send_nline.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> BC-Inval for line "
+          << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl;
 #endif
         break;
       }
-
-    case CC_SEND_WRITE_BRDCAST_HEADER:
-      {
-        // send first flit broadcast-inval (from WRITE FSM)
+      //////////////////////////////////
+      case CC_SEND_WRITE_BRDCAST_HEADER:   // send first flit broadcast-inval (from WRITE FSM)
+      {
         if(not p_dspin_out.read) break;
-
         r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE;
         break;
       }
-
-    case CC_SEND_WRITE_BRDCAST_NLINE:
-      {
-        // send second flit broadcast-inval (from WRITE FSM)
+      /////////////////////////////////
+      case CC_SEND_WRITE_BRDCAST_NLINE:   // send second flit broadcast-inval (from WRITE FSM)
+      {
         if(not p_dspin_out.read) break;
 
@@ -5802,19 +6332,14 @@
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".CC_SEND_WRITE_BRDCAST_NLINE> Broadcast-Inval for line "
-            << r_write_to_cc_send_nline.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_WRITE_BRDCAST_NLINE> BC-Inval for line "
+          << std::hex << r_write_to_cc_send_nline.read() << std::endl;
 #endif
         break;
       }
-
-    case CC_SEND_WRITE_UPDT_HEADER:
-      {
-        // send first flit for a multi-update (from WRITE FSM)
+      ///////////////////////////////
+      case CC_SEND_WRITE_UPDT_HEADER:   // send first flit for a multi-update (from WRITE FSM)
+      {
         if(m_write_to_cc_send_inst_fifo.rok())
         {
@@ -5833,10 +6358,8 @@
         break;
       }
-
-    case CC_SEND_WRITE_UPDT_NLINE:
-      {
-        // send second flit for a multi-update (from WRITE FSM)
+      //////////////////////////////
+      case CC_SEND_WRITE_UPDT_NLINE:   // send second flit for a multi-update (from WRITE FSM)
+      {
         if(not p_dspin_out.read) break;
-
         m_cpt_update_mult++;
 
@@ -5845,21 +6368,15 @@
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".CC_SEND_WRITE_UPDT_NLINE> Multicast-Update for line "
-            << r_write_to_cc_send_nline.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_WRITE_UPDT_NLINE> Multicast-Update for line "
+          << r_write_to_cc_send_nline.read() << std::endl;
 #endif
         break;
       }
-
-    case CC_SEND_WRITE_UPDT_DATA:
-      {
-        // send N data flits for a multi-update (from WRITE FSM)
+      /////////////////////////////
+      case CC_SEND_WRITE_UPDT_DATA:   // send N data flits for a multi-update (from WRITE FSM)
+      {
         if(not p_dspin_out.read) break;
-
         if(r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1))
         {
@@ -5872,19 +6389,15 @@
         break;
       }
-
-    case CC_SEND_CAS_BRDCAST_HEADER:
-      {
-        // send first flit for a broadcast-inval (from CAS FSM)
+      ////////////////////////////////
+      case CC_SEND_CAS_BRDCAST_HEADER:   // send first flit  broadcast-inval (from CAS FSM)
+      {
         if(not p_dspin_out.read) break;
-
         r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE;
         break;
       }
-
-    case CC_SEND_CAS_BRDCAST_NLINE:
-      {
-        // send second flit broadcast-inval (from CAS FSM)
+      ///////////////////////////////
+      case CC_SEND_CAS_BRDCAST_NLINE:   // send second flit broadcast-inval (from CAS FSM)
+      {
         if(not p_dspin_out.read) break;
-
         m_cpt_inval_brdcast++;
 
@@ -5893,19 +6406,14 @@
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for line "
-            << r_cas_to_cc_send_nline.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for line "
+          << r_cas_to_cc_send_nline.read() << std::endl;
 #endif
         break;
       }
-
-    case CC_SEND_CAS_UPDT_HEADER:
-      {
-        // send first flit for a multi-update (from CAS FSM)
+      /////////////////////////////
+      case CC_SEND_CAS_UPDT_HEADER:   // send first flit for a multi-update (from CAS FSM)
+      {
         if(m_cas_to_cc_send_inst_fifo.rok())
         {
@@ -5925,8 +6433,7 @@
         break;
       }
-
-    case CC_SEND_CAS_UPDT_NLINE:
-      {
-        // send second flit for a multi-update (from CAS FSM)
+      ////////////////////////////
+      case CC_SEND_CAS_UPDT_NLINE:   // send second flit for a multi-update (from CAS FSM)
+      {
         if(not p_dspin_out.read) break;
 
@@ -5937,19 +6444,14 @@
 
 #if DEBUG_MEMC_CC_SEND
-        if(m_debug_cc_send_fsm)
-        {
-          std::cout
-            << "  <MEMC " << name()
-            << ".CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line "
-            << r_cas_to_cc_send_nline.read()
-            << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line "
+          << r_cas_to_cc_send_nline.read() << std::endl;
 #endif
         break;
       }
-
-    case CC_SEND_CAS_UPDT_DATA:
-      {
-        // send first data for a multi-update (from CAS FSM)
+      ///////////////////////////
+      case CC_SEND_CAS_UPDT_DATA:   // send first data for a multi-update (from CAS FSM)
+      {
         if(not p_dspin_out.read) break;
 
@@ -5964,10 +6466,8 @@
         break;
       }
-
-    case CC_SEND_CAS_UPDT_DATA_HIGH:
-      {
-        // send second data for a multi-update (from CAS FSM)
+      ////////////////////////////////
+      case CC_SEND_CAS_UPDT_DATA_HIGH:   // send second data for a multi-update (from CAS FSM)
+      {
         if(not p_dspin_out.read) break;
-
         cas_to_cc_send_fifo_get = true;
         r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
@@ -5982,8 +6482,9 @@
   // The CC_RECEIVE fsm controls the DSPIN target port on the coherence
   // network.
-  ///////////////////////////////////////////////////////////////////////////////
+  //////////////////////////////////////////////////////////////////////////////
 
   switch(r_cc_receive_fsm.read())
   {
+    /////////////////////
     case CC_RECEIVE_IDLE:
       {
@@ -5995,11 +6496,11 @@
               DspinDhccpParam::FROM_L1_TYPE);
 
-        if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) ||
-           (type == DspinDhccpParam::TYPE_CLEANUP_INST) )
-        { 
+        if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or
+           (type == DspinDhccpParam::TYPE_CLEANUP_INST))
+        {
           r_cc_receive_fsm = CC_RECEIVE_CLEANUP;
           break;
         }
-        
+
         if(type == DspinDhccpParam::TYPE_MULTI_ACK)
         {
@@ -6008,63 +6509,70 @@
         }
 
-        assert(
-            false && 
-            "VCI_MEM_CACHE ERROR: Incorrect type in coherence request from "
-            "L1 Cache");
-        
+        assert(false and
+            "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
+            "Illegal type in coherence request");
+
         break;
       }
+    ////////////////////////
     case CC_RECEIVE_CLEANUP:
       {
-        // wait for a valid cleanup flit
-        // wait for a WOK in the CC_RECEIVE to CLEANUP fifo
-        if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) break;
-
-        bool eop = (
-            DspinDhccpParam::dspin_get(
-              p_dspin_in.data.read(),
-              DspinDhccpParam::FROM_L1_EOP)
-            == 0x1);
+        // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo
+
+        if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok())
+          break;
+
+        assert(not p_dspin_in.eop.read() and
+            "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
+            "CLEANUP command must have two flits");
 
         cc_receive_to_cleanup_fifo_put = true;
-        if(eop)
-        {
-          r_cc_receive_fsm = CC_RECEIVE_IDLE;
-        }
+        r_cc_receive_fsm               = CC_RECEIVE_CLEANUP_EOP;
 
         break;
       }
+    ////////////////////////////
+    case CC_RECEIVE_CLEANUP_EOP:
+      {
+        // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo
+
+        if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok())
+          break;
+
+        assert(p_dspin_in.eop.read() and
+            "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
+            "CLEANUP command must have two flits");
+
+        cc_receive_to_cleanup_fifo_put = true;
+        r_cc_receive_fsm               = CC_RECEIVE_IDLE;
+
+        break;
+      }
+
+    //////////////////////////
     case CC_RECEIVE_MULTI_ACK:
       {
-        // wait for a valid multicast acknowledgement flit
+        // write MULTI_ACK flit in CC_RECEIVE to MULTI_ACK fifo
+
         // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo
-        if(not p_dspin_in.write or not m_cc_receive_to_multi_ack_fifo.wok()) break;
-
-        bool eop = (
-            DspinDhccpParam::dspin_get(
-              p_dspin_in.data.read(),
-              DspinDhccpParam::FROM_L1_EOP) 
-            == 0x1);
-
-        cc_receive_to_multi_ack_fifo_put  = true;
-        if(eop)
-        {
-          r_cc_receive_fsm = CC_RECEIVE_IDLE;
-        }
-
+        if(not p_dspin_in.write or not m_cc_receive_to_multi_ack_fifo.wok())
+          break;
+
+        assert(p_dspin_in.eop.read() and
+            "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
+            "MULTI_ACK command must have one flit");
+
+        cc_receive_to_multi_ack_fifo_put = true;
+        r_cc_receive_fsm                 = CC_RECEIVE_IDLE;
         break;
       }
-    default:
-      {
-        assert(
-            false &&
-            "VCI_MEM_CACHE ERROR: Invalid state in CC_RECEIVE FSM");
-      }
   }
-  /////////////////////////////////////////////////////////////////////
+  //////////////////////////////////////////////////////////////////////////
   //    TGT_RSP FSM
-  /////////////////////////////////////////////////////////////////////
+  //////////////////////////////////////////////////////////////////////////
   // The TGT_RSP fsm sends the responses on the VCI target port
-  // with a round robin priority between six requests :
+  // with a round robin priority between eigth requests :
+  // - r_config_to_tgt_rsp_req
+  // - r_tgt_cmd_to_tgt_rsp_req
   // - r_read_to_tgt_rsp_req
   // - r_write_to_tgt_rsp_req
@@ -6073,14 +6581,22 @@
   // - r_xram_rsp_to_tgt_rsp_req
   // - r_multi_ack_to_tgt_rsp_req
-  // The  ordering is :  read > write > cas > xram > init > cleanup
-  /////////////////////////////////////////////////////////////////////
+  //
+  // The ordering is :
+  //   config >tgt_cmd > read > write > cas > xram > multi_ack > cleanup
+  //////////////////////////////////////////////////////////////////////////
 
   switch(r_tgt_rsp_fsm.read())
   {
-    case TGT_RSP_READ_IDLE:
-    { 
-      // write requests have the highest priority
-      if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+    /////////////////////////
+    case TGT_RSP_CONFIG_IDLE:  // tgt_cmd requests have the highest priority
+    {
+      if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      else if(r_read_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_READ;
+        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+      }
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
       else if(r_xram_rsp_to_tgt_rsp_req)
       {
@@ -6088,17 +6604,19 @@
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
-      else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
-      else if(r_read_to_tgt_rsp_req)
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      break;
+    }
+    //////////////////////////
+    case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority
+    {
+      if(r_read_to_tgt_rsp_req)
       {
         r_tgt_rsp_fsm = TGT_RSP_READ;
         r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
       }
-      break;
-    }
-    ////////////////////////
-    case TGT_RSP_WRITE_IDLE:  // cas requests have the highest priority
-    {
-      if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS;
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
       else if(r_xram_rsp_to_tgt_rsp_req)
       {
@@ -6106,6 +6624,24 @@
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
-      else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      break;
+    }
+    ///////////////////////
+    case TGT_RSP_READ_IDLE: // write requests have the highest priority
+    {
+      if(r_write_to_tgt_rsp_req)          r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS;
+      else if(r_xram_rsp_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_XRAM;
+        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+      }
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
       else if(r_read_to_tgt_rsp_req)
       {
@@ -6113,18 +6649,19 @@
         r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
       }
-
-      else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      break;
-    }
-    ///////////////////////
-    case TGT_RSP_CAS_IDLE:   // xram_rsp requests have the highest priority
-    {
-      if(r_xram_rsp_to_tgt_rsp_req)
+      break;
+    }
+    ////////////////////////
+    case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority
+    {
+      if(r_cas_to_tgt_rsp_req)            r_tgt_rsp_fsm = TGT_RSP_CAS;
+      else if(r_xram_rsp_to_tgt_rsp_req)
       {
         r_tgt_rsp_fsm = TGT_RSP_XRAM;
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
-      else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
       else if(r_read_to_tgt_rsp_req)
       {
@@ -6132,14 +6669,19 @@
         r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
       }
-      else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
       break;
     }
     ///////////////////////
-    case TGT_RSP_XRAM_IDLE:   // init requests have the highest priority
-    {
-
-      if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
-      else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+    case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority
+    {
+      if(r_xram_rsp_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_XRAM;
+        r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+      }
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
+      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
       else if(r_read_to_tgt_rsp_req)
       {
@@ -6147,6 +6689,23 @@
         r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
       }
-      else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      break;
+    }
+    ///////////////////////
+    case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority
+    {
+
+      if(r_multi_ack_to_tgt_rsp_req)      r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
+      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      else if(r_read_to_tgt_rsp_req)
+      {
+        r_tgt_rsp_fsm = TGT_RSP_READ;
+        r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+      }
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
       else if(r_xram_rsp_to_tgt_rsp_req)
       {
@@ -6156,8 +6715,10 @@
       break;
     }
-    ///////////////////////
-    case TGT_RSP_INIT_IDLE:   // cleanup requests have the highest priority
-    {
-      if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+    ////////////////////////////
+    case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority
+    {
+      if(r_cleanup_to_tgt_rsp_req)        r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_config_to_tgt_rsp_req)    r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
       else if(r_read_to_tgt_rsp_req)
       {
@@ -6165,6 +6726,6 @@
         r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
       }
-      else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
       else if(r_xram_rsp_to_tgt_rsp_req)
       {
@@ -6172,17 +6733,19 @@
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_INIT;
-      break;
-    }
-    ///////////////////////
-    case TGT_RSP_CLEANUP_IDLE:    // read requests have the highest priority
-    {
-      if(r_read_to_tgt_rsp_req)
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
+      break;
+    }
+    //////////////////////////
+    case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority
+    {
+      if(r_config_to_tgt_rsp_req)         r_tgt_rsp_fsm = TGT_RSP_CONFIG;
+      else if(r_tgt_cmd_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;
+      else if(r_read_to_tgt_rsp_req)
       {
         r_tgt_rsp_fsm = TGT_RSP_READ;
         r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
       }
-      else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;
-      else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+      else if(r_write_to_tgt_rsp_req)     r_tgt_rsp_fsm = TGT_RSP_WRITE;
+      else if(r_cas_to_tgt_rsp_req)       r_tgt_rsp_fsm = TGT_RSP_CAS  ;
       else if(r_xram_rsp_to_tgt_rsp_req)
       {
@@ -6190,6 +6753,52 @@
         r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
       }
-      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
-      else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK   ;
+      else if(r_cleanup_to_tgt_rsp_req)   r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+      break;
+    }
+    ////////////////////
+    case TGT_RSP_CONFIG:  // send the response for a config transaction
+    {
+      if ( p_vci_tgt.rspack )
+      {
+        r_config_to_tgt_rsp_req = false;
+        r_tgt_rsp_fsm           = TGT_RSP_CONFIG_IDLE;
+
+#if DEBUG_MEMC_TGT_RSP
+if( m_debug )
+{
+  std::cout
+    << "  <MEMC " << name()
+    << " TGT_RSP_CONFIG>  Config transaction completed response"
+    << " / rsrcid = " << std::hex << r_config_to_tgt_rsp_srcid.read()
+    << " / rtrdid = " << r_config_to_tgt_rsp_trdid.read()
+    << " / rpktid = " << r_config_to_tgt_rsp_pktid.read()
+    << std::endl;
+}
+#endif
+      }
+      break;
+    }
+    /////////////////////
+    case TGT_RSP_TGT_CMD: // send the response for a segmentation violation
+    {
+      if ( p_vci_tgt.rspack )
+      {
+        r_tgt_cmd_to_tgt_rsp_req = false;
+        r_tgt_rsp_fsm            = TGT_RSP_TGT_CMD_IDLE;
+
+#if DEBUG_MEMC_TGT_RSP
+if( m_debug )
+{
+  std::cout
+    << "  <MEMC " << name()
+    << " TGT_RSP_TGT_CMD> Segmentation violation response"
+    << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read()
+    << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read()
+    << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read()
+    << std::endl;
+}
+#endif
+      }
       break;
     }
@@ -6201,21 +6810,23 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if( m_debug_tgt_rsp_fsm )
+if( m_debug )
 {
   std::cout
-    << "  <MEMC " << name() << ".TGT_RSP_READ> Read response"
-    << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read()
+    << "  <MEMC " << name() << " TGT_RSP_READ> Read response"
+    << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read()
     << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read()
     << " / rpktid = " << r_read_to_tgt_rsp_pktid.read()
-    << " / rdata = " << std::hex << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
+    << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
     << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
 }
 #endif
-  
-        uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length.read() - 1;
+
+        uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() +
+                                 r_read_to_tgt_rsp_length.read() - 1;
         bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
         bool     is_ll         = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
 
-        if ( (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll))
+        if ((is_last_word              and not is_ll) or
+            (r_tgt_rsp_key_sent.read() and is_ll))
         {
           // Last word in case of READ or second flit in case if LL
@@ -6245,11 +6856,9 @@
 
 #if DEBUG_MEMC_TGT_RSP
-        if(m_debug_tgt_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".TGT_RSP_WRITE> Write response"
-                    << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read()
-                    << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read()
-                    << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_RSP_WRITE> Write response"
+          << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read()
+          << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read()
+          << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl;
 #endif
         r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
@@ -6258,5 +6867,5 @@
       break;
     }
-    ///////////////////
+    /////////////////////
     case TGT_RSP_CLEANUP:   // pas clair pour moi (AG)
     {
@@ -6265,11 +6874,9 @@
 
 #if DEBUG_MEMC_TGT_RSP
-        if(m_debug_tgt_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".TGT_RSP_CLEANUP> Cleanup response"
-                    << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read()
-                    << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
-                    << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response"
+          << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read()
+          << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
+          << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl;
 #endif
         r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
@@ -6278,5 +6885,5 @@
       break;
     }
-    //////////////////
+    /////////////////
     case TGT_RSP_CAS:    // send one atomic word response
     {
@@ -6285,11 +6892,9 @@
 
 #if DEBUG_MEMC_TGT_RSP
-        if(m_debug_tgt_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".TGT_RSP_CAS> CAS response"
-                    << " / rsrcid = " << std::dec << r_cas_to_tgt_rsp_srcid.read()
-                    << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read()
-                    << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_RSP_CAS> CAS response"
+          << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read()
+          << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read()
+          << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl;
 #endif
         r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE;
@@ -6298,6 +6903,5 @@
       break;
     }
-
-    ///////////////////////
+    //////////////////
     case TGT_RSP_XRAM:    // send the response after XRAM access
     {
@@ -6306,16 +6910,14 @@
 
 #if DEBUG_MEMC_TGT_RSP
-if( m_debug_tgt_rsp_fsm )
-{
-  std::cout 
-    << "  <MEMC " << name() << ".TGT_RSP_XRAM> Response following XRAM access"
-    << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read()
-    << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
-    << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read()
-    << " / rdata = " << std::hex << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
-    << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
-}
-#endif
-        uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1;
+if( m_debug )
+std::cout << "  <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access"
+          << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read()
+          << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
+          << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read()
+          << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
+          << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
+#endif
+        uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() +
+                                 r_xram_rsp_to_tgt_rsp_length.read() - 1;
         bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
         bool     is_ll         = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
@@ -6335,5 +6937,5 @@
           {
             r_tgt_rsp_key_sent = true;                     // Send second flit of ll
-          }                                                                            
+          }
           else
           {
@@ -6344,6 +6946,6 @@
       break;
     }
-    //////////////////
-    case TGT_RSP_INIT:    // send the write response after coherence transaction
+    ///////////////////////
+    case TGT_RSP_MULTI_ACK:    // send the write response after coherence transaction
     {
       if(p_vci_tgt.rspack)
@@ -6351,13 +6953,11 @@
 
 #if DEBUG_MEMC_TGT_RSP
-        if(m_debug_tgt_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << ".TGT_RSP_INIT> Write response after coherence transaction"
-                    << " / rsrcid = " << std::dec << r_multi_ack_to_tgt_rsp_srcid.read()
-                    << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read()
-                    << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl;
-        }
-#endif
-        r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
+if(m_debug)
+std::cout << "  <MEMC " << name() << " TGT_RSP_MULTI_ACK> Write response after coherence transaction"
+          << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read()
+          << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read()
+          << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl;
+#endif
+        r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE;
         r_multi_ack_to_tgt_rsp_req = false;
       }
@@ -6369,10 +6969,13 @@
   //    ALLOC_UPT FSM
   ////////////////////////////////////////////////////////////////////////////////////
-  // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
-  // with a round robin priority between three FSMs : MULTI_ACK > WRITE > XRAM_RSP > CLEANUP
-  // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
-  // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+  // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT),
+  // with a round robin priority between six FSMs, with the following order:
+  //  CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS
+  // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT.
   // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry.
+  // - The WRITE FSM initiates update transaction and sets a new entry in UPT.
+  // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT.
   // - The CLEANUP  FSM decrement an entry in UPT.
+  // - The CAS FSM does the same thing as the WRITE FSM.
   // The resource is always allocated.
   /////////////////////////////////////////////////////////////////////////////////////
@@ -6380,11 +6983,33 @@
   switch(r_alloc_upt_fsm.read())
   {
-
-      ////////////////////////
-    case ALLOC_UPT_MULTI_ACK:
-      if((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) &&
+      //////////////////////
+      case ALLOC_UPT_CONFIG:   // allocated to CONFIG FSM
+      if (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK)
+      {
+        if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
+          r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
+               
+        else if((r_write_fsm.read() == WRITE_UPT_LOCK) or
+                (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+
+        else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)
+          r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+
+        else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)
+          r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+
+        else if((r_cas_fsm.read() == CAS_UPT_LOCK) or
+                (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
+          r_alloc_upt_fsm = ALLOC_UPT_CAS;
+      }
+      break;
+
+      /////////////////////////
+      case ALLOC_UPT_MULTI_ACK:   // allocated to MULTI_ACK FSM
+      if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and
           (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR))
       {
-        if((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+        if((r_write_fsm.read() == WRITE_UPT_LOCK) or
             (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_WRITE;
@@ -6396,13 +7021,16 @@
           r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
 
-        else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_UPT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_CAS;
+
+        else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
       }
       break;
 
       /////////////////////
-    case ALLOC_UPT_WRITE:
-      if((r_write_fsm.read() != WRITE_UPT_LOCK) &&
+      case ALLOC_UPT_WRITE:   // allocated to WRITE FSM
+      if((r_write_fsm.read() != WRITE_UPT_LOCK) and
           (r_write_fsm.read() != WRITE_BC_UPT_LOCK))
       {
@@ -6413,8 +7041,11 @@
           r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
 
-        else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_UPT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_CAS;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
+
         else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
           r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
@@ -6423,5 +7054,5 @@
 
       ////////////////////////
-    case ALLOC_UPT_XRAM_RSP:
+      case ALLOC_UPT_XRAM_RSP:
       if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)
       {
@@ -6429,12 +7060,15 @@
           r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
 
-        else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_UPT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_CAS;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
+
         else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
           r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
 
-        else if((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
+        else if((r_write_fsm.read() == WRITE_UPT_LOCK)   or
                 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_WRITE;
@@ -6443,16 +7077,19 @@
 
       //////////////////////////
-    case ALLOC_UPT_CLEANUP:
-      if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK     ) &&
+      case ALLOC_UPT_CLEANUP:
+      if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK     ) and
          (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT))
       {
-        if((r_cas_fsm.read() == CAS_UPT_LOCK) ||
+        if((r_cas_fsm.read() == CAS_UPT_LOCK) or
             (r_cas_fsm.read() == CAS_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_CAS;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
+
         else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
           r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
 
-        else if((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_UPT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_WRITE;
@@ -6464,12 +7101,15 @@
 
       //////////////////////////
-    case ALLOC_UPT_CAS:
-      if((r_cas_fsm.read() != CAS_UPT_LOCK) &&
+      case ALLOC_UPT_CAS:
+      if((r_cas_fsm.read() != CAS_UPT_LOCK) and
           (r_cas_fsm.read() != CAS_BC_UPT_LOCK))
       {
-        if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
+        if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 
+          r_alloc_upt_fsm = ALLOC_UPT_CONFIG;
+
+        else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)
           r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;
 
-        else if((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_UPT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))
           r_alloc_upt_fsm = ALLOC_UPT_WRITE;
@@ -6489,6 +7129,6 @@
   ////////////////////////////////////////////////////////////////////////////////////
   // The ALLOC_DIR FSM allocates the access to the directory and
-  // the data cache with a round robin priority between 5 user FSMs :
-  // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP
+  // the data cache with a round robin priority between 6 user FSMs :
+  // The cyclic ordering is CONFIG > READ > WRITE > CAS > CLEANUP > XRAM_RSP
   // The ressource is always allocated.
   /////////////////////////////////////////////////////////////////////////////////////
@@ -6496,7 +7136,7 @@
   switch(r_alloc_dir_fsm.read())
   {
-    case ALLOC_DIR_RESET:
-      // Initializes the directory one SET each cycle. All the WAYS of a SET are
-      // initialize in parallel
+    /////////////////////
+    case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle.
+                          // All the WAYS of a SET initialized in parallel
 
       r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1);
@@ -6505,19 +7145,41 @@
       {
         m_cache_directory.init();
-
         r_alloc_dir_fsm = ALLOC_DIR_READ;
       }
       break;
 
-      ////////////////////
-    case ALLOC_DIR_READ:
-      if(((r_read_fsm.read()        != READ_DIR_REQ)   &&
-          (r_read_fsm.read()        != READ_DIR_LOCK)   &&
-          (r_read_fsm.read()        != READ_TRT_LOCK)   &&
-          (r_read_fsm.read()        != READ_HEAP_REQ))
-          ||
-          ((r_read_fsm.read()       == READ_TRT_LOCK)   &&
-           (r_alloc_trt_fsm.read()  == ALLOC_TRT_READ)))
-      {
+    //////////////////////
+    case ALLOC_DIR_CONFIG:    // allocated to CONFIG FSM
+    if ( (r_config_fsm.read()    != CONFIG_DIR_REQ) and
+         (r_config_fsm.read()    != CONFIG_DIR_ACCESS) and
+         (r_config_fsm.read()    != CONFIG_DIR_UPT_LOCK) )
+    {
+        if(r_read_fsm.read() == READ_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_READ;
+
+        else if(r_write_fsm.read() == WRITE_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+
+        else if(r_cas_fsm.read() == CAS_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CAS;
+
+        else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+
+        else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
+          r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+    }
+    break;
+
+    ////////////////////
+    case ALLOC_DIR_READ:    // allocated to READ FSM
+    if( ((r_read_fsm.read()      != READ_DIR_REQ)   and
+         (r_read_fsm.read()      != READ_DIR_LOCK)   and
+         (r_read_fsm.read()      != READ_TRT_LOCK)   and
+         (r_read_fsm.read()      != READ_HEAP_REQ))
+         or
+         ((r_read_fsm.read()       == READ_TRT_LOCK)   and
+          (r_alloc_trt_fsm.read()  == ALLOC_TRT_READ)) )
+    {
         if(r_write_fsm.read() == WRITE_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_WRITE;
@@ -6531,25 +7193,28 @@
         else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
-      }
-      break;
-
-      /////////////////////
-    case ALLOC_DIR_WRITE:
-      if(((r_write_fsm.read()       != WRITE_DIR_REQ)  &&
-          (r_write_fsm.read()       != WRITE_DIR_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_DIR_READ)  &&
-          (r_write_fsm.read()       != WRITE_DIR_HIT)  &&
-          (r_write_fsm.read()       != WRITE_BC_TRT_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_BC_UPT_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_MISS_TRT_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_UPT_LOCK)  &&
-          (r_write_fsm.read()       != WRITE_UPT_HEAP_LOCK))
-          ||
-          ((r_write_fsm.read()      == WRITE_UPT_HEAP_LOCK)  &&
-           (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE))
-          ||
-          ((r_write_fsm.read()      == WRITE_MISS_TRT_LOCK)  &&
-           (r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE)))
-      {
+
+        else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+    }
+    break;
+
+    /////////////////////
+    case ALLOC_DIR_WRITE:    // allocated to WRITE FSM
+    if(((r_write_fsm.read()       != WRITE_DIR_REQ)  and
+        (r_write_fsm.read()       != WRITE_DIR_LOCK)  and
+        (r_write_fsm.read()       != WRITE_DIR_READ)  and
+        (r_write_fsm.read()       != WRITE_DIR_HIT)  and
+        (r_write_fsm.read()       != WRITE_BC_TRT_LOCK)  and
+        (r_write_fsm.read()       != WRITE_BC_UPT_LOCK)  and
+        (r_write_fsm.read()       != WRITE_MISS_TRT_LOCK)  and
+        (r_write_fsm.read()       != WRITE_UPT_LOCK)  and
+        (r_write_fsm.read()       != WRITE_UPT_HEAP_LOCK))
+        or
+        ((r_write_fsm.read()      == WRITE_UPT_HEAP_LOCK)  and
+         (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE))
+        or
+        ((r_write_fsm.read()      == WRITE_MISS_TRT_LOCK)  and
+         (r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE)))
+    {
         if(r_cas_fsm.read() == CAS_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CAS;
@@ -6561,28 +7226,31 @@
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+
         else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
-      }
-      break;
-
-      ////////////////////
-    case ALLOC_DIR_CAS:
-      if(((r_cas_fsm.read()         != CAS_DIR_REQ)  &&
-          (r_cas_fsm.read()         != CAS_DIR_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_DIR_HIT_READ)  &&
-          (r_cas_fsm.read()         != CAS_DIR_HIT_COMPARE)  &&
-          (r_cas_fsm.read()         != CAS_DIR_HIT_WRITE)  &&
-          (r_cas_fsm.read()         != CAS_BC_TRT_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_BC_UPT_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_MISS_TRT_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_UPT_LOCK)  &&
-          (r_cas_fsm.read()         != CAS_UPT_HEAP_LOCK))
-          ||
-          ((r_cas_fsm.read()        == CAS_UPT_HEAP_LOCK)  &&
-           (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS))
-          ||
-          ((r_cas_fsm.read()        == CAS_MISS_TRT_LOCK)  &&
-           (r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS)))
-      {
+    }
+    break;
+
+    ///////////////////
+    case ALLOC_DIR_CAS:    // allocated to CAS FSM
+    if(((r_cas_fsm.read()         != CAS_DIR_REQ)  and
+        (r_cas_fsm.read()         != CAS_DIR_LOCK)  and
+        (r_cas_fsm.read()         != CAS_DIR_HIT_READ)  and
+        (r_cas_fsm.read()         != CAS_DIR_HIT_COMPARE)  and
+        (r_cas_fsm.read()         != CAS_DIR_HIT_WRITE)  and
+        (r_cas_fsm.read()         != CAS_BC_TRT_LOCK)  and
+        (r_cas_fsm.read()         != CAS_BC_UPT_LOCK)  and
+        (r_cas_fsm.read()         != CAS_MISS_TRT_LOCK)  and
+        (r_cas_fsm.read()         != CAS_UPT_LOCK)  and
+        (r_cas_fsm.read()         != CAS_UPT_HEAP_LOCK))
+        or
+        ((r_cas_fsm.read()        == CAS_UPT_HEAP_LOCK)  and
+         (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS))
+        or
+        ((r_cas_fsm.read()        == CAS_MISS_TRT_LOCK)  and
+         (r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS)))
+    {
         if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
@@ -6591,4 +7259,7 @@
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+
         else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
@@ -6596,17 +7267,20 @@
         else if(r_write_fsm.read() == WRITE_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_WRITE;
-      }
-      break;
-
-      ///////////////////////
-    case ALLOC_DIR_CLEANUP:
-      if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) &&
-          (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) &&
-          (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) &&
-          (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK))
-      {
+    }
+      break;
+
+    ///////////////////////
+    case ALLOC_DIR_CLEANUP:    // allocated to CLEANUP FSM
+    if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and
+        (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and
+        (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
+        (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK))
+    {
         if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
           r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+
         else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
@@ -6617,14 +7291,17 @@
         else if(r_cas_fsm.read() == CAS_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CAS;
-      }
-      break;
-
-      ////////////////////////
-    case ALLOC_DIR_XRAM_RSP:
-      if((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) &&
-          (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) &&
-          (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
-      {
-        if(r_read_fsm.read() == READ_DIR_REQ)
+    }
+    break;
+
+    ////////////////////////
+    case ALLOC_DIR_XRAM_RSP:    // allocated to XRAM_RSP FSM
+    if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and
+        (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and
+        (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
+    {
+        if(r_config_fsm.read() == CONFIG_DIR_REQ)
+          r_alloc_dir_fsm = ALLOC_DIR_CONFIG;
+
+        else if(r_read_fsm.read() == READ_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_READ;
 
@@ -6637,6 +7314,6 @@
         else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ)
           r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
-      }
-      break;
+    }
+    break;
 
   } // end switch alloc_dir_fsm
@@ -6653,21 +7330,21 @@
   switch(r_alloc_trt_fsm.read())
   {
-      ////////////////////
+    ////////////////////
     case ALLOC_TRT_READ:
       if(r_read_fsm.read() != READ_TRT_LOCK)
       {
-        if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+        if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
             (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
@@ -6675,19 +7352,19 @@
       break;
 
-      /////////////////////
+    /////////////////////
     case ALLOC_TRT_WRITE:
-      if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) &&
-          (r_write_fsm.read() != WRITE_BC_TRT_LOCK) &&
+      if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and
+          (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and
           (r_write_fsm.read() != WRITE_BC_UPT_LOCK))
       {
-        if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+        if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
             (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
@@ -6698,15 +7375,15 @@
       break;
 
-      ////////////////////
+    ////////////////////
     case ALLOC_TRT_CAS:
-      if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) &&
-          (r_cas_fsm.read() != CAS_BC_TRT_LOCK) &&
+      if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and
+          (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and
           (r_cas_fsm.read() != CAS_BC_UPT_LOCK))
       {
-        if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+        if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
             (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
 
-        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+        else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
@@ -6715,5 +7392,5 @@
           r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
@@ -6721,13 +7398,13 @@
       break;
 
-      ////////////////////////
+    ////////////////////////
     case ALLOC_TRT_XRAM_RSP:
-      if(((r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_LOCK)  ||
-          (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) &&
-          (r_xram_rsp_fsm.read()  != XRAM_RSP_TRT_COPY)  &&
-          (r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_UPDT)  &&
+      if(((r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_LOCK)  or
+          (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and
+          (r_xram_rsp_fsm.read()  != XRAM_RSP_TRT_COPY)  and
+          (r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_UPDT)  and
           (r_xram_rsp_fsm.read()  != XRAM_RSP_INVAL_LOCK))
       {
-        if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+        if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or
             (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))
           r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
@@ -6736,9 +7413,9 @@
           r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
@@ -6746,7 +7423,7 @@
       break;
 
-      ////////////////////////
+    ////////////////////////
     case ALLOC_TRT_IXR_RSP:
-      if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
+      if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and
           (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ))
       {
@@ -6754,13 +7431,13 @@
           r_alloc_trt_fsm = ALLOC_TRT_READ;
 
-        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||
+        else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or
                 (r_write_fsm.read() == WRITE_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_WRITE;
 
-        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||
+        else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or
                 (r_cas_fsm.read() == CAS_BC_TRT_LOCK))
           r_alloc_trt_fsm = ALLOC_TRT_CAS;
 
-        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) &&
+        else if((r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK) and
                 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP))
           r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
@@ -6774,6 +7451,6 @@
   ////////////////////////////////////////////////////////////////////////////////////
   // The ALLOC_HEAP FSM allocates the access to the heap
-  // with a round robin priority between 5 user FSMs :
-  // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP
+  // with a round robin priority between 6 user FSMs :
+  // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP > CONFIG
   // The ressource is always allocated.
   /////////////////////////////////////////////////////////////////////////////////////
@@ -6782,5 +7459,5 @@
   {
       ////////////////////
-    case ALLOC_HEAP_RESET:
+      case ALLOC_HEAP_RESET:
       // Initializes the heap one ENTRY each cycle.
 
@@ -6796,7 +7473,7 @@
 
       ////////////////////
-    case ALLOC_HEAP_READ:
-      if((r_read_fsm.read() != READ_HEAP_REQ) &&
-          (r_read_fsm.read() != READ_HEAP_LOCK) &&
+      case ALLOC_HEAP_READ:
+      if((r_read_fsm.read() != READ_HEAP_REQ) and
+          (r_read_fsm.read() != READ_HEAP_LOCK) and
           (r_read_fsm.read() != READ_HEAP_ERASE))
       {
@@ -6812,11 +7489,14 @@
         else if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
           r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+
+        else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+          r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
       }
       break;
 
       /////////////////////
-    case ALLOC_HEAP_WRITE:
-      if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) &&
-          (r_write_fsm.read() != WRITE_UPT_REQ) &&
+      case ALLOC_HEAP_WRITE:
+      if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and
+          (r_write_fsm.read() != WRITE_UPT_REQ) and
           (r_write_fsm.read() != WRITE_UPT_NEXT))
       {
@@ -6830,4 +7510,7 @@
           r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+          r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
+
         else if(r_read_fsm.read() == READ_HEAP_REQ)
           r_alloc_heap_fsm = ALLOC_HEAP_READ;
@@ -6836,7 +7519,7 @@
 
       ////////////////////
-    case ALLOC_HEAP_CAS:
-      if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) &&
-          (r_cas_fsm.read() != CAS_UPT_REQ) &&
+      case ALLOC_HEAP_CAS:
+      if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and
+          (r_cas_fsm.read() != CAS_UPT_REQ) and
           (r_cas_fsm.read() != CAS_UPT_NEXT))
       {
@@ -6847,4 +7530,7 @@
           r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+          r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
+
         else if(r_read_fsm.read() == READ_HEAP_REQ)
           r_alloc_heap_fsm = ALLOC_HEAP_READ;
@@ -6856,8 +7542,8 @@
 
       ///////////////////////
-    case ALLOC_HEAP_CLEANUP:
-      if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) &&
-          (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) &&
-          (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) &&
+      case ALLOC_HEAP_CLEANUP:
+      if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and
+          (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and
+          (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and
           (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN))
       {
@@ -6865,4 +7551,7 @@
           r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
 
+        else if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+          r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
+
         else if(r_read_fsm.read() == READ_HEAP_REQ)
           r_alloc_heap_fsm = ALLOC_HEAP_READ;
@@ -6877,7 +7566,30 @@
 
       ////////////////////////
-    case ALLOC_HEAP_XRAM_RSP:
-      if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) &&
+      case ALLOC_HEAP_XRAM_RSP:
+      if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and
           (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE))
+      {
+        if(r_config_fsm.read() == CONFIG_HEAP_REQ)
+          r_alloc_heap_fsm = ALLOC_HEAP_CONFIG;
+
+        else if(r_read_fsm.read() == READ_HEAP_REQ)
+          r_alloc_heap_fsm = ALLOC_HEAP_READ;
+
+        else if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK)
+          r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+
+        else if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK)
+          r_alloc_heap_fsm = ALLOC_HEAP_CAS;
+
+        else if(r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)
+          r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+
+      }
+      break;
+
+      ///////////////////////
+      case ALLOC_HEAP_CONFIG:
+      if((r_config_fsm.read() != CONFIG_HEAP_REQ) and
+          (r_config_fsm.read() != CONFIG_HEAP_SCAN))
       {
         if(r_read_fsm.read() == READ_HEAP_REQ)
@@ -6893,4 +7605,6 @@
           r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
 
+        if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)
+          r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
       }
       break;
@@ -6898,138 +7612,62 @@
   } // end switch alloc_heap_fsm
 
-
-  ////////////////////////////////////////////////////////////////////////////////////
+  /////////////////////////////////////////////////////////////////////
   //    TGT_CMD to READ FIFO
-  ////////////////////////////////////////////////////////////////////////////////////
-
-  if(cmd_read_fifo_put)
-  {
-    if(cmd_read_fifo_get)
-    {
-      m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
-      m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read() >>2);
-      m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
-      m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
-      m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
-    }
-    else
-    {
-      m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
-      m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read() >>2);
-      m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
-      m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
-      m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
-    }
-  }
-  else
-  {
-    if(cmd_read_fifo_get)
-    {
-      m_cmd_read_addr_fifo.simple_get();
-      m_cmd_read_length_fifo.simple_get();
-      m_cmd_read_srcid_fifo.simple_get();
-      m_cmd_read_trdid_fifo.simple_get();
-      m_cmd_read_pktid_fifo.simple_get();
-    }
-  }
+  /////////////////////////////////////////////////////////////////////
+
+  m_cmd_read_addr_fifo.update(   cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.address.read() );
+  m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.plen.read()>>2 );
+  m_cmd_read_srcid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.srcid.read() );
+  m_cmd_read_trdid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.trdid.read() );
+  m_cmd_read_pktid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+                                 p_vci_tgt.pktid.read() );
+
   /////////////////////////////////////////////////////////////////////
   //    TGT_CMD to WRITE FIFO
   /////////////////////////////////////////////////////////////////////
 
-  if(cmd_write_fifo_put)
-  {
-    if(cmd_write_fifo_get)
-    {
-      m_cmd_write_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
-      m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read());
-      m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
-      m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
-      m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
-      m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read());
-      m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read());
-    }
-    else
-    {
-      m_cmd_write_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
-      m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read());
-      m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
-      m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
-      m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
-      m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read());
-      m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read());
-    }
-  }
-  else
-  {
-    if(cmd_write_fifo_get)
-    {
-      m_cmd_write_addr_fifo.simple_get();
-      m_cmd_write_eop_fifo.simple_get();
-      m_cmd_write_srcid_fifo.simple_get();
-      m_cmd_write_trdid_fifo.simple_get();
-      m_cmd_write_pktid_fifo.simple_get();
-      m_cmd_write_data_fifo.simple_get();
-      m_cmd_write_be_fifo.simple_get();
-    }
-  }
+  m_cmd_write_addr_fifo.update(  cmd_write_fifo_get, cmd_write_fifo_put,
+                                 (addr_t)p_vci_tgt.address.read() );
+  m_cmd_write_eop_fifo.update(   cmd_write_fifo_get, cmd_write_fifo_put,
+                                 p_vci_tgt.eop.read() );
+  m_cmd_write_srcid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put,
+                                 p_vci_tgt.srcid.read() );
+  m_cmd_write_trdid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put,
+                                 p_vci_tgt.trdid.read() );
+  m_cmd_write_pktid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put,
+                                 p_vci_tgt.pktid.read() );
+  m_cmd_write_data_fifo.update(  cmd_write_fifo_get, cmd_write_fifo_put,
+                                 p_vci_tgt.wdata.read() );
+  m_cmd_write_be_fifo.update(    cmd_write_fifo_get, cmd_write_fifo_put,
+                                 p_vci_tgt.be.read() );
+
   ////////////////////////////////////////////////////////////////////////////////////
   //    TGT_CMD to CAS FIFO
   ////////////////////////////////////////////////////////////////////////////////////
 
-  if(cmd_cas_fifo_put)
-  {
-    if(cmd_cas_fifo_get)
-    {
-      m_cmd_cas_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
-      m_cmd_cas_eop_fifo.put_and_get(p_vci_tgt.eop.read());
-      m_cmd_cas_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
-      m_cmd_cas_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
-      m_cmd_cas_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
-      m_cmd_cas_wdata_fifo.put_and_get(p_vci_tgt.wdata.read());
-    }
-    else
-    {
-      m_cmd_cas_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
-      m_cmd_cas_eop_fifo.simple_put(p_vci_tgt.eop.read());
-      m_cmd_cas_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
-      m_cmd_cas_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
-      m_cmd_cas_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
-      m_cmd_cas_wdata_fifo.simple_put(p_vci_tgt.wdata.read());
-    }
-  }
-  else
-  {
-    if(cmd_cas_fifo_get)
-    {
-      m_cmd_cas_addr_fifo.simple_get();
-      m_cmd_cas_eop_fifo.simple_get();
-      m_cmd_cas_srcid_fifo.simple_get();
-      m_cmd_cas_trdid_fifo.simple_get();
-      m_cmd_cas_pktid_fifo.simple_get();
-      m_cmd_cas_wdata_fifo.simple_get();
-    }
-  }
+  m_cmd_cas_addr_fifo.update(  cmd_cas_fifo_get, cmd_cas_fifo_put,
+                               (addr_t)p_vci_tgt.address.read() );
+  m_cmd_cas_eop_fifo.update(   cmd_cas_fifo_get, cmd_cas_fifo_put,
+                               p_vci_tgt.eop.read() );
+  m_cmd_cas_srcid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put,
+                               p_vci_tgt.srcid.read() );
+  m_cmd_cas_trdid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put,
+                               p_vci_tgt.trdid.read() );
+  m_cmd_cas_pktid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put,
+                               p_vci_tgt.pktid.read() );
+  m_cmd_cas_wdata_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put,
+                               p_vci_tgt.wdata.read() );
+
   ////////////////////////////////////////////////////////////////////////////////////
   //    CC_RECEIVE to CLEANUP FIFO
   ////////////////////////////////////////////////////////////////////////////////////
 
-  if(cc_receive_to_cleanup_fifo_put)
-  {
-    if(cc_receive_to_cleanup_fifo_get)
-    {
-      m_cc_receive_to_cleanup_fifo.put_and_get(p_dspin_in.data.read());
-    }
-    else
-    {
-      m_cc_receive_to_cleanup_fifo.simple_put(p_dspin_in.data.read());
-    }
-  }
-  else
-  {
-    if(cc_receive_to_cleanup_fifo_get)
-    {
-      m_cc_receive_to_cleanup_fifo.simple_get();
-    }
-  }
+  m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get,
+                                       cc_receive_to_cleanup_fifo_put, 
+                                       p_dspin_in.data.read() );
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -7037,22 +7675,7 @@
   ////////////////////////////////////////////////////////////////////////////////////
 
-  if(cc_receive_to_multi_ack_fifo_put)
-  {
-    if(cc_receive_to_multi_ack_fifo_get)
-    {
-      m_cc_receive_to_multi_ack_fifo.put_and_get(p_dspin_in.data.read());
-    }
-    else
-    {
-      m_cc_receive_to_multi_ack_fifo.simple_put(p_dspin_in.data.read());
-    }
-  }
-  else
-  {
-    if(cc_receive_to_multi_ack_fifo_get)
-    {
-      m_cc_receive_to_multi_ack_fifo.simple_get();
-    }
-  }
+  m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get,
+                                         cc_receive_to_multi_ack_fifo_put, 
+                                         p_dspin_in.data.read() );
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -7060,102 +7683,51 @@
   ////////////////////////////////////////////////////////////////////////////////////
 
-  if(write_to_cc_send_fifo_put)
-  {
-    if(write_to_cc_send_fifo_get)
-    {
-      m_write_to_cc_send_inst_fifo.put_and_get(write_to_cc_send_fifo_inst);
-      m_write_to_cc_send_srcid_fifo.put_and_get(write_to_cc_send_fifo_srcid);
+  m_write_to_cc_send_inst_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put,
+                                       write_to_cc_send_fifo_inst );
+  m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put,
+                                        write_to_cc_send_fifo_srcid );
 #if L1_MULTI_CACHE
-      m_write_to_cc_send_cache_id_fifo.put_and_get(write_to_cc_send_fifo_cache_id);
-#endif
-    }
-    else
-    {
-      m_write_to_cc_send_inst_fifo.simple_put(write_to_cc_send_fifo_inst);
-      m_write_to_cc_send_srcid_fifo.simple_put(write_to_cc_send_fifo_srcid);
+  m_write_to_cc_send_cache_id_fifo.update( write_to_cc_send_fifo_get, write_to_cc_send_fifo_put,
+                                           write_to_cc_send_fifo_cache_id );
+#endif
+
+  ////////////////////////////////////////////////////////////////////////////////////
+  //    CONFIG to CC_SEND FIFO
+  ////////////////////////////////////////////////////////////////////////////////////
+
+  m_config_to_cc_send_inst_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put,
+                                        config_to_cc_send_fifo_inst );
+  m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put,
+                                         config_to_cc_send_fifo_srcid );
 #if L1_MULTI_CACHE
-      m_write_to_cc_send_cache_id_fifo.simple_put(write_to_cc_send_fifo_cache_id);
-#endif
-    }
-  }
-  else
-  {
-    if(write_to_cc_send_fifo_get)
-    {
-      m_write_to_cc_send_inst_fifo.simple_get();
-      m_write_to_cc_send_srcid_fifo.simple_get();
-#if L1_MULTI_CACHE
-      m_write_to_cc_send_cache_id_fifo.simple_get();
-#endif
-    }
-  }
+  m_config_to_cc_send_cache_id_fifo.update( config_to_cc_send_fifo_get, config_to_cc_send_fifo_put,
+                                            config_to_cc_send_fifo_cache_id );
+#endif
+
   ////////////////////////////////////////////////////////////////////////////////////
   //    XRAM_RSP to CC_SEND FIFO
   ////////////////////////////////////////////////////////////////////////////////////
 
-  if(xram_rsp_to_cc_send_fifo_put)
-  {
-    if(xram_rsp_to_cc_send_fifo_get)
-    {
-      m_xram_rsp_to_cc_send_inst_fifo.put_and_get(xram_rsp_to_cc_send_fifo_inst);
-      m_xram_rsp_to_cc_send_srcid_fifo.put_and_get(xram_rsp_to_cc_send_fifo_srcid);
+  m_xram_rsp_to_cc_send_inst_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put,
+                                          xram_rsp_to_cc_send_fifo_inst );
+  m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put,
+                                           xram_rsp_to_cc_send_fifo_srcid );
 #if L1_MULTI_CACHE
-      m_xram_rsp_to_cc_send_cache_id_fifo.put_and_get(xram_rsp_to_cc_send_fifo_cache_id);
-#endif
-    }
-    else
-    {
-      m_xram_rsp_to_cc_send_inst_fifo.simple_put(xram_rsp_to_cc_send_fifo_inst);
-      m_xram_rsp_to_cc_send_srcid_fifo.simple_put(xram_rsp_to_cc_send_fifo_srcid);
-#if L1_MULTI_CACHE
-      m_xram_rsp_to_cc_send_cache_id_fifo.simple_put(xram_rsp_to_cc_send_fifo_cache_id);
-#endif
-    }
-  }
-  else
-  {
-    if(xram_rsp_to_cc_send_fifo_get)
-    {
-      m_xram_rsp_to_cc_send_inst_fifo.simple_get();
-      m_xram_rsp_to_cc_send_srcid_fifo.simple_get();
-#if L1_MULTI_CACHE
-      m_xram_rsp_to_cc_send_cache_id_fifo.simple_get();
-#endif
-    }
-  }
+  m_xram_rsp_to_cc_send_cache_id_fifo.update( xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put,
+                                              xram_rsp_to_cc_send_fifo_cache_id );
+#endif
+
   ////////////////////////////////////////////////////////////////////////////////////
   //    CAS to CC_SEND FIFO
   ////////////////////////////////////////////////////////////////////////////////////
 
-  if(cas_to_cc_send_fifo_put)
-  {
-    if(cas_to_cc_send_fifo_get)
-    {
-      m_cas_to_cc_send_inst_fifo.put_and_get(cas_to_cc_send_fifo_inst);
-      m_cas_to_cc_send_srcid_fifo.put_and_get(cas_to_cc_send_fifo_srcid);
+  m_cas_to_cc_send_inst_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put,
+                                     cas_to_cc_send_fifo_inst );
+  m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put,
+                                      cas_to_cc_send_fifo_srcid );
 #if L1_MULTI_CACHE
-      m_cas_to_cc_send_cache_id_fifo.put_and_get(cas_to_cc_send_fifo_cache_id);
-#endif
-    }
-    else
-    {
-      m_cas_to_cc_send_inst_fifo.simple_put(cas_to_cc_send_fifo_inst);
-      m_cas_to_cc_send_srcid_fifo.simple_put(cas_to_cc_send_fifo_srcid);
-#if L1_MULTI_CACHE
-      m_cas_to_cc_send_cache_id_fifo.simple_put(cas_to_cc_send_fifo_cache_id);
-#endif
-    }
-  }
-  else
-  {
-    if(cas_to_cc_send_fifo_get)
-    {
-      m_cas_to_cc_send_inst_fifo.simple_get();
-      m_cas_to_cc_send_srcid_fifo.simple_get();
-#if L1_MULTI_CACHE
-      m_cas_to_cc_send_cache_id_fifo.simple_get();
-#endif
-    }
-  }
+  m_cas_to_cc_send_cache_id_fifo.update( cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put,
+                                         cas_to_cc_send_fifo_cache_id );
+#endif
 
   m_cpt_cycles++;
@@ -7171,5 +7743,5 @@
   ////////////////////////////////////////////////////////////
 
-  p_vci_ixr.be      = 0xF;
+  p_vci_ixr.be      = 0xFF;   // nor transmited to external ram
   p_vci_ixr.pktid   = 0;
   p_vci_ixr.srcid   = m_srcid_x;
@@ -7179,79 +7751,80 @@
   p_vci_ixr.clen    = 0;
   p_vci_ixr.cfixed  = false;
-
-  if(r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE)
+  p_vci_ixr.plen    = 64;
+
+  if(r_ixr_cmd_fsm.read() == IXR_CMD_READ)
   {
-    p_vci_ixr.cmd     = vci_param::CMD_READ;
-    p_vci_ixr.cmdval  = true;
-    p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read() *m_words*4);
-    p_vci_ixr.plen    = m_words*4;
-    p_vci_ixr.wdata   = 0x00000000;
-    p_vci_ixr.trdid   = r_read_to_ixr_cmd_trdid.read();
-    p_vci_ixr.eop     = true;
+    p_vci_ixr.cmd       = vci_param_ext::CMD_READ;
+    p_vci_ixr.cmdval    = true;
+    p_vci_ixr.address   = (addr_t)(r_read_to_ixr_cmd_nline.read() * m_words * 4);
+    p_vci_ixr.wdata     = 0;
+    p_vci_ixr.trdid     = r_read_to_ixr_cmd_trdid.read();
+    p_vci_ixr.eop       = true;
   }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS_NLINE)
+  else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS)
   {
     if(r_cas_to_ixr_cmd_write.read())
     {
-      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      size_t word       = r_ixr_cmd_cpt.read();
+      p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
       p_vci_ixr.cmdval  = true;
-      p_vci_ixr.address = (addr_t)((r_cas_to_ixr_cmd_nline.read() *m_words+r_ixr_cmd_cpt.read()) *4);
-      p_vci_ixr.plen    = m_words*4;
-      p_vci_ixr.wdata   = r_cas_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.address = (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words + word) * 4 );
+      p_vci_ixr.wdata   = ((wide_data_t)(r_cas_to_ixr_cmd_data[word].read()))  |
+                          ((wide_data_t)(r_cas_to_ixr_cmd_data[word+1].read()) << 32);
       p_vci_ixr.trdid   = r_cas_to_ixr_cmd_trdid.read();
-      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-2));
     }
     else
     {
-      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmd     = vci_param_ext::CMD_READ;
       p_vci_ixr.cmdval  = true;
       p_vci_ixr.address = (addr_t)(r_cas_to_ixr_cmd_nline.read() *m_words*4);
-      p_vci_ixr.plen    = m_words*4;
-      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.wdata   = 0;
       p_vci_ixr.trdid   = r_cas_to_ixr_cmd_trdid.read();
       p_vci_ixr.eop     = true;
     }
   }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE)
+  else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE)
   {
     if(r_write_to_ixr_cmd_write.read())
     {
-      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
       p_vci_ixr.cmdval  = true;
-      p_vci_ixr.address = (addr_t)((r_write_to_ixr_cmd_nline.read() *m_words+r_ixr_cmd_cpt.read()) *4);
-      p_vci_ixr.plen    = m_words*4;
-      p_vci_ixr.wdata   = r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.address = (addr_t)( (r_write_to_ixr_cmd_nline.read() * m_words +
+                                     r_ixr_cmd_cpt.read()) * 4 );
+      p_vci_ixr.wdata   = ((wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) |
+                          ((wide_data_t)(r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32));
       p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
-      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-2));
     }
     else
     {
-      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmd     = vci_param_ext::CMD_READ;
       p_vci_ixr.cmdval  = true;
       p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read() *m_words*4);
-      p_vci_ixr.plen    = m_words*4;
-      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.wdata   = 0;
       p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
       p_vci_ixr.eop     = true;
     }
   }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA)
+  else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM)
   {
-    p_vci_ixr.cmd     = vci_param::CMD_WRITE;
-    p_vci_ixr.cmdval  = true;
-    p_vci_ixr.address = (addr_t)((r_xram_rsp_to_ixr_cmd_nline.read() *m_words+r_ixr_cmd_cpt.read()) *4);
-    p_vci_ixr.plen    = m_words*4;
-    p_vci_ixr.wdata   = r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
-    p_vci_ixr.trdid   = r_xram_rsp_to_ixr_cmd_trdid.read();
-    p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+    p_vci_ixr.cmd       = vci_param_ext::CMD_WRITE;
+    p_vci_ixr.cmdval    = true;
+    p_vci_ixr.address   = (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words +
+                                   r_ixr_cmd_cpt.read()) * 4 );
+    p_vci_ixr.wdata     = ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) |
+                          ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()+1].read()) << 32));
+    p_vci_ixr.trdid     = r_xram_rsp_to_ixr_cmd_trdid.read();
+    p_vci_ixr.eop       = (r_ixr_cmd_cpt == (m_words-2));
   }
   else
   {
-    p_vci_ixr.cmdval  = false;
-    p_vci_ixr.address = 0;
-    p_vci_ixr.plen    = 0;
-    p_vci_ixr.wdata   = 0;
-    p_vci_ixr.trdid   = 0;
-    p_vci_ixr.eop = false;
+    p_vci_ixr.cmdval    = false;
+    p_vci_ixr.cmd       = vci_param_ext::CMD_READ;
+    p_vci_ixr.address   = 0;
+    p_vci_ixr.wdata     = 0;
+    p_vci_ixr.trdid     = 0;
+    p_vci_ixr.eop       = false;
   }
 
@@ -7260,8 +7833,8 @@
   ////////////////////////////////////////////////////
 
-  if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
-      (r_ixr_rsp_fsm.read()   == IXR_RSP_TRT_READ)) ||
+  if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and
+      (r_ixr_rsp_fsm.read()   == IXR_RSP_TRT_READ)) or
       (r_ixr_rsp_fsm.read()   == IXR_RSP_ACK))
-    
+
     p_vci_ixr.rspack = true;
 
@@ -7276,21 +7849,22 @@
   {
     case TGT_CMD_IDLE:
-      p_vci_tgt.cmdack  = false;
+      p_vci_tgt.cmdack = false;
+      break;
+
+    case TGT_CMD_CONFIG:
+    case TGT_CMD_ERROR:
+      p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read();
       break;
 
     case TGT_CMD_READ:
-      p_vci_tgt.cmdack  = m_cmd_read_addr_fifo.wok();
+      p_vci_tgt.cmdack = m_cmd_read_addr_fifo.wok();
       break;
 
     case TGT_CMD_WRITE:
-      p_vci_tgt.cmdack  = m_cmd_write_addr_fifo.wok();
+      p_vci_tgt.cmdack = m_cmd_write_addr_fifo.wok();
       break;
 
     case TGT_CMD_CAS:
-      p_vci_tgt.cmdack  = m_cmd_cas_addr_fifo.wok();
-      break;
-
-    default:
-      p_vci_tgt.cmdack  = false;
+      p_vci_tgt.cmdack = m_cmd_cas_addr_fifo.wok();
       break;
   }
@@ -7302,10 +7876,13 @@
   switch(r_tgt_rsp_fsm.read())
   {
+    case TGT_RSP_CONFIG_IDLE:
+    case TGT_RSP_TGT_CMD_IDLE:
     case TGT_RSP_READ_IDLE:
     case TGT_RSP_WRITE_IDLE:
     case TGT_RSP_CAS_IDLE:
     case TGT_RSP_XRAM_IDLE:
-    case TGT_RSP_INIT_IDLE:
+    case TGT_RSP_MULTI_ACK_IDLE:
     case TGT_RSP_CLEANUP_IDLE:
+    {
       p_vci_tgt.rspval  = false;
       p_vci_tgt.rsrcid  = 0;
@@ -7316,4 +7893,30 @@
       p_vci_tgt.reop    = false;
       break;
+    }
+    case TGT_RSP_CONFIG:
+    {
+      p_vci_tgt.rspval  = true;
+      p_vci_tgt.rdata   = 0;
+      p_vci_tgt.rsrcid  = r_config_to_tgt_rsp_srcid.read();
+      p_vci_tgt.rtrdid  = r_config_to_tgt_rsp_trdid.read();
+      p_vci_tgt.rpktid  = r_config_to_tgt_rsp_pktid.read();
+      p_vci_tgt.rerror  = r_config_to_tgt_rsp_error.read();
+      p_vci_tgt.reop    = true;
+
+      break;
+    }
+
+    case TGT_RSP_TGT_CMD:
+    {
+      p_vci_tgt.rspval  = true;
+      p_vci_tgt.rdata   = 0;
+      p_vci_tgt.rsrcid  = r_tgt_cmd_to_tgt_rsp_srcid.read();
+      p_vci_tgt.rtrdid  = r_tgt_cmd_to_tgt_rsp_trdid.read();
+      p_vci_tgt.rpktid  = r_tgt_cmd_to_tgt_rsp_pktid.read();
+      p_vci_tgt.rerror  = r_tgt_cmd_to_tgt_rsp_error.read();
+      p_vci_tgt.reop    = true;
+
+      break;
+    }
 
     case TGT_RSP_READ:
@@ -7346,5 +7949,5 @@
     case TGT_RSP_WRITE:
       p_vci_tgt.rspval   = true;
-      if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) && r_write_to_tgt_rsp_sc_fail.read())
+      if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read())
         p_vci_tgt.rdata  = 1;
       else
@@ -7404,5 +8007,5 @@
     }
 
-    case TGT_RSP_INIT:
+    case TGT_RSP_MULTI_ACK:
       p_vci_tgt.rspval   = true;
       p_vci_tgt.rdata    = 0; // Can be a CAS or SC rsp
@@ -7416,19 +8019,71 @@
 
   ////////////////////////////////////////////////////////////////////
-  // Initiator command signals on the p_dspin_out port (CC_SEND FSM)
+  //  p_dspin_out port (CC_SEND FSM)
   ////////////////////////////////////////////////////////////////////
 
   p_dspin_out.write = false;
+  p_dspin_out.eop   = false;
   p_dspin_out.data  = 0;
 
   switch(r_cc_send_fsm.read())
   {
-  
+    ///////////////////////////
+    case CC_SEND_CONFIG_IDLE:
     case CC_SEND_XRAM_RSP_IDLE:
     case CC_SEND_WRITE_IDLE:
     case CC_SEND_CAS_IDLE:
     case CC_SEND_CLEANUP_IDLE:
+    {
         break;
-
+    }
+    ////////////////////////////////
+    case CC_SEND_CONFIG_INVAL_HEADER:
+    {
+        uint8_t multi_inval_type;
+        if(m_config_to_cc_send_inst_fifo.read())
+        {
+          multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST;
+        }
+        else
+        {
+          multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA;
+        }
+
+        uint64_t flit = 0;
+        uint64_t dest = m_config_to_cc_send_srcid_fifo.read() <<
+                        (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    dest,
+                                    DspinDhccpParam::MULTI_INVAL_DEST);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    m_cc_global_id,
+                                    DspinDhccpParam::MULTI_INVAL_SRCID);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    r_config_to_cc_send_trdid.read(),
+                                    DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    multi_inval_type,
+                                    DspinDhccpParam::FROM_MC_TYPE);
+        p_dspin_out.write = true;
+        p_dspin_out.data  = flit;
+        break;
+    }
+    ////////////////////////////////
+    case CC_SEND_CONFIG_INVAL_NLINE:
+    {
+        uint64_t flit = 0;
+        DspinDhccpParam::dspin_set( flit,
+                                    r_config_to_cc_send_nline.read(),
+                                    DspinDhccpParam::MULTI_INVAL_NLINE);
+        p_dspin_out.eop   = true;
+        p_dspin_out.write = true;
+        p_dspin_out.data  = flit;
+        break;
+    }
+    ////////////////////////
     case CC_SEND_CLEANUP_ACK:
       {
@@ -7438,5 +8093,5 @@
           cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_INST;
         }
-        else 
+        else
         {
           cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_DATA;
@@ -7445,11 +8100,6 @@
         uint64_t flit = 0;
         uint64_t dest =
-          r_cleanup_to_cc_send_srcid.read() << 
-          (DspinDhccpParam::SRCID_WIDTH - vci_param::S);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            1ULL,
-            DspinDhccpParam::FROM_MC_EOP);
+          r_cleanup_to_cc_send_srcid.read() <<
+          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
 
         DspinDhccpParam::dspin_set(
@@ -7473,12 +8123,14 @@
             DspinDhccpParam::FROM_MC_TYPE);
 
+        p_dspin_out.eop   = true;
         p_dspin_out.write = true;
         p_dspin_out.data  = flit;
 
         break;
-      }
-
+    }
+
+    ///////////////////////////////////
     case CC_SEND_XRAM_RSP_INVAL_HEADER:
-      {
+    {
         if(not m_xram_rsp_to_cc_send_inst_fifo.rok()) break;
 
@@ -7488,5 +8140,5 @@
           multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST;
         }
-        else 
+        else
         {
           multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA;
@@ -7494,144 +8146,115 @@
 
         uint64_t flit = 0;
-        uint64_t dest =
-          m_xram_rsp_to_cc_send_srcid_fifo.read() << 
-          (DspinDhccpParam::SRCID_WIDTH - vci_param::S);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            dest,
-            DspinDhccpParam::MULTI_INVAL_DEST);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            m_cc_global_id,
-            DspinDhccpParam::MULTI_INVAL_SRCID);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            r_xram_rsp_to_cc_send_trdid.read(),
-            DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            multi_inval_type,
-            DspinDhccpParam::FROM_MC_TYPE);
-
-        p_dspin_out.write = true;
-        p_dspin_out.data  = flit; 
-
-        break;
-      }
-
-    case CC_SEND_XRAM_RSP_INVAL_NLINE:
-      {
-        uint64_t flit = 0;
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            1ULL,
-            DspinDhccpParam::FROM_MC_EOP);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            r_xram_rsp_to_cc_send_nline.read(),
-            DspinDhccpParam::MULTI_INVAL_NLINE);
-        
-
+        uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() <<
+                        (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    dest,
+                                    DspinDhccpParam::MULTI_INVAL_DEST);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    m_cc_global_id,
+                                    DspinDhccpParam::MULTI_INVAL_SRCID);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    r_xram_rsp_to_cc_send_trdid.read(),
+                                    DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    multi_inval_type,
+                                    DspinDhccpParam::FROM_MC_TYPE);
         p_dspin_out.write = true;
         p_dspin_out.data  = flit;
-
         break;
-      }
-
+    }
+
+    //////////////////////////////////
+    case CC_SEND_XRAM_RSP_INVAL_NLINE:
+    {
+        uint64_t flit = 0;
+
+        DspinDhccpParam::dspin_set( flit,
+                                    r_xram_rsp_to_cc_send_nline.read(),
+                                    DspinDhccpParam::MULTI_INVAL_NLINE);
+        p_dspin_out.eop   = true;
+        p_dspin_out.write = true;
+        p_dspin_out.data  = flit;
+        break;
+    }
+
+    /////////////////////////////////////
+    case CC_SEND_CONFIG_BRDCAST_HEADER:
     case CC_SEND_XRAM_RSP_BRDCAST_HEADER:
     case CC_SEND_WRITE_BRDCAST_HEADER:
     case CC_SEND_CAS_BRDCAST_HEADER:
-      {
+    {
         uint64_t flit = 0;
 
-        DspinDhccpParam::dspin_set(
-            flit,
-            m_broadcast_address,
-            DspinDhccpParam::BROADCAST_BOX);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            m_cc_global_id,
-            DspinDhccpParam::BROADCAST_SRCID);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            1ULL,
-            DspinDhccpParam::FROM_MC_BC);
-
+        DspinDhccpParam::dspin_set( flit,
+                                    m_broadcast_boundaries,
+                                    DspinDhccpParam::BROADCAST_BOX);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    m_cc_global_id,
+                                    DspinDhccpParam::BROADCAST_SRCID);
+
+        DspinDhccpParam::dspin_set( flit,
+                                    1ULL,
+                                    DspinDhccpParam::FROM_MC_BC);
         p_dspin_out.write = true;
         p_dspin_out.data  = flit;
-
         break;
-      }
-
+    }
+    ////////////////////////////////////
     case CC_SEND_XRAM_RSP_BRDCAST_NLINE:
-      {
+    {
         uint64_t flit = 0;
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            1ULL,
-            DspinDhccpParam::FROM_MC_EOP);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            r_xram_rsp_to_cc_send_nline.read(),
-            DspinDhccpParam::BROADCAST_NLINE);
-
+        DspinDhccpParam::dspin_set( flit,
+                                    r_xram_rsp_to_cc_send_nline.read(),
+                                    DspinDhccpParam::BROADCAST_NLINE);
         p_dspin_out.write = true;
+        p_dspin_out.eop   = true;
         p_dspin_out.data  = flit;
-
         break;
-      }
-
+    }
+    //////////////////////////////////
+    case CC_SEND_CONFIG_BRDCAST_NLINE:
+    {
+        uint64_t flit = 0;
+        DspinDhccpParam::dspin_set( flit,
+                                    r_config_to_cc_send_nline.read(),
+                                    DspinDhccpParam::BROADCAST_NLINE);
+        p_dspin_out.write = true;
+        p_dspin_out.eop   = true;
+        p_dspin_out.data  = flit;
+        break;
+    }
+    /////////////////////////////////
     case CC_SEND_WRITE_BRDCAST_NLINE:
-      {
+    {
         uint64_t flit = 0;
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            1ULL,
-            DspinDhccpParam::FROM_MC_EOP);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            r_write_to_cc_send_nline.read(),
-            DspinDhccpParam::BROADCAST_NLINE);
-
+        DspinDhccpParam::dspin_set( flit,
+                                    r_write_to_cc_send_nline.read(),
+                                    DspinDhccpParam::BROADCAST_NLINE);
         p_dspin_out.write = true;
+        p_dspin_out.eop   = true;
         p_dspin_out.data  = flit;
-
         break;
-      }
-
+    }
+    ///////////////////////////////
     case CC_SEND_CAS_BRDCAST_NLINE:
-      {
+    {
         uint64_t flit = 0;
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            1ULL,
-            DspinDhccpParam::FROM_MC_EOP);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            r_cas_to_cc_send_nline.read(),
-            DspinDhccpParam::BROADCAST_NLINE);
-
+        DspinDhccpParam::dspin_set( flit,
+                                    r_cas_to_cc_send_nline.read(),
+                                    DspinDhccpParam::BROADCAST_NLINE);
         p_dspin_out.write = true;
+        p_dspin_out.eop   = true;
         p_dspin_out.data  = flit;
-
         break;
-      }
-
+    }
+    ///////////////////////////////
     case CC_SEND_WRITE_UPDT_HEADER:
-      {
+    {
         if(not m_write_to_cc_send_inst_fifo.rok()) break;
 
@@ -7641,5 +8264,5 @@
           multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST;
         }
-        else 
+        else
         {
           multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA;
@@ -7648,6 +8271,6 @@
         uint64_t flit = 0;
         uint64_t dest =
-          m_write_to_cc_send_srcid_fifo.read() << 
-          (DspinDhccpParam::SRCID_WIDTH - vci_param::S);
+          m_write_to_cc_send_srcid_fifo.read() <<
+          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
 
         DspinDhccpParam::dspin_set(
@@ -7675,8 +8298,8 @@
 
         break;
-      }
-
+    }
+    //////////////////////////////
     case CC_SEND_WRITE_UPDT_NLINE:
-      {
+    {
         uint64_t flit = 0;
 
@@ -7695,20 +8318,10 @@
 
         break;
-      }
-
+    }
+    /////////////////////////////
     case CC_SEND_WRITE_UPDT_DATA:
-      {
-        uint8_t multi_updt_eop;
-        if(  r_cc_send_cpt.read() ==
-            (r_write_to_cc_send_count.read()-1))
-        {
-          multi_updt_eop = 1;
-        }
-        else
-        {
-          multi_updt_eop = 0;
-        }
-
-        uint8_t multi_updt_cpt  = 
+    {
+
+        uint8_t multi_updt_cpt  =
           r_cc_send_cpt.read() + r_write_to_cc_send_index.read();
 
@@ -7717,9 +8330,4 @@
 
         uint64_t flit = 0;
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            (uint64_t)multi_updt_eop,
-            DspinDhccpParam::FROM_MC_EOP);
 
         DspinDhccpParam::dspin_set(
@@ -7734,11 +8342,12 @@
 
         p_dspin_out.write = true;
+        p_dspin_out.eop   = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1));
         p_dspin_out.data  = flit;
 
         break;
-      }
-
+    }
+    ////////////////////////////
     case CC_SEND_CAS_UPDT_HEADER:
-      {
+    {
         if (not m_cas_to_cc_send_inst_fifo.rok()) break;
 
@@ -7748,5 +8357,5 @@
           multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST;
         }
-        else 
+        else
         {
           multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA;
@@ -7755,6 +8364,6 @@
         uint64_t flit = 0;
         uint64_t dest =
-          m_cas_to_cc_send_srcid_fifo.read() << 
-          (DspinDhccpParam::SRCID_WIDTH - vci_param::S);
+          m_cas_to_cc_send_srcid_fifo.read() <<
+          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
 
         DspinDhccpParam::dspin_set(
@@ -7782,8 +8391,8 @@
 
         break;
-      }
-
+    }
+    ////////////////////////////
     case CC_SEND_CAS_UPDT_NLINE:
-      {
+    {
         uint64_t flit = 0;
 
@@ -7802,24 +8411,9 @@
 
         break;
-      }
-
+    }
+    ///////////////////////////
     case CC_SEND_CAS_UPDT_DATA:
-      {
-        uint8_t multi_updt_eop;
-        if(not r_cas_to_cc_send_is_long.read())
-        {
-          multi_updt_eop = 1;
-        }
-        else
-        {
-          multi_updt_eop = 0;
-        }
-
+    {
         uint64_t flit = 0;
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            (uint64_t)multi_updt_eop,
-            DspinDhccpParam::FROM_MC_EOP);
 
         DspinDhccpParam::dspin_set(
@@ -7834,17 +8428,13 @@
 
         p_dspin_out.write = true;
+        p_dspin_out.eop   = not r_cas_to_cc_send_is_long.read();
         p_dspin_out.data  = flit;
 
         break;
-      }
-
+    }
+    ////////////////////////////////
     case CC_SEND_CAS_UPDT_DATA_HIGH:
-      {
+    {
         uint64_t flit = 0;
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            1ULL,
-            DspinDhccpParam::FROM_MC_EOP);
 
         DspinDhccpParam::dspin_set(
@@ -7859,12 +8449,13 @@
 
         p_dspin_out.write = true;
+        p_dspin_out.eop   = true;
         p_dspin_out.data  = flit;
 
         break;
-      }
+    }
   }
 
   ///////////////////////////////////////////////////////////////////
-  // Target command signals from the p_dspin_in port (CC_RECEIVE FSM)
+  //  p_dspin_in port (CC_RECEIVE FSM)
   ///////////////////////////////////////////////////////////////////
   p_dspin_in.read = false;
@@ -7876,4 +8467,5 @@
       }
     case CC_RECEIVE_CLEANUP:
+    case CC_RECEIVE_CLEANUP_EOP:
       {
         p_dspin_in.read = m_cc_receive_to_cleanup_fifo.wok();
