Changeset 441 for branches/v5/modules/vci_mem_cache/caba/source/src
- Timestamp:
- Jul 17, 2013, 10:54:07 AM (11 years ago)
- File:
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- 1 edited
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branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r440 r441 136 136 "CONFIG_DIR_REQ", 137 137 "CONFIG_DIR_ACCESS", 138 "CONFIG_DIR_ UPT_LOCK",138 "CONFIG_DIR_IVT_LOCK", 139 139 "CONFIG_BC_SEND", 140 140 "CONFIG_BC_WAIT", … … 180 180 "WRITE_MISS_XRAM_REQ", 181 181 "WRITE_BC_TRT_LOCK", 182 "WRITE_BC_ UPT_LOCK",182 "WRITE_BC_IVT_LOCK", 183 183 "WRITE_BC_DIR_INVAL", 184 184 "WRITE_BC_CC_SEND", … … 235 235 "CAS_UPT_NEXT", 236 236 "CAS_BC_TRT_LOCK", 237 "CAS_BC_ UPT_LOCK",237 "CAS_BC_IVT_LOCK", 238 238 "CAS_BC_DIR_INVAL", 239 239 "CAS_BC_CC_SEND", … … 258 258 "CLEANUP_HEAP_CLEAN", 259 259 "CLEANUP_HEAP_FREE", 260 "CLEANUP_ UPT_LOCK",261 "CLEANUP_ UPT_DECREMENT",262 "CLEANUP_ UPT_CLEAR",260 "CLEANUP_IVT_LOCK", 261 "CLEANUP_IVT_DECREMENT", 262 "CLEANUP_IVT_CLEAR", 263 263 "CLEANUP_WRITE_RSP", 264 264 "CLEANUP_CONFIG_ACK", … … 328 328 const size_t trt_lines, // number of TRT entries 329 329 const size_t upt_lines, // number of UPT entries 330 const size_t ivt_lines, // number of IVT entries 330 331 const size_t debug_start_cycle, 331 332 const bool debug_ok) … … 337 338 p_vci_tgt( "p_vci_tgt" ), 338 339 p_vci_ixr( "p_vci_ixr" ), 339 p_dspin_in( "p_dspin_in" ), 340 p_dspin_out( "p_dspin_out" ), 340 p_dspin_p2m( "p_dspin_p2m" ), 341 p_dspin_m2p( "p_dspin_m2p" ), 342 p_dspin_clack( "p_dspin_clack" ), 341 343 342 344 m_seglist( mtp.getSegmentList(tgtid_d) ), … … 355 357 m_upt_lines(upt_lines), 356 358 m_upt(upt_lines), 359 m_ivt(ivt_lines), 357 360 m_cache_directory(nways, nsets, nwords, vci_param_int::N), 358 361 m_cache_data(nways, nsets, nwords), … … 446 449 r_alloc_trt_fsm("r_alloc_trt_fsm"), 447 450 r_alloc_upt_fsm("r_alloc_upt_fsm"), 451 r_alloc_ivt_fsm("r_alloc_ivt_fsm"), 448 452 r_alloc_heap_fsm("r_alloc_heap_fsm"), 449 453 r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") … … 678 682 r_alloc_trt_fsm = ALLOC_TRT_READ; 679 683 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 684 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 680 685 r_ixr_rsp_fsm = IXR_RSP_IDLE; 681 686 r_xram_rsp_fsm = XRAM_RSP_IDLE; … … 689 694 m_trt.init(); 690 695 m_upt.init(); 696 m_ivt.init(); 691 697 m_llsc_table.init(); 692 698 … … 1509 1515 r_config_dir_next_ptr = entry.ptr; 1510 1516 1511 r_config_fsm = CONFIG_DIR_ UPT_LOCK;1517 r_config_fsm = CONFIG_DIR_IVT_LOCK; 1512 1518 } 1513 1519 else if ( entry.valid and // hit & sync command … … 1538 1544 } 1539 1545 ///////////////////////// 1540 case CONFIG_DIR_ UPT_LOCK: // enter this state in case of INVAL command1541 // Try to get both DIR & UPT locks, and return1542 // to LOOP state if UPT full.1543 // Register inval in UPT, and invalidate the1544 // directory if UPT not full.1545 { 1546 if ( r_alloc_ upt_fsm.read() == ALLOC_UPT_CONFIG )1546 case CONFIG_DIR_IVT_LOCK: // enter this state in case of INVAL command 1547 // Try to get both DIR & IVT locks, and return 1548 // to LOOP state if IVT full. 1549 // Register inval in IVT, and invalidate the 1550 // directory if IVT not full. 1551 { 1552 if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) 1547 1553 { 1548 1554 size_t set = m_y[(addr_t)(r_config_address.read())]; … … 1558 1564 #if DEBUG_MEMC_CONFIG 1559 1565 if(m_debug) 1560 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1566 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1561 1567 << " No copies in L1 : inval DIR entry" << std::endl; 1562 1568 #endif 1563 1569 } 1564 else // try to register inval in UPT1570 else // try to register inval in IVT 1565 1571 { 1566 1572 bool wok = false; … … 1573 1579 size_t nb_copies = r_config_dir_count.read(); 1574 1580 1575 wok = m_ upt.set(false, // it's an inval transaction1581 wok = m_ivt.set(false, // it's an inval transaction 1576 1582 broadcast, 1577 1583 false, // no response required … … 1583 1589 nb_copies, 1584 1590 index); 1585 if ( wok ) // UPT success => inval DIR slot1591 if ( wok ) // IVT success => inval DIR slot 1586 1592 { 1587 1593 m_cache_directory.inval( way, set ); 1588 r_config_ upt_index = index;1594 r_config_ivt_index = index; 1589 1595 if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; 1590 1596 else r_config_fsm = CONFIG_INV_SEND; … … 1592 1598 #if DEBUG_MEMC_CONFIG 1593 1599 if(m_debug) 1594 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1595 << " Inval DIR entry and register inval in UPT"1600 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1601 << " Inval DIR entry and register inval in IVT" 1596 1602 << " : index = " << std::dec << index 1597 1603 << " / broadcast = " << broadcast << std::endl; 1598 1604 #endif 1599 1605 } 1600 else // UPT full => release both DIR and UPT locks1606 else // IVT full => release both DIR and IVT locks 1601 1607 { 1602 1608 r_config_fsm = CONFIG_LOOP; … … 1604 1610 #if DEBUG_MEMC_CONFIG 1605 1611 if(m_debug) 1606 std::cout << " <MEMC " << name() << " CONFIG_DIR_ UPT_LOCK>"1607 << " UPT full : release DIR & UPT locks and retry" << std::endl;1612 std::cout << " <MEMC " << name() << " CONFIG_DIR_IVT_LOCK>" 1613 << " IVT full : release DIR & IVT locks and retry" << std::endl; 1608 1614 #endif 1609 1615 } … … 1620 1626 r_config_to_cc_send_multi_req = false; 1621 1627 r_config_to_cc_send_brdcast_req = true; 1622 r_config_to_cc_send_trdid = r_config_ upt_index.read();1628 r_config_to_cc_send_trdid = r_config_ivt_index.read(); 1623 1629 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 1624 1630 r_cleanup_to_config_ack = false; … … 1660 1666 r_config_to_cc_send_multi_req = true; 1661 1667 r_config_to_cc_send_brdcast_req = false; 1662 r_config_to_cc_send_trdid = r_config_ upt_index.read();1668 r_config_to_cc_send_trdid = r_config_ivt_index.read(); 1663 1669 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 1664 1670 r_multi_ack_to_config_ack = false; … … 2744 2750 2745 2751 wok = m_upt.set(true, // it's an update transaction 2746 false, 2747 true, 2748 false, 2752 false, // it's not a broadcast 2753 true, // response required 2754 false, // no acknowledge required 2749 2755 srcid, 2750 2756 trdid, … … 2900 2906 entry.owner.inst) // put the next srcid in the fifo 2901 2907 { 2902 dec_upt_counter 2908 dec_upt_counter = false; 2903 2909 write_to_cc_send_fifo_put = true; 2904 2910 write_to_cc_send_fifo_inst = entry.owner.inst; … … 2953 2959 { 2954 2960 r_write_to_cc_send_multi_req = true; 2955 if(r_write_to_dec.read() or dec_upt_counter) 2961 if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; 2956 2962 else r_write_fsm = WRITE_IDLE; 2957 2963 } … … 3196 3202 { 3197 3203 r_write_trt_index = wok_index; 3198 r_write_fsm = WRITE_BC_ UPT_LOCK;3204 r_write_fsm = WRITE_BC_IVT_LOCK; 3199 3205 } 3200 3206 else // wait an empty entry in TRT … … 3213 3219 3214 3220 ////////////////////// 3215 case WRITE_BC_ UPT_LOCK: // register BC transaction in UPT3216 { 3217 if(r_alloc_ upt_fsm.read() == ALLOC_UPT_WRITE)3221 case WRITE_BC_IVT_LOCK: // register BC transaction in IVT 3222 { 3223 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) 3218 3224 { 3219 3225 bool wok = false; … … 3225 3231 size_t nb_copies = r_write_count.read(); 3226 3232 3227 wok = m_ upt.set(false, // it's an inval transaction3228 true, 3229 true, 3230 false, 3233 wok = m_ivt.set(false, // it's an inval transaction 3234 true, // it's a broadcast 3235 true, // response required 3236 false, // no acknowledge required 3231 3237 srcid, 3232 3238 trdid, … … 3238 3244 #if DEBUG_MEMC_WRITE 3239 3245 if( m_debug and wok ) 3240 std::cout << " <MEMC " << name() << " WRITE_BC_ UPT_LOCK> Register broadcast inval in UPT"3246 std::cout << " <MEMC " << name() << " WRITE_BC_IVT_LOCK> Register broadcast inval in IVT" 3241 3247 << " / nb_copies = " << r_write_count.read() << std::endl; 3242 3248 #endif … … 3244 3250 3245 3251 if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; 3246 else 3252 else r_write_fsm = WRITE_WAIT; 3247 3253 } 3248 3254 break; … … 3255 3261 // and invalidate the line in directory 3256 3262 if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or 3257 (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or3258 3263 (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or 3264 (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) 3259 3265 { 3260 3266 std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; 3261 std::cout << "bad TRT, DIR, or UPT allocation" << std::endl;3267 std::cout << "bad TRT, DIR, or IVT allocation" << std::endl; 3262 3268 exit(0); 3263 3269 } … … 3787 3793 } 3788 3794 ///////////////////////// 3789 case XRAM_RSP_INVAL_LOCK: // Take the UPT lock to check a possible pending inval3790 { 3791 if(r_alloc_ upt_fsm == ALLOC_UPT_XRAM_RSP)3795 case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval 3796 { 3797 if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) 3792 3798 { 3793 3799 size_t index = 0; 3794 if(m_ upt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval3800 if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval 3795 3801 { 3796 3802 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 3799 3805 if(m_debug) 3800 3806 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3801 << " Get acces to UPT, but line invalidation registered"3807 << " Get acces to IVT, but line invalidation registered" 3802 3808 << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline 3803 3809 << " / index = " << std::dec << index << std::endl; … … 3805 3811 3806 3812 } 3807 else if(m_ upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full3813 else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full 3808 3814 { 3809 3815 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 3812 3818 if(m_debug) 3813 3819 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3814 << " Get acces to UPT, but inval required and UPT full" << std::endl;3820 << " Get acces to IVT, but inval required and IVT full" << std::endl; 3815 3821 #endif 3816 3822 } … … 3822 3828 if(m_debug) 3823 3829 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3824 << " Get acces to UPT" << std::endl;3830 << " Get acces to IVT" << std::endl; 3825 3831 #endif 3826 3832 } … … 3842 3848 /////////////////////// 3843 3849 case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) 3844 // and possibly set an inval request in UPT3850 // and possibly set an inval request in IVT 3845 3851 { 3846 3852 // check if this is an instruction read, this means pktid is either … … 3900 3906 m_cache_directory.write(set, way, entry); 3901 3907 3902 // request an invalidattion request in UPT for victim line3908 // request an invalidattion request in IVT for victim line 3903 3909 if(r_xram_rsp_victim_inval.read()) 3904 3910 { … … 3907 3913 size_t count_copies = r_xram_rsp_victim_count.read(); 3908 3914 3909 bool wok = m_ upt.set(false, // it's an inval transaction3915 bool wok = m_ivt.set(false, // it's an inval transaction 3910 3916 broadcast, // set broadcast bit 3911 3917 false, // no response required … … 3918 3924 index); 3919 3925 3920 r_xram_rsp_ upt_index = index;3926 r_xram_rsp_ivt_index = index; 3921 3927 3922 3928 if(!wok) 3923 3929 { 3924 3930 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT" 3925 << " update_tab entry free but write unsuccessful" << std::endl;3931 << " invalidate_tab entry free but write unsuccessful" << std::endl; 3926 3932 exit(0); 3927 3933 } … … 4032 4038 r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); 4033 4039 r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); 4034 r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ upt_index;4040 r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; 4035 4041 xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); 4036 4042 xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); … … 4377 4383 else // miss : check UPT for a pending invalidation transaction 4378 4384 { 4379 r_cleanup_fsm = CLEANUP_ UPT_LOCK;4385 r_cleanup_fsm = CLEANUP_IVT_LOCK; 4380 4386 } 4381 4387 … … 4835 4841 } 4836 4842 ////////////////////// 4837 case CLEANUP_ UPT_LOCK: // get the lock protecting the UPT to search a pending4843 case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending 4838 4844 // invalidate transaction matching the cleanup 4839 4845 { 4840 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP) break;4846 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; 4841 4847 4842 4848 size_t index = 0; 4843 4849 bool match_inval; 4844 4850 4845 match_inval = m_ upt.search_inval(r_cleanup_nline.read(), index);4851 match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); 4846 4852 4847 4853 if ( not match_inval ) // no pending inval … … 4852 4858 if(m_debug) 4853 4859 std::cout << " <MEMC " << name() 4854 << " CLEANUP_ UPT_LOCK> Unexpected cleanup"4855 << " with no corresponding UPT entry:"4860 << " CLEANUP_IVT_LOCK> Unexpected cleanup" 4861 << " with no corresponding IVT entry:" 4856 4862 << " address = " << std::hex 4857 4863 << (r_cleanup_nline.read() *4*m_words) … … 4862 4868 4863 4869 // pending inval 4864 r_cleanup_write_srcid = m_ upt.srcid(index);4865 r_cleanup_write_trdid = m_ upt.trdid(index);4866 r_cleanup_write_pktid = m_ upt.pktid(index);4867 r_cleanup_need_rsp = m_ upt.need_rsp(index);4868 r_cleanup_need_ack = m_ upt.need_ack(index);4870 r_cleanup_write_srcid = m_ivt.srcid(index); 4871 r_cleanup_write_trdid = m_ivt.trdid(index); 4872 r_cleanup_write_pktid = m_ivt.pktid(index); 4873 r_cleanup_need_rsp = m_ivt.need_rsp(index); 4874 r_cleanup_need_ack = m_ivt.need_ack(index); 4869 4875 r_cleanup_index = index; 4870 4876 4871 r_cleanup_fsm = CLEANUP_ UPT_DECREMENT;4877 r_cleanup_fsm = CLEANUP_IVT_DECREMENT; 4872 4878 4873 4879 #if DEBUG_MEMC_CLEANUP 4874 4880 if(m_debug) 4875 4881 std::cout << " <MEMC " << name() 4876 << " CLEANUP_ UPT_LOCK> Cleanup matching pending"4877 << " invalidate transaction on UPT:"4882 << " CLEANUP_IVT_LOCK> Cleanup matching pending" 4883 << " invalidate transaction on IVT:" 4878 4884 << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 4879 << " / upt_entry = " << index << std::endl;4885 << " / ivt_entry = " << index << std::endl; 4880 4886 #endif 4881 4887 break; 4882 4888 } 4883 4889 /////////////////////////// 4884 case CLEANUP_ UPT_DECREMENT: // decrement response counter in UPT matching entry4885 { 4886 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP)4890 case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry 4891 { 4892 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) 4887 4893 { 4888 4894 std::cout 4889 4895 << "VCI_MEM_CACHE ERROR " << name() 4890 << " CLEANUP_ UPT_DECREMENT state" << std::endl4891 << "Bad UPT allocation"4896 << " CLEANUP_IVT_DECREMENT state" << std::endl 4897 << "Bad IVT allocation" 4892 4898 << std::endl; 4893 4899 … … 4896 4902 4897 4903 size_t count = 0; 4898 m_ upt.decrement(r_cleanup_index.read(), count);4904 m_ivt.decrement(r_cleanup_index.read(), count); 4899 4905 4900 4906 if(count == 0) // multi inval transaction completed 4901 4907 { 4902 r_cleanup_fsm = CLEANUP_ UPT_CLEAR;4908 r_cleanup_fsm = CLEANUP_IVT_CLEAR; 4903 4909 } 4904 4910 else // multi inval transaction not completed … … 4909 4915 #if DEBUG_MEMC_CLEANUP 4910 4916 if(m_debug) 4911 std::cout << " <MEMC " << name() << " CLEANUP_ UPT_DECREMENT>"4912 << " Decrement response counter in UPT:"4913 << " UPT_index = " << r_cleanup_index.read()4917 std::cout << " <MEMC " << name() << " CLEANUP_IVT_DECREMENT>" 4918 << " Decrement response counter in IVT:" 4919 << " IVT_index = " << r_cleanup_index.read() 4914 4920 << " / rsp_count = " << count << std::endl; 4915 4921 #endif … … 4917 4923 } 4918 4924 /////////////////////// 4919 case CLEANUP_ UPT_CLEAR: // Clear UPT entry4920 { 4921 if(r_alloc_ upt_fsm.read() != ALLOC_UPT_CLEANUP)4925 case CLEANUP_IVT_CLEAR: // Clear IVT entry 4926 { 4927 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) 4922 4928 { 4923 4929 std::cout 4924 4930 << "VCI_MEM_CACHE ERROR " << name() 4925 << " CLEANUP_ UPT_CLEAR state" << std::endl4926 << "Bad UPT allocation"4931 << " CLEANUP_IVT_CLEAR state" << std::endl 4932 << "Bad IVT allocation" 4927 4933 << std::endl; 4928 4934 … … 4930 4936 } 4931 4937 4932 m_ upt.clear(r_cleanup_index.read());4938 m_ivt.clear(r_cleanup_index.read()); 4933 4939 4934 4940 if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; … … 4939 4945 if(m_debug) 4940 4946 std::cout << " <MEMC " << name() 4941 << " CLEANUP_ UPT_CLEAR> Clear entry in UPT:"4942 << " UPT_index = " << r_cleanup_index.read() << std::endl;4947 << " CLEANUP_IVT_CLEAR> Clear entry in IVT:" 4948 << " IVT_index = " << r_cleanup_index.read() << std::endl; 4943 4949 #endif 4944 4950 break; … … 4985 4991 } 4986 4992 //////////////////////// 4987 case CLEANUP_SEND_CLACK: 4993 case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command 4988 4994 // on the coherence network (request to the CC_SEND FSM). 4989 4995 // wait if pending request to the CC_SEND FSM … … 5238 5244 !r_cas_to_cc_send_brdcast_req.read()) 5239 5245 { 5240 r_cas_fsm = CAS_UPT_LOCK; // multi update required5246 r_cas_fsm = CAS_UPT_LOCK; // multi update required 5241 5247 } 5242 5248 else … … 5509 5515 { 5510 5516 r_cas_trt_index = wok_index; 5511 r_cas_fsm = CAS_BC_ UPT_LOCK;5517 r_cas_fsm = CAS_BC_IVT_LOCK; 5512 5518 } 5513 5519 else … … 5524 5530 } 5525 5531 ///////////////////// 5526 case CAS_BC_ UPT_LOCK: // register a broadcast inval transaction in UPT5532 case CAS_BC_IVT_LOCK: // register a broadcast inval transaction in IVT 5527 5533 // write data in cache in case of successful registration 5528 5534 { 5529 if(r_alloc_ upt_fsm.read() == ALLOC_UPT_CAS)5535 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) 5530 5536 { 5531 5537 bool wok = false; … … 5537 5543 size_t nb_copies = r_cas_count.read(); 5538 5544 5539 // register a broadcast inval transaction in UPT5540 wok = m_ upt.set(false, // it's an inval transaction5541 true, 5542 true, 5543 false, 5545 // register a broadcast inval transaction in IVT 5546 wok = m_ivt.set(false, // it's an inval transaction 5547 true, // it's a broadcast 5548 true, // response required 5549 false, // no acknowledge required 5544 5550 srcid, 5545 5551 trdid, … … 5549 5555 index); 5550 5556 5551 if(wok) // UPT not full5557 if(wok) // IVT not full 5552 5558 { 5553 5559 // cache update … … 5577 5583 if(m_debug) 5578 5584 std::cout << " <MEMC " << name() 5579 << " CAS_BC_ UPT_LOCK> Register a broadcast inval transaction in UPT"5585 << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT" 5580 5586 << " / nline = " << std::hex << nline 5581 5587 << " / count = " << std::dec << nb_copies 5582 << " / upt_index = " << index << std::endl;5583 #endif 5584 } 5585 else // releases the lock protecting UPT5588 << " / ivt_index = " << index << std::endl; 5589 #endif 5590 } 5591 else // releases the lock protecting IVT 5586 5592 { 5587 5593 r_cas_fsm = CAS_WAIT; … … 5594 5600 { 5595 5601 if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and 5596 (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and5597 5602 (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and 5603 (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) 5598 5604 { 5599 5605 // set TRT … … 6199 6205 if(m_config_to_cc_send_inst_fifo.rok()) 6200 6206 { 6201 if(not p_dspin_ out.read) break;6207 if(not p_dspin_m2p.read) break; 6202 6208 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; 6203 6209 break; … … 6210 6216 case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) 6211 6217 { 6212 if(not p_dspin_ out.read) break;6218 if(not p_dspin_m2p.read) break; 6213 6219 m_cpt_inval_mult++; 6214 6220 config_to_cc_send_fifo_get = true; … … 6226 6232 case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) 6227 6233 { 6228 if(not p_dspin_ out.read) break;6234 if(not p_dspin_m2p.read) break; 6229 6235 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; 6230 6236 break; … … 6233 6239 case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) 6234 6240 { 6235 if(not p_dspin_ out.read) break;6241 if(not p_dspin_m2p.read) break; 6236 6242 m_cpt_inval_brdcast++; 6237 6243 r_config_to_cc_send_brdcast_req = false; … … 6249 6255 case CC_SEND_CLEANUP_ACK: // send one flit for a cleanup acknowledgement 6250 6256 { 6251 if(not p_dspin_ out.read) break;6257 if(not p_dspin_m2p.read) break; 6252 6258 6253 6259 r_cleanup_to_cc_send_req = false; … … 6267 6273 if(m_xram_rsp_to_cc_send_inst_fifo.rok()) 6268 6274 { 6269 if(not p_dspin_ out.read) break;6275 if(not p_dspin_m2p.read) break; 6270 6276 r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; 6271 6277 break; … … 6278 6284 case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) 6279 6285 { 6280 if(not p_dspin_ out.read) break;6286 if(not p_dspin_m2p.read) break; 6281 6287 m_cpt_inval_mult++; 6282 6288 xram_rsp_to_cc_send_fifo_get = true; … … 6294 6300 case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) 6295 6301 { 6296 if(not p_dspin_ out.read) break;6302 if(not p_dspin_m2p.read) break; 6297 6303 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; 6298 6304 break; … … 6301 6307 case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) 6302 6308 { 6303 if(not p_dspin_ out.read) break;6309 if(not p_dspin_m2p.read) break; 6304 6310 m_cpt_inval_brdcast++; 6305 6311 r_xram_rsp_to_cc_send_brdcast_req = false; … … 6317 6323 case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) 6318 6324 { 6319 if(not p_dspin_ out.read) break;6325 if(not p_dspin_m2p.read) break; 6320 6326 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; 6321 6327 break; … … 6324 6330 case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) 6325 6331 { 6326 if(not p_dspin_ out.read) break;6332 if(not p_dspin_m2p.read) break; 6327 6333 6328 6334 m_cpt_inval_brdcast++; … … 6344 6350 if(m_write_to_cc_send_inst_fifo.rok()) 6345 6351 { 6346 if(not p_dspin_ out.read) break;6352 if(not p_dspin_m2p.read) break; 6347 6353 6348 6354 r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; … … 6361 6367 case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) 6362 6368 { 6363 if(not p_dspin_ out.read) break;6369 if(not p_dspin_m2p.read) break; 6364 6370 m_cpt_update_mult++; 6365 6371 … … 6378 6384 case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) 6379 6385 { 6380 if(not p_dspin_ out.read) break;6386 if(not p_dspin_m2p.read) break; 6381 6387 if(r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)) 6382 6388 { … … 6392 6398 case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) 6393 6399 { 6394 if(not p_dspin_ out.read) break;6400 if(not p_dspin_m2p.read) break; 6395 6401 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; 6396 6402 break; … … 6399 6405 case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) 6400 6406 { 6401 if(not p_dspin_ out.read) break;6407 if(not p_dspin_m2p.read) break; 6402 6408 m_cpt_inval_brdcast++; 6403 6409 … … 6418 6424 if(m_cas_to_cc_send_inst_fifo.rok()) 6419 6425 { 6420 if(not p_dspin_ out.read) break;6426 if(not p_dspin_m2p.read) break; 6421 6427 6422 6428 r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; … … 6436 6442 case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) 6437 6443 { 6438 if(not p_dspin_ out.read) break;6444 if(not p_dspin_m2p.read) break; 6439 6445 6440 6446 m_cpt_update_mult++; … … 6454 6460 case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) 6455 6461 { 6456 if(not p_dspin_ out.read) break;6462 if(not p_dspin_m2p.read) break; 6457 6463 6458 6464 if(r_cas_to_cc_send_is_long.read()) … … 6469 6475 case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) 6470 6476 { 6471 if(not p_dspin_ out.read) break;6477 if(not p_dspin_m2p.read) break; 6472 6478 cas_to_cc_send_fifo_get = true; 6473 6479 r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; … … 6489 6495 case CC_RECEIVE_IDLE: 6490 6496 { 6491 if(not p_dspin_ in.write) break;6497 if(not p_dspin_p2m.write) break; 6492 6498 6493 6499 uint8_t type = 6494 6500 DspinDhccpParam::dspin_get( 6495 p_dspin_ in.data.read(),6501 p_dspin_p2m.data.read(), 6496 6502 DspinDhccpParam::FROM_L1_TYPE); 6497 6503 … … 6520 6526 // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo 6521 6527 6522 if(not p_dspin_ in.write or not m_cc_receive_to_cleanup_fifo.wok())6528 if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) 6523 6529 break; 6524 6530 6525 assert(not p_dspin_ in.eop.read() and6531 assert(not p_dspin_p2m.eop.read() and 6526 6532 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 6527 6533 "CLEANUP command must have two flits"); … … 6537 6543 // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo 6538 6544 6539 if(not p_dspin_ in.write or not m_cc_receive_to_cleanup_fifo.wok())6545 if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) 6540 6546 break; 6541 6547 6542 assert(p_dspin_ in.eop.read() and6548 assert(p_dspin_p2m.eop.read() and 6543 6549 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 6544 6550 "CLEANUP command must have two flits"); … … 6556 6562 6557 6563 // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo 6558 if(not p_dspin_ in.write or not m_cc_receive_to_multi_ack_fifo.wok())6564 if(not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) 6559 6565 break; 6560 6566 6561 assert(p_dspin_ in.eop.read() and6567 assert(p_dspin_p2m.eop.read() and 6562 6568 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 6563 6569 "MULTI_ACK command must have one flit"); … … 6969 6975 // ALLOC_UPT FSM 6970 6976 //////////////////////////////////////////////////////////////////////////////////// 6971 // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT), 6972 // with a round robin priority between six FSMs, with the following order: 6973 // CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS 6974 // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT. 6977 // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), 6978 // with a round robin priority between three FSMs, with the following order: 6979 // WRITE -> CAS -> MULTI_ACK 6980 // - The WRITE FSM initiates update transaction and sets a new entry in UPT. 6981 // - The CAS FSM does the same thing as the WRITE FSM. 6975 6982 // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. 6976 // - The WRITE FSM initiates update transaction and sets a new entry in UPT.6977 // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT.6978 // - The CLEANUP FSM decrement an entry in UPT.6979 // - The CAS FSM does the same thing as the WRITE FSM.6980 6983 // The resource is always allocated. 6981 6984 ///////////////////////////////////////////////////////////////////////////////////// 6982 6983 6985 switch(r_alloc_upt_fsm.read()) 6984 6986 { 6985 //////////////////////6986 case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM6987 if (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK)6988 {6989 if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)6990 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;6991 6992 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or6993 (r_write_fsm.read() == WRITE_BC_UPT_LOCK))6994 r_alloc_upt_fsm = ALLOC_UPT_WRITE;6995 6996 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)6997 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;6998 6999 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)7000 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;7001 7002 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or7003 (r_cas_fsm.read() == CAS_BC_UPT_LOCK))7004 r_alloc_upt_fsm = ALLOC_UPT_CAS;7005 }7006 break;7007 7008 6987 ///////////////////////// 7009 case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM 7010 if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and 7011 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 7012 { 7013 if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7014 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7015 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7016 7017 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7018 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7019 7020 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7021 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7022 7023 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7024 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7025 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7026 7027 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7028 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7029 } 7030 break; 7031 7032 ///////////////////// 7033 case ALLOC_UPT_WRITE: // allocated to WRITE FSM 7034 if((r_write_fsm.read() != WRITE_UPT_LOCK) and 7035 (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) 7036 { 7037 if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7038 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7039 7040 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7041 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7042 7043 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7044 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7045 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7046 7047 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7048 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7049 7050 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7051 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7052 } 7053 break; 7054 7055 //////////////////////// 7056 case ALLOC_UPT_XRAM_RSP: 7057 if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 7058 { 7059 if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7060 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7061 7062 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7063 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7064 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7065 7066 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7067 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7068 7069 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7070 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7071 7072 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7073 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7074 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7075 } 7076 break; 7077 6988 case ALLOC_UPT_WRITE: // allocated to WRITE FSM 6989 if (r_write_fsm.read() != WRITE_UPT_LOCK) 6990 { 6991 if (r_cas_fsm.read() == CAS_UPT_LOCK) 6992 r_alloc_upt_fsm = ALLOC_UPT_CAS; 6993 6994 else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6995 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 6996 } 6997 break; 6998 6999 ///////////////////////// 7000 case ALLOC_UPT_CAS: // allocated to CAS FSM 7001 if (r_cas_fsm.read() != CAS_UPT_LOCK) 7002 { 7003 if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7004 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7005 7006 else if (r_write_fsm.read() == WRITE_UPT_LOCK) 7007 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7008 } 7009 break; 7010 7011 ///////////////////////// 7012 case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM 7013 if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and 7014 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 7015 { 7016 if (r_write_fsm.read() == WRITE_UPT_LOCK) 7017 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7018 7019 else if (r_cas_fsm.read() == CAS_UPT_LOCK) 7020 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7021 } 7022 break; 7023 } // end switch r_alloc_upt_fsm 7024 7025 //////////////////////////////////////////////////////////////////////////////////// 7026 // ALLOC_IVT FSM 7027 //////////////////////////////////////////////////////////////////////////////////// 7028 // The ALLOC_IVT FSM allocates the access to the Invalidate Table (IVT), 7029 // with a round robin priority between five FSMs, with the following order: 7030 // WRITE -> XRAM_RSP -> CLEANUP -> CAS -> CONFIG 7031 // - The WRITE FSM initiates broadcast invalidate transactions and sets a new entry 7032 // in IVT. 7033 // - The CAS FSM does the same thing as the WRITE FSM. 7034 // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets 7035 // a new entry in the IVT 7036 // - The CONFIG FSM does the same thing as the XRAM_RSP FSM 7037 // - The CLEANUP FSM complete those trasactions and erase the IVT entry. 7038 // The resource is always allocated. 7039 ///////////////////////////////////////////////////////////////////////////////////// 7040 switch(r_alloc_ivt_fsm.read()) 7041 { 7078 7042 ////////////////////////// 7079 case ALLOC_UPT_CLEANUP: 7080 if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) and 7081 (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT)) 7082 { 7083 if((r_cas_fsm.read() == CAS_UPT_LOCK) or 7084 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7085 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7086 7087 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7088 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7089 7090 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7091 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7092 7093 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7094 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7095 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7096 7097 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7098 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7099 } 7100 break; 7043 case ALLOC_IVT_WRITE: // allocated to WRITE FSM 7044 if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) 7045 { 7046 if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7047 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7048 7049 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7050 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7051 7052 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7053 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7054 7055 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7056 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7057 } 7058 break; 7101 7059 7102 7060 ////////////////////////// 7103 case ALLOC_UPT_CAS: 7104 if((r_cas_fsm.read() != CAS_UPT_LOCK) and 7105 (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) 7106 { 7107 if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7108 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7109 7110 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7111 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7112 7113 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 7114 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7115 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7116 7117 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7118 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7119 7120 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7121 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7122 } 7123 break; 7124 7125 } // end switch r_alloc_upt_fsm 7061 case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM 7062 if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 7063 { 7064 if(r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7065 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7066 7067 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7068 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7069 7070 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7071 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7072 7073 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7074 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7075 } 7076 break; 7077 7078 ////////////////////////// 7079 case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM 7080 if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and 7081 (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) 7082 { 7083 if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7084 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7085 7086 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7087 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7088 7089 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7090 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7091 7092 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7093 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7094 } 7095 break; 7096 7097 ////////////////////////// 7098 case ALLOC_IVT_CAS: // allocated to CAS FSM 7099 if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) 7100 { 7101 if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7102 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7103 7104 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7105 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7106 7107 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7108 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7109 7110 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7111 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7112 } 7113 break; 7114 7115 ////////////////////////// 7116 case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM 7117 if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) 7118 { 7119 if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7120 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7121 7122 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7123 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7124 7125 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7126 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7127 7128 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7129 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7130 } 7131 break; 7132 7133 } // end switch r_alloc_ivt_fsm 7126 7134 7127 7135 //////////////////////////////////////////////////////////////////////////////////// … … 7153 7161 if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and 7154 7162 (r_config_fsm.read() != CONFIG_DIR_ACCESS) and 7155 (r_config_fsm.read() != CONFIG_DIR_ UPT_LOCK) )7163 (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) ) 7156 7164 { 7157 7165 if(r_read_fsm.read() == READ_DIR_REQ) … … 7206 7214 (r_write_fsm.read() != WRITE_DIR_HIT) and 7207 7215 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 7208 (r_write_fsm.read() != WRITE_BC_ UPT_LOCK) and7216 (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and 7209 7217 (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 7210 7218 (r_write_fsm.read() != WRITE_UPT_LOCK) and … … 7242 7250 (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and 7243 7251 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 7244 (r_cas_fsm.read() != CAS_BC_ UPT_LOCK) and7252 (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and 7245 7253 (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 7246 7254 (r_cas_fsm.read() != CAS_UPT_LOCK) and … … 7356 7364 if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 7357 7365 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 7358 (r_write_fsm.read() != WRITE_BC_ UPT_LOCK))7366 (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) 7359 7367 { 7360 7368 if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or … … 7379 7387 if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 7380 7388 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 7381 (r_cas_fsm.read() != CAS_BC_ UPT_LOCK))7389 (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) 7382 7390 { 7383 7391 if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and … … 7669 7677 m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, 7670 7678 cc_receive_to_cleanup_fifo_put, 7671 p_dspin_ in.data.read() );7679 p_dspin_p2m.data.read() ); 7672 7680 7673 7681 //////////////////////////////////////////////////////////////////////////////////// … … 7677 7685 m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, 7678 7686 cc_receive_to_multi_ack_fifo_put, 7679 p_dspin_ in.data.read() );7687 p_dspin_p2m.data.read() ); 7680 7688 7681 7689 //////////////////////////////////////////////////////////////////////////////////// … … 8019 8027 8020 8028 //////////////////////////////////////////////////////////////////// 8021 // p_dspin_ outport (CC_SEND FSM)8029 // p_dspin_m2p port (CC_SEND FSM) 8022 8030 //////////////////////////////////////////////////////////////////// 8023 8031 8024 p_dspin_ out.write = false;8025 p_dspin_ out.eop = false;8026 p_dspin_ out.data = 0;8032 p_dspin_m2p.write = false; 8033 p_dspin_m2p.eop = false; 8034 p_dspin_m2p.data = 0; 8027 8035 8028 8036 switch(r_cc_send_fsm.read()) … … 8069 8077 multi_inval_type, 8070 8078 DspinDhccpParam::FROM_MC_TYPE); 8071 p_dspin_ out.write = true;8072 p_dspin_ out.data = flit;8079 p_dspin_m2p.write = true; 8080 p_dspin_m2p.data = flit; 8073 8081 break; 8074 8082 } … … 8080 8088 r_config_to_cc_send_nline.read(), 8081 8089 DspinDhccpParam::MULTI_INVAL_NLINE); 8082 p_dspin_ out.eop = true;8083 p_dspin_ out.write = true;8084 p_dspin_ out.data = flit;8090 p_dspin_m2p.eop = true; 8091 p_dspin_m2p.write = true; 8092 p_dspin_m2p.data = flit; 8085 8093 break; 8086 8094 } … … 8123 8131 DspinDhccpParam::FROM_MC_TYPE); 8124 8132 8125 p_dspin_ out.eop = true;8126 p_dspin_ out.write = true;8127 p_dspin_ out.data = flit;8133 p_dspin_m2p.eop = true; 8134 p_dspin_m2p.write = true; 8135 p_dspin_m2p.data = flit; 8128 8136 8129 8137 break; … … 8164 8172 multi_inval_type, 8165 8173 DspinDhccpParam::FROM_MC_TYPE); 8166 p_dspin_ out.write = true;8167 p_dspin_ out.data = flit;8174 p_dspin_m2p.write = true; 8175 p_dspin_m2p.data = flit; 8168 8176 break; 8169 8177 } … … 8177 8185 r_xram_rsp_to_cc_send_nline.read(), 8178 8186 DspinDhccpParam::MULTI_INVAL_NLINE); 8179 p_dspin_ out.eop = true;8180 p_dspin_ out.write = true;8181 p_dspin_ out.data = flit;8187 p_dspin_m2p.eop = true; 8188 p_dspin_m2p.write = true; 8189 p_dspin_m2p.data = flit; 8182 8190 break; 8183 8191 } … … 8202 8210 1ULL, 8203 8211 DspinDhccpParam::FROM_MC_BC); 8204 p_dspin_ out.write = true;8205 p_dspin_ out.data = flit;8212 p_dspin_m2p.write = true; 8213 p_dspin_m2p.data = flit; 8206 8214 break; 8207 8215 } … … 8213 8221 r_xram_rsp_to_cc_send_nline.read(), 8214 8222 DspinDhccpParam::BROADCAST_NLINE); 8215 p_dspin_ out.write = true;8216 p_dspin_ out.eop = true;8217 p_dspin_ out.data = flit;8223 p_dspin_m2p.write = true; 8224 p_dspin_m2p.eop = true; 8225 p_dspin_m2p.data = flit; 8218 8226 break; 8219 8227 } … … 8225 8233 r_config_to_cc_send_nline.read(), 8226 8234 DspinDhccpParam::BROADCAST_NLINE); 8227 p_dspin_ out.write = true;8228 p_dspin_ out.eop = true;8229 p_dspin_ out.data = flit;8235 p_dspin_m2p.write = true; 8236 p_dspin_m2p.eop = true; 8237 p_dspin_m2p.data = flit; 8230 8238 break; 8231 8239 } … … 8237 8245 r_write_to_cc_send_nline.read(), 8238 8246 DspinDhccpParam::BROADCAST_NLINE); 8239 p_dspin_ out.write = true;8240 p_dspin_ out.eop = true;8241 p_dspin_ out.data = flit;8247 p_dspin_m2p.write = true; 8248 p_dspin_m2p.eop = true; 8249 p_dspin_m2p.data = flit; 8242 8250 break; 8243 8251 } … … 8249 8257 r_cas_to_cc_send_nline.read(), 8250 8258 DspinDhccpParam::BROADCAST_NLINE); 8251 p_dspin_ out.write = true;8252 p_dspin_ out.eop = true;8253 p_dspin_ out.data = flit;8259 p_dspin_m2p.write = true; 8260 p_dspin_m2p.eop = true; 8261 p_dspin_m2p.data = flit; 8254 8262 break; 8255 8263 } … … 8294 8302 DspinDhccpParam::FROM_MC_TYPE); 8295 8303 8296 p_dspin_ out.write = true;8297 p_dspin_ out.data = flit;8304 p_dspin_m2p.write = true; 8305 p_dspin_m2p.data = flit; 8298 8306 8299 8307 break; … … 8314 8322 DspinDhccpParam::MULTI_UPDT_NLINE); 8315 8323 8316 p_dspin_ out.write = true;8317 p_dspin_ out.data = flit;8324 p_dspin_m2p.write = true; 8325 p_dspin_m2p.data = flit; 8318 8326 8319 8327 break; … … 8341 8349 DspinDhccpParam::MULTI_UPDT_DATA); 8342 8350 8343 p_dspin_ out.write = true;8344 p_dspin_ out.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1));8345 p_dspin_ out.data = flit;8351 p_dspin_m2p.write = true; 8352 p_dspin_m2p.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)); 8353 p_dspin_m2p.data = flit; 8346 8354 8347 8355 break; … … 8387 8395 DspinDhccpParam::FROM_MC_TYPE); 8388 8396 8389 p_dspin_ out.write = true;8390 p_dspin_ out.data = flit;8397 p_dspin_m2p.write = true; 8398 p_dspin_m2p.data = flit; 8391 8399 8392 8400 break; … … 8407 8415 DspinDhccpParam::MULTI_UPDT_NLINE); 8408 8416 8409 p_dspin_ out.write = true;8410 p_dspin_ out.data = flit;8417 p_dspin_m2p.write = true; 8418 p_dspin_m2p.data = flit; 8411 8419 8412 8420 break; … … 8427 8435 DspinDhccpParam::MULTI_UPDT_DATA); 8428 8436 8429 p_dspin_ out.write = true;8430 p_dspin_ out.eop = not r_cas_to_cc_send_is_long.read();8431 p_dspin_ out.data = flit;8437 p_dspin_m2p.write = true; 8438 p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); 8439 p_dspin_m2p.data = flit; 8432 8440 8433 8441 break; … … 8448 8456 DspinDhccpParam::MULTI_UPDT_DATA); 8449 8457 8450 p_dspin_ out.write = true;8451 p_dspin_ out.eop = true;8452 p_dspin_ out.data = flit;8458 p_dspin_m2p.write = true; 8459 p_dspin_m2p.eop = true; 8460 p_dspin_m2p.data = flit; 8453 8461 8454 8462 break; … … 8457 8465 8458 8466 /////////////////////////////////////////////////////////////////// 8459 // p_dspin_ inport (CC_RECEIVE FSM)8467 // p_dspin_p2m port (CC_RECEIVE FSM) 8460 8468 /////////////////////////////////////////////////////////////////// 8461 p_dspin_ in.read = false;8469 p_dspin_p2m.read = false; 8462 8470 switch(r_cc_receive_fsm.read()) 8463 8471 { … … 8469 8477 case CC_RECEIVE_CLEANUP_EOP: 8470 8478 { 8471 p_dspin_ in.read = m_cc_receive_to_cleanup_fifo.wok();8479 p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); 8472 8480 break; 8473 8481 } 8474 8482 case CC_RECEIVE_MULTI_ACK: 8475 8483 { 8476 p_dspin_ in.read = m_cc_receive_to_multi_ack_fifo.wok();8484 p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); 8477 8485 break; 8478 8486 }
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