Index: branches/v5/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- branches/v5/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 440) +++ branches/v5/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 441) @@ -5,5 +5,5 @@ __version__ = "$Revision: 295 $" -Module('caba:vci_mem_cache', +Module('caba:vci_mem_cache_branch', classname = 'soclib::caba::VciMemCache', @@ -48,10 +48,14 @@ Port('caba:vci_target' , 'p_vci_tgt'), Port('caba:vci_initiator', 'p_vci_ixr'), - Port('caba:dspin_input', - 'p_dspin_in', + Port('caba:dspin_p2m', + 'p_dspin_p2m', dspin_data_size = parameter.Reference('dspin_in_width') ), - Port('caba:dspin_output', - 'p_dspin_out', + Port('caba:dspin_m2p', + 'p_dspin_m2p', + dspin_data_size = parameter.Reference('dspin_out_width') + ), + Port('caba:dspin_clack', + 'p_dspin_clack', dspin_data_size = parameter.Reference('dspin_out_width') ), Index: branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 440) +++ branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 441) @@ -54,4 +54,5 @@ #define TRT_ENTRIES 4 // Number of entries in TRT #define UPT_ENTRIES 4 // Number of entries in UPT +#define IVT_ENTRIES 4 // Number of entries in IVT #define HEAP_ENTRIES 1024 // Number of entries in HEAP @@ -165,5 +166,5 @@ CONFIG_DIR_REQ, CONFIG_DIR_ACCESS, - CONFIG_DIR_UPT_LOCK, + CONFIG_DIR_IVT_LOCK, CONFIG_BC_SEND, CONFIG_BC_WAIT, @@ -213,5 +214,5 @@ WRITE_MISS_XRAM_REQ, WRITE_BC_TRT_LOCK, - WRITE_BC_UPT_LOCK, + WRITE_BC_IVT_LOCK, WRITE_BC_DIR_INVAL, WRITE_BC_CC_SEND, @@ -276,5 +277,5 @@ CAS_UPT_NEXT, CAS_BC_TRT_LOCK, - CAS_BC_UPT_LOCK, + CAS_BC_IVT_LOCK, CAS_BC_DIR_INVAL, CAS_BC_CC_SEND, @@ -301,7 +302,7 @@ CLEANUP_HEAP_CLEAN, CLEANUP_HEAP_FREE, - CLEANUP_UPT_LOCK, - CLEANUP_UPT_DECREMENT, - CLEANUP_UPT_CLEAR, + CLEANUP_IVT_LOCK, + CLEANUP_IVT_DECREMENT, + CLEANUP_IVT_CLEAR, CLEANUP_WRITE_RSP, CLEANUP_CONFIG_ACK, @@ -334,10 +335,17 @@ enum alloc_upt_fsm_state_e { - ALLOC_UPT_CONFIG, ALLOC_UPT_WRITE, - ALLOC_UPT_XRAM_RSP, - ALLOC_UPT_MULTI_ACK, - ALLOC_UPT_CLEANUP, - ALLOC_UPT_CAS + ALLOC_UPT_CAS, + ALLOC_UPT_MULTI_ACK + }; + + /* States of the ALLOC_IVT fsm */ + enum alloc_ivt_fsm_state_e + { + ALLOC_IVT_WRITE, + ALLOC_IVT_XRAM_RSP, + ALLOC_IVT_CLEANUP, + ALLOC_IVT_CAS, + ALLOC_IVT_CONFIG }; @@ -450,6 +458,7 @@ soclib::caba::VciTarget p_vci_tgt; soclib::caba::VciInitiator p_vci_ixr; - soclib::caba::DspinInput p_dspin_in; - soclib::caba::DspinOutput p_dspin_out; + soclib::caba::DspinInput p_dspin_p2m; + soclib::caba::DspinOutput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_clack; VciMemCache( @@ -467,4 +476,5 @@ const size_t trt_lines=TRT_ENTRIES, const size_t upt_lines=UPT_ENTRIES, + const size_t ivt_lines=IVT_ENTRIES, const size_t debug_start_cycle=0, const bool debug_ok=false ); @@ -501,5 +511,6 @@ TransactionTab m_trt; // xram transaction table uint32_t m_upt_lines; - UpdateTab m_upt; // pending update & invalidate + UpdateTab m_upt; // pending update + UpdateTab m_ivt; // pending invalidate CacheDirectory m_cache_directory; // data cache directory CacheData m_cache_data; // data array[set][way][word] @@ -590,5 +601,5 @@ sc_signal r_config_heap_next; // current pointer to scan HEAP - sc_signal r_config_upt_index; // UPT index + sc_signal r_config_ivt_index; // IVT index // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) @@ -871,5 +882,5 @@ sc_signal r_xram_rsp_victim_ptr; // victim line pointer to the heap sc_signal * r_xram_rsp_victim_data; // victim line data - sc_signal r_xram_rsp_upt_index; // UPT entry index + sc_signal r_xram_rsp_ivt_index; // IVT entry index sc_signal r_xram_rsp_next_ptr; // Next pointer to the heap @@ -952,4 +963,10 @@ //////////////////////////////////////////////////// + // Registers controlled by ALLOC_IVT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_ivt_fsm; + + //////////////////////////////////////////////////// // Registers controlled by ALLOC_HEAP fsm //////////////////////////////////////////////////// Index: branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 440) +++ branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 441) @@ -136,5 +136,5 @@ "CONFIG_DIR_REQ", "CONFIG_DIR_ACCESS", - "CONFIG_DIR_UPT_LOCK", + "CONFIG_DIR_IVT_LOCK", "CONFIG_BC_SEND", "CONFIG_BC_WAIT", @@ -180,5 +180,5 @@ "WRITE_MISS_XRAM_REQ", "WRITE_BC_TRT_LOCK", - "WRITE_BC_UPT_LOCK", + "WRITE_BC_IVT_LOCK", "WRITE_BC_DIR_INVAL", "WRITE_BC_CC_SEND", @@ -235,5 +235,5 @@ "CAS_UPT_NEXT", "CAS_BC_TRT_LOCK", - "CAS_BC_UPT_LOCK", + "CAS_BC_IVT_LOCK", "CAS_BC_DIR_INVAL", "CAS_BC_CC_SEND", @@ -258,7 +258,7 @@ "CLEANUP_HEAP_CLEAN", "CLEANUP_HEAP_FREE", - "CLEANUP_UPT_LOCK", - "CLEANUP_UPT_DECREMENT", - "CLEANUP_UPT_CLEAR", + "CLEANUP_IVT_LOCK", + "CLEANUP_IVT_DECREMENT", + "CLEANUP_IVT_CLEAR", "CLEANUP_WRITE_RSP", "CLEANUP_CONFIG_ACK", @@ -328,4 +328,5 @@ const size_t trt_lines, // number of TRT entries const size_t upt_lines, // number of UPT entries + const size_t ivt_lines, // number of IVT entries const size_t debug_start_cycle, const bool debug_ok) @@ -337,6 +338,7 @@ p_vci_tgt( "p_vci_tgt" ), p_vci_ixr( "p_vci_ixr" ), - p_dspin_in( "p_dspin_in" ), - p_dspin_out( "p_dspin_out" ), + p_dspin_p2m( "p_dspin_p2m" ), + p_dspin_m2p( "p_dspin_m2p" ), + p_dspin_clack( "p_dspin_clack" ), m_seglist( mtp.getSegmentList(tgtid_d) ), @@ -355,4 +357,5 @@ m_upt_lines(upt_lines), m_upt(upt_lines), + m_ivt(ivt_lines), m_cache_directory(nways, nsets, nwords, vci_param_int::N), m_cache_data(nways, nsets, nwords), @@ -446,4 +449,5 @@ r_alloc_trt_fsm("r_alloc_trt_fsm"), r_alloc_upt_fsm("r_alloc_upt_fsm"), + r_alloc_ivt_fsm("r_alloc_ivt_fsm"), r_alloc_heap_fsm("r_alloc_heap_fsm"), r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") @@ -678,4 +682,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; r_alloc_upt_fsm = ALLOC_UPT_WRITE; + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; r_ixr_rsp_fsm = IXR_RSP_IDLE; r_xram_rsp_fsm = XRAM_RSP_IDLE; @@ -689,4 +694,5 @@ m_trt.init(); m_upt.init(); + m_ivt.init(); m_llsc_table.init(); @@ -1509,5 +1515,5 @@ r_config_dir_next_ptr = entry.ptr; - r_config_fsm = CONFIG_DIR_UPT_LOCK; + r_config_fsm = CONFIG_DIR_IVT_LOCK; } else if ( entry.valid and // hit & sync command @@ -1538,11 +1544,11 @@ } ///////////////////////// - case CONFIG_DIR_UPT_LOCK: // enter this state in case of INVAL command - // Try to get both DIR & UPT locks, and return - // to LOOP state if UPT full. - // Register inval in UPT, and invalidate the - // directory if UPT not full. - { - if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) + case CONFIG_DIR_IVT_LOCK: // enter this state in case of INVAL command + // Try to get both DIR & IVT locks, and return + // to LOOP state if IVT full. + // Register inval in IVT, and invalidate the + // directory if IVT not full. + { + if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) { size_t set = m_y[(addr_t)(r_config_address.read())]; @@ -1558,9 +1564,9 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " +std::cout << " " << " No copies in L1 : inval DIR entry" << std::endl; #endif } - else // try to register inval in UPT + else // try to register inval in IVT { bool wok = false; @@ -1573,5 +1579,5 @@ size_t nb_copies = r_config_dir_count.read(); - wok = m_upt.set(false, // it's an inval transaction + wok = m_ivt.set(false, // it's an inval transaction broadcast, false, // no response required @@ -1583,8 +1589,8 @@ nb_copies, index); - if ( wok ) // UPT success => inval DIR slot + if ( wok ) // IVT success => inval DIR slot { m_cache_directory.inval( way, set ); - r_config_upt_index = index; + r_config_ivt_index = index; if ( broadcast ) r_config_fsm = CONFIG_BC_SEND; else r_config_fsm = CONFIG_INV_SEND; @@ -1592,11 +1598,11 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " - << " Inval DIR entry and register inval in UPT" +std::cout << " " + << " Inval DIR entry and register inval in IVT" << " : index = " << std::dec << index << " / broadcast = " << broadcast << std::endl; #endif } - else // UPT full => release both DIR and UPT locks + else // IVT full => release both DIR and IVT locks { r_config_fsm = CONFIG_LOOP; @@ -1604,6 +1610,6 @@ #if DEBUG_MEMC_CONFIG if(m_debug) -std::cout << " " - << " UPT full : release DIR & UPT locks and retry" << std::endl; +std::cout << " " + << " IVT full : release DIR & IVT locks and retry" << std::endl; #endif } @@ -1620,5 +1626,5 @@ r_config_to_cc_send_multi_req = false; r_config_to_cc_send_brdcast_req = true; - r_config_to_cc_send_trdid = r_config_upt_index.read(); + r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; r_cleanup_to_config_ack = false; @@ -1660,5 +1666,5 @@ r_config_to_cc_send_multi_req = true; r_config_to_cc_send_brdcast_req = false; - r_config_to_cc_send_trdid = r_config_upt_index.read(); + r_config_to_cc_send_trdid = r_config_ivt_index.read(); r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; r_multi_ack_to_config_ack = false; @@ -2744,7 +2750,7 @@ wok = m_upt.set(true, // it's an update transaction - false, // it's not a broadcast - true, // response required - false, // no acknowledge required + false, // it's not a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -2900,5 +2906,5 @@ entry.owner.inst) // put the next srcid in the fifo { - dec_upt_counter = false; + dec_upt_counter = false; write_to_cc_send_fifo_put = true; write_to_cc_send_fifo_inst = entry.owner.inst; @@ -2953,5 +2959,5 @@ { r_write_to_cc_send_multi_req = true; - if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; + if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; else r_write_fsm = WRITE_IDLE; } @@ -3196,5 +3202,5 @@ { r_write_trt_index = wok_index; - r_write_fsm = WRITE_BC_UPT_LOCK; + r_write_fsm = WRITE_BC_IVT_LOCK; } else // wait an empty entry in TRT @@ -3213,7 +3219,7 @@ ////////////////////// - case WRITE_BC_UPT_LOCK: // register BC transaction in UPT - { - if(r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) + case WRITE_BC_IVT_LOCK: // register BC transaction in IVT + { + if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) { bool wok = false; @@ -3225,8 +3231,8 @@ size_t nb_copies = r_write_count.read(); - wok = m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -3238,5 +3244,5 @@ #if DEBUG_MEMC_WRITE if( m_debug and wok ) -std::cout << " Register broadcast inval in UPT" +std::cout << " Register broadcast inval in IVT" << " / nb_copies = " << r_write_count.read() << std::endl; #endif @@ -3244,5 +3250,5 @@ if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; - else r_write_fsm = WRITE_WAIT; + else r_write_fsm = WRITE_WAIT; } break; @@ -3255,9 +3261,9 @@ // and invalidate the line in directory if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or - (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or - (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) + (r_alloc_ivt_fsm.read() != ALLOC_IVT_WRITE) or + (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) { std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl; - std::cout << "bad TRT, DIR, or UPT allocation" << std::endl; + std::cout << "bad TRT, DIR, or IVT allocation" << std::endl; exit(0); } @@ -3787,10 +3793,10 @@ } ///////////////////////// - case XRAM_RSP_INVAL_LOCK: // Take the UPT lock to check a possible pending inval - { - if(r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP) + case XRAM_RSP_INVAL_LOCK: // Take the IVT lock to check a possible pending inval + { + if(r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) { size_t index = 0; - if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval + if(m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval { r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; @@ -3799,5 +3805,5 @@ if(m_debug) std::cout << " " - << " Get acces to UPT, but line invalidation registered" + << " Get acces to IVT, but line invalidation registered" << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline << " / index = " << std::dec << index << std::endl; @@ -3805,5 +3811,5 @@ } - else if(m_upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full + else if(m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full { r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; @@ -3812,5 +3818,5 @@ if(m_debug) std::cout << " " - << " Get acces to UPT, but inval required and UPT full" << std::endl; + << " Get acces to IVT, but inval required and IVT full" << std::endl; #endif } @@ -3822,5 +3828,5 @@ if(m_debug) std::cout << " " - << " Get acces to UPT" << std::endl; + << " Get acces to IVT" << std::endl; #endif } @@ -3842,5 +3848,5 @@ /////////////////////// case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) - // and possibly set an inval request in UPT + // and possibly set an inval request in IVT { // check if this is an instruction read, this means pktid is either @@ -3900,5 +3906,5 @@ m_cache_directory.write(set, way, entry); - // request an invalidattion request in UPT for victim line + // request an invalidattion request in IVT for victim line if(r_xram_rsp_victim_inval.read()) { @@ -3907,5 +3913,5 @@ size_t count_copies = r_xram_rsp_victim_count.read(); - bool wok = m_upt.set(false, // it's an inval transaction + bool wok = m_ivt.set(false, // it's an inval transaction broadcast, // set broadcast bit false, // no response required @@ -3918,10 +3924,10 @@ index); - r_xram_rsp_upt_index = index; + r_xram_rsp_ivt_index = index; if(!wok) { std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT" - << " update_tab entry free but write unsuccessful" << std::endl; + << " invalidate_tab entry free but write unsuccessful" << std::endl; exit(0); } @@ -4032,5 +4038,5 @@ r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); - r_xram_rsp_to_cc_send_trdid = r_xram_rsp_upt_index; + r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); @@ -4377,5 +4383,5 @@ else // miss : check UPT for a pending invalidation transaction { - r_cleanup_fsm = CLEANUP_UPT_LOCK; + r_cleanup_fsm = CLEANUP_IVT_LOCK; } @@ -4835,13 +4841,13 @@ } ////////////////////// - case CLEANUP_UPT_LOCK: // get the lock protecting the UPT to search a pending + case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending // invalidate transaction matching the cleanup { - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) break; + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; size_t index = 0; bool match_inval; - match_inval = m_upt.search_inval(r_cleanup_nline.read(), index); + match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); if ( not match_inval ) // no pending inval @@ -4852,6 +4858,6 @@ if(m_debug) std::cout << " Unexpected cleanup" - << " with no corresponding UPT entry:" + << " CLEANUP_IVT_LOCK> Unexpected cleanup" + << " with no corresponding IVT entry:" << " address = " << std::hex << (r_cleanup_nline.read() *4*m_words) @@ -4862,32 +4868,32 @@ // pending inval - r_cleanup_write_srcid = m_upt.srcid(index); - r_cleanup_write_trdid = m_upt.trdid(index); - r_cleanup_write_pktid = m_upt.pktid(index); - r_cleanup_need_rsp = m_upt.need_rsp(index); - r_cleanup_need_ack = m_upt.need_ack(index); + r_cleanup_write_srcid = m_ivt.srcid(index); + r_cleanup_write_trdid = m_ivt.trdid(index); + r_cleanup_write_pktid = m_ivt.pktid(index); + r_cleanup_need_rsp = m_ivt.need_rsp(index); + r_cleanup_need_ack = m_ivt.need_ack(index); r_cleanup_index = index; - r_cleanup_fsm = CLEANUP_UPT_DECREMENT; + r_cleanup_fsm = CLEANUP_IVT_DECREMENT; #if DEBUG_MEMC_CLEANUP if(m_debug) std::cout << " Cleanup matching pending" - << " invalidate transaction on UPT:" + << " CLEANUP_IVT_LOCK> Cleanup matching pending" + << " invalidate transaction on IVT:" << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 - << " / upt_entry = " << index << std::endl; + << " / ivt_entry = " << index << std::endl; #endif break; } /////////////////////////// - case CLEANUP_UPT_DECREMENT: // decrement response counter in UPT matching entry - { - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) + case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry + { + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) { std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_UPT_DECREMENT state" << std::endl - << "Bad UPT allocation" + << " CLEANUP_IVT_DECREMENT state" << std::endl + << "Bad IVT allocation" << std::endl; @@ -4896,9 +4902,9 @@ size_t count = 0; - m_upt.decrement(r_cleanup_index.read(), count); + m_ivt.decrement(r_cleanup_index.read(), count); if(count == 0) // multi inval transaction completed { - r_cleanup_fsm = CLEANUP_UPT_CLEAR; + r_cleanup_fsm = CLEANUP_IVT_CLEAR; } else // multi inval transaction not completed @@ -4909,7 +4915,7 @@ #if DEBUG_MEMC_CLEANUP if(m_debug) -std::cout << " " - << " Decrement response counter in UPT:" - << " UPT_index = " << r_cleanup_index.read() +std::cout << " " + << " Decrement response counter in IVT:" + << " IVT_index = " << r_cleanup_index.read() << " / rsp_count = " << count << std::endl; #endif @@ -4917,12 +4923,12 @@ } /////////////////////// - case CLEANUP_UPT_CLEAR: // Clear UPT entry - { - if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) + case CLEANUP_IVT_CLEAR: // Clear IVT entry + { + if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) { std::cout << "VCI_MEM_CACHE ERROR " << name() - << " CLEANUP_UPT_CLEAR state" << std::endl - << "Bad UPT allocation" + << " CLEANUP_IVT_CLEAR state" << std::endl + << "Bad IVT allocation" << std::endl; @@ -4930,5 +4936,5 @@ } - m_upt.clear(r_cleanup_index.read()); + m_ivt.clear(r_cleanup_index.read()); if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; @@ -4939,6 +4945,6 @@ if(m_debug) std::cout << " Clear entry in UPT:" - << " UPT_index = " << r_cleanup_index.read() << std::endl; + << " CLEANUP_IVT_CLEAR> Clear entry in IVT:" + << " IVT_index = " << r_cleanup_index.read() << std::endl; #endif break; @@ -4985,5 +4991,5 @@ } //////////////////////// - case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command + case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command // on the coherence network (request to the CC_SEND FSM). // wait if pending request to the CC_SEND FSM @@ -5238,5 +5244,5 @@ !r_cas_to_cc_send_brdcast_req.read()) { - r_cas_fsm = CAS_UPT_LOCK; // multi update required + r_cas_fsm = CAS_UPT_LOCK; // multi update required } else @@ -5509,5 +5515,5 @@ { r_cas_trt_index = wok_index; - r_cas_fsm = CAS_BC_UPT_LOCK; + r_cas_fsm = CAS_BC_IVT_LOCK; } else @@ -5524,8 +5530,8 @@ } ///////////////////// - case CAS_BC_UPT_LOCK: // register a broadcast inval transaction in UPT + case CAS_BC_IVT_LOCK: // register a broadcast inval transaction in IVT // write data in cache in case of successful registration { - if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) + if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) { bool wok = false; @@ -5537,9 +5543,9 @@ size_t nb_copies = r_cas_count.read(); - // register a broadcast inval transaction in UPT - wok = m_upt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required + // register a broadcast inval transaction in IVT + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required srcid, trdid, @@ -5549,5 +5555,5 @@ index); - if(wok) // UPT not full + if(wok) // IVT not full { // cache update @@ -5577,11 +5583,11 @@ if(m_debug) std::cout << " Register a broadcast inval transaction in UPT" + << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT" << " / nline = " << std::hex << nline << " / count = " << std::dec << nb_copies - << " / upt_index = " << index << std::endl; -#endif - } - else // releases the lock protecting UPT + << " / ivt_index = " << index << std::endl; +#endif + } + else // releases the lock protecting IVT { r_cas_fsm = CAS_WAIT; @@ -5594,6 +5600,6 @@ { if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and - (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) + (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) { // set TRT @@ -6199,5 +6205,5 @@ if(m_config_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; break; @@ -6210,5 +6216,5 @@ case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_mult++; config_to_cc_send_fifo_get = true; @@ -6226,5 +6232,5 @@ case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; break; @@ -6233,5 +6239,5 @@ case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; r_config_to_cc_send_brdcast_req = false; @@ -6249,5 +6255,5 @@ case CC_SEND_CLEANUP_ACK: // send one flit for a cleanup acknowledgement { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cleanup_to_cc_send_req = false; @@ -6267,5 +6273,5 @@ if(m_xram_rsp_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; break; @@ -6278,5 +6284,5 @@ case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_mult++; xram_rsp_to_cc_send_fifo_get = true; @@ -6294,5 +6300,5 @@ case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; break; @@ -6301,5 +6307,5 @@ case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; r_xram_rsp_to_cc_send_brdcast_req = false; @@ -6317,5 +6323,5 @@ case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; break; @@ -6324,5 +6330,5 @@ case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; @@ -6344,5 +6350,5 @@ if(m_write_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; @@ -6361,5 +6367,5 @@ case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_update_mult++; @@ -6378,5 +6384,5 @@ case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; if(r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)) { @@ -6392,5 +6398,5 @@ case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; break; @@ -6399,5 +6405,5 @@ case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_inval_brdcast++; @@ -6418,5 +6424,5 @@ if(m_cas_to_cc_send_inst_fifo.rok()) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; @@ -6436,5 +6442,5 @@ case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; m_cpt_update_mult++; @@ -6454,5 +6460,5 @@ case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; if(r_cas_to_cc_send_is_long.read()) @@ -6469,5 +6475,5 @@ case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) { - if(not p_dspin_out.read) break; + if(not p_dspin_m2p.read) break; cas_to_cc_send_fifo_get = true; r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; @@ -6489,9 +6495,9 @@ case CC_RECEIVE_IDLE: { - if(not p_dspin_in.write) break; + if(not p_dspin_p2m.write) break; uint8_t type = DspinDhccpParam::dspin_get( - p_dspin_in.data.read(), + p_dspin_p2m.data.read(), DspinDhccpParam::FROM_L1_TYPE); @@ -6520,8 +6526,8 @@ // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo - if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - assert(not p_dspin_in.eop.read() and + assert(not p_dspin_p2m.eop.read() and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "CLEANUP command must have two flits"); @@ -6537,8 +6543,8 @@ // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo - if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - assert(p_dspin_in.eop.read() and + assert(p_dspin_p2m.eop.read() and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "CLEANUP command must have two flits"); @@ -6556,8 +6562,8 @@ // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo - if(not p_dspin_in.write or not m_cc_receive_to_multi_ack_fifo.wok()) + if(not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) break; - assert(p_dspin_in.eop.read() and + assert(p_dspin_p2m.eop.read() and "VCI_MEM_CACHE ERROR in CC_RECEIVE : " "MULTI_ACK command must have one flit"); @@ -6969,159 +6975,161 @@ // ALLOC_UPT FSM //////////////////////////////////////////////////////////////////////////////////// - // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT), - // with a round robin priority between six FSMs, with the following order: - // CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS - // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT. + // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), + // with a round robin priority between three FSMs, with the following order: + // WRITE -> CAS -> MULTI_ACK + // - The WRITE FSM initiates update transaction and sets a new entry in UPT. + // - The CAS FSM does the same thing as the WRITE FSM. // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. - // - The WRITE FSM initiates update transaction and sets a new entry in UPT. - // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT. - // - The CLEANUP FSM decrement an entry in UPT. - // - The CAS FSM does the same thing as the WRITE FSM. // The resource is always allocated. ///////////////////////////////////////////////////////////////////////////////////// - switch(r_alloc_upt_fsm.read()) { - ////////////////////// - case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM - if (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK) - { - if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - } - break; - ///////////////////////// - case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM - if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and - (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) - { - if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - } - break; - - ///////////////////// - case ALLOC_UPT_WRITE: // allocated to WRITE FSM - if((r_write_fsm.read() != WRITE_UPT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) - { - if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - } - break; - - //////////////////////// - case ALLOC_UPT_XRAM_RSP: - if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) - { - if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - - else if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - } - break; - + case ALLOC_UPT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_UPT_LOCK) + { + if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + + else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + } + break; + + ///////////////////////// + case ALLOC_UPT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_UPT_LOCK) + { + if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + + else if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + } + break; + + ///////////////////////// + case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM + if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and + (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) + { + if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + } + break; + } // end switch r_alloc_upt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_IVT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_IVT FSM allocates the access to the Invalidate Table (IVT), + // with a round robin priority between five FSMs, with the following order: + // WRITE -> XRAM_RSP -> CLEANUP -> CAS -> CONFIG + // - The WRITE FSM initiates broadcast invalidate transactions and sets a new entry + // in IVT. + // - The CAS FSM does the same thing as the WRITE FSM. + // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets + // a new entry in the IVT + // - The CONFIG FSM does the same thing as the XRAM_RSP FSM + // - The CLEANUP FSM complete those trasactions and erase the IVT entry. + // The resource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + switch(r_alloc_ivt_fsm.read()) + { ////////////////////////// - case ALLOC_UPT_CLEANUP: - if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) and - (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT)) - { - if((r_cas_fsm.read() == CAS_UPT_LOCK) or - (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_CAS; - - else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - } - break; + case ALLOC_IVT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + } + break; ////////////////////////// - case ALLOC_UPT_CAS: - if((r_cas_fsm.read() != CAS_UPT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) - { - if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CONFIG; - - else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; - - else if((r_write_fsm.read() == WRITE_UPT_LOCK) or - (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) - r_alloc_upt_fsm = ALLOC_UPT_WRITE; - - else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; - - else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) - r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; - } - break; - - } // end switch r_alloc_upt_fsm + case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM + if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) + { + if(r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + } + break; + + ////////////////////////// + case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM + if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and + (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) + { + if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + } + break; + + ////////////////////////// + case ALLOC_IVT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) + { + if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + } + break; + + ////////////////////////// + case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM + if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) + { + if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + } + break; + + } // end switch r_alloc_ivt_fsm //////////////////////////////////////////////////////////////////////////////////// @@ -7153,5 +7161,5 @@ if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and (r_config_fsm.read() != CONFIG_DIR_ACCESS) and - (r_config_fsm.read() != CONFIG_DIR_UPT_LOCK) ) + (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) ) { if(r_read_fsm.read() == READ_DIR_REQ) @@ -7206,5 +7214,5 @@ (r_write_fsm.read() != WRITE_DIR_HIT) and (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and (r_write_fsm.read() != WRITE_UPT_LOCK) and @@ -7242,5 +7250,5 @@ (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and (r_cas_fsm.read() != CAS_UPT_LOCK) and @@ -7356,5 +7364,5 @@ if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) + (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) { if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or @@ -7379,5 +7387,5 @@ if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) + (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) { if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and @@ -7669,5 +7677,5 @@ m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, cc_receive_to_cleanup_fifo_put, - p_dspin_in.data.read() ); + p_dspin_p2m.data.read() ); //////////////////////////////////////////////////////////////////////////////////// @@ -7677,5 +7685,5 @@ m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, cc_receive_to_multi_ack_fifo_put, - p_dspin_in.data.read() ); + p_dspin_p2m.data.read() ); //////////////////////////////////////////////////////////////////////////////////// @@ -8019,10 +8027,10 @@ //////////////////////////////////////////////////////////////////// - // p_dspin_out port (CC_SEND FSM) + // p_dspin_m2p port (CC_SEND FSM) //////////////////////////////////////////////////////////////////// - p_dspin_out.write = false; - p_dspin_out.eop = false; - p_dspin_out.data = 0; + p_dspin_m2p.write = false; + p_dspin_m2p.eop = false; + p_dspin_m2p.data = 0; switch(r_cc_send_fsm.read()) @@ -8069,6 +8077,6 @@ multi_inval_type, DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8080,7 +8088,7 @@ r_config_to_cc_send_nline.read(), DspinDhccpParam::MULTI_INVAL_NLINE); - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8123,7 +8131,7 @@ DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8164,6 +8172,6 @@ multi_inval_type, DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8177,7 +8185,7 @@ r_xram_rsp_to_cc_send_nline.read(), DspinDhccpParam::MULTI_INVAL_NLINE); - p_dspin_out.eop = true; - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8202,6 +8210,6 @@ 1ULL, DspinDhccpParam::FROM_MC_BC); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; } @@ -8213,7 +8221,7 @@ r_xram_rsp_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8225,7 +8233,7 @@ r_config_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8237,7 +8245,7 @@ r_write_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8249,7 +8257,7 @@ r_cas_to_cc_send_nline.read(), DspinDhccpParam::BROADCAST_NLINE); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; } @@ -8294,6 +8302,6 @@ DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8314,6 +8322,6 @@ DspinDhccpParam::MULTI_UPDT_NLINE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8341,7 +8349,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)); - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = (r_cc_send_cpt.read() == (r_write_to_cc_send_count.read()-1)); + p_dspin_m2p.data = flit; break; @@ -8387,6 +8395,6 @@ DspinDhccpParam::FROM_MC_TYPE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8407,6 +8415,6 @@ DspinDhccpParam::MULTI_UPDT_NLINE); - p_dspin_out.write = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; break; @@ -8427,7 +8435,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = not r_cas_to_cc_send_is_long.read(); - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); + p_dspin_m2p.data = flit; break; @@ -8448,7 +8456,7 @@ DspinDhccpParam::MULTI_UPDT_DATA); - p_dspin_out.write = true; - p_dspin_out.eop = true; - p_dspin_out.data = flit; + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; break; @@ -8457,7 +8465,7 @@ /////////////////////////////////////////////////////////////////// - // p_dspin_in port (CC_RECEIVE FSM) + // p_dspin_p2m port (CC_RECEIVE FSM) /////////////////////////////////////////////////////////////////// - p_dspin_in.read = false; + p_dspin_p2m.read = false; switch(r_cc_receive_fsm.read()) { @@ -8469,10 +8477,10 @@ case CC_RECEIVE_CLEANUP_EOP: { - p_dspin_in.read = m_cc_receive_to_cleanup_fifo.wok(); + p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); break; } case CC_RECEIVE_MULTI_ACK: { - p_dspin_in.read = m_cc_receive_to_multi_ack_fifo.wok(); + p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); break; }