Index: branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 441)
+++ branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 442)
@@ -125,10 +125,8 @@
         CC_SEND_WRITE_IDLE,
         CC_SEND_CAS_IDLE,
-        CC_SEND_CLEANUP_IDLE,
         CC_SEND_CONFIG_INVAL_HEADER,
         CC_SEND_CONFIG_INVAL_NLINE,
         CC_SEND_CONFIG_BRDCAST_HEADER,
         CC_SEND_CONFIG_BRDCAST_NLINE,
-        CC_SEND_CLEANUP_ACK,
         CC_SEND_XRAM_RSP_BRDCAST_HEADER,
         CC_SEND_XRAM_RSP_BRDCAST_NLINE,
@@ -790,11 +788,4 @@
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
 
-      // Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
-      sc_signal<bool>     r_cleanup_to_cc_send_req;       // valid request
-      sc_signal<size_t>   r_cleanup_to_cc_send_srcid;     // L1 srcid
-      sc_signal<size_t>   r_cleanup_to_cc_send_set_index; // L1 set index
-      sc_signal<size_t>   r_cleanup_to_cc_send_way_index; // L1 way index
-      sc_signal<bool>     r_cleanup_to_cc_send_inst;      // Instruction Cleanup Ack
-
       ///////////////////////////////////////////////////////
       // Registers controlled by CAS fsm
Index: branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 441)
+++ branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 442)
@@ -99,10 +99,8 @@
   "CC_SEND_WRITE_IDLE",
   "CC_SEND_CAS_IDLE",
-  "CC_SEND_CLEANUP_IDLE",
   "CC_SEND_CONFIG_INVAL_HEADER",
   "CC_SEND_CONFIG_INVAL_NLINE",
   "CC_SEND_CONFIG_BRDCAST_HEADER",
   "CC_SEND_CONFIG_BRDCAST_NLINE",
-  "CC_SEND_CLEANUP_ACK",
   "CC_SEND_XRAM_RSP_BRDCAST_HEADER",
   "CC_SEND_XRAM_RSP_BRDCAST_NLINE",
@@ -4254,5 +4252,5 @@
         DspinDhccpParam::dspin_get(
             flit,
-            DspinDhccpParam::FROM_L1_TYPE);
+            DspinDhccpParam::P2M_TYPE);
 
       r_cleanup_way_index =
@@ -4992,14 +4990,7 @@
     ////////////////////////
     case CLEANUP_SEND_CLACK:  // acknowledgement to a cleanup command
-                              // on the coherence network (request to the CC_SEND FSM).
-                              // wait if pending request to the CC_SEND FSM
-    {
-      if(r_cleanup_to_cc_send_req.read()) break;
-
-      r_cleanup_to_cc_send_req       = true;
-      r_cleanup_to_cc_send_set_index = r_cleanup_nline.read() & 0xFFFF;
-      r_cleanup_to_cc_send_way_index = r_cleanup_way_index.read();
-      r_cleanup_to_cc_send_srcid     = r_cleanup_srcid.read();
-      r_cleanup_to_cc_send_inst      = r_cleanup_inst.read();
+                              // on the coherence CLACK network.
+    {
+      if(not p_dspin_clack.read) break;
 
       r_cleanup_fsm = CLEANUP_IDLE;
@@ -5844,9 +5835,6 @@
   // network, used to update or invalidate cache lines in L1 caches.
   //
-  // This fsm is used also to acknowledge CLEANUP a command after request from
-  // the CLEANUP fsm.
-  //
-  // It implements a round-robin priority between the five possible client FSMs
-  //     XRAM_RSP > CAS > CLEANUP > WRITE > CONFIG 
+  // It implements a round-robin priority between the four possible client FSMs
+  //     XRAM_RSP > CAS > WRITE > CONFIG 
   //
   // Each FSM can request the next services:
@@ -5860,6 +5848,4 @@
   //   r_config_to_cc_send_brdcast_req : broadcast-inval
   //   
-  // - r_cleanup_to_cc_send_req : cleanup acknowledgement
-  //
   // An inval request is a double DSPIN flit command containing:
   // 1. the index of the line to be invalidated.
@@ -5904,10 +5890,4 @@
           break;
         }
-        // CLEANUP
-        if (r_cleanup_to_cc_send_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CLEANUP_ACK;
-          break;
-        }
         // WRITE
         if(m_write_to_cc_send_inst_fifo.rok() or
@@ -5983,10 +5963,4 @@
           break;
         }
-        // CLEANUP
-        if (r_cleanup_to_cc_send_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CLEANUP_ACK;
-          break;
-        }
         // WRITE
         if(m_write_to_cc_send_inst_fifo.rok() or
@@ -6022,10 +5996,4 @@
           break;
         }
-        // CLEANUP
-        if(r_cleanup_to_cc_send_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CLEANUP_ACK;
-          break;
-        }
         // WRITE
         if(m_write_to_cc_send_inst_fifo.rok() or
@@ -6075,9 +6043,4 @@
       case CC_SEND_CAS_IDLE:   // CLEANUP FSM has highest priority
       {
-        if(r_cleanup_to_cc_send_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CLEANUP_ACK;
-          break;
-        }
         if(m_write_to_cc_send_inst_fifo.rok() or
             r_write_to_cc_send_multi_req.read())
@@ -6130,70 +6093,4 @@
           r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
           m_cpt_inval++;
-          break;
-        }
-        break;
-      }
-      //////////////////////////
-      case CC_SEND_CLEANUP_IDLE:   // WRITE FSM has highest priority
-      {
-        // WRITE
-        if(m_write_to_cc_send_inst_fifo.rok() or
-            r_write_to_cc_send_multi_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
-          m_cpt_update++;
-          break;
-        }
-        if(r_write_to_cc_send_brdcast_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
-          m_cpt_inval++;
-          break;
-        }
-        // CONFIG
-        if(r_config_to_cc_send_multi_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
-          m_cpt_inval++;
-          break;
-        }
-        if(r_config_to_cc_send_brdcast_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
-          m_cpt_inval++;
-          break;
-        }
-        // XRAM_RSP
-        if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
-            r_xram_rsp_to_cc_send_multi_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
-          m_cpt_inval++;
-          break;
-        }
-        if(r_xram_rsp_to_cc_send_brdcast_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
-          m_cpt_inval++;
-          break;
-        }
-        // CAS
-        if(m_cas_to_cc_send_inst_fifo.rok() or
-            r_cas_to_cc_send_multi_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
-          m_cpt_update++;
-          break;
-        }
-        if(r_cas_to_cc_send_brdcast_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
-          m_cpt_inval++;
-          break;
-        }
-        // CLEANUP
-        if(r_cleanup_to_cc_send_req.read())
-        {
-          r_cc_send_fsm = CC_SEND_CLEANUP_ACK;
           break;
         }
@@ -6249,20 +6146,4 @@
           << " CC_SEND_CONFIG_BRDCAST_NLINE> BC-Inval for line "
           << std::hex << r_config_to_cc_send_nline.read() << std::endl;
-#endif
-        break;
-      }
-      /////////////////////////
-      case CC_SEND_CLEANUP_ACK:   // send one flit for a cleanup acknowledgement 
-      {
-        if(not p_dspin_m2p.read) break;
-
-        r_cleanup_to_cc_send_req = false;
-        r_cc_send_fsm = CC_SEND_CLEANUP_IDLE;
-
-#if DEBUG_MEMC_CC_SEND
-if(m_debug)
-std::cout << "  <MEMC " << name()
-          << " CC_SEND_CLEANUP_ACK> Cleanup Ack for srcid "
-          << std::hex << r_cleanup_to_cc_send_srcid.read() << std::endl;
 #endif
         break;
@@ -6500,5 +6381,5 @@
           DspinDhccpParam::dspin_get(
               p_dspin_p2m.data.read(),
-              DspinDhccpParam::FROM_L1_TYPE);
+              DspinDhccpParam::P2M_TYPE);
 
         if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or
@@ -8041,5 +7922,4 @@
     case CC_SEND_WRITE_IDLE:
     case CC_SEND_CAS_IDLE:
-    case CC_SEND_CLEANUP_IDLE:
     {
         break;
@@ -8076,5 +7956,5 @@
         DspinDhccpParam::dspin_set( flit,
                                     multi_inval_type,
-                                    DspinDhccpParam::FROM_MC_TYPE);
+                                    DspinDhccpParam::M2P_TYPE);
         p_dspin_m2p.write = true;
         p_dspin_m2p.data  = flit;
@@ -8093,49 +7973,4 @@
         break;
     }
-    ////////////////////////
-    case CC_SEND_CLEANUP_ACK:
-      {
-        uint8_t cleanup_ack_type;
-        if(r_cleanup_to_cc_send_inst.read())
-        {
-          cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_INST;
-        }
-        else
-        {
-          cleanup_ack_type = DspinDhccpParam::TYPE_CLEANUP_ACK_DATA;
-        }
-
-        uint64_t flit = 0;
-        uint64_t dest =
-          r_cleanup_to_cc_send_srcid.read() <<
-          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            dest,
-            DspinDhccpParam::CLEANUP_ACK_DEST);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            r_cleanup_to_cc_send_set_index.read(),
-            DspinDhccpParam::CLEANUP_ACK_SET);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            r_cleanup_to_cc_send_way_index.read(),
-            DspinDhccpParam::CLEANUP_ACK_WAY);
-
-        DspinDhccpParam::dspin_set(
-            flit,
-            cleanup_ack_type,
-            DspinDhccpParam::FROM_MC_TYPE);
-
-        p_dspin_m2p.eop   = true;
-        p_dspin_m2p.write = true;
-        p_dspin_m2p.data  = flit;
-
-        break;
-    }
-
     ///////////////////////////////////
     case CC_SEND_XRAM_RSP_INVAL_HEADER:
@@ -8171,5 +8006,5 @@
         DspinDhccpParam::dspin_set( flit,
                                     multi_inval_type,
-                                    DspinDhccpParam::FROM_MC_TYPE);
+                                    DspinDhccpParam::M2P_TYPE);
         p_dspin_m2p.write = true;
         p_dspin_m2p.data  = flit;
@@ -8209,5 +8044,5 @@
         DspinDhccpParam::dspin_set( flit,
                                     1ULL,
-                                    DspinDhccpParam::FROM_MC_BC);
+                                    DspinDhccpParam::M2P_BC);
         p_dspin_m2p.write = true;
         p_dspin_m2p.data  = flit;
@@ -8300,5 +8135,5 @@
             flit,
             multi_updt_type,
-            DspinDhccpParam::FROM_MC_TYPE);
+            DspinDhccpParam::M2P_TYPE);
 
         p_dspin_m2p.write = true;
@@ -8393,5 +8228,5 @@
             flit,
             multi_updt_type,
-            DspinDhccpParam::FROM_MC_TYPE);
+            DspinDhccpParam::M2P_TYPE);
 
         p_dspin_m2p.write = true;
@@ -8464,12 +8299,84 @@
   }
 
+  ////////////////////////////////////////////////////////////////////
+  //  p_dspin_clack port (CLEANUP FSM)
+  ////////////////////////////////////////////////////////////////////
+
+  switch(r_cleanup_fsm.read())
+  {
+    case CLEANUP_IDLE:
+    case CLEANUP_GET_NLINE:
+    case CLEANUP_DIR_REQ:
+    case CLEANUP_DIR_LOCK:
+    case CLEANUP_DIR_WRITE:
+    case CLEANUP_HEAP_REQ:
+    case CLEANUP_HEAP_LOCK:
+    case CLEANUP_HEAP_SEARCH:
+    case CLEANUP_HEAP_CLEAN:
+    case CLEANUP_HEAP_FREE:
+    case CLEANUP_IVT_LOCK:
+    case CLEANUP_IVT_DECREMENT:
+    case CLEANUP_IVT_CLEAR:
+    case CLEANUP_WRITE_RSP:
+    case CLEANUP_CONFIG_ACK:
+      p_dspin_clack.write = false;
+      p_dspin_clack.eop   = false;
+      p_dspin_clack.data  = 0;
+
+      break;
+
+    case CLEANUP_SEND_CLACK: 
+      {
+        uint8_t cleanup_ack_type;
+        if(r_cleanup_inst.read())
+        {
+          cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST;
+        }
+        else
+        {
+          cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA;
+        }
+
+        uint64_t flit = 0;
+        uint64_t dest =
+          r_cleanup_srcid.read() <<
+          (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S);
+
+        DspinDhccpParam::dspin_set(
+            flit,
+            dest,
+            DspinDhccpParam::CLACK_DEST);
+
+        DspinDhccpParam::dspin_set(
+            flit,
+            r_cleanup_nline.read() & 0xFFFF,
+            DspinDhccpParam::CLACK_SET);
+
+        DspinDhccpParam::dspin_set(
+            flit,
+            r_cleanup_way_index.read(),
+            DspinDhccpParam::CLACK_WAY);
+
+        DspinDhccpParam::dspin_set(
+            flit,
+            cleanup_ack_type,
+            DspinDhccpParam::CLACK_TYPE);
+
+        p_dspin_clack.eop   = true;
+        p_dspin_clack.write = true;
+        p_dspin_clack.data  = flit;
+      }
+      break;
+  }
+
   ///////////////////////////////////////////////////////////////////
   //  p_dspin_p2m port (CC_RECEIVE FSM)
   ///////////////////////////////////////////////////////////////////
-  p_dspin_p2m.read = false;
+  //
   switch(r_cc_receive_fsm.read())
   {
     case CC_RECEIVE_IDLE:
       {
+        p_dspin_p2m.read = false;
         break;
       }
