- Timestamp:
- Jul 18, 2013, 11:37:47 AM (11 years ago)
- Location:
- branches/v5/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_vcache_wrapper.h (modified) (6 diffs)
-
src/vci_cc_vcache_wrapper.cpp (modified) (74 diffs)
Legend:
- Unmodified
- Added
- Removed
-
branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r443 r446 89 89 // handling coherence requests 90 90 ICACHE_CC_CHECK, 91 ICACHE_CC_UPDT, 91 92 ICACHE_CC_INVAL, 92 ICACHE_CC_UPDT,93 ICACHE_CC_BROADCAST,94 93 ICACHE_CC_SEND_WAIT, 95 94 }; … … 138 137 // handling coherence requests 139 138 DCACHE_CC_CHECK, 139 DCACHE_CC_UPDT, 140 140 DCACHE_CC_INVAL, 141 DCACHE_CC_UPDT,142 DCACHE_CC_BROADCAST,143 141 DCACHE_CC_SEND_WAIT, 144 142 // handling TLB inval (after a coherence or XTN request) … … 285 283 286 284 public: 287 sc_in<bool> p_clk; 288 sc_in<bool> p_resetn; 289 sc_in<bool> p_irq[iss_t::n_irq]; 290 soclib::caba::VciInitiator<vci_param> p_vci; 291 soclib::caba::DspinInput <dspin_in_width> p_dspin_in; 292 soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; 285 sc_in<bool> p_clk; 286 sc_in<bool> p_resetn; 287 sc_in<bool> p_irq[iss_t::n_irq]; 288 soclib::caba::VciInitiator<vci_param> p_vci; 289 soclib::caba::DspinInput<dspin_in_width> p_dspin_m2p; 290 soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m; 291 soclib::caba::DspinInput<dspin_in_width> p_dspin_clack; 293 292 294 293 private: … … 371 370 sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing 372 371 372 // coherence clack handling 373 sc_signal<bool> r_icache_clack_req; // clack request 374 sc_signal<size_t> r_icache_clack_way; // clack way 375 sc_signal<size_t> r_icache_clack_set; // clack set 376 373 377 // icache flush handling 374 378 sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush … … 444 448 sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing 445 449 450 // coherence clack handling 451 sc_signal<bool> r_dcache_clack_req; // clack request 452 sc_signal<size_t> r_dcache_clack_way; // clack way 453 sc_signal<size_t> r_dcache_clack_set; // clack set 454 446 455 // dcache flush handling 447 456 sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush … … 537 546 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address 538 547 548 /////////////////////////////////// 549 // DSPIN CLACK INTERFACE REGISTER 550 /////////////////////////////////// 551 sc_signal<bool> r_dspin_clack_req; 552 sc_signal<uint64_t> r_dspin_clack_flit; 553 539 554 ////////////////////////////////////////////////////////////////// 540 555 // processor, write buffer, caches , TLBs -
branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r444 r446 62 62 63 63 "ICACHE_CC_CHECK", 64 "ICACHE_CC_UPDT", 64 65 "ICACHE_CC_INVAL", 65 "ICACHE_CC_UPDT",66 "ICACHE_CC_BROADCAST",67 66 "ICACHE_CC_SEND_WAIT", 68 67 }; … … 110 109 111 110 "DCACHE_CC_CHECK", 111 "DCACHE_CC_UPDT", 112 112 "DCACHE_CC_INVAL", 113 "DCACHE_CC_UPDT",114 "DCACHE_CC_BROADCAST",115 113 "DCACHE_CC_SEND_WAIT", 116 114 … … 216 214 p_resetn("p_resetn"), 217 215 p_vci("p_vci"), 218 p_dspin_in("p_dspin_in"), 219 p_dspin_out("p_dspin_out"), 216 p_dspin_m2p("p_dspin_m2p"), 217 p_dspin_p2m("p_dspin_p2m"), 218 p_dspin_clack("p_dspin_clack"), 220 219 221 220 m_cacheability_table( mtd.getCacheabilityTable() ), … … 755 754 r_icache_cc_send_req = false; 756 755 756 r_icache_clack_req = false; 757 757 758 // No pending write in pipeline 758 759 r_dcache_wbuf_req = false; … … 775 776 r_dcache_cc_send_req = false; 776 777 778 r_dcache_clack_req = false; 779 777 780 // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs 778 781 r_cc_receive_icache_req = false; … … 789 792 r_icache_miss_inval = false; 790 793 r_dcache_miss_inval = false; 794 795 r_dspin_clack_req = false; 791 796 792 797 // No signalisation of errors … … 1014 1019 // 5/ uncacheable read miss => ICACHE_UNC_REQ 1015 1020 { 1021 // coherence clack interrupt 1022 if ( r_icache_clack_req.read() ) 1023 { 1024 r_icache_fsm = ICACHE_CC_CHECK; 1025 r_icache_fsm_save = r_icache_fsm.read(); 1026 break; 1027 } 1028 1016 1029 // coherence interrupt 1017 1030 if ( r_cc_receive_icache_req.read() ) … … 1242 1255 // external coherence request are accepted in this state. 1243 1256 { 1257 // coherence clack interrupt 1258 if ( r_icache_clack_req.read() ) 1259 { 1260 r_icache_fsm = ICACHE_CC_CHECK; 1261 r_icache_fsm_save = r_icache_fsm.read(); 1262 break; 1263 } 1264 1244 1265 // coherence interrupt 1245 1266 if ( r_cc_receive_icache_req.read() ) … … 1286 1307 // A cleanup request is generated for each valid line 1287 1308 { 1309 // coherence clack interrupt 1310 if ( r_icache_clack_req.read() ) 1311 { 1312 r_icache_fsm = ICACHE_CC_CHECK; 1313 r_icache_fsm_save = r_icache_fsm.read(); 1314 break; 1315 } 1316 1288 1317 // coherence request (from CC_RECEIVE FSM) 1289 1318 if ( r_cc_receive_icache_req.read() ) … … 1484 1513 { 1485 1514 if (m_ireq.valid) m_cost_ins_miss_frz++; 1515 1516 // coherence clack interrupt 1517 if ( r_icache_clack_req.read() ) 1518 { 1519 r_icache_fsm = ICACHE_CC_CHECK; 1520 r_icache_fsm_save = r_icache_fsm.read(); 1521 break; 1522 } 1486 1523 1487 1524 // coherence interrupt … … 1574 1611 if (m_ireq.valid) m_cost_ins_miss_frz++; 1575 1612 1613 // coherence clack interrupt 1614 if ( r_icache_clack_req.read() ) 1615 { 1616 r_icache_fsm = ICACHE_CC_CHECK; 1617 r_icache_fsm_save = r_icache_fsm.read(); 1618 break; 1619 } 1620 1576 1621 // coherence interrupt 1577 1622 if ( r_cc_receive_icache_req.read() ) … … 1645 1690 if ( m_ireq.valid ) m_cost_ins_miss_frz++; 1646 1691 1692 // coherence clack interrupt 1693 if ( r_icache_clack_req.read() ) 1694 { 1695 r_icache_fsm = ICACHE_CC_CHECK; 1696 r_icache_fsm_save = r_icache_fsm.read(); 1697 break; 1698 } 1699 1647 1700 // coherence interrupt 1648 1701 if ( r_cc_receive_icache_req.read() ) … … 1716 1769 case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM 1717 1770 { 1771 // coherence clack interrupt 1772 if ( r_icache_clack_req.read() ) 1773 { 1774 r_icache_fsm = ICACHE_CC_CHECK; 1775 r_icache_fsm_save = r_icache_fsm.read(); 1776 break; 1777 } 1778 1718 1779 // coherence interrupt 1719 1780 if ( r_cc_receive_icache_req.read() ) … … 1756 1817 paddr_t mask = ~((m_icache_words<<2)-1); 1757 1818 1758 if (r_ cc_receive_icache_type.read() == CC_TYPE_CLACK)1819 if (r_icache_clack_req.read()) 1759 1820 // We switch the directory slot to EMPTY state 1760 1821 // and reset r_icache_miss_clack if the cleanup ack … … 1768 1829 #endif 1769 1830 r_icache.write_dir( 0, 1770 r_ cc_receive_icache_way.read(),1771 r_ cc_receive_icache_set.read(),1831 r_icache_clack_way.read(), 1832 r_icache_clack_set.read(), 1772 1833 CACHE_SLOT_STATE_EMPTY); 1773 1834 1774 if ( (r_icache_miss_set.read() == r_ cc_receive_icache_set.read()) and1775 (r_icache_miss_way.read() == r_ cc_receive_icache_way.read()) )1835 if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and 1836 (r_icache_miss_way.read() == r_icache_clack_way.read()) ) 1776 1837 r_icache_miss_clack = false; 1777 1838 1778 1839 r_icache_fsm = r_icache_fsm_save.read() ; 1779 r_ cc_receive_icache_req = false;1840 r_icache_clack_req = false; 1780 1841 1781 1842 #if DEBUG_ICACHE … … 1784 1845 std::cout << " <PROC " << name() 1785 1846 << " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state" 1786 << " set = " << r_ cc_receive_icache_set.read()1787 << " / way = " << r_ cc_receive_icache_way.read() << std::endl;1847 << " set = " << r_icache_clack_set.read() 1848 << " / way = " << r_icache_clack_way.read() << std::endl; 1788 1849 } 1789 1850 #endif … … 1840 1901 r_icache_cc_set = set; 1841 1902 1842 if ( 1903 if (state == CACHE_SLOT_STATE_VALID) // hit 1843 1904 { 1844 1905 // need to update the cache state … … 1849 1910 r_icache_cc_word = r_cc_receive_word_idx.read(); 1850 1911 } 1851 else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval 1912 else if ((r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) || // hit inval 1913 (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST)) // hit broadcast 1852 1914 { 1853 1915 r_icache_fsm = ICACHE_CC_INVAL; 1854 }1855 else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast1856 {1857 r_icache_fsm = ICACHE_CC_BROADCAST;1858 1916 } 1859 1917 } … … 1875 1933 } 1876 1934 } 1877 break;1878 }1879 /////////////////////1880 case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state1881 {1882 1883 #if DEBUG_ICACHE1884 if ( m_debug_activated )1885 {1886 std::cout << " <PROC " << name()1887 << " ICACHE_CC_INVAL> slot returns to empty state"1888 << " set = " << r_icache_cc_set.read()1889 << " / way = " << r_icache_cc_way.read() << std::endl;1890 }1891 #endif1892 1893 #ifdef INSTRUMENTATION1894 m_cpt_icache_dir_read++;1895 #endif1896 if (r_icache_cc_need_write.read())1897 {1898 r_icache.write_dir( 0,1899 r_icache_cc_way.read(),1900 r_icache_cc_set.read(),1901 CACHE_SLOT_STATE_EMPTY );1902 // no need to write in the cache anymore1903 r_icache_cc_need_write = false;1904 }1905 1906 // multicast acknowledgement1907 // send a request to cc_send_fsm1908 if(not r_icache_cc_send_req.read()) // cc_send is available1909 {1910 // coherence request completed1911 r_cc_receive_icache_req = false;1912 // request multicast acknowledgement1913 r_icache_cc_send_req = true;1914 r_icache_cc_send_nline = r_cc_receive_icache_nline.read();1915 r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();1916 r_icache_cc_send_type = CC_TYPE_MULTI_ACK;1917 1918 r_icache_fsm = r_icache_fsm_save.read();1919 }1920 //else wait for previous cc_send request to be sent1921 1935 break; 1922 1936 } … … 1984 1998 } 1985 1999 ///////////////////////// 1986 case ICACHE_CC_ BROADCAST: // hit broadcast: switch slot to ZOMBI state1987 2000 case ICACHE_CC_INVAL: // hit invalidate : switch slot to ZOMBI state 2001 // and request a cleanup 1988 2002 { 1989 2003 … … 1992 2006 { 1993 2007 std::cout << " <PROC " << name() 1994 << " ICACHE_CC_ BROADCAST> Slot goes to zombi state "2008 << " ICACHE_CC_INVAL > Slot goes to zombi state " 1995 2009 << " set = " << r_icache_cc_set.read() 1996 2010 << " / way = " << r_icache_cc_way.read() << std::endl; … … 2308 2322 } 2309 2323 2324 // coherence clack request (from DSPIN CLACK) 2325 else if ( r_dcache_clack_req.read() ) 2326 { 2327 r_dcache_fsm = DCACHE_CC_CHECK; 2328 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 2329 } 2310 2330 // coherence request (from CC_RECEIVE FSM) 2311 2331 else if ( r_cc_receive_dcache_req.read() ) … … 2912 2932 case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache 2913 2933 { 2934 // coherence clack request (from DSPIN CLACK) 2935 if ( r_dcache_clack_req.read() ) 2936 { 2937 r_dcache_fsm = DCACHE_CC_CHECK; 2938 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 2939 break; 2940 } 2941 2914 2942 // coherence request (from CC_RECEIVE FSM) 2915 2943 if ( r_cc_receive_dcache_req.read() ) … … 3209 3237 case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache 3210 3238 { 3239 // coherence clack request (from DSPIN CLACK) 3240 if ( r_dcache_clack_req.read() ) 3241 { 3242 r_dcache_fsm = DCACHE_CC_CHECK; 3243 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3244 break; 3245 } 3246 3211 3247 // coherence request (from CC_RECEIVE FSM) 3212 3248 if ( r_cc_receive_dcache_req.read() ) … … 3506 3542 3507 3543 { 3544 // coherence clack request (from DSPIN CLACK) 3545 if ( r_dcache_clack_req.read() ) 3546 { 3547 r_dcache_fsm = DCACHE_CC_CHECK; 3548 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3549 break; 3550 } 3551 3508 3552 // coherence request (from CC_RECEIVE FSM) 3509 3553 if ( r_cc_receive_dcache_req.read() ) … … 3577 3621 // as there is a risk of dead-lock 3578 3622 { 3623 // coherence clack request (from DSPIN CLACK) 3624 if ( r_dcache_clack_req.read() ) 3625 { 3626 r_dcache_fsm = DCACHE_CC_CHECK; 3627 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3628 break; 3629 } 3630 3579 3631 // coherence request (from CC_RECEIVE FSM) 3580 3632 if ( r_cc_receive_dcache_req.read() ) … … 3582 3634 r_dcache_fsm = DCACHE_CC_CHECK; 3583 3635 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3636 break; 3584 3637 } 3585 3638 … … 3598 3651 // and because it can exist a simultaneous ITLB miss 3599 3652 { 3653 // coherence clack request (from DSPIN CLACK) 3654 if ( r_dcache_clack_req.read() ) 3655 { 3656 r_dcache_fsm = DCACHE_CC_CHECK; 3657 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3658 break; 3659 } 3660 3600 3661 // coherence request (from CC_RECEIVE FSM) 3601 3662 if ( r_cc_receive_dcache_req.read() ) … … 3633 3694 // returns to IDLE and flush TLBs when last slot 3634 3695 { 3696 // coherence clack request (from DSPIN CLACK) 3697 if ( r_dcache_clack_req.read() ) 3698 { 3699 r_dcache_fsm = DCACHE_CC_CHECK; 3700 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3701 break; 3702 } 3703 3635 3704 // coherence request (from CC_RECEIVE FSM) 3636 3705 if ( r_cc_receive_dcache_req.read() ) … … 3893 3962 { 3894 3963 if ( m_dreq.valid) m_cost_data_miss_frz++; 3964 3965 // coherence clack request (from DSPIN CLACK) 3966 if ( r_dcache_clack_req.read() ) 3967 { 3968 r_dcache_fsm = DCACHE_CC_CHECK; 3969 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 3970 break; 3971 } 3895 3972 3896 3973 // coherence request (from CC_RECEIVE FSM) … … 4009 4086 { 4010 4087 if ( m_dreq.valid) m_cost_data_miss_frz++; 4088 4089 // coherence clack request (from DSPIN CLACK) 4090 if ( r_dcache_clack_req.read() ) 4091 { 4092 r_dcache_fsm = DCACHE_CC_CHECK; 4093 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4094 break; 4095 } 4011 4096 4012 4097 // coherence request (from CC_RECEIVE FSM) … … 4125 4210 if ( m_dreq.valid) m_cost_data_miss_frz++; 4126 4211 4212 // coherence clack request (from DSPIN CLACK) 4213 if ( r_dcache_clack_req.read() ) 4214 { 4215 r_dcache_fsm = DCACHE_CC_CHECK; 4216 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4217 break; 4218 } 4219 4127 4220 // coherence request (from CC_RECEIVE FSM) 4128 4221 if ( r_cc_receive_dcache_req.read() ) … … 4199 4292 case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read 4200 4293 { 4294 // coherence clack request (from DSPIN CLACK) 4295 if ( r_dcache_clack_req.read() ) 4296 { 4297 r_dcache_fsm = DCACHE_CC_CHECK; 4298 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4299 break; 4300 } 4301 4201 4302 // coherence request (from CC_RECEIVE FSM) 4202 4303 if ( r_cc_receive_dcache_req.read() ) … … 4236 4337 case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction 4237 4338 { 4339 // coherence clack request (from DSPIN CLACK) 4340 if ( r_dcache_clack_req.read() ) 4341 { 4342 r_dcache_fsm = DCACHE_CC_CHECK; 4343 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4344 break; 4345 } 4346 4238 4347 // coherence request (from CC_RECEIVE FSM) 4239 4348 if ( r_cc_receive_dcache_req.read() ) … … 4282 4391 case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction 4283 4392 { 4393 // coherence clack request (from DSPIN CLACK) 4394 if ( r_dcache_clack_req.read() ) 4395 { 4396 r_dcache_fsm = DCACHE_CC_CHECK; 4397 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4398 break; 4399 } 4400 4284 4401 // coherence request (from CC_RECEIVE FSM) 4285 4402 if ( r_cc_receive_dcache_req.read() ) … … 4374 4491 // - if the CAS is a failure, we just retry the write. 4375 4492 { 4493 // coherence clack request (from DSPIN CLACK) 4494 if ( r_dcache_clack_req.read() ) 4495 { 4496 r_dcache_fsm = DCACHE_CC_CHECK; 4497 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4498 break; 4499 } 4500 4376 4501 // coherence request (from CC_RECEIVE FSM) 4377 4502 if ( r_cc_receive_dcache_req.read() ) … … 4432 4557 #endif 4433 4558 4434 if (r_ cc_receive_dcache_type.read() == CC_TYPE_CLACK)4559 if (r_dcache_clack_req.read()) 4435 4560 // We switch the directory slot to EMPTY state 4436 4561 // and reset r_icache_miss_clack if the cleanup ack … … 4444 4569 #endif 4445 4570 r_dcache.write_dir( 0, 4446 r_ cc_receive_dcache_way.read(),4447 r_ cc_receive_dcache_set.read(),4571 r_dcache_clack_way.read(), 4572 r_dcache_clack_set.read(), 4448 4573 CACHE_SLOT_STATE_EMPTY); 4449 4574 4450 if ( (r_dcache_miss_set.read() == r_ cc_receive_dcache_set.read()) and4451 (r_dcache_miss_way.read() == r_ cc_receive_dcache_way.read()) )4575 if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and 4576 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) 4452 4577 r_dcache_miss_clack = false; 4453 4578 4454 4579 r_dcache_fsm = r_dcache_fsm_cc_save.read() ; 4455 r_ cc_receive_dcache_req = false;4580 r_dcache_clack_req = false; 4456 4581 #if DEBUG_DCACHE 4457 4582 if ( m_debug_activated ) … … 4459 4584 std::cout << " <PROC " << name() 4460 4585 << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state" 4461 << " set = " << r_ cc_receive_dcache_set.read()4462 << " / way = " << r_ cc_receive_dcache_way.read() << std::endl;4586 << " set = " << r_dcache_clack_set.read() 4587 << " / way = " << r_dcache_clack_way.read() << std::endl; 4463 4588 } 4464 4589 #endif … … 4526 4651 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4527 4652 } 4528 else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval 4653 else if ((r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) || // hit broadcast 4654 (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL )) // hit inval 4529 4655 { 4530 4656 r_dcache_fsm = DCACHE_CC_INVAL; 4531 }4532 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast4533 {4534 r_dcache_fsm = DCACHE_CC_BROADCAST;4535 4657 } 4536 4658 } … … 4565 4687 break; 4566 4688 } 4567 /////////////////////4568 case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state,4569 // after possible invalidation of copies in TLBs4570 {4571 size_t way = r_dcache_cc_way.read();4572 size_t set = r_dcache_cc_set.read();4573 4574 if (r_dcache_cc_need_write.read())4575 {4576 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval4577 {4578 r_dcache_in_tlb[way*m_dcache_sets+set] = false;4579 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();4580 r_dcache_tlb_inval_set = 0;4581 r_dcache_fsm_scan_save = r_dcache_fsm.read();4582 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;4583 break;4584 }4585 else4586 {4587 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush4588 {4589 r_itlb.reset();4590 r_dtlb.reset();4591 r_dcache_contains_ptd[way*m_dcache_sets+set] = false;4592 4593 #if DEBUG_DCACHE4594 if ( m_debug_activated )4595 {4596 std::cout << " <PROC " << name()4597 << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;4598 }4599 #endif4600 }4601 4602 r_dcache.write_dir( 0,4603 way,4604 set,4605 CACHE_SLOT_STATE_EMPTY );4606 4607 r_dcache_cc_need_write = false;4608 4609 #if DEBUG_DCACHE4610 if ( m_debug_activated )4611 {4612 std::cout << " <PROC " << name()4613 << " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec4614 << " / WAY = " << way4615 << " / SET = " << set << std::endl;4616 }4617 #endif4618 }4619 }4620 // multicast acknowledgement4621 // send a request to cc_send_fsm4622 if(not r_dcache_cc_send_req.read()) // cc_send is available4623 {4624 // coherence request completed4625 r_cc_receive_dcache_req = false;4626 // request multicast acknowledgement4627 r_dcache_cc_send_req = true;4628 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();4629 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();4630 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;4631 4632 r_dcache_fsm = r_dcache_fsm_cc_save.read();4633 }4634 //else wait for previous cc_send request to be sent4635 break;4636 }4637 4689 /////////////////// 4638 4690 case DCACHE_CC_UPDT: // hit update: write one word per cycle, … … 4729 4781 } 4730 4782 ///////////////////////// 4731 case DCACHE_CC_ BROADCAST: // hit broadcast: switch state to ZOMBI state4732 4733 4783 case DCACHE_CC_INVAL: // hit invalidate : switch state to ZOMBI state 4784 // and request a cleanup, after possible 4785 // invalidation of copies in TLBs 4734 4786 { 4735 4787 size_t way = r_dcache_cc_way.read(); … … 4760 4812 { 4761 4813 std::cout << " <PROC " << name() 4762 << " DCACHE_CC_ BROADCAST> Flush DTLB & ITLB" << std::endl;4814 << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl; 4763 4815 } 4764 4816 #endif … … 4777 4829 { 4778 4830 std::cout << " <PROC " << name() 4779 << " DCACHE_CC_ BROADCAST> Slot goes to ZOMBI state "4831 << " DCACHE_CC_INVAL > Slot goes to ZOMBI state " 4780 4832 << " SET = " << set 4781 4833 << " / WAY = " << way << std::endl; … … 5389 5441 { 5390 5442 // wait for the first flit to be consumed 5391 if (p_dspin_ out.read.read())5443 if (p_dspin_p2m.read.read()) 5392 5444 r_cc_send_fsm = CC_SEND_CLEANUP_2; 5393 5445 … … 5398 5450 { 5399 5451 // wait for the second flit to be consumed 5400 if (p_dspin_ out.read.read())5452 if (p_dspin_p2m.read.read()) 5401 5453 { 5402 5454 if (r_cc_send_last_client.read() == 0) // dcache active request … … 5414 5466 { 5415 5467 // wait for the flit to be consumed 5416 if(p_dspin_ out.read.read())5468 if(p_dspin_p2m.read.read()) 5417 5469 { 5418 5470 if(r_cc_send_last_client.read() == 0) // dcache active request … … 5445 5497 { 5446 5498 // a coherence request has arrived 5447 if (p_dspin_ in.write.read())5499 if (p_dspin_m2p.write.read()) 5448 5500 { 5449 5501 // initialize dspin received data 5450 uint64_t receive_data = p_dspin_ in.data.read();5502 uint64_t receive_data = p_dspin_m2p.data.read(); 5451 5503 // initialize coherence packet type 5452 5504 uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, … … 5458 5510 { 5459 5511 r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER; 5460 }5461 // test for a CLACK5462 else if ((receive_type == DspinDhccpParam::TYPE_CLACK_DATA) or5463 (receive_type == DspinDhccpParam::TYPE_CLACK_INST))5464 {5465 r_cc_receive_fsm = CC_RECEIVE_CLACK;5466 5512 } 5467 5513 // test for a multi updt … … 5479 5525 break; 5480 5526 } 5481 //////////////////////5482 case CC_RECEIVE_CLACK:5483 {5484 // initialize dspin received data5485 uint64_t receive_data = p_dspin_in.data.read();5486 5487 // for data CLACK, wait for dcache to take the request5488 if ((r_cc_receive_data_ins.read() == 0) and5489 not (r_cc_receive_dcache_req.read()))5490 {5491 // request dcache to handle the CLACK5492 r_cc_receive_dcache_req = true;5493 r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data,5494 DspinDhccpParam::CLACK_SET) &5495 ((1ULL<<(uint32_log2(m_dcache_sets)))-1);5496 r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data,5497 DspinDhccpParam::CLACK_WAY) &5498 ((1ULL<<(uint32_log2(m_dcache_ways)))-1);5499 r_cc_receive_dcache_type = CC_TYPE_CLACK;5500 // get back to idle state5501 r_cc_receive_fsm = CC_RECEIVE_IDLE;5502 break;5503 }5504 // for ins CLACK, wait for icache to take the request5505 if ((r_cc_receive_data_ins.read() == 1) and5506 not (r_cc_receive_icache_req.read()))5507 {5508 // request icache to handle the CLACK5509 r_cc_receive_icache_req = true;5510 r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data,5511 DspinDhccpParam::CLACK_SET) &5512 ((1ULL<<(uint32_log2(m_icache_sets)))-1);5513 r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data,5514 DspinDhccpParam::CLACK_WAY) &5515 ((1ULL<<(uint32_log2(m_icache_ways)))-1);5516 r_cc_receive_icache_type = CC_TYPE_CLACK;5517 // get back to idle state5518 r_cc_receive_fsm = CC_RECEIVE_IDLE;5519 break;5520 }5521 // keep waiting for the correct cache to accept the request5522 break;5523 }5524 5527 /////////////////////////////// 5525 5528 case CC_RECEIVE_BRDCAST_HEADER: … … 5533 5536 { 5534 5537 // initialize dspin received data 5535 uint64_t receive_data = p_dspin_ in.data.read();5538 uint64_t receive_data = p_dspin_m2p.data.read(); 5536 5539 // wait for both dcache and icache to take the request 5537 5540 // TODO maybe we need to wait for both only to leave the state, but … … 5540 5543 if (not (r_cc_receive_icache_req.read()) and 5541 5544 not (r_cc_receive_dcache_req.read()) and 5542 (p_dspin_ in.write.read()))5545 (p_dspin_m2p.write.read())) 5543 5546 { 5544 5547 // request dcache to handle the BROADCAST … … 5563 5566 { 5564 5567 // sample updt tab index in the HEADER, then skip to second flit 5565 uint64_t receive_data = p_dspin_ in.data.read();5568 uint64_t receive_data = p_dspin_m2p.data.read(); 5566 5569 // for data INVAL, wait for dcache to take the request 5567 5570 if ((r_cc_receive_data_ins.read() == 0) and … … 5589 5592 { 5590 5593 // sample nline in the second flit 5591 uint64_t receive_data = p_dspin_ in.data.read();5594 uint64_t receive_data = p_dspin_m2p.data.read(); 5592 5595 // for data INVAL, wait for dcache to take the request 5593 5596 if ( (r_cc_receive_data_ins.read() == 0) and 5594 5597 not (r_cc_receive_dcache_req.read()) and 5595 (p_dspin_ in.write.read()) )5598 (p_dspin_m2p.write.read()) ) 5596 5599 { 5597 5600 // request dcache to handle the INVAL … … 5604 5607 } 5605 5608 // for ins INVAL, wait for icache to take the request 5606 if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_ in.write.read()))5609 if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read())) 5607 5610 { 5608 5611 // request icache to handle the INVAL … … 5621 5624 { 5622 5625 // sample updt tab index in the HEADER, than skip to second flit 5623 uint64_t receive_data = p_dspin_ in.data.read();5626 uint64_t receive_data = p_dspin_m2p.data.read(); 5624 5627 // for data INVAL, wait for dcache to take the request and fifo to 5625 5628 // be empty … … 5645 5648 { 5646 5649 // sample nline and word index in the second flit 5647 uint64_t receive_data = p_dspin_ in.data.read();5650 uint64_t receive_data = p_dspin_m2p.data.read(); 5648 5651 // for data INVAL, wait for dcache to take the request and fifo to 5649 5652 // be empty … … 5651 5654 not (r_cc_receive_dcache_req.read()) and 5652 5655 r_cc_receive_updt_fifo_be.empty() and 5653 (p_dspin_ in.write.read()) )5656 (p_dspin_m2p.write.read()) ) 5654 5657 { 5655 5658 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); … … 5665 5668 not (r_cc_receive_icache_req.read()) and 5666 5669 r_cc_receive_updt_fifo_be.empty() and 5667 (p_dspin_ in.write.read()))5670 (p_dspin_m2p.write.read())) 5668 5671 { 5669 5672 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); … … 5681 5684 case CC_RECEIVE_UPDT_DATA: 5682 5685 { 5683 if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_ in.write.read()))5686 if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_m2p.write.read())) 5684 5687 r_cc_receive_dcache_req = true; 5685 if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_ in.write.read()))5688 if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read())) 5686 5689 r_cc_receive_icache_req = true; 5687 5690 5688 5691 // wait for the fifo 5689 if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_ in.write.read()))5690 { 5691 uint64_t receive_data = p_dspin_ in.data.read();5692 bool receive_eop = p_dspin_ in.eop.read();5692 if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) 5693 { 5694 uint64_t receive_data = p_dspin_m2p.data.read(); 5695 bool receive_eop = p_dspin_m2p.eop.read(); 5693 5696 cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); 5694 5697 cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); … … 5700 5703 } 5701 5704 } // end switch CC_RECEIVE FSM 5705 5706 ///////////////// DSPIN CLACK interface /////////////// 5707 5708 uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 5709 DspinDhccpParam::CLACK_TYPE); 5710 5711 size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 5712 DspinDhccpParam::CLACK_WAY); 5713 5714 size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 5715 DspinDhccpParam::CLACK_SET); 5716 5717 bool dspin_clack_get = false; 5718 bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); 5719 bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); 5720 5721 if (r_dspin_clack_req.read()) 5722 { 5723 // CLACK DATA: Send request to DCACHE FSM 5724 if (dcache_clack_request and not r_dcache_clack_req.read()){ 5725 r_dcache_clack_req = true; 5726 r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); 5727 r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); 5728 dspin_clack_get = true; 5729 } 5730 5731 // CLACK INST: Send request to ICACHE FSM 5732 else if (icache_clack_request and not r_icache_clack_req.read()){ 5733 r_icache_clack_req = true; 5734 r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); 5735 r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1); 5736 dspin_clack_get = true; 5737 } 5738 } 5739 else 5740 { 5741 dspin_clack_get = true; 5742 } 5743 5744 if (dspin_clack_get) 5745 { 5746 r_dspin_clack_req = p_dspin_clack.write.read(); 5747 r_dspin_clack_flit = p_dspin_clack.data.read(); 5748 } 5702 5749 5703 5750 ///////////////// Response FIFOs update ////////////////////// … … 5897 5944 case CC_SEND_IDLE: 5898 5945 { 5899 p_dspin_ out.write = false;5946 p_dspin_p2m.write = false; 5900 5947 break; 5901 5948 } … … 5959 6006 } 5960 6007 // send flit 5961 p_dspin_ out.data = dspin_send_data;5962 p_dspin_ out.write = true;5963 p_dspin_ out.eop = false;6008 p_dspin_p2m.data = dspin_send_data; 6009 p_dspin_p2m.write = true; 6010 p_dspin_p2m.eop = false; 5964 6011 break; 5965 6012 } … … 5985 6032 } 5986 6033 // send flit 5987 p_dspin_ out.data = dspin_send_data;5988 p_dspin_ out.write = true;5989 p_dspin_ out.eop = true;6034 p_dspin_p2m.data = dspin_send_data; 6035 p_dspin_p2m.write = true; 6036 p_dspin_p2m.eop = true; 5990 6037 break; 5991 6038 } … … 6034 6081 } 6035 6082 // send flit 6036 p_dspin_ out.data = dspin_send_data;6037 p_dspin_ out.write = true;6038 p_dspin_ out.eop = true;6083 p_dspin_p2m.data = dspin_send_data; 6084 p_dspin_p2m.write = true; 6085 p_dspin_p2m.eop = true; 6039 6086 6040 6087 break; … … 6050 6097 case CC_RECEIVE_IDLE: 6051 6098 { 6052 p_dspin_ in.read = false;6099 p_dspin_m2p.read = false; 6053 6100 break; 6054 6101 } … … 6058 6105 if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or 6059 6106 ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) 6060 p_dspin_ in.read = true;6107 p_dspin_m2p.read = true; 6061 6108 else 6062 p_dspin_ in.read = false;6109 p_dspin_m2p.read = false; 6063 6110 break; 6064 6111 } … … 6066 6113 case CC_RECEIVE_BRDCAST_HEADER: 6067 6114 { 6068 p_dspin_ in.read = true;6115 p_dspin_m2p.read = true; 6069 6116 break; 6070 6117 } … … 6076 6123 // flip_flop to check that ? 6077 6124 if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read())) 6078 p_dspin_ in.read = true;6125 p_dspin_m2p.read = true; 6079 6126 else 6080 p_dspin_ in.read = false;6127 p_dspin_m2p.read = false; 6081 6128 break; 6082 6129 } … … 6086 6133 if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or 6087 6134 ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) 6088 p_dspin_ in.read = true;6135 p_dspin_m2p.read = true; 6089 6136 else 6090 p_dspin_ in.read = false;6137 p_dspin_m2p.read = false; 6091 6138 break; 6092 6139 } … … 6094 6141 case CC_RECEIVE_INVAL_NLINE: 6095 6142 { 6096 p_dspin_ in.read = true;6143 p_dspin_m2p.read = true; 6097 6144 break; 6098 6145 } … … 6107 6154 not r_cc_receive_icache_req.read()) and 6108 6155 r_cc_receive_updt_fifo_be.empty())) 6109 p_dspin_ in.read = true;6156 p_dspin_m2p.read = true; 6110 6157 else 6111 p_dspin_ in.read = false;6158 p_dspin_m2p.read = false; 6112 6159 break; 6113 6160 } … … 6122 6169 not (r_cc_receive_icache_req.read()) and 6123 6170 r_cc_receive_updt_fifo_be.empty())) 6124 p_dspin_ in.read = true;6171 p_dspin_m2p.read = true; 6125 6172 else 6126 p_dspin_ in.read = false;6173 p_dspin_m2p.read = false; 6127 6174 break; 6128 6175 } … … 6131 6178 { 6132 6179 if (r_cc_receive_updt_fifo_be.wok()) 6133 p_dspin_ in.read = true;6180 p_dspin_m2p.read = true; 6134 6181 else 6135 p_dspin_ in.read = false;6182 p_dspin_m2p.read = false; 6136 6183 break; 6137 6184 } 6138 6185 } // end switch CC_RECEIVE FSM 6139 6186 6187 int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6188 DspinDhccpParam::CLACK_TYPE); 6189 6190 bool dspin_clack_get = false; 6191 bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); 6192 bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); 6193 6194 if (r_dspin_clack_req.read()) 6195 { 6196 // CLACK DATA: wait if pending request to DCACHE FSM 6197 if (dcache_clack_request and not r_dcache_clack_req.read()) 6198 { 6199 dspin_clack_get = true; 6200 } 6201 6202 // CLACK INST: wait if pending request to ICACHE FSM 6203 else if (icache_clack_request and not r_icache_clack_req.read()) 6204 { 6205 dspin_clack_get = true; 6206 } 6207 } 6208 else 6209 { 6210 dspin_clack_get = true; 6211 } 6212 6213 p_dspin_clack.read = dspin_clack_get; 6140 6214 } // end genMoore 6141 6215
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