Index: /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 445) +++ /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 446) @@ -89,7 +89,6 @@ // handling coherence requests ICACHE_CC_CHECK, + ICACHE_CC_UPDT, ICACHE_CC_INVAL, - ICACHE_CC_UPDT, - ICACHE_CC_BROADCAST, ICACHE_CC_SEND_WAIT, }; @@ -138,7 +137,6 @@ // handling coherence requests DCACHE_CC_CHECK, + DCACHE_CC_UPDT, DCACHE_CC_INVAL, - DCACHE_CC_UPDT, - DCACHE_CC_BROADCAST, DCACHE_CC_SEND_WAIT, // handling TLB inval (after a coherence or XTN request) @@ -285,10 +283,11 @@ public: - sc_in p_clk; - sc_in p_resetn; - sc_in p_irq[iss_t::n_irq]; - soclib::caba::VciInitiator p_vci; - soclib::caba::DspinInput p_dspin_in; - soclib::caba::DspinOutput p_dspin_out; + sc_in p_clk; + sc_in p_resetn; + sc_in p_irq[iss_t::n_irq]; + soclib::caba::VciInitiator p_vci; + soclib::caba::DspinInput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_p2m; + soclib::caba::DspinInput p_dspin_clack; private: @@ -371,4 +370,9 @@ sc_signal r_icache_cc_need_write; // activate the cache for writing + // coherence clack handling + sc_signal r_icache_clack_req; // clack request + sc_signal r_icache_clack_way; // clack way + sc_signal r_icache_clack_set; // clack set + // icache flush handling sc_signal r_icache_flush_count; // slot counter used for cache flush @@ -444,4 +448,9 @@ sc_signal r_dcache_cc_need_write; // activate the cache for writing + // coherence clack handling + sc_signal r_dcache_clack_req; // clack request + sc_signal r_dcache_clack_way; // clack way + sc_signal r_dcache_clack_set; // clack set + // dcache flush handling sc_signal r_dcache_flush_count; // slot counter used for cache flush @@ -537,4 +546,10 @@ sc_signal r_cc_receive_dcache_nline; // cache line physical address + /////////////////////////////////// + // DSPIN CLACK INTERFACE REGISTER + /////////////////////////////////// + sc_signal r_dspin_clack_req; + sc_signal r_dspin_clack_flit; + ////////////////////////////////////////////////////////////////// // processor, write buffer, caches , TLBs Index: /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 445) +++ /branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 446) @@ -62,7 +62,6 @@ "ICACHE_CC_CHECK", + "ICACHE_CC_UPDT", "ICACHE_CC_INVAL", - "ICACHE_CC_UPDT", - "ICACHE_CC_BROADCAST", "ICACHE_CC_SEND_WAIT", }; @@ -110,7 +109,6 @@ "DCACHE_CC_CHECK", + "DCACHE_CC_UPDT", "DCACHE_CC_INVAL", - "DCACHE_CC_UPDT", - "DCACHE_CC_BROADCAST", "DCACHE_CC_SEND_WAIT", @@ -216,6 +214,7 @@ p_resetn("p_resetn"), p_vci("p_vci"), - p_dspin_in("p_dspin_in"), - p_dspin_out("p_dspin_out"), + p_dspin_m2p("p_dspin_m2p"), + p_dspin_p2m("p_dspin_p2m"), + p_dspin_clack("p_dspin_clack"), m_cacheability_table( mtd.getCacheabilityTable() ), @@ -755,4 +754,6 @@ r_icache_cc_send_req = false; + r_icache_clack_req = false; + // No pending write in pipeline r_dcache_wbuf_req = false; @@ -775,4 +776,6 @@ r_dcache_cc_send_req = false; + r_dcache_clack_req = false; + // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs r_cc_receive_icache_req = false; @@ -789,4 +792,6 @@ r_icache_miss_inval = false; r_dcache_miss_inval = false; + + r_dspin_clack_req = false; // No signalisation of errors @@ -1014,4 +1019,12 @@ // 5/ uncacheable read miss => ICACHE_UNC_REQ { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1242,4 +1255,12 @@ // external coherence request are accepted in this state. { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1286,4 +1307,12 @@ // A cleanup request is generated for each valid line { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_icache_req.read() ) @@ -1484,4 +1513,12 @@ { if (m_ireq.valid) m_cost_ins_miss_frz++; + + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } // coherence interrupt @@ -1574,4 +1611,12 @@ if (m_ireq.valid) m_cost_ins_miss_frz++; + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1645,4 +1690,12 @@ if ( m_ireq.valid ) m_cost_ins_miss_frz++; + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1716,4 +1769,12 @@ case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + // coherence interrupt if ( r_cc_receive_icache_req.read() ) @@ -1756,5 +1817,5 @@ paddr_t mask = ~((m_icache_words<<2)-1); - if (r_cc_receive_icache_type.read() == CC_TYPE_CLACK) + if (r_icache_clack_req.read()) // We switch the directory slot to EMPTY state // and reset r_icache_miss_clack if the cleanup ack @@ -1768,14 +1829,14 @@ #endif r_icache.write_dir( 0, - r_cc_receive_icache_way.read(), - r_cc_receive_icache_set.read(), + r_icache_clack_way.read(), + r_icache_clack_set.read(), CACHE_SLOT_STATE_EMPTY); - if ( (r_icache_miss_set.read() == r_cc_receive_icache_set.read()) and - (r_icache_miss_way.read() == r_cc_receive_icache_way.read()) ) + if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and + (r_icache_miss_way.read() == r_icache_clack_way.read()) ) r_icache_miss_clack = false; r_icache_fsm = r_icache_fsm_save.read() ; - r_cc_receive_icache_req = false; + r_icache_clack_req = false; #if DEBUG_ICACHE @@ -1784,6 +1845,6 @@ std::cout << " CC_TYPE_CLACK slot returns to empty state" - << " set = " << r_cc_receive_icache_set.read() - << " / way = " << r_cc_receive_icache_way.read() << std::endl; + << " set = " << r_icache_clack_set.read() + << " / way = " << r_icache_clack_way.read() << std::endl; } #endif @@ -1840,5 +1901,5 @@ r_icache_cc_set = set; - if ( state == CACHE_SLOT_STATE_VALID) // hit + if (state == CACHE_SLOT_STATE_VALID) // hit { // need to update the cache state @@ -1849,11 +1910,8 @@ r_icache_cc_word = r_cc_receive_word_idx.read(); } - else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval + else if ((r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) || // hit inval + (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST)) // hit broadcast { r_icache_fsm = ICACHE_CC_INVAL; - } - else if (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST) // hit broadcast - { - r_icache_fsm = ICACHE_CC_BROADCAST; } } @@ -1875,48 +1933,4 @@ } } - break; - } - ///////////////////// - case ICACHE_CC_INVAL: // hit inval : switch slot to EMPTY state - { - -#if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " slot returns to empty state" - << " set = " << r_icache_cc_set.read() - << " / way = " << r_icache_cc_way.read() << std::endl; -} -#endif - -#ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; -#endif - if (r_icache_cc_need_write.read()) - { - r_icache.write_dir( 0, - r_icache_cc_way.read(), - r_icache_cc_set.read(), - CACHE_SLOT_STATE_EMPTY ); - // no need to write in the cache anymore - r_icache_cc_need_write = false; - } - - // multicast acknowledgement - // send a request to cc_send_fsm - if(not r_icache_cc_send_req.read()) // cc_send is available - { - // coherence request completed - r_cc_receive_icache_req = false; - // request multicast acknowledgement - r_icache_cc_send_req = true; - r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); - r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); - r_icache_cc_send_type = CC_TYPE_MULTI_ACK; - - r_icache_fsm = r_icache_fsm_save.read(); - } - //else wait for previous cc_send request to be sent break; } @@ -1984,6 +1998,6 @@ } ///////////////////////// - case ICACHE_CC_BROADCAST: // hit broadcast : switch slot to ZOMBI state - // and request a cleanup + case ICACHE_CC_INVAL: // hit invalidate : switch slot to ZOMBI state + // and request a cleanup { @@ -1992,5 +2006,5 @@ { std::cout << " Slot goes to zombi state " + << " ICACHE_CC_INVAL > Slot goes to zombi state " << " set = " << r_icache_cc_set.read() << " / way = " << r_icache_cc_way.read() << std::endl; @@ -2308,4 +2322,10 @@ } + // coherence clack request (from DSPIN CLACK) + else if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + } // coherence request (from CC_RECEIVE FSM) else if ( r_cc_receive_dcache_req.read() ) @@ -2912,4 +2932,12 @@ case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3209,4 +3237,12 @@ case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3506,4 +3542,12 @@ { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3577,4 +3621,12 @@ // as there is a risk of dead-lock { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3582,4 +3634,5 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; } @@ -3598,4 +3651,12 @@ // and because it can exist a simultaneous ITLB miss { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3633,4 +3694,12 @@ // returns to IDLE and flush TLBs when last slot { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -3893,4 +3962,12 @@ { if ( m_dreq.valid) m_cost_data_miss_frz++; + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } // coherence request (from CC_RECEIVE FSM) @@ -4009,4 +4086,12 @@ { if ( m_dreq.valid) m_cost_data_miss_frz++; + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } // coherence request (from CC_RECEIVE FSM) @@ -4125,4 +4210,12 @@ if ( m_dreq.valid) m_cost_data_miss_frz++; + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4199,4 +4292,12 @@ case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4236,4 +4337,12 @@ case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4282,4 +4391,12 @@ case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4374,4 +4491,12 @@ // - if the CAS is a failure, we just retry the write. { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + // coherence request (from CC_RECEIVE FSM) if ( r_cc_receive_dcache_req.read() ) @@ -4432,5 +4557,5 @@ #endif - if (r_cc_receive_dcache_type.read() == CC_TYPE_CLACK) + if (r_dcache_clack_req.read()) // We switch the directory slot to EMPTY state // and reset r_icache_miss_clack if the cleanup ack @@ -4444,14 +4569,14 @@ #endif r_dcache.write_dir( 0, - r_cc_receive_dcache_way.read(), - r_cc_receive_dcache_set.read(), + r_dcache_clack_way.read(), + r_dcache_clack_set.read(), CACHE_SLOT_STATE_EMPTY); - if ( (r_dcache_miss_set.read() == r_cc_receive_dcache_set.read()) and - (r_dcache_miss_way.read() == r_cc_receive_dcache_way.read()) ) + if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and + (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) r_dcache_miss_clack = false; r_dcache_fsm = r_dcache_fsm_cc_save.read() ; - r_cc_receive_dcache_req = false; + r_dcache_clack_req = false; #if DEBUG_DCACHE if ( m_debug_activated ) @@ -4459,6 +4584,6 @@ std::cout << " CC_TYPE_CLACK Switch slot to EMPTY state" - << " set = " << r_cc_receive_dcache_set.read() - << " / way = " << r_cc_receive_dcache_way.read() << std::endl; + << " set = " << r_dcache_clack_set.read() + << " / way = " << r_dcache_clack_way.read() << std::endl; } #endif @@ -4526,11 +4651,8 @@ r_dcache_cc_word = r_cc_receive_word_idx.read(); } - else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval + else if ((r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) || // hit broadcast + (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL )) // hit inval { r_dcache_fsm = DCACHE_CC_INVAL; - } - else if ( r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit broadcast - { - r_dcache_fsm = DCACHE_CC_BROADCAST; } } @@ -4565,74 +4687,4 @@ break; } - ///////////////////// - case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state, - // after possible invalidation of copies in TLBs - { - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - - if (r_dcache_cc_need_write.read()) - { - if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval - { - r_dcache_in_tlb[way*m_dcache_sets+set] = false; - r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = r_dcache_fsm.read(); - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - break; - } - else - { - if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush - { - r_itlb.reset(); - r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; - -#if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Flush DTLB & ITLB" << std::endl; -} -#endif - } - - r_dcache.write_dir( 0, - way, - set, - CACHE_SLOT_STATE_EMPTY ); - - r_dcache_cc_need_write = false; - -#if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Switch slot to EMPTY state:" << std::dec - << " / WAY = " << way - << " / SET = " << set << std::endl; -} -#endif - } - } - // multicast acknowledgement - // send a request to cc_send_fsm - if(not r_dcache_cc_send_req.read()) // cc_send is available - { - // coherence request completed - r_cc_receive_dcache_req = false; - // request multicast acknowledgement - r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); - r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); - r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; - - r_dcache_fsm = r_dcache_fsm_cc_save.read(); - } - //else wait for previous cc_send request to be sent - break; - } /////////////////// case DCACHE_CC_UPDT: // hit update: write one word per cycle, @@ -4729,7 +4781,7 @@ } ///////////////////////// - case DCACHE_CC_BROADCAST: // hit broadcast : switch state to ZOMBI state - // and request a cleanup, after possible - // invalidation of copies in TLBs + case DCACHE_CC_INVAL: // hit invalidate : switch state to ZOMBI state + // and request a cleanup, after possible + // invalidation of copies in TLBs { size_t way = r_dcache_cc_way.read(); @@ -4760,5 +4812,5 @@ { std::cout << " Flush DTLB & ITLB" << std::endl; + << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl; } #endif @@ -4777,5 +4829,5 @@ { std::cout << " Slot goes to ZOMBI state " + << " DCACHE_CC_INVAL > Slot goes to ZOMBI state " << " SET = " << set << " / WAY = " << way << std::endl; @@ -5389,5 +5441,5 @@ { // wait for the first flit to be consumed - if (p_dspin_out.read.read()) + if (p_dspin_p2m.read.read()) r_cc_send_fsm = CC_SEND_CLEANUP_2; @@ -5398,5 +5450,5 @@ { // wait for the second flit to be consumed - if (p_dspin_out.read.read()) + if (p_dspin_p2m.read.read()) { if (r_cc_send_last_client.read() == 0) // dcache active request @@ -5414,5 +5466,5 @@ { // wait for the flit to be consumed - if(p_dspin_out.read.read()) + if(p_dspin_p2m.read.read()) { if(r_cc_send_last_client.read() == 0) // dcache active request @@ -5445,8 +5497,8 @@ { // a coherence request has arrived - if (p_dspin_in.write.read()) + if (p_dspin_m2p.write.read()) { // initialize dspin received data - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // initialize coherence packet type uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, @@ -5458,10 +5510,4 @@ { r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER; - } - // test for a CLACK - else if ((receive_type == DspinDhccpParam::TYPE_CLACK_DATA) or - (receive_type == DspinDhccpParam::TYPE_CLACK_INST)) - { - r_cc_receive_fsm = CC_RECEIVE_CLACK; } // test for a multi updt @@ -5479,47 +5525,4 @@ break; } - ////////////////////// - case CC_RECEIVE_CLACK: - { - // initialize dspin received data - uint64_t receive_data = p_dspin_in.data.read(); - - // for data CLACK, wait for dcache to take the request - if ((r_cc_receive_data_ins.read() == 0) and - not (r_cc_receive_dcache_req.read())) - { - // request dcache to handle the CLACK - r_cc_receive_dcache_req = true; - r_cc_receive_dcache_set = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::CLACK_SET) & - ((1ULL<<(uint32_log2(m_dcache_sets)))-1); - r_cc_receive_dcache_way = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::CLACK_WAY) & - ((1ULL<<(uint32_log2(m_dcache_ways)))-1); - r_cc_receive_dcache_type = CC_TYPE_CLACK; - // get back to idle state - r_cc_receive_fsm = CC_RECEIVE_IDLE; - break; - } - // for ins CLACK, wait for icache to take the request - if ((r_cc_receive_data_ins.read() == 1) and - not (r_cc_receive_icache_req.read())) - { - // request icache to handle the CLACK - r_cc_receive_icache_req = true; - r_cc_receive_icache_set = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::CLACK_SET) & - ((1ULL<<(uint32_log2(m_icache_sets)))-1); - r_cc_receive_icache_way = DspinDhccpParam::dspin_get(receive_data, - DspinDhccpParam::CLACK_WAY) & - ((1ULL<<(uint32_log2(m_icache_ways)))-1); - r_cc_receive_icache_type = CC_TYPE_CLACK; - // get back to idle state - r_cc_receive_fsm = CC_RECEIVE_IDLE; - break; - } - // keep waiting for the correct cache to accept the request - break; - } /////////////////////////////// case CC_RECEIVE_BRDCAST_HEADER: @@ -5533,5 +5536,5 @@ { // initialize dspin received data - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // wait for both dcache and icache to take the request // TODO maybe we need to wait for both only to leave the state, but @@ -5540,5 +5543,5 @@ if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and - (p_dspin_in.write.read())) + (p_dspin_m2p.write.read())) { // request dcache to handle the BROADCAST @@ -5563,5 +5566,5 @@ { // sample updt tab index in the HEADER, then skip to second flit - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request if ((r_cc_receive_data_ins.read() == 0) and @@ -5589,9 +5592,9 @@ { // sample nline in the second flit - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request if ( (r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and - (p_dspin_in.write.read()) ) + (p_dspin_m2p.write.read()) ) { // request dcache to handle the INVAL @@ -5604,5 +5607,5 @@ } // for ins INVAL, wait for icache to take the request - if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read())) + if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read())) { // request icache to handle the INVAL @@ -5621,5 +5624,5 @@ { // sample updt tab index in the HEADER, than skip to second flit - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request and fifo to // be empty @@ -5645,5 +5648,5 @@ { // sample nline and word index in the second flit - uint64_t receive_data = p_dspin_in.data.read(); + uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request and fifo to // be empty @@ -5651,5 +5654,5 @@ not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and - (p_dspin_in.write.read()) ) + (p_dspin_m2p.write.read()) ) { r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); @@ -5665,5 +5668,5 @@ not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and - (p_dspin_in.write.read())) + (p_dspin_m2p.write.read())) { r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); @@ -5681,14 +5684,14 @@ case CC_RECEIVE_UPDT_DATA: { - if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read())) + if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_m2p.write.read())) r_cc_receive_dcache_req = true; - if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read())) + if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read())) r_cc_receive_icache_req = true; // wait for the fifo - if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read())) - { - uint64_t receive_data = p_dspin_in.data.read(); - bool receive_eop = p_dspin_in.eop.read(); + if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) + { + uint64_t receive_data = p_dspin_m2p.data.read(); + bool receive_eop = p_dspin_m2p.eop.read(); cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); @@ -5700,4 +5703,48 @@ } } // end switch CC_RECEIVE FSM + + ///////////////// DSPIN CLACK interface /////////////// + + uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_TYPE); + + size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_WAY); + + size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_SET); + + bool dspin_clack_get = false; + bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); + bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); + + if (r_dspin_clack_req.read()) + { + // CLACK DATA: Send request to DCACHE FSM + if (dcache_clack_request and not r_dcache_clack_req.read()){ + r_dcache_clack_req = true; + r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); + r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); + dspin_clack_get = true; + } + + // CLACK INST: Send request to ICACHE FSM + else if (icache_clack_request and not r_icache_clack_req.read()){ + r_icache_clack_req = true; + r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); + r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1); + dspin_clack_get = true; + } + } + else + { + dspin_clack_get = true; + } + + if (dspin_clack_get) + { + r_dspin_clack_req = p_dspin_clack.write.read(); + r_dspin_clack_flit = p_dspin_clack.data.read(); + } ///////////////// Response FIFOs update ////////////////////// @@ -5897,5 +5944,5 @@ case CC_SEND_IDLE: { - p_dspin_out.write = false; + p_dspin_p2m.write = false; break; } @@ -5959,7 +6006,7 @@ } // send flit - p_dspin_out.data = dspin_send_data; - p_dspin_out.write = true; - p_dspin_out.eop = false; + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = false; break; } @@ -5985,7 +6032,7 @@ } // send flit - p_dspin_out.data = dspin_send_data; - p_dspin_out.write = true; - p_dspin_out.eop = true; + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = true; break; } @@ -6034,7 +6081,7 @@ } // send flit - p_dspin_out.data = dspin_send_data; - p_dspin_out.write = true; - p_dspin_out.eop = true; + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = true; break; @@ -6050,5 +6097,5 @@ case CC_RECEIVE_IDLE: { - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } @@ -6058,7 +6105,7 @@ if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) - p_dspin_in.read = true; + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } @@ -6066,5 +6113,5 @@ case CC_RECEIVE_BRDCAST_HEADER: { - p_dspin_in.read = true; + p_dspin_m2p.read = true; break; } @@ -6076,7 +6123,7 @@ // flip_flop to check that ? if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read())) - p_dspin_in.read = true; + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } @@ -6086,7 +6133,7 @@ if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) - p_dspin_in.read = true; + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } @@ -6094,5 +6141,5 @@ case CC_RECEIVE_INVAL_NLINE: { - p_dspin_in.read = true; + p_dspin_m2p.read = true; break; } @@ -6107,7 +6154,7 @@ not r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())) - p_dspin_in.read = true; + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } @@ -6122,7 +6169,7 @@ not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())) - p_dspin_in.read = true; + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } @@ -6131,11 +6178,38 @@ { if (r_cc_receive_updt_fifo_be.wok()) - p_dspin_in.read = true; + p_dspin_m2p.read = true; else - p_dspin_in.read = false; + p_dspin_m2p.read = false; break; } } // end switch CC_RECEIVE FSM + int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_TYPE); + + bool dspin_clack_get = false; + bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); + bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); + + if (r_dspin_clack_req.read()) + { + // CLACK DATA: wait if pending request to DCACHE FSM + if (dcache_clack_request and not r_dcache_clack_req.read()) + { + dspin_clack_get = true; + } + + // CLACK INST: wait if pending request to ICACHE FSM + else if (icache_clack_request and not r_icache_clack_req.read()) + { + dspin_clack_get = true; + } + } + else + { + dspin_clack_get = true; + } + + p_dspin_clack.read = dspin_clack_get; } // end genMoore