Index: /branches/v5/platforms/tsar_generic_xbar/Makefile
===================================================================
--- /branches/v5/platforms/tsar_generic_xbar/Makefile	(revision 447)
+++ /branches/v5/platforms/tsar_generic_xbar/Makefile	(revision 447)
@@ -0,0 +1,6 @@
+simul.x: top.cpp top.desc
+	soclib-cc -P -p top.desc -I. -o simul.x
+
+clean:
+	soclib-cc -x -p top.desc -I.
+	rm -rf *.o *.x term*
Index: /branches/v5/platforms/tsar_generic_xbar/soclib.conf
===================================================================
--- /branches/v5/platforms/tsar_generic_xbar/soclib.conf	(revision 447)
+++ /branches/v5/platforms/tsar_generic_xbar/soclib.conf	(revision 447)
@@ -0,0 +1,2 @@
+
+config.addDescPath("/Users/alain/soc/tsar-trunk-svn-2013/")
Index: /branches/v5/platforms/tsar_generic_xbar/top.cpp
===================================================================
--- /branches/v5/platforms/tsar_generic_xbar/top.cpp	(revision 447)
+++ /branches/v5/platforms/tsar_generic_xbar/top.cpp	(revision 447)
@@ -0,0 +1,860 @@
+/////////////////////////////////////////////////////////////////////////
+// File: top.cpp 
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : may 2013
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture.
+// The physical address space is 40 bits.
+//
+// The number of clusters cannot be larger than 256.
+// The number of processors per cluster cannot be larger than 8.
+// 
+// - It uses four dspin_local_crossbar per cluster as local interconnect 
+// - It uses two virtual_dspin routers per cluster as global interconnect
+// - It uses the vci_cc_vcache_wrapper 
+// - It uses the vci_mem_cache
+// - It contains one vci_xicu per cluster.
+// - It contains one vci_multi_dma per cluster.
+// - It contains one vci_simple_ram per cluster to model the L3 cache.
+//
+// The communication between the MemCache and the Xram is 64 bits.
+//
+// All clusters are identical, but the cluster 0 (called io_cluster), 
+// contains 5 extra components:
+// - the boot rom (BROM)
+// - the disk controller (BDEV)
+// - the multi-channel network controller (MNIC)
+// - the multi-channel tty controller (MTTY)
+// - the frame buffer controller (FBUF)
+//
+// It is build with one single component implementing a cluster,
+// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd)
+//
+// The IRQs are connected to XICUs as follow:
+// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
+// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
+// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
+// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
+// 
+// Some hardware parameters are used when compiling the OS, and are used 
+// by this top.cpp file. They must be defined in the hard_config.h file :
+// - CLUSTER_X        : number of clusters in a row (power of 2)
+// - CLUSTER_Y        : number of clusters in a column (power of 2)
+// - CLUSTER_SIZE     : size of the segment allocated to a cluster
+// - NB_PROCS_MAX     : number of processors per cluster (power of 2)
+// - NB_DMA_CHANNELS  : number of DMA channels per cluster (< 9)
+// - NB_TTY_CHANNELS  : number of TTY channels in I/O cluster (< 16)
+// - NB_NIC_CHANNELS  : number of NIC channels in I/O cluster (< 9)
+// 
+// Some other hardware parameters are not used when compiling the OS,
+// and can be directly defined in this top.cpp file:
+// - XRAM_LATENCY     : external ram latency 
+// - MEMC_WAYS        : L2 cache number of ways
+// - MEMC_SETS        : L2 cache number of sets
+// - L1_IWAYS     
+// - L1_ISETS    
+// - L1_DWAYS   
+// - L1_DSETS  
+// - FBUF_X_SIZE      : width of frame buffer (pixels)
+// - FBUF_Y_SIZE      : heigth of frame buffer (lines)
+// - BDEV_SECTOR_SIZE : block size for block drvice
+// - BDEV_IMAGE_NAME  : file pathname for block device 
+// - NIC_RX_NAME      : file pathname for NIC received packets
+// - NIC_TX_NAME      : file pathname for NIC transmited packets
+// - NIC_TIMEOUT      : max number of cycles before closing a container
+/////////////////////////////////////////////////////////////////////////
+// General policy for 40 bits physical address decoding:
+// All physical segments base addresses are multiple of 1 Mbytes
+// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) 
+// The (x_width + y_width) MSB bits (left aligned) define
+// the cluster index, and the LADR bits define the local index:
+//      | X_ID  | Y_ID  |---| LADR |     OFFSET          |
+//      |x_width|y_width|---|  8   |       24            |
+/////////////////////////////////////////////////////////////////////////
+// General policy for 14 bits SRCID decoding:
+// Each component is identified by (x_id, y_id, l_id) tuple.
+//      | X_ID  | Y_ID  |---| L_ID |
+//      |x_width|y_width|---|  6   |
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "tsar_xbar_cluster.h"
+#include "alloc_elems.h"
+
+///////////////////////////////////////////////////
+//      OS
+///////////////////////////////////////////////////
+#define USE_ALMOS 0
+
+#define almos_bootloader_pathname "bootloader.bin"
+#define almos_kernel_pathname     "kernel-soclib.bin@0xbfc10000:D"
+#define almos_archinfo_pathname   "arch-info.bin@0xBFC08000:D"
+
+///////////////////////////////////////////////////
+//               Parallelisation
+///////////////////////////////////////////////////
+#define USE_OPENMP               0
+
+#if USE_OPENMP
+#include <omp.h>
+#endif
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)   (y + YMAX*x)
+
+///////////////////////////////////////////////////////////
+//          DSPIN parameters           
+///////////////////////////////////////////////////////////
+
+#define dspin_cmd_width      39
+#define dspin_rsp_width      32
+
+///////////////////////////////////////////////////////////
+//          VCI parameters           
+///////////////////////////////////////////////////////////
+
+#define vci_cell_width_int    4
+#define vci_cell_width_ext    8
+
+#define vci_plen_width        8
+#define vci_address_width     40
+#define vci_rerror_width      1
+#define vci_clen_width        1
+#define vci_rflag_width       1
+#define vci_srcid_width       14
+#define vci_pktid_width       4
+#define vci_trdid_width       4
+#define vci_wrplen_width      1
+
+////////////////////////////////////////////////////////////
+//    Main Hardware Parameters values         
+//////////////////////i/////////////////////////////////////
+
+#include "hard_config.h"
+
+////////////////////////////////////////////////////////////
+//    Secondary Hardware Parameters         
+//////////////////////i/////////////////////////////////////
+
+#define XMAX                  CLUSTER_X
+#define YMAX                  CLUSTER_Y
+
+#define XRAM_LATENCY          0
+
+#define MEMC_WAYS             16
+#define MEMC_SETS             256
+
+#define L1_IWAYS              4
+#define L1_ISETS              64
+
+#define L1_DWAYS              4
+#define L1_DSETS              64
+
+#define FBUF_X_SIZE           128
+#define FBUF_Y_SIZE           128
+
+#define BDEV_SECTOR_SIZE      512
+#define BDEV_IMAGE_NAME       "images.raw"
+
+#define NIC_RX_NAME           "giet_vm/nic/rx_packets.txt"
+#define NIC_TX_NAME           "giet_vm/nic/tx_packets.txt"
+#define NIC_TIMEOUT           10000
+
+#define NORTH                 0
+#define SOUTH                 1
+#define EAST                  2
+#define WEST                  3
+
+////////////////////////////////////////////////////////////
+//    Software to be loaded in ROM & RAM         
+//////////////////////i/////////////////////////////////////
+
+#define SOFT_NAME             "soft.elf"
+
+////////////////////////////////////////////////////////////
+//     DEBUG Parameters default values         
+//////////////////////i/////////////////////////////////////
+
+#define MAX_FROZEN_CYCLES     10000
+
+/////////////////////////////////////////////////////////
+//    Physical segments definition
+/////////////////////////////////////////////////////////
+// There is 3 segments replicated in all clusters
+// and 5 specific segments in the "IO" cluster 
+// (containing address 0xBF000000)
+/////////////////////////////////////////////////////////
+
+// specific segments in "IO" cluster : absolute physical address
+
+#define BROM_BASE       0x00BFC00000      
+#define BROM_SIZE       0x0000100000   // 1 Mbytes
+
+#define FBUF_BASE       0x00B2000000      
+#define FBUF_SIZE       FBUF_X_SIZE * FBUF_Y_SIZE
+
+#define BDEV_BASE       0x00B3000000      
+#define BDEV_SIZE       0x0000001000   // 4 Kbytes
+
+#define MTTY_BASE       0x00B4000000      
+#define MTTY_SIZE       0x0000001000   // 4 Kbytes
+
+#define MNIC_BASE       0x00B5000000      
+#define MNIC_SIZE       0x0000080000   // 512 Kbytes (for 8 channels)
+
+// replicated segments : address is incremented by a cluster offset 
+//     offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+#define MEMC_BASE       0x0000000000      
+#define MEMC_SIZE       0x0010000000   // 256 Mbytes per cluster
+
+#define XICU_BASE       0x00B0000000      
+#define XICU_SIZE       0x0000001000   // 4 Kbytes
+
+#define MDMA_BASE       0x00B1000000      
+#define MDMA_SIZE       0x0000001000 * NB_DMA_CHANNELS  // 4 Kbytes per channel  
+
+////////////////////////////////////////////////////////////////////
+//     TGTID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+////////////////////////////////////////////////////////////////////
+
+#define MEMC_TGTID      0
+#define XICU_TGTID      1
+#define MDMA_TGTID      2
+#define MTTY_TGTID      3
+#define FBUF_TGTID      4
+#define BDEV_TGTID      5
+#define MNIC_TGTID      6
+#define BROM_TGTID      7
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+   using namespace sc_core;
+   using namespace soclib::caba;
+   using namespace soclib::common;
+
+
+   char     soft_name[256]   = SOFT_NAME;          // pathname to binary code
+   uint64_t ncycles          = 100000000000;       // simulated cycles
+   char     disk_name[256]   = BDEV_IMAGE_NAME;    // pathname to the disk image
+   char     nic_rx_name[256] = NIC_RX_NAME;        // pathname to the rx packets file
+   char     nic_tx_name[256] = NIC_TX_NAME;        // pathname to the tx packets file
+   ssize_t  threads_nr       = 1;                  // simulator's threads number
+   bool     debug_ok         = false;              // trace activated
+   size_t   debug_period     = 1;                  // trace period
+   size_t   debug_memc_id    = 0;                  // index of memc to be traced 
+   size_t   debug_proc_id    = 0;                  // index of proc to be traced
+   uint32_t debug_from       = 0;                  // trace start cycle
+   uint32_t frozen_cycles    = MAX_FROZEN_CYCLES;  // monitoring frozen processor
+   size_t   cluster_io_id    = 0;                  // index of cluster containing IOs
+
+   ////////////// command line arguments //////////////////////
+   if (argc > 1)
+   {
+      for (int n = 1; n < argc; n = n + 2)
+      {
+         if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
+         {
+            ncycles = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+         {
+            strcpy(soft_name, argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+         {
+            strcpy(disk_name, argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+         {
+            debug_ok = true;
+            debug_from = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
+         {
+            debug_memc_id = atoi(argv[n+1]);
+            assert( (debug_memc_id < (XMAX*YMAX) ) && 
+                   "debug_memc_id larger than XMAX * YMAX" );
+         }
+         else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
+         {
+            debug_proc_id = atoi(argv[n+1]);
+            assert( (debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX) ) && 
+                   "debug_proc_id larger than XMAX * YMAX * NB_PROCS" );
+         }
+         else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
+         {
+            threads_nr = atoi(argv[n+1]);
+            threads_nr = (threads_nr < 1) ? 1 : threads_nr;
+         }
+         else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
+         {
+            frozen_cycles = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
+         {
+            debug_period = atoi(argv[n+1]);
+         }
+         else
+         {
+            std::cout << "   Arguments are (key,value) couples." << std::endl;
+            std::cout << "   The order is not important." << std::endl;
+            std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+            std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+            std::cout << "     -DISK pathname_for_disk_image" << std::endl;
+            std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+            std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+            std::cout << "     -THREADS simulator's threads number" << std::endl;
+            std::cout << "     -FROZEN max_number_of_lines" << std::endl;
+            std::cout << "     -PERIOD number_of_cycles between trace" << std::endl;
+            std::cout << "     -MEMCID index_memc_to_be_traced" << std::endl;
+            std::cout << "     -PROCID index_proc_to_be_traced" << std::endl;
+            exit(0);
+         }
+      }
+   }
+
+    // checking hardware parameters
+    assert( ( (XMAX == 1) or (XMAX == 2) or (XMAX == 4) or
+              (XMAX == 8) or (XMAX == 16) ) and
+              "The XMAX parameter must be 1, 2, 4, 8 or 16" );
+
+    assert( ( (YMAX == 1) or (YMAX == 2) or (YMAX == 4) or
+              (YMAX == 8) or (YMAX == 16) ) and
+              "The YMAX parameter must be 1, 2, 4, 8 or 16" );
+
+    assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
+              (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
+             "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
+
+    assert( (NB_DMA_CHANNELS < 9) and
+            "The NB_DMA_CHANNELS parameter must be smaller than 9" );
+
+    assert( (NB_TTY_CHANNELS < 15) and
+            "The NB_TTY_CHANNELS parameter must be smaller than 15" );
+
+    assert( (NB_NIC_CHANNELS < 9) and
+            "The NB_NIC_CHANNELS parameter must be smaller than 9" );
+
+    assert( (vci_address_width == vci_address_width) and
+            "address widths must be equal on internal & external networks" );
+
+    assert( (vci_address_width == 40) and
+            "VCI address width must be 40 bits" );
+
+    std::cout << std::endl;
+    std::cout << " - XMAX             = " << XMAX << std::endl;
+    std::cout << " - YMAX             = " << YMAX << std::endl;
+    std::cout << " - NB_PROCS_MAX     = " << NB_PROCS_MAX <<  std::endl;
+    std::cout << " - NB_DMA_CHANNELS  = " << NB_DMA_CHANNELS <<  std::endl;
+    std::cout << " - NB_TTY_CHANNELS  = " << NB_TTY_CHANNELS <<  std::endl;
+    std::cout << " - NB_NIC_CHANNELS  = " << NB_NIC_CHANNELS <<  std::endl;
+    std::cout << " - MEMC_WAYS        = " << MEMC_WAYS << std::endl;
+    std::cout << " - MEMC_SETS        = " << MEMC_SETS << std::endl;
+    std::cout << " - RAM_LATENCY      = " << XRAM_LATENCY << std::endl;
+    std::cout << " - MAX_FROZEN       = " << frozen_cycles << std::endl;
+
+    std::cout << std::endl;
+
+    // Internal and External VCI parameters definition
+    typedef soclib::caba::VciParams<vci_cell_width_int,
+                                    vci_plen_width,
+                                    vci_address_width,
+                                    vci_rerror_width,
+                                    vci_clen_width,
+                                    vci_rflag_width,
+                                    vci_srcid_width,
+                                    vci_pktid_width,
+                                    vci_trdid_width,
+                                    vci_wrplen_width> vci_param_int;
+
+    typedef soclib::caba::VciParams<vci_cell_width_ext,
+                                    vci_plen_width,
+                                    vci_address_width,
+                                    vci_rerror_width,
+                                    vci_clen_width,
+                                    vci_rflag_width,
+                                    vci_srcid_width,
+                                    vci_pktid_width,
+                                    vci_trdid_width,
+                                    vci_wrplen_width> vci_param_ext;
+
+#if USE_OPENMP
+   omp_set_dynamic(false);
+   omp_set_num_threads(threads_nr);
+   std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+   // Define parameters depending on mesh size
+   size_t   x_width;
+   size_t   y_width;
+
+   if      (XMAX == 1) x_width = 0;
+   else if (XMAX == 2) x_width = 1;
+   else if (XMAX <= 4) x_width = 2;
+   else if (XMAX <= 8) x_width = 3;
+   else                     x_width = 4;
+
+   if      (YMAX == 1) y_width = 0;
+   else if (YMAX == 2) y_width = 1;
+   else if (YMAX <= 4) y_width = 2;
+   else if (YMAX <= 8) y_width = 3;
+   else                     y_width = 4;
+
+   /////////////////////
+   //  Mapping Tables
+   /////////////////////
+
+   // internal network
+   MappingTable maptabd(vci_address_width, 
+                        IntTab(x_width + y_width, 16 - x_width - y_width), 
+                        IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), 
+                        0x00FF000000);
+
+   for (size_t x = 0; x < XMAX; x++)
+   {
+      for (size_t y = 0; y < YMAX; y++)
+      {
+         sc_uint<vci_address_width> offset;
+         offset = (sc_uint<vci_address_width>)cluster(x,y) 
+                   << (vci_address_width-x_width-y_width);
+
+         std::ostringstream    sh;
+         sh << "seg_memc_" << x << "_" << y;
+         maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, 
+                             IntTab(cluster(x,y),MEMC_TGTID), true));
+
+         std::ostringstream    si;
+         si << "seg_xicu_" << x << "_" << y;
+         maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, 
+                             IntTab(cluster(x,y),XICU_TGTID), false));
+
+         std::ostringstream    sd;
+         sd << "seg_mdma_" << x << "_" << y;
+         maptabd.add(Segment(sd.str(), MDMA_BASE+offset, MDMA_SIZE, 
+                             IntTab(cluster(x,y),MDMA_TGTID), false));
+
+         if ( cluster(x,y) == cluster_io_id )
+         {
+            maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, 
+                        IntTab(cluster(x,y),MTTY_TGTID), false));
+            maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, 
+                        IntTab(cluster(x,y),FBUF_TGTID), false));
+            maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, 
+                        IntTab(cluster(x,y),BDEV_TGTID), false));
+            maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, 
+                        IntTab(cluster(x,y),MNIC_TGTID), false));
+            maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, 
+                        IntTab(cluster(x,y),BROM_TGTID), true));
+         }
+      }
+   }
+   std::cout << maptabd << std::endl;
+
+   // external network
+   MappingTable maptabx(vci_address_width, 
+                        IntTab(x_width+y_width), 
+                        IntTab(x_width+y_width), 
+                        0xFFFF000000ULL);
+
+   for (size_t x = 0; x < XMAX; x++)
+   {
+      for (size_t y = 0; y < YMAX ; y++)
+      { 
+
+         sc_uint<vci_address_width> offset;
+         offset = (sc_uint<vci_address_width>)cluster(x,y) 
+                   << (vci_address_width-x_width-y_width);
+
+         std::ostringstream sh;
+         sh << "x_seg_memc_" << x << "_" << y;
+
+         maptabx.add(Segment(sh.str(), MEMC_BASE+offset, 
+                     MEMC_SIZE, IntTab(cluster(x,y)), false));
+      }
+   }
+   std::cout << maptabx << std::endl;
+
+   ////////////////////
+   // Signals
+   ///////////////////
+
+   sc_clock           signal_clk("clk");
+   sc_signal<bool>    signal_resetn("resetn");
+
+   // Horizontal inter-clusters DSPIN signals
+   DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc =
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 2);
+   DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec =
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 2);
+   DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc =
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2);
+   DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec =
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX, 2);
+
+   // Vertical inter-clusters DSPIN signals
+   DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc =
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 2);
+   DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec =
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 2);
+   DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc =
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2);
+   DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec =
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1, 2);
+
+   // Mesh boundaries DSPIN signals
+   DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in =
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in", XMAX, YMAX, 2, 4);
+   DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out =
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", XMAX, YMAX, 2, 4);
+   DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in =
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in", XMAX, YMAX, 2, 4);
+   DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out =
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", XMAX, YMAX, 2, 4);
+
+
+   ////////////////////////////
+   //      Loader    
+   ////////////////////////////
+
+#if USE_ALMOS
+   soclib::common::Loader loader(almos_bootloader_pathname,
+                                 almos_archinfo_pathname,
+                                 almos_kernel_pathname);
+#else
+   soclib::common::Loader loader(soft_name);
+#endif
+
+   typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+   proc_iss::set_loader(loader);
+
+   ////////////////////////////
+   // Clusters construction
+   ////////////////////////////
+
+   TsarXbarCluster<dspin_cmd_width,
+                   dspin_rsp_width,
+                   vci_param_int,
+                   vci_param_ext>*          clusters[XMAX][YMAX];
+
+#if USE_OPENMP
+#pragma omp parallel
+    {
+#pragma omp for
+#endif
+        for(size_t i = 0; i  < (XMAX * YMAX); i++)
+        {
+            size_t x = i / YMAX;
+            size_t y = i % YMAX;
+
+#if USE_OPENMP
+#pragma omp critical
+            {
+#endif
+            std::cout << std::endl;
+            std::cout << "Cluster_" << x << "_" << y << std::endl;
+            std::cout << std::endl;
+
+            std::ostringstream sc;
+            sc << "cluster_" << x << "_" << y;
+            clusters[x][y] = new TsarXbarCluster<dspin_cmd_width,
+                                                 dspin_rsp_width,
+                                                 vci_param_int,
+                                                 vci_param_ext>
+            (
+                sc.str().c_str(),
+                NB_PROCS_MAX,
+                NB_TTY_CHANNELS,  
+                NB_DMA_CHANNELS, 
+                x,
+                y,
+                cluster(x,y),
+                maptabd,
+                maptabx,
+                x_width,
+                y_width,
+                vci_srcid_width - x_width - y_width,   // l_id width,
+                MEMC_TGTID,
+                XICU_TGTID,
+                MDMA_TGTID,
+                FBUF_TGTID,
+                MTTY_TGTID,
+                BROM_TGTID,
+                MNIC_TGTID,
+                BDEV_TGTID,
+                MEMC_WAYS,
+                MEMC_SETS,
+                L1_IWAYS,
+                L1_ISETS,
+                L1_DWAYS,
+                L1_DSETS,
+                XRAM_LATENCY,
+                (cluster(x,y) == cluster_io_id),
+                FBUF_X_SIZE,
+                FBUF_Y_SIZE,
+                disk_name,
+                BDEV_SECTOR_SIZE,
+                NB_NIC_CHANNELS,
+                nic_rx_name,
+                nic_tx_name,
+                NIC_TIMEOUT,
+                loader,
+                frozen_cycles,
+                debug_from   ,
+                debug_ok and (cluster(x,y) == debug_memc_id),
+                debug_ok and (cluster(x,y) == debug_proc_id) 
+            );
+
+#if USE_OPENMP
+            } // end critical
+#endif
+        } // end for
+#if USE_OPENMP
+    }
+#endif
+
+   ///////////////////////////////////////////////////////////////
+   //     Net-list 
+   ///////////////////////////////////////////////////////////////
+
+   // Clock & RESET
+   for (size_t x = 0; x < (XMAX); x++){
+      for (size_t y = 0; y < YMAX; y++){
+         clusters[x][y]->p_clk                         (signal_clk);
+         clusters[x][y]->p_resetn                      (signal_resetn);
+      }
+   }
+
+   // Inter Clusters horizontal connections
+   if (XMAX > 1){
+      for (size_t x = 0; x < (XMAX-1); x++){
+         for (size_t y = 0; y < YMAX; y++){
+            for (size_t k = 0; k < 2; k++){
+               clusters[x][y]->p_cmd_out[k][EAST]      (signal_dspin_h_cmd_inc[x][y][k]);
+               clusters[x+1][y]->p_cmd_in[k][WEST]     (signal_dspin_h_cmd_inc[x][y][k]);
+               clusters[x][y]->p_cmd_in[k][EAST]       (signal_dspin_h_cmd_dec[x][y][k]);
+               clusters[x+1][y]->p_cmd_out[k][WEST]    (signal_dspin_h_cmd_dec[x][y][k]);
+               clusters[x][y]->p_rsp_out[k][EAST]      (signal_dspin_h_rsp_inc[x][y][k]);
+               clusters[x+1][y]->p_rsp_in[k][WEST]     (signal_dspin_h_rsp_inc[x][y][k]);
+               clusters[x][y]->p_rsp_in[k][EAST]       (signal_dspin_h_rsp_dec[x][y][k]);
+               clusters[x+1][y]->p_rsp_out[k][WEST]    (signal_dspin_h_rsp_dec[x][y][k]);
+            }
+         }
+      }
+   }
+   std::cout << std::endl << "Horizontal connections established" << std::endl;   
+
+   // Inter Clusters vertical connections
+   if (YMAX > 1) {
+      for (size_t y = 0; y < (YMAX-1); y++){
+         for (size_t x = 0; x < XMAX; x++){
+            for (size_t k = 0; k < 2; k++){
+               clusters[x][y]->p_cmd_out[k][NORTH]     (signal_dspin_v_cmd_inc[x][y][k]);
+               clusters[x][y+1]->p_cmd_in[k][SOUTH]    (signal_dspin_v_cmd_inc[x][y][k]);
+               clusters[x][y]->p_cmd_in[k][NORTH]      (signal_dspin_v_cmd_dec[x][y][k]);
+               clusters[x][y+1]->p_cmd_out[k][SOUTH]   (signal_dspin_v_cmd_dec[x][y][k]);
+               clusters[x][y]->p_rsp_out[k][NORTH]     (signal_dspin_v_rsp_inc[x][y][k]);
+               clusters[x][y+1]->p_rsp_in[k][SOUTH]    (signal_dspin_v_rsp_inc[x][y][k]);
+               clusters[x][y]->p_rsp_in[k][NORTH]      (signal_dspin_v_rsp_dec[x][y][k]);
+               clusters[x][y+1]->p_rsp_out[k][SOUTH]   (signal_dspin_v_rsp_dec[x][y][k]);
+            }
+         }
+      }
+   }
+   std::cout << "Vertical connections established" << std::endl;
+
+   // East & West boundary cluster connections
+   for (size_t y = 0; y < YMAX; y++)
+   {
+      for (size_t k = 0; k < 2; k++)
+      {
+         clusters[0][y]->p_cmd_in[k][WEST]             (signal_dspin_false_cmd_in[0][y][k][WEST]);
+         clusters[0][y]->p_cmd_out[k][WEST]            (signal_dspin_false_cmd_out[0][y][k][WEST]);
+         clusters[0][y]->p_rsp_in[k][WEST]             (signal_dspin_false_rsp_in[0][y][k][WEST]);
+         clusters[0][y]->p_rsp_out[k][WEST]            (signal_dspin_false_rsp_out[0][y][k][WEST]);
+
+         clusters[XMAX-1][y]->p_cmd_in[k][EAST]   (signal_dspin_false_cmd_in[XMAX-1][y][k][EAST]);
+         clusters[XMAX-1][y]->p_cmd_out[k][EAST]  (signal_dspin_false_cmd_out[XMAX-1][y][k][EAST]);
+         clusters[XMAX-1][y]->p_rsp_in[k][EAST]   (signal_dspin_false_rsp_in[XMAX-1][y][k][EAST]);
+         clusters[XMAX-1][y]->p_rsp_out[k][EAST]  (signal_dspin_false_rsp_out[XMAX-1][y][k][EAST]);
+      }
+   }
+
+   // North & South boundary clusters connections
+   for (size_t x = 0; x < XMAX; x++)
+   {
+      for (size_t k = 0; k < 2; k++)
+      {
+         clusters[x][0]->p_cmd_in[k][SOUTH]            (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
+         clusters[x][0]->p_cmd_out[k][SOUTH]           (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
+         clusters[x][0]->p_rsp_in[k][SOUTH]            (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
+         clusters[x][0]->p_rsp_out[k][SOUTH]           (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
+
+         clusters[x][YMAX-1]->p_cmd_in[k][NORTH]  (signal_dspin_false_cmd_in[x][YMAX-1][k][NORTH]);
+         clusters[x][YMAX-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][YMAX-1][k][NORTH]);
+         clusters[x][YMAX-1]->p_rsp_in[k][NORTH]  (signal_dspin_false_rsp_in[x][YMAX-1][k][NORTH]);
+         clusters[x][YMAX-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][YMAX-1][k][NORTH]);
+      }
+   }
+   std::cout << "North, South, West, East connections established" << std::endl;
+   std::cout << std::endl;
+
+
+   ////////////////////////////////////////////////////////
+   //   Simulation
+   ///////////////////////////////////////////////////////
+
+   sc_start(sc_core::sc_time(0, SC_NS));
+   signal_resetn = false;
+
+   // network boundaries signals
+   for (size_t x = 0; x < XMAX ; x++){
+      for (size_t y = 0; y < YMAX ; y++){
+         for (size_t k = 0; k < 2; k++){
+            for (size_t a = 0; a < 4; a++){
+               signal_dspin_false_cmd_in [x][y][k][a].write = false;
+               signal_dspin_false_cmd_in [x][y][k][a].read  = true;
+               signal_dspin_false_cmd_out[x][y][k][a].write = false;
+               signal_dspin_false_cmd_out[x][y][k][a].read  = true;
+
+               signal_dspin_false_rsp_in [x][y][k][a].write = false;
+               signal_dspin_false_rsp_in [x][y][k][a].read  = true;
+               signal_dspin_false_rsp_out[x][y][k][a].write = false;
+               signal_dspin_false_rsp_out[x][y][k][a].read  = true;
+            }
+         }
+      }
+   }
+
+   sc_start(sc_core::sc_time(1, SC_NS));
+   signal_resetn = true;
+
+   for (uint64_t n = 1; n < ncycles; n++)
+   {
+      // Monitor a specific address for L1 & L2 caches
+      //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL);
+      //clusters[1][0]->memc->copies_monitor(0x800002C000ULL);
+
+      if (debug_ok and (n > debug_from) and (n % debug_period == 0))
+      {
+         std::cout << "****************** cycle " << std::dec << n ;
+         std::cout << " ************************************************" << std::endl;
+
+        // trace proc[debug_proc_id] 
+        size_t l = debug_proc_id % NB_PROCS_MAX ;
+        size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ;
+        size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ;
+
+        std::ostringstream proc_signame;
+        proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
+        std::ostringstream p2m_signame;
+        p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ;
+        std::ostringstream m2p_signame;
+        m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ;
+        std::ostringstream p_cmd_signame;
+        p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ;
+        std::ostringstream p_rsp_signame;
+        p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ;
+
+        clusters[x][y]->proc[l]->print_trace();
+        clusters[x][y]->wi_proc[l]->print_trace();
+        clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
+        clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str());
+        clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str());
+        clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str());
+        clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str());
+
+        clusters[x][y]->xbar_rsp_d->print_trace();
+        clusters[x][y]->xbar_cmd_d->print_trace();
+        clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD");
+        clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD");
+        clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP");
+        clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP");
+
+        // trace memc[debug_memc_id] 
+        x = debug_memc_id / YMAX;
+        y = debug_memc_id % YMAX;
+
+        std::ostringstream smemc;
+        smemc << "[SIG]MEMC_" << x << "_" << y;
+        std::ostringstream sxram;
+        sxram << "[SIG]XRAM_" << x << "_" << y;
+        std::ostringstream sm2p;
+        sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ;
+        std::ostringstream sp2m;
+        sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ;
+        std::ostringstream m_cmd_signame;
+        m_cmd_signame << "[SIG]MEMC_" << x << "_" << y <<  " CMD" ;
+        std::ostringstream m_rsp_signame;
+        m_rsp_signame << "[SIG]MEMC_" << x << "_" << y <<  " RSP" ;
+
+        clusters[x][y]->memc->print_trace();
+        clusters[x][y]->wt_memc->print_trace();
+        clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
+        clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
+        clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str());
+        clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str());
+        clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str());
+        clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str());
+        
+        // trace replicated peripherals
+//        clusters[1][1]->mdma->print_trace();
+//        clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1");
+//        clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1");
+        
+
+        // trace external peripherals
+        size_t io_x   = cluster_io_id / YMAX;
+        size_t io_y   = cluster_io_id % YMAX;
+        
+        clusters[io_x][io_y]->brom->print_trace();
+        clusters[io_x][io_y]->wt_brom->print_trace();
+        clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM");
+        clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD");
+        clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP");
+
+//        clusters[io_x][io_y]->bdev->print_trace();
+//        clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
+//        clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
+      }
+
+      sc_start(sc_core::sc_time(1, SC_NS));
+   }
+   return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+   try {
+      return _main(argc, argv);
+   } catch (std::exception &e) {
+      std::cout << e.what() << std::endl;
+   } catch (...) {
+      std::cout << "Unknown exception occured" << std::endl;
+      throw;
+   }
+   return 1;
+}
+
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
Index: /branches/v5/platforms/tsar_generic_xbar/top.desc
===================================================================
--- /branches/v5/platforms/tsar_generic_xbar/top.desc	(revision 447)
+++ /branches/v5/platforms/tsar_generic_xbar/top.desc	(revision 447)
@@ -0,0 +1,46 @@
+
+# -*- python -*-
+
+# internal VCI parameters values
+vci_cell_size_int   = 4
+vci_cell_size_ext   = 8
+
+vci_plen_size       = 8
+vci_addr_size       = 40
+vci_rerror_size     = 1
+vci_clen_size       = 1
+vci_rflag_size      = 1
+vci_srcid_size      = 14
+vci_pktid_size      = 4
+vci_trdid_size      = 4
+vci_wrplen_size     = 1
+
+# DSPIN network parameters values
+dspin_cmd_flit_size     = 39
+dspin_rsp_flit_size     = 32
+
+todo = Platform('caba', 'top.cpp',
+
+	uses = [
+            Uses('caba:tsar_xbar_cluster', 
+                  vci_data_width_int = vci_cell_size_int,
+                  vci_data_width_ext = vci_cell_size_ext,
+                  dspin_cmd_width    = dspin_cmd_flit_size,
+                  dspin_rsp_width    = dspin_rsp_flit_size),
+
+	        Uses('common:elf_file_loader'),
+            Uses('common:plain_file_loader'),
+           ],
+
+    # default VCI parameters (global variables)
+    cell_size   = vci_cell_size_int,  
+	plen_size   = vci_plen_size,
+	addr_size   = vci_addr_size,
+	rerror_size = vci_rerror_size,
+	clen_size   = vci_clen_size,
+	rflag_size  = vci_rflag_size,
+	srcid_size  = vci_srcid_size,
+	pktid_size  = vci_pktid_size,
+	trdid_size  = vci_trdid_size,
+	wrplen_size = vci_wrplen_size,
+)
Index: /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd
===================================================================
--- /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd	(revision 447)
+++ /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd	(revision 447)
@@ -0,0 +1,98 @@
+
+# -*- python -*-
+
+Module('caba:tsar_xbar_cluster', 
+    classname = 'soclib::caba::TsarXbarCluster',
+	tmpl_parameters = [
+		parameter.Int('dspin_cmd_width'),
+		parameter.Int('dspin_rsp_width'),
+        parameter.Module('vci_param_int', default = 'caba:vci_param',
+                          cell_size = parameter.Reference('vci_data_width_int')),
+        parameter.Module('vci_param_ext', default = 'caba:vci_param',
+                          cell_size = parameter.Reference('vci_data_width_ext')),
+        ],
+
+	header_files = [ '../source/include/tsar_xbar_cluster.h', 
+        ],
+
+	implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', 
+        ],
+
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+              
+		Uses('caba:vci_cc_vcache_wrapper', 
+              cell_size       = parameter.Reference('vci_data_width_int'),
+              dspin_in_width  = parameter.Reference('dspin_cmd_width'),
+              dspin_out_width = parameter.Reference('dspin_rsp_width'),
+              iss_t           = 'common:gdb_iss', 
+              gdb_iss_t       = 'common:mips32el'),
+
+		Uses('caba:vci_mem_cache',
+              memc_cell_size_int = parameter.Reference('vci_data_width_int'),
+              memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
+              dspin_in_width  = parameter.Reference('dspin_rsp_width'),
+              dspin_out_width = parameter.Reference('dspin_cmd_width')),
+
+		Uses('caba:vci_simple_rom',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+		Uses('caba:vci_simple_ram',
+              cell_size       = parameter.Reference('vci_data_width_ext')),
+
+        Uses('caba:vci_xicu',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+        Uses('caba:dspin_local_crossbar', 
+              flit_width      = parameter.Reference('dspin_cmd_width')),
+
+        Uses('caba:dspin_local_crossbar', 
+              flit_width      = parameter.Reference('dspin_rsp_width')),
+
+        Uses('caba:virtual_dspin_router', 
+              flit_width      = parameter.Reference('dspin_cmd_width')),
+
+        Uses('caba:virtual_dspin_router', 
+              flit_width      = parameter.Reference('dspin_rsp_width')),
+            
+        Uses('caba:vci_multi_tty',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+        Uses('caba:vci_framebuffer',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+        Uses('caba:vci_multi_nic',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+		Uses('caba:vci_block_device_tsar',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+		Uses('caba:vci_multi_dma',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+        Uses('caba:vci_dspin_target_wrapper',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+        Uses('caba:vci_dspin_initiator_wrapper',
+              cell_size       = parameter.Reference('vci_data_width_int')),
+
+		Uses('common:elf_file_loader'),
+		],
+
+	ports = [
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		Port('caba:dspin_output', 'p_cmd_out', [2, 4], 
+              dspin_data_size = parameter.Reference('dspin_cmd_width')),
+		Port('caba:dspin_input', 'p_cmd_in', [2, 4], 
+              dspin_data_size = parameter.Reference('dspin_cmd_width')),
+		Port('caba:dspin_output', 'p_rsp_out', [2, 4], 
+              dspin_data_size = parameter.Reference('dspin_rsp_width')), 
+		Port('caba:dspin_input', 'p_rsp_in', [2, 4], 
+              dspin_data_size = parameter.Reference('dspin_rsp_width')),
+		],
+)
+
+
Index: /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
===================================================================
--- /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h	(revision 447)
+++ /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h	(revision 447)
@@ -0,0 +1,254 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsar_xbar_cluster.h
+// Author: Alain Greiner
+// Copyright: UPMC/LIP6
+// Date : march 2013
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef SOCLIB_CABA_TSAR_XBAR_CLUSTER_H
+#define SOCLIB_CABA_TSAR_XBAR_CLUSTER_H
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_simple_rom.h"
+#include "vci_xicu.h"
+#include "dspin_local_crossbar.h"
+#include "vci_dspin_initiator_wrapper.h"
+#include "vci_dspin_target_wrapper.h"
+#include "virtual_dspin_router.h"
+#include "vci_multi_tty.h"
+#include "vci_multi_nic.h"
+#include "vci_block_device_tsar.h"
+#include "vci_framebuffer.h"
+#include "vci_multi_dma.h"
+#include "vci_mem_cache.h"
+#include "vci_cc_vcache_wrapper.h"
+
+namespace soclib { namespace caba {
+
+///////////////////////////////////////////////////////////////////////////
+template<size_t dspin_cmd_width,
+         size_t dspin_rsp_width,
+         typename vci_param_int,
+         typename vci_param_ext>  class TsarXbarCluster
+///////////////////////////////////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    public:
+
+    // Ports
+    sc_in<bool>                                     p_clk;
+    sc_in<bool>                                     p_resetn;
+    soclib::caba::DspinOutput<dspin_cmd_width>      **p_cmd_out;
+    soclib::caba::DspinInput<dspin_cmd_width>       **p_cmd_in;
+    soclib::caba::DspinOutput<dspin_rsp_width>      **p_rsp_out;
+    soclib::caba::DspinInput<dspin_rsp_width>       **p_rsp_in;
+
+    // interrupt signals
+    sc_signal<bool>         signal_false;
+    sc_signal<bool>         signal_proc_it[8];
+    sc_signal<bool>         signal_irq_mdma[8];
+    sc_signal<bool>         signal_irq_mtty[23];
+    sc_signal<bool>         signal_irq_mnic_rx[8];  // unused
+    sc_signal<bool>         signal_irq_mnic_tx[8];  // unused
+    sc_signal<bool>         signal_irq_bdev;
+
+    // DSPIN signals between DSPIN routers and local_crossbars
+    DspinSignals<dspin_cmd_width>   signal_dspin_cmd_l2g_d;
+    DspinSignals<dspin_cmd_width>   signal_dspin_cmd_g2l_d;
+    DspinSignals<dspin_cmd_width>   signal_dspin_m2p_l2g_c;
+    DspinSignals<dspin_cmd_width>   signal_dspin_m2p_g2l_c;
+    DspinSignals<dspin_cmd_width>   signal_dspin_clack_l2g_c;
+    DspinSignals<dspin_cmd_width>   signal_dspin_clack_g2l_c;
+    DspinSignals<dspin_rsp_width>   signal_dspin_rsp_l2g_d;
+    DspinSignals<dspin_rsp_width>   signal_dspin_rsp_g2l_d;
+    DspinSignals<dspin_rsp_width>   signal_dspin_p2m_l2g_c;
+    DspinSignals<dspin_rsp_width>   signal_dspin_p2m_g2l_c;
+
+    // Direct VCI signals to VCI/DSPIN wrappers
+    VciSignals<vci_param_int>       signal_vci_ini_proc[8];
+    VciSignals<vci_param_int>       signal_vci_ini_mdma;
+    VciSignals<vci_param_int>       signal_vci_ini_bdev;
+
+    VciSignals<vci_param_int>       signal_vci_tgt_memc;
+    VciSignals<vci_param_int>       signal_vci_tgt_xicu;
+    VciSignals<vci_param_int>       signal_vci_tgt_mdma;
+    VciSignals<vci_param_int>       signal_vci_tgt_mtty;
+    VciSignals<vci_param_int>       signal_vci_tgt_bdev;
+    VciSignals<vci_param_int>       signal_vci_tgt_brom;
+    VciSignals<vci_param_int>       signal_vci_tgt_fbuf;
+    VciSignals<vci_param_int>       signal_vci_tgt_mnic;
+
+    // Direct DSPIN signals to local crossbars
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_proc_i[8];
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_proc_i[8];
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_mdma_i;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_mdma_i;
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_bdev_i;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_bdev_i;
+
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_memc_t;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_memc_t;
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_xicu_t;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_xicu_t;
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_mdma_t;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_mdma_t;
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_mtty_t;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_mtty_t;
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_bdev_t;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_bdev_t;
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_brom_t;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_brom_t;
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_fbuf_t;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_fbuf_t;
+    DspinSignals<dspin_cmd_width>     signal_dspin_cmd_mnic_t;
+    DspinSignals<dspin_rsp_width>     signal_dspin_rsp_mnic_t;
+
+    // Coherence DSPIN signals to local crossbar
+    DspinSignals<dspin_cmd_width>     signal_dspin_m2p_memc;
+    DspinSignals<dspin_cmd_width>     signal_dspin_clack_memc;
+    DspinSignals<dspin_rsp_width>     signal_dspin_p2m_memc;
+    DspinSignals<dspin_cmd_width>     signal_dspin_m2p_proc[8];
+    DspinSignals<dspin_cmd_width>     signal_dspin_clack_proc[8];
+    DspinSignals<dspin_rsp_width>     signal_dspin_p2m_proc[8];
+
+    // external RAM to MEMC VCI signal
+    VciSignals<vci_param_ext>         signal_vci_xram;
+
+    // Components
+
+    VciCcVCacheWrapper<vci_param_int,
+                       dspin_cmd_width,
+                       dspin_rsp_width,
+                       GdbServer<Mips32ElIss> >*  proc[8];
+
+    VciDspinInitiatorWrapper<vci_param_int,
+                             dspin_cmd_width,
+                             dspin_rsp_width>*    wi_proc[8];
+
+    VciMemCache<vci_param_int,
+                vci_param_ext,
+                dspin_rsp_width,
+                dspin_cmd_width>*                 memc;
+
+    VciDspinTargetWrapper<vci_param_int,
+                          dspin_cmd_width,
+                          dspin_rsp_width>*       wt_memc;
+
+    VciXicu<vci_param_int>*                       xicu;
+
+    VciDspinTargetWrapper<vci_param_int,
+                          dspin_cmd_width,
+                          dspin_rsp_width>*       wt_xicu;
+
+    VciMultiDma<vci_param_int>*                   mdma;
+
+    VciDspinInitiatorWrapper<vci_param_int,
+                             dspin_cmd_width,
+                             dspin_rsp_width>*    wi_mdma;
+
+    VciDspinTargetWrapper<vci_param_int,
+                          dspin_cmd_width,
+                          dspin_rsp_width>*       wt_mdma;
+
+    VciSimpleRam<vci_param_ext>*                  xram;
+
+    VciSimpleRom<vci_param_int>*                  brom;
+
+    VciDspinTargetWrapper<vci_param_int,
+                          dspin_cmd_width,
+                          dspin_rsp_width>*       wt_brom;
+
+    VciMultiTty<vci_param_int>*                   mtty;
+
+    VciDspinTargetWrapper<vci_param_int,
+                          dspin_cmd_width,
+                          dspin_rsp_width>*       wt_mtty;
+
+    VciFrameBuffer<vci_param_int>*                fbuf;
+
+    VciDspinTargetWrapper<vci_param_int,
+                          dspin_cmd_width,
+                          dspin_rsp_width>*       wt_fbuf;
+
+    VciMultiNic<vci_param_int>*                   mnic;
+
+    VciDspinTargetWrapper<vci_param_int,
+                          dspin_cmd_width,
+                          dspin_rsp_width>*       wt_mnic;
+
+    VciBlockDeviceTsar<vci_param_int>*            bdev;
+
+    VciDspinInitiatorWrapper<vci_param_int,
+                             dspin_cmd_width,
+                             dspin_rsp_width>*    wi_bdev;
+
+    VciDspinTargetWrapper<vci_param_int,
+                          dspin_cmd_width,
+                          dspin_rsp_width>*       wt_bdev;
+
+    DspinLocalCrossbar<dspin_cmd_width>*          xbar_cmd_d;
+    DspinLocalCrossbar<dspin_rsp_width>*          xbar_rsp_d;
+    DspinLocalCrossbar<dspin_cmd_width>*          xbar_m2p_c;
+    DspinLocalCrossbar<dspin_rsp_width>*          xbar_p2m_c;
+    DspinLocalCrossbar<dspin_cmd_width>*          xbar_clack_c;
+
+    VirtualDspinRouter<dspin_cmd_width>*          router_cmd;
+    VirtualDspinRouter<dspin_rsp_width>*          router_rsp;
+
+    TsarXbarCluster( sc_module_name                     insname,
+                     size_t                             nb_procs,      // processors
+                     size_t                             nb_ttys,       // TTY terminals
+                     size_t                             nb_dmas,       //  DMA channels
+                     size_t                             x,             // x coordinate
+                     size_t                             y,             // y coordinate
+                     size_t                             cluster,       // y + ymax*x
+                     const soclib::common::MappingTable &mtd,          // internal
+                     const soclib::common::MappingTable &mtx,          // external
+                     size_t                             x_width,       // x field bits
+                     size_t                             y_width,       // y field bits
+                     size_t                             l_width,       // l field bits
+                     size_t                             tgtid_memc,
+                     size_t                             tgtid_xicu,
+                     size_t                             tgtid_mdma,
+                     size_t                             tgtid_fbuf,
+                     size_t                             tgtid_mtty,
+                     size_t                             tgtid_brom,
+                     size_t                             tgtid_mnic,
+                     size_t                             tgtid_bdev,
+                     size_t                             memc_ways,
+                     size_t                             memc_sets,
+                     size_t                             l1_i_ways,
+                     size_t                             l1_i_sets,
+                     size_t                             l1_d_ways,
+                     size_t                             l1_d_sets,
+                     size_t                             xram_latency,  // external ram
+                     bool                               io,            // I/O cluster
+                     size_t                             xfb,           // fbf pixels
+                     size_t                             yfb,           // fbf lines
+                     char*                              disk_name,     // virtual disk
+                     size_t                             block_size,    // block size
+                     size_t                             nic_channels,  // number channels
+                     char*                              nic_rx_name,   // filename rx
+                     char*                              nic_tx_name,   // filename tx
+                     uint32_t                           nic_timeout,   // cycles
+                     const Loader                       &loader,
+                     uint32_t                           frozen_cycles,
+                     uint32_t                           start_debug_cycle,
+                     bool                               memc_debug_ok,
+                     bool                               proc_debug_ok);
+
+};
+}}
+
+#endif
Index: /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp
===================================================================
--- /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp	(revision 447)
+++ /branches/v5/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp	(revision 447)
@@ -0,0 +1,724 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsar_xbar_cluster.cpp
+// Author: Alain Greiner
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+// This file define a TSAR cluster architecture with virtual memory:
+// - It uses two virtual_dspin_router as distributed global interconnect
+// - It uses four dspin_local_crossbar as local interconnect
+// - It uses the vci_cc_vcache_wrapper
+// - It uses the vci_mem_cache
+// - It contains a private RAM with a variable latency to emulate the L3 cache
+// - It can contains 1, 2 or 4 processors
+// - Each processor has a private dma channel (vci_multi_dma)
+// - It uses the vci_xicu interrupt controller
+// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
+// - The Multi-TTY component controls up to 15 terminals.
+// - Each Multi-DMA component controls up to 8 DMA channels.
+// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
+// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
+// - The BDEV IRQ is connected to IRQ_IN[31]
+//////////////////////////////////////////////////////////////////////////////////
+
+#include "../include/tsar_xbar_cluster.h"
+
+
+namespace soclib {
+namespace caba  {
+
+////////////////////////////////////////////////////////////////////////////////////
+template<size_t dspin_cmd_width,
+         size_t dspin_rsp_width,
+         typename vci_param_int,
+         typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
+                                                 dspin_rsp_width,
+                                                 vci_param_int,
+                                                 vci_param_ext>::TsarXbarCluster(
+////////////////////////////////////////////////////////////////////////////////////
+         sc_module_name                     insname,
+         size_t                             nb_procs,
+         size_t                             nb_ttys,
+         size_t                             nb_dmas,
+         size_t                             x_id,
+         size_t                             y_id,
+         size_t                             cluster_id,
+         const soclib::common::MappingTable &mtd,
+         const soclib::common::MappingTable &mtx,
+         size_t                             x_width,
+         size_t                             y_width,
+         size_t                             l_width,
+         size_t                             tgtid_memc,
+         size_t                             tgtid_xicu,
+         size_t                             tgtid_mdma,
+         size_t                             tgtid_fbuf,
+         size_t                             tgtid_mtty,
+         size_t                             tgtid_brom,
+         size_t                             tgtid_mnic,
+         size_t                             tgtid_bdev,
+         size_t                             memc_ways,
+         size_t                             memc_sets,
+         size_t                             l1_i_ways,
+         size_t                             l1_i_sets,
+         size_t                             l1_d_ways,
+         size_t                             l1_d_sets,
+         size_t                             xram_latency,
+         bool                               io,
+         size_t                             xfb,
+         size_t                             yfb,
+         char*                              disk_name,
+         size_t                             block_size,
+         size_t                             nic_channels,
+         char*                              nic_rx_name,
+         char*                              nic_tx_name,
+         uint32_t                           nic_timeout,
+         const Loader                      &loader,
+         uint32_t                           frozen_cycles,
+         uint32_t                           debug_start_cycle,
+         bool                               memc_debug_ok,
+         bool                               proc_debug_ok)
+            : soclib::caba::BaseModule(insname),
+            p_clk("clk"),
+            p_resetn("resetn")
+
+{
+    // Vectors of ports definition
+    p_cmd_in        = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 2, 4);
+    p_cmd_out       = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 2, 4);
+    p_rsp_in        = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 2, 4);
+    p_rsp_out       = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 2, 4);
+
+    /////////////////////////////////////////////////////////////////////////////
+    // Components definition
+    /////////////////////////////////////////////////////////////////////////////
+
+    for (size_t p = 0; p < nb_procs; p++)
+    {
+        std::ostringstream sproc;
+        sproc << "proc_" << x_id << "_" << y_id << "_" << p;
+        proc[p] = new VciCcVCacheWrapper<vci_param_int,
+                                         dspin_cmd_width,
+                                         dspin_rsp_width,
+                                         GdbServer<Mips32ElIss> >(
+                      sproc.str().c_str(),
+                      cluster_id*nb_procs + p,        // GLOBAL PROC_ID
+                      mtd,                            // Mapping Table
+                      IntTab(cluster_id,p),           // SRCID
+                      (cluster_id << l_width) + p,    // CC_GLOBAL_ID
+                      8,                              // ITLB ways
+                      8,                              // ITLB sets
+                      8,                              // DTLB ways
+                      8,                              // DTLB sets
+                      l1_i_ways,l1_i_sets,16,         // ICACHE size
+                      l1_d_ways,l1_d_sets,16,         // DCACHE size
+                      4,                              // WBUF nlines
+                      4,                              // WBUF nwords
+                      x_width,
+                      y_width,
+                      frozen_cycles,                  // max frozen cycles
+                      debug_start_cycle,
+                      proc_debug_ok);
+
+        std::ostringstream swip;
+        swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
+        wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
+                                                  dspin_cmd_width,
+                                                  dspin_rsp_width>(
+                     swip.str().c_str(),
+                     x_width + y_width + l_width);
+    }
+
+    /////////////////////////////////////////////////////////////////////////////
+    std::ostringstream smemc;
+    smemc << "memc_" << x_id << "_" << y_id;
+    memc = new VciMemCache<vci_param_int,
+                           vci_param_ext,
+                           dspin_rsp_width,
+                           dspin_cmd_width>(
+                     smemc.str().c_str(),
+                     mtd,                                // Mapping Table direct space
+                     mtx,                                // Mapping Table external space
+                     IntTab(cluster_id),                 // SRCID external space
+                     IntTab(cluster_id, tgtid_memc),     // TGTID direct space
+                     (cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
+                     memc_ways, memc_sets, 16,           // CACHE SIZE
+                     3,                                  // MAX NUMBER OF COPIES
+                     4096,                               // HEAP SIZE
+                     8,                                  // TRANSACTION TABLE DEPTH
+                     8,                                  // UPDATE TABLE DEPTH
+                     8,                                  // INVALIDATE TABLE DEPTH
+                     debug_start_cycle,
+                     memc_debug_ok );
+
+    wt_memc = new VciDspinTargetWrapper<vci_param_int,
+                                        dspin_cmd_width,
+                                        dspin_rsp_width>(
+                     "wt_memc",
+                     x_width + y_width + l_width);
+
+    /////////////////////////////////////////////////////////////////////////////
+    std::ostringstream sxram;
+    sxram << "xram_" << x_id << "_" << y_id;
+    xram = new VciSimpleRam<vci_param_ext>(
+                     sxram.str().c_str(),
+                     IntTab(cluster_id),
+                     mtx,
+                     loader,
+                     xram_latency);
+
+    /////////////////////////////////////////////////////////////////////////////
+    std::ostringstream sxicu;
+    sxicu << "xicu_" << x_id << "_" << y_id;
+    xicu = new VciXicu<vci_param_int>(
+                     sxicu.str().c_str(),
+                     mtd,                               // mapping table
+                     IntTab(cluster_id, tgtid_xicu),    // TGTID_D
+                     nb_procs,                          // number of timer IRQs
+                     32,                                // number of hard IRQs
+                     32,                                // number of soft IRQs
+                     nb_procs);                         // number of output IRQs
+
+    wt_xicu = new VciDspinTargetWrapper<vci_param_int,
+                                        dspin_cmd_width,
+                                        dspin_rsp_width>(
+                     "wt_xicu",
+                     x_width + y_width + l_width);
+
+    /////////////////////////////////////////////////////////////////////////////
+    std::ostringstream smdma;
+    smdma << "mdma_" << x_id << "_" << y_id;
+    mdma = new VciMultiDma<vci_param_int>(
+                     smdma.str().c_str(),
+                     mtd,
+                     IntTab(cluster_id, nb_procs),        // SRCID
+                     IntTab(cluster_id, tgtid_mdma),      // TGTID
+                     64,                                  // burst size
+                     nb_dmas);                            // number of IRQs
+
+    wt_mdma = new VciDspinTargetWrapper<vci_param_int,
+                                        dspin_cmd_width,
+                                        dspin_rsp_width>(
+                     "wt_mdma",
+                     x_width + y_width + l_width);
+
+    wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
+                                           dspin_cmd_width,
+                                           dspin_rsp_width>(
+                     "wi_mdma",
+                     x_width + y_width + l_width);
+
+    /////////////////////////////////////////////////////////////////////////////
+    size_t nb_direct_initiators      = nb_procs + 1;
+    size_t nb_direct_targets         = 3;
+    if ( io )
+    {
+        nb_direct_initiators         = nb_procs + 2;
+        nb_direct_targets            = 8;
+    }
+
+    xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
+                     "xbar_cmd_d",
+                     mtd,                          // mapping table
+                     x_id, y_id,                   // cluster coordinates
+                     x_width, y_width, l_width,
+                     nb_direct_initiators,         // number of local of sources
+                     nb_direct_targets,            // number of local dests 
+                     2, 2,                         // fifo depths  
+                     true,                         // CMD
+                     true,                         // use local routing table 
+                     false );                      // no broadcast
+
+    /////////////////////////////////////////////////////////////////////////////
+    xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
+                     "xbar_rsp_d",
+                     mtd,                          // mapping table
+                     x_id, y_id,                   // cluster coordinates
+                     x_width, y_width, l_width,
+                     nb_direct_targets,            // number of local sources
+                     nb_direct_initiators,         // number of local dests
+                     2, 2,                         // fifo depths  
+                     false,                        // RSP
+                     false,                        // don't use local routing table 
+                     false );                      // no broadcast
+
+    /////////////////////////////////////////////////////////////////////////////
+    xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
+                     "xbar_m2p_c",
+                     mtd,                          // mapping table
+                     x_id, y_id,                   // cluster coordinates
+                     x_width, y_width, l_width,
+                     1,                            // number of local sources
+                     nb_procs,                     // number of local targets 
+                     2, 2,                         // fifo depths
+                     true,                         // CMD
+                     false,                        // don't use local routing table
+                     true );                       // broadcast
+
+    /////////////////////////////////////////////////////////////////////////////
+    xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
+                     "xbar_p2m_c",
+                     mtd,                          // mapping table
+                     x_id, y_id,                   // cluster coordinates
+                     x_width, y_width, 0,          // l_width unused on p2m network
+                     nb_procs,                     // number of local sources
+                     1,                            // number of local dests
+                     2, 2,                         // fifo depths
+                     false,                        // RSP
+                     false,                        // don't use local routing table
+                     false );                      // no broadcast 
+
+    /////////////////////////////////////////////////////////////////////////////
+    xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
+                     "xbar_clack_c",
+                     mtd,                          // mapping table
+                     x_id, y_id,                   // cluster coordinates
+                     x_width, y_width, l_width,
+                     1,                            // number of local sources
+                     nb_procs,                     // number of local targets 
+                     1, 1,                         // fifo depths
+                     true,                         // CMD
+                     false,                        // don't use local routing table
+                     false);                       // broadcast
+
+    /////////////////////////////////////////////////////////////////////////////
+    router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
+                     "router_cmd",
+                     x_id,y_id,                    // coordinate in the mesh
+                     x_width, y_width,             // x & y fields width
+                     4,4);                         // input & output fifo depths
+
+    /////////////////////////////////////////////////////////////////////////////
+    router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
+                     "router_rsp",
+                     x_id,y_id,                    // coordinates in mesh
+                     x_width, y_width,             // x & y fields width
+                     4,4);                         // input & output fifo depths
+
+    // IO cluster components
+    if ( io )
+    {
+        /////////////////////////////////////////////
+        brom = new VciSimpleRom<vci_param_int>(
+                     "brom",
+                     IntTab(cluster_id, tgtid_brom),
+                     mtd,
+                     loader);
+
+        wt_brom = new VciDspinTargetWrapper<vci_param_int,
+                                            dspin_cmd_width,
+                                            dspin_rsp_width>(
+                     "wt_brom",
+                     x_width + y_width + l_width);
+
+        /////////////////////////////////////////////
+        fbuf = new VciFrameBuffer<vci_param_int>(
+                     "fbuf",
+                     IntTab(cluster_id, tgtid_fbuf),
+                     mtd,
+                     xfb, yfb);
+
+        wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
+                                            dspin_cmd_width,
+                                            dspin_rsp_width>(
+                     "wt_fbuf",
+                     x_width + y_width + l_width);
+
+        /////////////////////////////////////////////
+        bdev = new VciBlockDeviceTsar<vci_param_int>(
+                     "bdev",
+                     mtd,
+                     IntTab(cluster_id, nb_procs+1),
+                     IntTab(cluster_id, tgtid_bdev),
+                     disk_name,
+                     block_size,
+                     64);            // burst size
+
+        wt_bdev = new VciDspinTargetWrapper<vci_param_int,
+                                            dspin_cmd_width,
+                                            dspin_rsp_width>(
+                     "wt_bdev",
+                     x_width + y_width + l_width);
+
+        wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
+                                               dspin_cmd_width,
+                                               dspin_rsp_width>(
+                     "wi_bdev",
+                     x_width + y_width + l_width);
+
+        /////////////////////////////////////////////
+        mnic = new VciMultiNic<vci_param_int>(
+                     "mnic",
+                     IntTab(cluster_id, tgtid_mnic),
+                     mtd,
+                     nic_channels,
+                     nic_rx_name,
+                     nic_tx_name,
+                     0,             // mac_4 address
+                     0 );           // mac_2 address
+
+        wt_mnic = new VciDspinTargetWrapper<vci_param_int,
+                                            dspin_cmd_width,
+                                            dspin_rsp_width>(
+                     "wt_mnic",
+                     x_width + y_width + l_width);
+
+        /////////////////////////////////////////////
+        std::vector<std::string> vect_names;
+        for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
+        {
+            std::ostringstream term_name;
+            term_name <<  "term" << tid;
+            vect_names.push_back(term_name.str().c_str());
+        }
+        mtty = new VciMultiTty<vci_param_int>(
+                     "mtty",
+                     IntTab(cluster_id, tgtid_mtty),
+                     mtd,
+                     vect_names);
+
+        wt_mtty = new VciDspinTargetWrapper<vci_param_int,
+                                            dspin_cmd_width,
+                                            dspin_rsp_width>(
+                     "wt_mtty",
+                     x_width + y_width + l_width);
+    }
+
+    ////////////////////////////////////
+    // Connections are defined here
+    ////////////////////////////////////
+
+    //////////////////////// CMD ROUTER and RSP ROUTER
+    router_cmd->p_clk                        (this->p_clk);
+    router_cmd->p_resetn                     (this->p_resetn);
+    router_rsp->p_clk                        (this->p_clk);
+    router_rsp->p_resetn                     (this->p_resetn);
+    for (int x = 0; x < 2; x++)
+    {
+        for(int y = 0; y < 4; y++)
+        {
+            router_cmd->p_out[x][y]          (this->p_cmd_out[x][y]);
+            router_cmd->p_in[x][y]           (this->p_cmd_in[x][y]);
+            router_rsp->p_out[x][y]          (this->p_rsp_out[x][y]);
+            router_rsp->p_in[x][y]           (this->p_rsp_in[x][y]);
+        }
+    }
+
+    router_cmd->p_out[0][4]                  (signal_dspin_cmd_g2l_d);
+    router_cmd->p_out[1][4]                  (signal_dspin_m2p_g2l_c);
+    router_cmd->p_in[0][4]                   (signal_dspin_cmd_l2g_d);
+    router_cmd->p_in[1][4]                   (signal_dspin_m2p_l2g_c);
+
+    router_rsp->p_out[0][4]                  (signal_dspin_rsp_g2l_d);
+    router_rsp->p_out[1][4]                  (signal_dspin_p2m_g2l_c);
+    router_rsp->p_in[0][4]                   (signal_dspin_rsp_l2g_d);
+    router_rsp->p_in[1][4]                   (signal_dspin_p2m_l2g_c);
+
+    std::cout << "  - CMD & RSP routers connected" << std::endl;
+
+    ///////////////////// CMD DSPIN  local crossbar direct
+    xbar_cmd_d->p_clk                            (this->p_clk);
+    xbar_cmd_d->p_resetn                         (this->p_resetn);
+    xbar_cmd_d->p_global_out                     (signal_dspin_cmd_l2g_d);
+    xbar_cmd_d->p_global_in                      (signal_dspin_cmd_g2l_d);
+
+    xbar_cmd_d->p_local_out[tgtid_memc]          (signal_dspin_cmd_memc_t);
+    xbar_cmd_d->p_local_out[tgtid_xicu]          (signal_dspin_cmd_xicu_t);
+    xbar_cmd_d->p_local_out[tgtid_mdma]          (signal_dspin_cmd_mdma_t);
+
+    xbar_cmd_d->p_local_in[nb_procs]             (signal_dspin_cmd_mdma_i);
+
+    for (size_t p = 0; p < nb_procs; p++)
+        xbar_cmd_d->p_local_in[p]                (signal_dspin_cmd_proc_i[p]);
+
+    if ( io )
+    {
+        xbar_cmd_d->p_local_out[tgtid_mtty]      (signal_dspin_cmd_mtty_t);
+        xbar_cmd_d->p_local_out[tgtid_brom]      (signal_dspin_cmd_brom_t);
+        xbar_cmd_d->p_local_out[tgtid_bdev]      (signal_dspin_cmd_bdev_t);
+        xbar_cmd_d->p_local_out[tgtid_fbuf]      (signal_dspin_cmd_fbuf_t);
+        xbar_cmd_d->p_local_out[tgtid_mnic]      (signal_dspin_cmd_mnic_t);
+
+        xbar_cmd_d->p_local_in[nb_procs+1]       (signal_dspin_cmd_bdev_i);
+    }
+
+    std::cout << "  - Command Direct crossbar connected" << std::endl;
+
+    //////////////////////// RSP DSPIN  local crossbar direct
+    xbar_rsp_d->p_clk                            (this->p_clk);
+    xbar_rsp_d->p_resetn                         (this->p_resetn);
+    xbar_rsp_d->p_global_out                     (signal_dspin_rsp_l2g_d);
+    xbar_rsp_d->p_global_in                      (signal_dspin_rsp_g2l_d);
+
+    xbar_rsp_d->p_local_in[tgtid_memc]           (signal_dspin_rsp_memc_t);
+    xbar_rsp_d->p_local_in[tgtid_xicu]           (signal_dspin_rsp_xicu_t);
+    xbar_rsp_d->p_local_in[tgtid_mdma]           (signal_dspin_rsp_mdma_t);
+
+    xbar_rsp_d->p_local_out[nb_procs]            (signal_dspin_rsp_mdma_i);
+
+    for (size_t p = 0; p < nb_procs; p++)
+        xbar_rsp_d->p_local_out[p]               (signal_dspin_rsp_proc_i[p]);
+
+    if ( io )
+    {
+        xbar_rsp_d->p_local_in[tgtid_mtty]       (signal_dspin_rsp_mtty_t);
+        xbar_rsp_d->p_local_in[tgtid_brom]       (signal_dspin_rsp_brom_t);
+        xbar_rsp_d->p_local_in[tgtid_bdev]       (signal_dspin_rsp_bdev_t);
+        xbar_rsp_d->p_local_in[tgtid_fbuf]       (signal_dspin_rsp_fbuf_t);
+        xbar_rsp_d->p_local_in[tgtid_mnic]       (signal_dspin_rsp_mnic_t);
+
+        xbar_rsp_d->p_local_out[nb_procs+1]      (signal_dspin_rsp_bdev_i);
+    }
+
+    std::cout << "  - Response Direct crossbar connected" << std::endl;
+
+    ////////////////////// M2P DSPIN local crossbar coherence
+    xbar_m2p_c->p_clk                            (this->p_clk);
+    xbar_m2p_c->p_resetn                         (this->p_resetn);
+    xbar_m2p_c->p_global_out                     (signal_dspin_m2p_l2g_c);
+    xbar_m2p_c->p_global_in                      (signal_dspin_m2p_g2l_c);
+    xbar_m2p_c->p_local_in[0]                    (signal_dspin_m2p_memc);
+    for (size_t p = 0; p < nb_procs; p++)
+        xbar_m2p_c->p_local_out[p]               (signal_dspin_m2p_proc[p]);
+
+    std::cout << "  - M2P Coherence crossbar connected" << std::endl;
+
+    ////////////////////// CLACK DSPIN local crossbar coherence
+    xbar_clack_c->p_clk                          (this->p_clk);
+    xbar_clack_c->p_resetn                       (this->p_resetn);
+    xbar_clack_c->p_global_out                   (signal_dspin_clack_l2g_c);
+    xbar_clack_c->p_global_in                    (signal_dspin_clack_g2l_c);
+    xbar_clack_c->p_local_in[0]                  (signal_dspin_clack_memc);
+    for (size_t p = 0; p < nb_procs; p++)
+        xbar_clack_c->p_local_out[p]               (signal_dspin_clack_proc[p]);
+
+    std::cout << "  - Clack Coherence crossbar connected" << std::endl;
+
+    ////////////////////////// P2M DSPIN local crossbar coherence
+    xbar_p2m_c->p_clk                            (this->p_clk);
+    xbar_p2m_c->p_resetn                         (this->p_resetn);
+    xbar_p2m_c->p_global_out                     (signal_dspin_p2m_l2g_c);
+    xbar_p2m_c->p_global_in                      (signal_dspin_p2m_g2l_c);
+    xbar_p2m_c->p_local_out[0]                   (signal_dspin_p2m_memc);
+    for (size_t p = 0; p < nb_procs; p++)
+        xbar_p2m_c->p_local_in[p]                (signal_dspin_p2m_proc[p]);
+
+    std::cout << "  - P2M Coherence crossbar connected" << std::endl;
+
+
+    //////////////////////////////////// Processors
+    for (size_t p = 0; p < nb_procs; p++)
+    {
+        proc[p]->p_clk                      (this->p_clk);
+        proc[p]->p_resetn                   (this->p_resetn);
+        proc[p]->p_vci                      (signal_vci_ini_proc[p]);
+        proc[p]->p_dspin_m2p                (signal_dspin_m2p_proc[p]);
+        proc[p]->p_dspin_p2m                (signal_dspin_p2m_proc[p]);
+        proc[p]->p_dspin_clack              (signal_dspin_clack_proc[p]);
+        proc[p]->p_irq[0]                   (signal_proc_it[p]);
+        for ( size_t j = 1 ; j < 6 ; j++)
+        {
+            proc[p]->p_irq[j]               (signal_false);
+        }
+
+        wi_proc[p]->p_clk                   (this->p_clk);
+        wi_proc[p]->p_resetn                (this->p_resetn);
+        wi_proc[p]->p_dspin_cmd             (signal_dspin_cmd_proc_i[p]);
+        wi_proc[p]->p_dspin_rsp             (signal_dspin_rsp_proc_i[p]);
+        wi_proc[p]->p_vci                   (signal_vci_ini_proc[p]);
+    }
+
+    std::cout << "  - Processors connected" << std::endl;
+
+    ///////////////////////////////////// XICU
+    xicu->p_clk                        (this->p_clk);
+    xicu->p_resetn                     (this->p_resetn);
+    xicu->p_vci                        (signal_vci_tgt_xicu);
+    for ( size_t p=0 ; p<nb_procs ; p++)
+    {
+        xicu->p_irq[p]                 (signal_proc_it[p]);
+    }
+    for ( size_t i=0 ; i<32 ; i++)
+    {
+        if ( io ) // I/O cluster
+        {
+            if      (i < 8)                  xicu->p_hwi[i] (signal_false);
+            else if (i < (8 + nb_dmas))      xicu->p_hwi[i] (signal_irq_mdma[i-8]);
+            else if (i < 16)                 xicu->p_hwi[i] (signal_false);
+            else if (i < (16 + nb_ttys))     xicu->p_hwi[i] (signal_irq_mtty[i-16]);
+            else if (i < 31)                 xicu->p_hwi[i] (signal_false);
+            else                             xicu->p_hwi[i] (signal_irq_bdev);
+        }
+        else      // other clusters
+        {
+            if      (i < 8)                  xicu->p_hwi[i] (signal_false);
+            else if (i < (8 + nb_dmas))      xicu->p_hwi[i] (signal_irq_mdma[i-8]);
+            else                             xicu->p_hwi[i] (signal_false);
+        }
+    }
+
+    // wrapper XICU
+    wt_xicu->p_clk                     (this->p_clk);
+    wt_xicu->p_resetn                  (this->p_resetn);
+    wt_xicu->p_dspin_cmd               (signal_dspin_cmd_xicu_t);
+    wt_xicu->p_dspin_rsp               (signal_dspin_rsp_xicu_t);
+    wt_xicu->p_vci                     (signal_vci_tgt_xicu);
+
+    std::cout << "  - XICU connected" << std::endl;
+
+    //////////////////////////////////////////////// MEMC
+    memc->p_clk                        (this->p_clk);
+    memc->p_resetn                     (this->p_resetn);
+    memc->p_vci_ixr                    (signal_vci_xram);
+    memc->p_vci_tgt                    (signal_vci_tgt_memc);
+    memc->p_dspin_p2m                  (signal_dspin_p2m_memc);
+    memc->p_dspin_m2p                  (signal_dspin_m2p_memc);
+    memc->p_dspin_clack                (signal_dspin_clack_memc);
+
+    // wrapper MEMC
+    wt_memc->p_clk                     (this->p_clk);
+    wt_memc->p_resetn                  (this->p_resetn);
+    wt_memc->p_dspin_cmd               (signal_dspin_cmd_memc_t);
+    wt_memc->p_dspin_rsp               (signal_dspin_rsp_memc_t);
+    wt_memc->p_vci                     (signal_vci_tgt_memc);
+
+    std::cout << "  - MEMC connected" << std::endl;
+
+    /////////////////////////////////////////////// XRAM
+    xram->p_clk                        (this->p_clk);
+    xram->p_resetn                     (this->p_resetn);
+    xram->p_vci                        (signal_vci_xram);
+
+    std::cout << "  - XRAM connected" << std::endl;
+
+    ////////////////////////////////////////////// MDMA
+    mdma->p_clk                        (this->p_clk);
+    mdma->p_resetn                     (this->p_resetn);
+    mdma->p_vci_target                 (signal_vci_tgt_mdma);
+    mdma->p_vci_initiator              (signal_vci_ini_mdma);
+    for (size_t i=0 ; i<nb_dmas ; i++)
+        mdma->p_irq[i]                 (signal_irq_mdma[i]);
+
+    // wrapper tgt MDMA
+    wt_mdma->p_clk                     (this->p_clk);
+    wt_mdma->p_resetn                  (this->p_resetn);
+    wt_mdma->p_dspin_cmd               (signal_dspin_cmd_mdma_t);
+    wt_mdma->p_dspin_rsp               (signal_dspin_rsp_mdma_t);
+    wt_mdma->p_vci                     (signal_vci_tgt_mdma);
+
+    // wrapper ini MDMA
+    wi_mdma->p_clk                     (this->p_clk);
+    wi_mdma->p_resetn                  (this->p_resetn);
+    wi_mdma->p_dspin_cmd               (signal_dspin_cmd_mdma_i);
+    wi_mdma->p_dspin_rsp               (signal_dspin_rsp_mdma_i);
+    wi_mdma->p_vci                     (signal_vci_ini_mdma);
+
+    std::cout << "  - MDMA connected" << std::endl;
+
+    /////////////////////////////// Components in I/O cluster
+
+    if ( io )
+    {
+        // BDEV
+        bdev->p_clk                    (this->p_clk);
+        bdev->p_resetn                 (this->p_resetn);
+        bdev->p_irq                    (signal_irq_bdev);
+        bdev->p_vci_target             (signal_vci_tgt_bdev);
+        bdev->p_vci_initiator          (signal_vci_ini_bdev);
+
+        // wrapper tgt BDEV
+        wt_bdev->p_clk                 (this->p_clk);
+        wt_bdev->p_resetn              (this->p_resetn);
+        wt_bdev->p_dspin_cmd           (signal_dspin_cmd_bdev_t);
+        wt_bdev->p_dspin_rsp           (signal_dspin_rsp_bdev_t);
+        wt_bdev->p_vci                 (signal_vci_tgt_bdev);
+
+        // wrapper ini BDEV
+        wi_bdev->p_clk                 (this->p_clk);
+        wi_bdev->p_resetn              (this->p_resetn);
+        wi_bdev->p_dspin_cmd           (signal_dspin_cmd_bdev_i);
+        wi_bdev->p_dspin_rsp           (signal_dspin_rsp_bdev_i);
+        wi_bdev->p_vci                 (signal_vci_ini_bdev);
+
+        std::cout << "  - BDEV connected" << std::endl;
+
+        // FBUF
+        fbuf->p_clk                    (this->p_clk);
+        fbuf->p_resetn                 (this->p_resetn);
+        fbuf->p_vci                    (signal_vci_tgt_fbuf);
+
+        // wrapper tgt FBUF
+        wt_fbuf->p_clk                 (this->p_clk);
+        wt_fbuf->p_resetn              (this->p_resetn);
+        wt_fbuf->p_dspin_cmd           (signal_dspin_cmd_fbuf_t);
+        wt_fbuf->p_dspin_rsp           (signal_dspin_rsp_fbuf_t);
+        wt_fbuf->p_vci                 (signal_vci_tgt_fbuf);
+
+        std::cout << "  - FBUF connected" << std::endl;
+
+        // MNIC
+        mnic->p_clk                    (this->p_clk);
+        mnic->p_resetn                 (this->p_resetn);
+        mnic->p_vci                    (signal_vci_tgt_mnic);
+        for ( size_t i=0 ; i<nic_channels ; i++ )
+        {
+            mnic->p_rx_irq[i]          (signal_irq_mnic_rx[i]);
+            mnic->p_tx_irq[i]          (signal_irq_mnic_tx[i]);
+        }
+
+        // wrapper tgt MNIC
+        wt_mnic->p_clk                 (this->p_clk);
+        wt_mnic->p_resetn              (this->p_resetn);
+        wt_mnic->p_dspin_cmd           (signal_dspin_cmd_mnic_t);
+        wt_mnic->p_dspin_rsp           (signal_dspin_rsp_mnic_t);
+        wt_mnic->p_vci                 (signal_vci_tgt_mnic);
+
+        std::cout << "  - MNIC connected" << std::endl;
+
+        // BROM
+        brom->p_clk                    (this->p_clk);
+        brom->p_resetn                 (this->p_resetn);
+        brom->p_vci                    (signal_vci_tgt_brom);
+
+        // wrapper tgt BROM
+        wt_brom->p_clk                 (this->p_clk);
+        wt_brom->p_resetn              (this->p_resetn);
+        wt_brom->p_dspin_cmd           (signal_dspin_cmd_brom_t);
+        wt_brom->p_dspin_rsp           (signal_dspin_rsp_brom_t);
+        wt_brom->p_vci                 (signal_vci_tgt_brom);
+
+        std::cout << "  - BROM connected" << std::endl;
+
+        // MTTY
+        mtty->p_clk                    (this->p_clk);
+        mtty->p_resetn                 (this->p_resetn);
+        mtty->p_vci                    (signal_vci_tgt_mtty);
+        for ( size_t i=0 ; i<nb_ttys ; i++ )
+        {
+            mtty->p_irq[i]             (signal_irq_mtty[i]);
+        }
+
+        // wrapper tgt MTTY
+        wt_mtty->p_clk                 (this->p_clk);
+        wt_mtty->p_resetn              (this->p_resetn);
+        wt_mtty->p_dspin_cmd           (signal_dspin_cmd_mtty_t);
+        wt_mtty->p_dspin_rsp           (signal_dspin_rsp_mtty_t);
+        wt_mtty->p_vci                 (signal_vci_tgt_mtty);
+
+        std::cout << "  - MTTY connected" << std::endl;
+   }
+} // end constructor
+
+}}
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+
+
+