Changeset 449 for trunk/modules/vci_mem_cache/caba/source/src
- Timestamp:
- Jul 18, 2013, 5:54:32 PM (11 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r439 r449 518 518 r_cas_rdata = new sc_signal<data_t>[2]; 519 519 520 // Allocation for debug 521 m_debug_previous_data = new sc_signal<data_t>[nwords]; 522 m_debug_data = new sc_signal<data_t>[nwords]; 520 523 521 524 SC_METHOD(transition); … … 545 548 546 549 //////////////////////////////////////////////// 547 tmpl(void) ::check_monitor( const char *buf, 548 addr_t addr, 550 tmpl(void) ::check_monitor( addr_t addr, 549 551 data_t data, 550 552 bool read ) … … 554 556 (addr < m_monitor_base + m_monitor_length)) 555 557 { 556 if ( read ) std::cout << " Monitor MEMC Read "; 557 else std::cout << " Monitor MEMC Write "; 558 std::cout << buf 559 << " / Address = " << std::hex << addr 558 if ( read ) std::cout << " Monitor MEMC Read "; 559 else std::cout << " Monitor MEMC Write"; 560 std::cout << " / Address = " << std::hex << addr 560 561 << " / Data = " << data 561 562 << " at cycle " << std::dec << m_cpt_cycles << std::endl; … … 564 565 565 566 ///////////////////////////////////////////////////// 566 tmpl(void) ::c opies_monitor(addr_t addr)567 tmpl(void) ::cache_monitor(addr_t addr) 567 568 ///////////////////////////////////////////////////// 568 569 { 569 DirectoryEntry entry = m_cache_directory.read_neutral(addr); 570 571 if((entry.count != m_debug_previous_count) or 572 (entry.valid != m_debug_previous_hit)) 573 { 574 std::cout << "Monitor MEMC " << name() 575 << " at cycle " << std::dec << m_cpt_cycles 576 << " for address " << std::hex << addr 577 << " / HIT = " << entry.valid 578 << " / COUNT = " << std::dec << entry.count << std::endl; 579 } 580 m_debug_previous_count = entry.count; 581 m_debug_previous_hit = entry.valid; 570 size_t way = 0; 571 size_t set = 0; 572 DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set ); 573 574 bool data_change = false; 575 576 if ( entry.valid ) 577 { 578 m_cache_data.read_line( way, set, m_debug_data ); 579 580 for ( size_t i = 0 ; i<m_words ; i++ ) 581 { 582 if ( m_debug_previous_valid and 583 (m_debug_data[i].read() != m_debug_previous_data[i].read()) ) 584 data_change = true; 585 m_debug_previous_data[i] = m_debug_data[i].read(); 586 } 587 } 588 589 if ( (entry.valid != m_debug_previous_valid) or 590 (entry.valid and (entry.count != m_debug_previous_count)) or 591 (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change ) 592 { 593 std::cout << "Monitor MEMC " << name() 594 << " at cycle " << std::dec << m_cpt_cycles 595 << " for address " << std::hex << addr 596 << " / HIT = " << std::dec << entry.valid 597 << " / WAY = " << way 598 << " / COUNT = " << entry.count 599 << " / DIRTY = " << entry.dirty 600 << " / DATA_CHANGE = " << entry.count 601 << std::endl; 602 } 603 m_debug_previous_count = entry.count; 604 m_debug_previous_valid = entry.valid; 605 m_debug_previous_dirty = entry.dirty; 582 606 } 583 607 … … 683 707 684 708 m_debug = false; 685 m_debug_previous_hit = false; 709 m_debug_previous_valid = false; 710 m_debug_previous_dirty = false; 686 711 m_debug_previous_count = 0; 687 712 … … 1428 1453 // 1429 1454 // From the software point of view, a configuration request is a sequence 1430 // of 6 atomic accesses :1455 // of 6 atomic accesses in an uncached segment: 1431 1456 // - Read MEMC_LOCK : Get the lock 1432 1457 // - Write MEMC_ADDR_LO : Set the buffer address LSB … … 1583 1608 nb_copies, 1584 1609 index); 1610 1585 1611 if ( wok ) // UPT success => inval DIR slot 1586 1612 { … … 1865 1891 DirectoryEntry entry = 1866 1892 m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); 1867 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) // access the global table ONLY when we have an LL cmd 1893 // access the global table ONLY when we have an LL cmd 1894 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) 1868 1895 { 1869 1896 r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); … … 1927 1954 1928 1955 ////////////////// 1929 case READ_DIR_HIT: 1930 { 1931 // read data in cache & update the directory 1932 // we enter this state in 3 cases: 1933 // - the read request is uncachable 1934 // - the cache line is in counter mode 1935 // - the cache line is valid but not replcated 1936 1937 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 1938 { 1939 // check if this is an instruction read, this means pktid is either 1940 // TYPE_READ_INS_UNC 0bX010 with TSAR encoding 1941 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 1942 bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 1943 // check if this is a cached read, this means pktid is either 1944 // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding 1945 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 1946 bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); 1947 bool is_cnt = r_read_is_cnt.read(); 1948 1949 // read data in the cache 1950 size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; 1951 size_t way = r_read_way.read(); 1952 1953 m_cache_data.read_line(way, set, r_read_data); 1954 1955 // update the cache directory 1956 DirectoryEntry entry; 1957 entry.valid = true; 1958 entry.is_cnt = is_cnt; 1959 entry.dirty = r_read_dirty.read(); 1960 entry.tag = r_read_tag.read(); 1961 entry.lock = r_read_lock.read(); 1962 entry.ptr = r_read_ptr.read(); 1963 if(cached_read) // Cached read => we must update the copies 1964 { 1965 if(!is_cnt) // Not counter mode 1966 { 1967 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 1956 case READ_DIR_HIT: // read data in cache & update the directory 1957 // we enter this state in 3 cases: 1958 // - the read request is uncachable 1959 // - the cache line is in counter mode 1960 // - the cache line is valid but not replicated 1961 1962 { 1963 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 1964 { 1965 // check if this is an instruction read, this means pktid is either 1966 // TYPE_READ_INS_UNC 0bX010 with TSAR encoding 1967 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 1968 bool inst_read = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 1969 // check if this is a cached read, this means pktid is either 1970 // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding 1971 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 1972 bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); 1973 bool is_cnt = r_read_is_cnt.read(); 1974 1975 // read data in the cache 1976 size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; 1977 size_t way = r_read_way.read(); 1978 1979 m_cache_data.read_line(way, set, r_read_data); 1980 1981 if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); 1982 1983 // update the cache directory 1984 DirectoryEntry entry; 1985 entry.valid = true; 1986 entry.is_cnt = is_cnt; 1987 entry.dirty = r_read_dirty.read(); 1988 entry.tag = r_read_tag.read(); 1989 entry.lock = r_read_lock.read(); 1990 entry.ptr = r_read_ptr.read(); 1991 1992 if(cached_read) // Cached read => we must update the copies 1993 { 1994 if(!is_cnt) // Not counter mode 1995 { 1996 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 1968 1997 #if L1_MULTI_CACHE 1969 entry.owner.cache_id = m_cmd_read_pktid_fifo.read();1970 #endif 1971 entry.owner.inst = inst_read;1972 entry.count = r_read_count.read() + 1;1973 }1974 else // Counter mode1975 {1976 entry.owner.srcid = 0;1998 entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); 1999 #endif 2000 entry.owner.inst = inst_read; 2001 entry.count = r_read_count.read() + 1; 2002 } 2003 else // Counter mode 2004 { 2005 entry.owner.srcid = 0; 1977 2006 #if L1_MULTI_CACHE 1978 entry.owner.cache_id = 0;1979 #endif 1980 entry.owner.inst = false;1981 entry.count = r_read_count.read() + 1;1982 }1983 }1984 else// Uncached read1985 {1986 entry.owner.srcid = r_read_copy.read();2007 entry.owner.cache_id = 0; 2008 #endif 2009 entry.owner.inst = false; 2010 entry.count = r_read_count.read() + 1; 2011 } 2012 } 2013 else // Uncached read 2014 { 2015 entry.owner.srcid = r_read_copy.read(); 1987 2016 #if L1_MULTI_CACHE 1988 entry.owner.cache_id = r_read_copy_cache.read();1989 #endif 1990 entry.owner.inst = r_read_copy_inst.read();1991 entry.count = r_read_count.read();1992 }2017 entry.owner.cache_id = r_read_copy_cache.read(); 2018 #endif 2019 entry.owner.inst = r_read_copy_inst.read(); 2020 entry.count = r_read_count.read(); 2021 } 1993 2022 1994 2023 #if DEBUG_MEMC_READ … … 2004 2033 #endif 2005 2034 2006 if(m_monitor_ok) 2007 { 2008 char buf[80]; 2009 snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", 2010 (int)m_cmd_read_srcid_fifo.read(), 2011 (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0)); 2012 check_monitor(buf, m_cmd_read_addr_fifo.read(), r_read_data[0], true); 2013 } 2014 2015 2016 m_cache_directory.write(set, way, entry); 2017 r_read_fsm = READ_RSP; 2018 } 2019 break; 2020 } 2021 2035 m_cache_directory.write(set, way, entry); 2036 r_read_fsm = READ_RSP; 2037 } 2038 break; 2039 } 2022 2040 /////////////////// 2023 2041 case READ_HEAP_REQ: // Get the lock to the HEAP directory … … 2050 2068 2051 2069 m_cache_data.read_line(way, set, r_read_data); 2070 2071 if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); 2052 2072 2053 2073 // update the cache directory … … 2417 2437 2418 2438 #if DEBUG_MEMC_WRITE 2419 if(m_debug) 2420 { 2421 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 2422 << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read() 2423 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 2424 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 2425 } 2439 if(m_debug) 2440 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 2441 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() 2442 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 2443 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 2426 2444 #endif 2427 2445 } … … 2436 2454 2437 2455 #if DEBUG_MEMC_WRITE 2438 if(m_debug) 2439 { 2440 std::cout << " <MEMC " << name() 2441 << " WRITE_NEXT> Write another word in local buffer" 2442 << std::endl; 2443 } 2456 if(m_debug) 2457 std::cout << " <MEMC " << name() 2458 << " WRITE_NEXT> Write another word in local buffer" 2459 << std::endl; 2444 2460 #endif 2445 2461 m_cpt_write_cells++; … … 2520 2536 2521 2537 #if DEBUG_MEMC_WRITE 2522 if(m_debug) 2523 { 2524 std::cout 2525 << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock " 2526 << std::endl; 2527 } 2538 if(m_debug) 2539 std::cout << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock " 2540 << std::endl; 2528 2541 #endif 2529 2542 … … 2532 2545 2533 2546 //////////////////// 2534 case WRITE_DIR_LOCK: 2535 // access directory to check hit/miss 2547 case WRITE_DIR_LOCK: // access directory to check hit/miss 2536 2548 { 2537 2549 if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) … … 2570 2582 2571 2583 #if DEBUG_MEMC_WRITE 2572 2573 2574 2575 2576 << "hit = " << std::dec << entry.valid2577 << "count = " << entry.count2578 << " is_cnt = " << entry.is_cnt << std::endl;2579 2580 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_tableSC access" << std::endl;2581 2582 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_tableSW access" << std::endl;2583 2584 if(m_debug) 2585 { 2586 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: " 2587 << " address = " << std::hex << r_write_address.read() 2588 << " / hit = " << std::dec << entry.valid 2589 << " / count = " << entry.count 2590 << " / is_cnt = " << entry.is_cnt ; 2591 if((r_write_pktid.read() & 0x7) == TYPE_SC) 2592 std::cout << " / SC access" << std::endl; 2593 else 2594 std::cout << " / SW access" << std::endl; 2595 } 2584 2596 #endif 2585 2597 } … … 2592 2604 exit(0); 2593 2605 } 2594 2595 break; 2596 } 2597 2606 break; 2607 } 2598 2608 //////////////////// 2599 2609 case WRITE_DIR_READ: // read the cache and complete the buffer when be!=0xF … … 2620 2630 2621 2631 #if DEBUG_MEMC_WRITE 2622 if(m_debug) 2623 { 2624 std::cout << " <MEMC " << name() << " WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl; 2625 } 2632 if(m_debug) 2633 std::cout << " <MEMC " << name() << " WRITE_DIR_READ>" 2634 << " Read the cache to complete local buffer" << std::endl; 2626 2635 #endif 2627 2636 break; … … 2636 2645 entry.valid = true; 2637 2646 entry.dirty = true; 2638 entry.tag = r_write_tag.read();2647 entry.tag = r_write_tag.read(); 2639 2648 entry.is_cnt = r_write_is_cnt.read(); 2640 2649 entry.lock = r_write_lock.read(); … … 2663 2672 // (tests for sc requests) 2664 2673 bool no_update = ( (r_write_count.read() == 0) or 2665 (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC))); 2674 (owner and (r_write_count.read() ==1) and 2675 (r_write_pktid.read() != TYPE_SC))); 2666 2676 2667 2677 // write data in the cache if no coherence transaction … … 2675 2685 { 2676 2686 addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; 2677 char buf[80]; 2678 snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", 2679 (int)r_write_srcid.read()); 2680 check_monitor(buf, address, r_write_data[word].read(), false); 2687 check_monitor( address, r_write_data[word].read(), false); 2681 2688 } 2682 2689 } … … 2727 2734 break; 2728 2735 } 2729 2730 2736 //////////////////// 2731 2737 case WRITE_UPT_LOCK: // Try to register the update request in UPT … … 2766 2772 { 2767 2773 addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2; 2768 char buf[80]; 2769 snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", (int)srcid); 2770 check_monitor(buf, address, r_write_data[word].read(), false); 2774 check_monitor( address, r_write_data[word].read(), false); 2771 2775 } 2772 2776 } … … 3868 3872 { 3869 3873 addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2; 3870 check_monitor( "XRAM_RSP_DIR_UPDT",address, r_xram_rsp_trt_buf.wdata[word], false);3874 check_monitor( address, r_xram_rsp_trt_buf.wdata[word], false); 3871 3875 } 3872 3876 } … … 5262 5266 { 5263 5267 addr_t address = m_cmd_cas_addr_fifo.read(); 5264 char buf[80]; 5265 snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 5266 (int)m_cmd_cas_srcid_fifo.read()); 5267 check_monitor(buf, address, r_cas_wdata.read(), false); 5268 check_monitor( address, r_cas_wdata.read(), false); 5268 5269 5269 5270 if(r_cas_cpt.read() == 4) 5270 check_monitor( buf,address+4, m_cmd_cas_wdata_fifo.read(), false);5271 check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); 5271 5272 } 5272 5273 … … 5327 5328 { 5328 5329 addr_t address = m_cmd_cas_addr_fifo.read(); 5329 char buf[80]; 5330 snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 5331 (int)m_cmd_cas_srcid_fifo.read()); 5332 check_monitor(buf, address, r_cas_wdata.read(), false); 5330 check_monitor( address, r_cas_wdata.read(), false); 5333 5331 5334 5332 if(r_cas_cpt.read() ==4) 5335 check_monitor( buf,address+4, m_cmd_cas_wdata_fifo.read(), false);5333 check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); 5336 5334 } 5337 5335 } … … 5564 5562 { 5565 5563 addr_t address = m_cmd_cas_addr_fifo.read(); 5566 char buf[80]; 5567 snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", 5568 (int)m_cmd_cas_srcid_fifo.read()); 5569 check_monitor(buf, address, r_cas_wdata.read(), false); 5564 check_monitor( address, r_cas_wdata.read(), false); 5565 5570 5566 if(r_cas_cpt.read() ==4) 5571 check_monitor( buf,address+4, m_cmd_cas_wdata_fifo.read(), false);5567 check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false); 5572 5568 } 5573 5569 r_cas_upt_index = index;
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