Index: trunk/platforms/tsar_generic_iob/Makefile =================================================================== --- trunk/platforms/tsar_generic_iob/Makefile (revision 450) +++ trunk/platforms/tsar_generic_iob/Makefile (revision 450) @@ -0,0 +1,6 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x tty* Index: trunk/platforms/tsar_generic_iob/giet_vm =================================================================== --- trunk/platforms/tsar_generic_iob/giet_vm (revision 450) +++ trunk/platforms/tsar_generic_iob/giet_vm (revision 450) @@ -0,0 +1,1 @@ +link ../../../giet_vm Index: trunk/platforms/tsar_generic_iob/soclib.conf =================================================================== --- trunk/platforms/tsar_generic_iob/soclib.conf (revision 450) +++ trunk/platforms/tsar_generic_iob/soclib.conf (revision 450) @@ -0,0 +1,2 @@ + +config.addDescPath("/Users/alain/soc/tsar-trunk-svn-2013/") Index: trunk/platforms/tsar_generic_iob/top.cpp =================================================================== --- trunk/platforms/tsar_generic_iob/top.cpp (revision 450) +++ trunk/platforms/tsar_generic_iob/top.cpp (revision 450) @@ -0,0 +1,1482 @@ +/////////////////////////////////////////////////////////////////////////////// +// File: top.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : august 2013 +// This program is released under the GNU public license +/////////////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture using an IO network emulating +// an external bus (i.e. Hypertransport) to access external peripherals: +// +// - boot rom (BROM) +// - disk controller (BDEV) +// - multi-channel network controller (MNIC) +// - multi-channel chbuf dma controller (CDMA) +// - multi-channel tty controller (MTTY) +// - frame buffer controller (FBUF) +// +// The internal physical address space is 40 bits. +// +// It contains a 2D mesh of clusters communicating through 3 networks: +// +// 1) the INT network supports Read/Write transactions +// between processors and L2 caches or peripherals. +// (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) +// It supports also coherence transactions between L1 & L2 caches. +// 3) the RAM network is emulating the 3D network between L2 caches +// and L3 caches, and is implemented as a 2D network between L2 caches, +// the two IO bridges and physical RAMs disributed in all clusters. +// (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) +// 4) the IOX network connects the two IO bridge components to the +// 6 external peripheral controllers. +// (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) +// +// The top-cell contains XMAX * YMAX clusters, plus a VGMN component +// implementing the IO network, plus 6 external peripherals : +// +// All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) +// contain an extra IO bridge component. These IOB0 & IOB1 components are +// connected to the three networks (INT, RAM, IOX). +// The number of clusters cannot be larger than 256. +// The number of processors per cluster cannot be larger than 8. +// +// - It uses two dspin_local_crossbar per cluster to implement the +// local interconnect correponding to the INT network. +// - It uses two dspin_local_crossbar per cluster to implement the +// local interconnect correponding to the coherence INT network. +// - It uses two virtual_dspin_router per cluster to implement +// the INT network (routing both the direct and coherence trafic). +// - It uses two dspin_router per cluster to implement the RAM network. +// - It uses the vci_cc_vcache_wrapper. +// - It uses the vci_mem_cache. +// - It contains one vci_xicu and one vci_multi_dma per cluster. +// - It contains one vci_simple ram per cluster to model the L3 cache. +// +// The TsarIobCluster component is defined in files +// tsar_iob_cluster.* (with * = cpp, h, sd) +// +// In all clusters, the IRQs are connected to XICU as follow: +// - IRQ_IN[0] to IRQ_IN[3] are connected to 4 MDMA channels +// +// In cluster(0,0), the IRQs are connected to XICUs as follow: +// - IRQ_IN[0] to IRQ_IN[3] are connected to 4 MDMA channels. +// - IRQ_IN[4] to IRQ_IN[5] are connected to 2 NIC_RX channels. +// - IRQ_IN[6] to IRQ_IN[7] are connected to 2 NIC_TX channels. +// - IRQ_IN[8] to IRQ_IN[11] are connected to 4 CDMA channels +// - IRQ_IN[12] to IRQ_IN[30] are connected to 19 TTY channels +// - IRQ_IN[31] is connected to BDEV +// +// The main hardware parameters must be defined in the hard_config.h file : +// - XMAX : number of clusters in a row (power of 2) +// - YMAX : number of clusters in a column (power of 2) +// - CLUSTER_SIZE : size of the segment allocated to a cluster +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) +// - NB_TTY_CHANNELS : number of TTY channels in I/O network (< 16) +// - NB_NIC_CHANNELS : number of NIC channels in I/O network (< 9) +// +// Some secondary hardware parameters must be defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - BDEV_SECTOR_SIZE : block size for block drvice +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_TIMEOUT : max number of cycles before closing a container +// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// | X_ID | Y_ID |---| LADR | OFFSET | +// |x_width|y_width|---| 8 | 24 | +// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// | X_ID | Y_ID |---| L_ID | +// |x_width|y_width|---| 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" + +#include "tsar_iob_cluster.h" +#include "vci_chbuf_dma.h" +#include "vci_multi_tty.h" +#include "vci_multi_nic.h" +#include "vci_simple_rom.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "vci_iox_network.h" + +#include "alloc_elems.h" + +/////////////////////////////////////////////////// +// OS +/////////////////////////////////////////////////// +#define USE_ALMOS 0 + +#define almos_bootloader_pathname "bootloader.bin" +#define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" +#define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// +#define USE_OPENMP 0 + +#if USE_OPENMP +#include +#endif + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define dspin_int_cmd_width 39 +#define dspin_int_rsp_width 32 + +#define dspin_ram_cmd_width 64 +#define dspin_ram_rsp_width 64 + +/////////////////////////////////////////////////////////// +// VCI fields width for the 3 VCI networks +/////////////////////////////////////////////////////////// + +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 + +#define vci_plen_width 8 +#define vci_address_width 40 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Main Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#include "giet_vm/hard_config.h" + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#define XMAX CLUSTER_X +#define YMAX CLUSTER_Y + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 + +#define BDEV_SECTOR_SIZE 512 +#define BDEV_IMAGE_NAME "giet_vm/display/images.raw" + +#define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" +#define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" +#define NIC_TIMEOUT 10000 + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +#define cluster(x,y) ((y) + YMAX*(x)) + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM & RAM +//////////////////////i///////////////////////////////////// + +#define BOOT_SOFT_NAME "giet_vm/soft.elf" + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////i///////////////////////////////////// + +#define MAX_FROZEN_CYCLES 10000 + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// + +// Non replicated peripherals + +#define BROM_BASE 0x00BFC00000 +#define BROM_SIZE 0x0000100000 // 1 M Kbytes + +#define IOBX_BASE 0x00BE000000 +#define IOBX_SIZE 0x0000001000 // 4 K Kbytes + +#define BDEV_BASE 0x00B3000000 +#define BDEV_SIZE 0x0000001000 // 4 Kbytes + +#define MTTY_BASE 0x00B4000000 +#define MTTY_SIZE 0x0000001000 * NB_TTY_CHANNELS // 4 Kbytes + +#define MNIC_BASE 0x00B5000000 +#define MNIC_SIZE 0x0000080000 // 512 Kbytes + +#define CDMA_BASE 0x00B6000000 +#define CDMA_SIZE 0x0000001000 * (NB_NIC_CHANNELS * 2) // 4 Kbytes per channel + +#define FBUF_BASE 0x00B7000000 +#define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE + +// replicated segments : address is incremented by a cluster offset +// offset = cluster(x,y) << (address_width-x_width-y_width); + +#define XRAM_BASE 0x0000000000 +#define XRAM_SIZE 0x0010000000 // 256 Mbytes + +#define XICU_BASE 0x00B0000000 +#define XICU_SIZE 0x0000001000 // 4 Kbytes + +#define MDMA_BASE 0x00B1000000 +#define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel + +#define MEMC_BASE 0x00B2000000 +#define MEMC_SIZE 0x0000001000 // 4 Kbytes + + +//////////////////////////////////////////////////////////////////////// +// SRCID definition +//////////////////////////////////////////////////////////////////////// +// All initiators are in the same indexing space (14 bits). +// The SRCID is structured in two fields: +// - The 10 MSB bits define the cluster index (left aligned) +// - The 4 LSB bits define the local index. +// Two different initiators cannot have the same SRCID, but a given +// initiator can have two alias SRCIDs: +// - Internal initiators (procs, mdma) are replicated in all clusters, +// and each initiator has one single SRCID. +// - External initiators (bdev, cdma) are not replicated, but can be +// accessed in 2 clusters : cluster_iob0 and cluster_iob1. +// They have the same local index, but two different cluster indexes. +// As cluster_iob0 and cluster_iob1 contain both internal initiators +// and external initiators, they must have different local indexes. +// Consequence: For a local interconnect, the INI_ID port index +// is NOT equal to the SRCID local index, and the local interconnect +// must make a translation: SRCID => INI_ID (port index) +//////////////////////////////////////////////////////////////////////// + +#define PROC_LOCAL_SRCID 0 // from 0 to 7 +#define MDMA_LOCAL_SRCID 8 +#define IOBX_LOCAL_SRCID 9 +#define BDEV_LOCAL_SRCID 10 +#define CDMA_LOCAL_SRCID 11 +#define MEMC_LOCAL_SRCID 12 + +//////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for INT local interconnect +//////////////////////////////////////////////////////////////////// + +#define INT_MEMC_TGT_ID 0 +#define INT_XICU_TGT_ID 1 +#define INT_MDMA_TGT_ID 2 +#define INT_IOBX_TGT_ID 3 + +#define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) +#define INT_MDMA_INI_ID NB_PROCS_MAX +#define INT_IOBX_INI_ID (NB_PROCS_MAX+1) + +//////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for RAM local interconnect +//////////////////////////////////////////////////////////////////// + +#define RAM_XRAM_TGT_ID 0 + +#define RAM_MEMC_INI_ID 0 +#define RAM_IOBX_INI_ID 1 + +//////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for I0X local interconnect +//////////////////////////////////////////////////////////////////// + +#define IOX_IOB0_TGT_ID 0 // don't change this value +#define IOX_IOB1_TGT_ID 1 // don't change this value +#define IOX_FBUF_TGT_ID 2 +#define IOX_BDEV_TGT_ID 3 +#define IOX_MNIC_TGT_ID 4 +#define IOX_CDMA_TGT_ID 5 +#define IOX_BROM_TGT_ID 6 +#define IOX_MTTY_TGT_ID 7 + +#define IOX_IOB0_INI_ID 0 // Don't change this value +#define IOX_IOB1_INI_ID 1 // Don't change this value +#define IOX_BDEV_INI_ID 2 +#define IOX_CDMA_INI_ID 3 + +///////////////////////////////////////////////////////////////////// +int _main(int argc, char *argv[]) +///////////////////////////////////////////////////////////////////// +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + + char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code + size_t ncycles = 1000000000; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc + size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc + bool debug_iob = false; // trace iob0 & iob1 when true + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 + size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 + size_t block_size = BDEV_SECTOR_SIZE; // disk block size + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1 vci_param_int; + + typedef soclib::caba::VciParams vci_param_ext; + + // Define parameters depending on mesh size + size_t x_width; + size_t y_width; + + if (XMAX == 1) x_width = 0; + else if (XMAX == 2) x_width = 1; + else if (XMAX <= 4) x_width = 2; + else if (XMAX <= 8) x_width = 3; + else x_width = 4; + + if (YMAX == 1) y_width = 0; + else if (YMAX == 2) y_width = 1; + else if (YMAX <= 4) y_width = 2; + else if (YMAX <= 8) y_width = 3; + else y_width = 4; + + ///////////////////////////////////////////////////////////////////// + // INT network mapping table + // - two levels address decoding for commands + // - two levels srcid decoding for responses + // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster + // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster + ///////////////////////////////////////////////////////////////////// + MappingTable maptab_int( vci_address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + 0x00FF000000); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX; y++) + { + uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + bool config = true; + + // the four following segments are defined in all clusters + + std::ostringstream smemc_conf; + smemc_conf << "int_seg_memc_conf_" << x << "_" << y; + maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE, + IntTab(cluster(x,y),INT_MEMC_TGT_ID), true, config )); + + std::ostringstream smemc_xram; + smemc_xram << "int_seg_memc_xram_" << x << "_" << y; + maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE, + IntTab(cluster(x,y),INT_MEMC_TGT_ID), true)); + + std::ostringstream sxicu; + sxicu << "int_seg_xicu_" << x << "_" << y; + maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE, + IntTab(cluster(x,y),INT_XICU_TGT_ID), false)); + + std::ostringstream smdma; + smdma << "int_seg_mdma_" << x << "_" << y; + maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE, + IntTab(cluster(x,y),INT_MDMA_TGT_ID), false)); + + // the following segments are only defined in cluster_iob0 or in cluster_iob1 + + if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) + { + std::ostringstream siobx; + siobx << "int_seg_iobx_" << x << "_" << y; + maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), false, config )); + + std::ostringstream stty; + stty << "int_seg_mtty_" << x << "_" << y; + maptab_int.add(Segment(stty.str(), MTTY_BASE+offset, MTTY_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); + + std::ostringstream sfbf; + sfbf << "int_seg_fbuf_" << x << "_" << y; + maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); + + std::ostringstream sbdv; + sbdv << "int_seg_bdev_" << x << "_" << y; + maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); + + std::ostringstream snic; + snic << "int_seg_mnic_" << x << "_" << y; + maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); + + std::ostringstream srom; + srom << "int_seg_brom_" << x << "_" << y; + maptab_int.add(Segment(srom.str(), BROM_BASE+offset, BROM_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), true)); + + std::ostringstream sdma; + sdma << "int_seg_cdma_" << x << "_" << y; + maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), false)); + } + + // This define the mapping between the SRCIDs + // and the port index on the local interconnect. + + maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), INT_MDMA_INI_ID ); + + maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), INT_IOBX_INI_ID ); + + for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) + maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), INT_PROC_INI_ID+p ); + } + } + std::cout << "INT network " << maptab_int << std::endl; + + ///////////////////////////////////////////////////////////////////////// + // RAM network mapping table + // - two levels address decoding for commands + // - two levels srcid decoding for responses + // - 2 local initiators (MEMC, IOBX) per cluster + // (IOBX component only in cluster_iob0 and cluster_iob1) + // - 1 local target (XRAM) per cluster + //////////////////////////////////////////////////////////////////////// + MappingTable maptab_ram( vci_address_width, + IntTab(x_width+y_width, 16 - x_width - y_width), + IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), + 0x00FF000000); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + + std::ostringstream sxram; + sxram << "ext_seg_xram_" << x << "_" << y; + maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, + XRAM_SIZE, IntTab(cluster(x,y), 0), false)); + } + } + + // This define the mapping between the initiators (identified by their + // global SRCID) and the port index on the RAM local interconnect. + // External initiator have two alias SRCID (iob0 / iob1) + + maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), RAM_IOBX_INI_ID ); + maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), RAM_IOBX_INI_ID ); + + maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), RAM_IOBX_INI_ID ); + maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), RAM_IOBX_INI_ID ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), RAM_MEMC_INI_ID ); + + std::cout << "RAM network " << maptab_ram << std::endl; + + /////////////////////////////////////////////////////////////////////// + // IOX network mapping table + // - two levels address decoding for commands + // - two levels srcid decoding for responses + // - 4 initiators (IOB0, IOB1, BDEV, CDMA) + // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC) + /////////////////////////////////////////////////////////////////////// + MappingTable maptab_iox( vci_address_width, + IntTab(x_width+y_width, 16 - x_width - y_width), + IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), + 0x00FF000000); + + // compute base addresses for cluster_iob0 and cluster_iob1 + uint64_t iob0_base = ((uint64_t)cluster_iob0) << (vci_address_width - x_width - y_width); + uint64_t iob1_base = ((uint64_t)cluster_iob1) << (vci_address_width - x_width - y_width); + + // Each peripheral can be accessed through two segments, + // depending on the used IOB (IOB0 or IOB1). + maptab_iox.add(Segment("iox_seg_mtty_0", MTTY_BASE + iob0_base, MTTY_SIZE, + IntTab(cluster_iob0,IOX_MTTY_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_mtty_1", MTTY_BASE + iob1_base, MTTY_SIZE, + IntTab(cluster_iob1,IOX_MTTY_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE, + IntTab(cluster_iob0,IOX_FBUF_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE, + IntTab(cluster_iob1,IOX_FBUF_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE, + IntTab(cluster_iob0,IOX_BDEV_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE, + IntTab(cluster_iob1,IOX_BDEV_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE, + IntTab(cluster_iob0,IOX_MNIC_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE, + IntTab(cluster_iob1,IOX_MNIC_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE, + IntTab(cluster_iob0,IOX_CDMA_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE, + IntTab(cluster_iob1,IOX_CDMA_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_brom_0", BROM_BASE + iob0_base, BROM_SIZE, + IntTab(cluster_iob0,IOX_BROM_TGT_ID), false)); + + maptab_iox.add(Segment("iox_seg_brom_1", BROM_BASE + iob1_base, BROM_SIZE, + IntTab(cluster_iob1,IOX_BROM_TGT_ID), false)); + + // Each physical RAM can be accessed through IOB0, or through IOB1. + // if IOMMU is not activated, addresses are 40 bits (physical addresses), + // and the choice depends on on address bit A[39]. + // if IOMMU is activated the addresses use only 32 bits (virtual addresses), + // and the choice depends on address bit A[31]. + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + + if ( x < (XMAX/2) ) // send command to XRAM through IOB0 + { + std::ostringstream siob0; + siob0 << "iox_seg_xram_" << x << "_" << y; + maptab_iox.add(Segment(siob0.str(), offset, 0x80000000, + IntTab(cluster_iob0,IOX_IOB0_TGT_ID), false)); + } + else // send command to XRAM through IOB1 + { + std::ostringstream siob1; + siob1 << "iox_seg_xram_" << x << "_" << y; + maptab_iox.add(Segment(siob1.str(), offset, 0x80000000, + IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); + } + } + } + // useful when IOMMU activated + maptab_iox.add(Segment("iox_seg_xram ", 0xc0000000, 0x40000000, + IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); + + // This define the mapping between the initiators (identified by the SRCID) + // and the port index on the IOX local interconnect. + // External initiator have two alias SRCID (iob0 / iob1 access) + + maptab_iox.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), IOX_CDMA_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), IOX_CDMA_INI_ID ); + + maptab_iox.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), IOX_BDEV_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), IOX_BDEV_INI_ID ); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + if ( x < (XMAX/2) ) // send response to proc or mdma through IOB0 + { + maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID ), IOX_IOB0_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+1 ), IOX_IOB0_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+2 ), IOX_IOB0_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+3 ), IOX_IOB0_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), IOX_IOB0_INI_ID ); + } + else // send response to proc or mdma through IOB1 + { + maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID ), IOX_IOB1_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+1 ), IOX_IOB1_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+2 ), IOX_IOB1_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+3 ), IOX_IOB1_INI_ID ); + maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), IOX_IOB1_INI_ID ); + } + } + } + + std::cout << "IOX network " << maptab_iox << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + sc_signal signal_unused_irq[32]; + sc_signal signal_irq_bdev; + sc_signal signal_irq_mnic_rx[NB_NIC_CHANNELS]; + sc_signal signal_irq_mnic_tx[NB_NIC_CHANNELS]; + sc_signal signal_irq_mtty[NB_TTY_CHANNELS]; + sc_signal signal_irq_cdma[NB_NIC_CHANNELS*2]; + + // VCI signals for IOX network + VciSignals signal_vci_ini_iob0("signal_vci_ini_iob0"); + VciSignals signal_vci_ini_iob1("signal_vci_ini_iob1"); + VciSignals signal_vci_ini_bdev("signal_vci_ini_bdev"); + VciSignals signal_vci_ini_cdma("signal_vci_ini_cdma"); + + VciSignals signal_vci_tgt_iob0("signal_vci_tgt_iob0"); + VciSignals signal_vci_tgt_iob1("signal_vci_tgt_iob1"); + VciSignals signal_vci_tgt_mtty("signal_vci_tgt_mtty"); + VciSignals signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); + VciSignals signal_vci_tgt_mnic("signal_vci_tgt_mnic"); + VciSignals signal_vci_tgt_brom("signal_vci_tgt_brom"); + VciSignals signal_vci_tgt_bdev("signal_vci_tgt_bdev"); + VciSignals signal_vci_tgt_cdma("signal_vci_tgt_cdma"); + + // Horizontal inter-clusters INT network DSPIN + DspinSignals*** signal_dspin_int_cmd_h_inc = + alloc_elems >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 2); + DspinSignals*** signal_dspin_int_cmd_h_dec = + alloc_elems >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 2); + DspinSignals*** signal_dspin_int_rsp_h_inc = + alloc_elems >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); + DspinSignals*** signal_dspin_int_rsp_h_dec = + alloc_elems >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); + + // Vertical inter-clusters INT network DSPIN + DspinSignals*** signal_dspin_int_cmd_v_inc = + alloc_elems >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 2); + DspinSignals*** signal_dspin_int_cmd_v_dec = + alloc_elems >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 2); + DspinSignals*** signal_dspin_int_rsp_v_inc = + alloc_elems >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); + DspinSignals*** signal_dspin_int_rsp_v_dec = + alloc_elems >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); + + // Mesh boundaries INT network DSPIN + DspinSignals**** signal_dspin_false_int_cmd_in = + alloc_elems >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 2, 4); + DspinSignals**** signal_dspin_false_int_cmd_out = + alloc_elems >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 2, 4); + DspinSignals**** signal_dspin_false_int_rsp_in = + alloc_elems >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 2, 4); + DspinSignals**** signal_dspin_false_int_rsp_out = + alloc_elems >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 2, 4); + + + // Horizontal inter-clusters RAM network DSPIN + DspinSignals** signal_dspin_ram_cmd_h_inc = + alloc_elems >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_cmd_h_dec = + alloc_elems >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_rsp_h_inc = + alloc_elems >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_rsp_h_dec = + alloc_elems >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); + + // Vertical inter-clusters RAM network DSPIN + DspinSignals** signal_dspin_ram_cmd_v_inc = + alloc_elems >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_cmd_v_dec = + alloc_elems >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_rsp_v_inc = + alloc_elems >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_rsp_v_dec = + alloc_elems >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); + + // Mesh boundaries RAM network DSPIN + DspinSignals*** signal_dspin_false_ram_cmd_in = + alloc_elems >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_cmd_out = + alloc_elems >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_rsp_in = + alloc_elems >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_rsp_out = + alloc_elems >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); + + //////////////////////////// + // Loader + //////////////////////////// + +#if USE_ALMOS + soclib::common::Loader loader(almos_bootloader_pathname, + almos_archinfo_pathname, + almos_kernel_pathname); +#else + soclib::common::Loader loader(soft_name); +#endif + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////////////////// + // Instanciated Hardware Components + //////////////////////////////////////// + + std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; + + // IOX network + VciIoxNetwork* iox_network; + iox_network = new VciIoxNetwork( "iox_network", + maptab_iox, + 0, // cluster_id + 8, // number of targets + 4 ); // number of initiators + // boot ROM + VciSimpleRom* iox_brom; + iox_brom = new VciSimpleRom( "iox_brom", + IntTab(0, IOX_BROM_TGT_ID), + maptab_iox, + loader ); + // Network Controller + VciMultiNic* iox_mnic; + iox_mnic = new VciMultiNic( "iox_mnic", + IntTab(0, IOX_MNIC_TGT_ID), + maptab_iox, + NB_NIC_CHANNELS, + nic_rx_name, + nic_tx_name, + 0, // mac_4 address + 0 ); // mac_2 address + + // Frame Buffer + VciFrameBuffer* iox_fbuf; + iox_fbuf = new VciFrameBuffer( "iox_fbuf", + IntTab(0, IOX_FBUF_TGT_ID), + maptab_iox, + FBUF_X_SIZE, FBUF_Y_SIZE ); + + // Block Device + VciBlockDeviceTsar* iox_bdev; + iox_bdev = new VciBlockDeviceTsar( "iox_bdev", + maptab_iox, + IntTab(0, BDEV_LOCAL_SRCID), + IntTab(0, IOX_BDEV_TGT_ID), + disk_name, + block_size, + 64); // burst size (bytes) + + // Chained Buffer DMA controller + VciChbufDma* iox_cdma; + iox_cdma = new VciChbufDma( "iox_cdma", + maptab_iox, + IntTab(0, CDMA_LOCAL_SRCID), + IntTab(0, IOX_CDMA_TGT_ID), + 64, // burst size (bytes) + 2*NB_NIC_CHANNELS ); + // Multi-TTY controller + std::vector vect_names; + for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) + { + std::ostringstream term_name; + term_name << "term" << tid; + vect_names.push_back(term_name.str().c_str()); + } + VciMultiTty* iox_mtty; + iox_mtty = new VciMultiTty( "iox_mtty", + IntTab(0, IOX_MTTY_TGT_ID), + maptab_iox, + vect_names); + // Clusters + TsarIobCluster* clusters[XMAX][YMAX]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for(size_t i = 0; i < (XMAX * YMAX); i++) + { + size_t x = i / YMAX; + size_t y = i % YMAX; + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; + std::cout << std::endl; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarIobCluster + ( + sc.str().c_str(), + NB_PROCS_MAX, + NB_DMA_CHANNELS, + x, + y, + XMAX, + YMAX, + + maptab_int, + maptab_ram, + maptab_iox, + + x_width, + y_width, + vci_srcid_width - x_width - y_width, // l_id width, + + INT_MEMC_TGT_ID, + INT_XICU_TGT_ID, + INT_MDMA_TGT_ID, + INT_IOBX_TGT_ID, + + INT_PROC_INI_ID, + INT_MDMA_INI_ID, + INT_IOBX_INI_ID, + + RAM_XRAM_TGT_ID, + + RAM_MEMC_INI_ID, + RAM_MEMC_INI_ID, + + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + XRAM_LATENCY, + + loader, + + frozen_cycles, + debug_from, + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id), + debug_ok and debug_iob + ); + +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + std::cout << std::endl; + + /////////////////////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////////////////////// + + // IOX network connexion + iox_network->p_clk (signal_clk); + iox_network->p_resetn (signal_resetn); + iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); + iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); + iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); + iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); + iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); + iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); + iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); + iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); + iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); + iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); + iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); + iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); + + // BDEV connexion + iox_bdev->p_clk (signal_clk); + iox_bdev->p_resetn (signal_resetn); + iox_bdev->p_irq (signal_irq_bdev); + iox_bdev->p_vci_target (signal_vci_tgt_bdev); + iox_bdev->p_vci_initiator (signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // FBUF connexion + iox_fbuf->p_clk (signal_clk); + iox_fbuf->p_resetn (signal_resetn); + iox_fbuf->p_vci (signal_vci_tgt_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // MNIC connexion + iox_mnic->p_clk (signal_clk); + iox_mnic->p_resetn (signal_resetn); + iox_mnic->p_vci (signal_vci_tgt_mnic); + for ( size_t i=0 ; ip_rx_irq[i] (signal_irq_mnic_rx[i]); + iox_mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + std::cout << " - MNIC connected" << std::endl; + + // BROM connexion + iox_brom->p_clk (signal_clk); + iox_brom->p_resetn (signal_resetn); + iox_brom->p_vci (signal_vci_tgt_brom); + + std::cout << " - BROM connected" << std::endl; + + // MTTY connexion + iox_mtty->p_clk (signal_clk); + iox_mtty->p_resetn (signal_resetn); + iox_mtty->p_vci (signal_vci_tgt_mtty); + for ( size_t i=0 ; ip_irq[i] (signal_irq_mtty[i]); + } + + std::cout << " - MTTY connected" << std::endl; + + // CDMA connexion + iox_cdma->p_clk (signal_clk); + iox_cdma->p_resetn (signal_resetn); + iox_cdma->p_vci_target (signal_vci_tgt_cdma); + iox_cdma->p_vci_initiator (signal_vci_ini_cdma); + for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) + { + iox_cdma->p_irq[i] (signal_irq_cdma[i]); + } + + std::cout << " - CDMA connected" << std::endl; + + // IRQ connexions (for cluster_iob0 only) + size_t mx = 12 + NB_TTY_CHANNELS; + for ( size_t n=0 ; n<32 ; n++ ) + { + if ( n < 4 ) clusters[0][0]->p_irq[n]->bind (signal_unused_irq[n]); + else if ( n < 6 ) clusters[0][0]->p_irq[n]->bind (signal_irq_mnic_rx[n-4]); + else if ( n < 8 ) clusters[0][0]->p_irq[n]->bind (signal_irq_mnic_tx[n-6]); + else if ( n < 12 ) clusters[0][0]->p_irq[n]->bind (signal_irq_cdma[n-8]); + else if ( n < mx ) clusters[0][0]->p_irq[n]->bind (signal_irq_mtty[n-12]); + else if ( n < 31 ) clusters[0][0]->p_irq[n]->bind (signal_unused_irq[n]); + else clusters[0][0]->p_irq[n]->bind (signal_irq_bdev); + } + + // IOB0 cluster connexion to IOX network + clusters[0][0]->p_vci_iox_ini->bind (signal_vci_ini_iob0); + clusters[0][0]->p_vci_iox_tgt->bind (signal_vci_tgt_iob0); + + // IOB1 cluster connexion to IOX network + clusters[XMAX-1][YMAX-1]->p_vci_iox_ini->bind (signal_vci_ini_iob1); + clusters[XMAX-1][YMAX-1]->p_vci_iox_tgt->bind (signal_vci_tgt_iob1); + + // All clusters Clock & RESET connexions + for ( size_t x = 0; x < (XMAX); x++ ) + { + for (size_t y = 0; y < YMAX; y++) + { + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (XMAX > 1) + { + for (size_t x = 0; x < (XMAX-1); x++) + { + for (size_t y = 0; y < YMAX; y++) + { + for (size_t k = 0; k < 2; k++) + { + clusters[x][y]->p_dspin_int_cmd_out[k][EAST] (signal_dspin_int_cmd_h_inc[x][y][k]); + clusters[x+1][y]->p_dspin_int_cmd_in[k][WEST] (signal_dspin_int_cmd_h_inc[x][y][k]); + clusters[x][y]->p_dspin_int_cmd_in[k][EAST] (signal_dspin_int_cmd_h_dec[x][y][k]); + clusters[x+1][y]->p_dspin_int_cmd_out[k][WEST] (signal_dspin_int_cmd_h_dec[x][y][k]); + clusters[x][y]->p_dspin_int_rsp_out[k][EAST] (signal_dspin_int_rsp_h_inc[x][y][k]); + clusters[x+1][y]->p_dspin_int_rsp_in[k][WEST] (signal_dspin_int_rsp_h_inc[x][y][k]); + clusters[x][y]->p_dspin_int_rsp_in[k][EAST] (signal_dspin_int_rsp_h_dec[x][y][k]); + clusters[x+1][y]->p_dspin_int_rsp_out[k][WEST] (signal_dspin_int_rsp_h_dec[x][y][k]); + } + + clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); + clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); + clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); + clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); + clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); + clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); + clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); + clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); + } + } + } + + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (YMAX > 1) + { + for (size_t y = 0; y < (YMAX-1); y++) + { + for (size_t x = 0; x < XMAX; x++) + { + for (size_t k = 0; k < 2; k++) + { + clusters[x][y]->p_dspin_int_cmd_out[k][NORTH] (signal_dspin_int_cmd_v_inc[x][y][k]); + clusters[x][y+1]->p_dspin_int_cmd_in[k][SOUTH] (signal_dspin_int_cmd_v_inc[x][y][k]); + clusters[x][y]->p_dspin_int_cmd_in[k][NORTH] (signal_dspin_int_cmd_v_dec[x][y][k]); + clusters[x][y+1]->p_dspin_int_cmd_out[k][SOUTH] (signal_dspin_int_cmd_v_dec[x][y][k]); + clusters[x][y]->p_dspin_int_rsp_out[k][NORTH] (signal_dspin_int_rsp_v_inc[x][y][k]); + clusters[x][y+1]->p_dspin_int_rsp_in[k][SOUTH] (signal_dspin_int_rsp_v_inc[x][y][k]); + clusters[x][y]->p_dspin_int_rsp_in[k][NORTH] (signal_dspin_int_rsp_v_dec[x][y][k]); + clusters[x][y+1]->p_dspin_int_rsp_out[k][SOUTH] (signal_dspin_int_rsp_v_dec[x][y][k]); + } + + clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); + clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); + clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); + clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); + clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); + clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); + clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); + clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); + } + } + } + + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < YMAX; y++) + { + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_dspin_int_cmd_in[k][WEST] (signal_dspin_false_int_cmd_in[0][y][k][WEST]); + clusters[0][y]->p_dspin_int_cmd_out[k][WEST] (signal_dspin_false_int_cmd_out[0][y][k][WEST]); + clusters[0][y]->p_dspin_int_rsp_in[k][WEST] (signal_dspin_false_int_rsp_in[0][y][k][WEST]); + clusters[0][y]->p_dspin_int_rsp_out[k][WEST] (signal_dspin_false_int_rsp_out[0][y][k][WEST]); + + clusters[XMAX-1][y]->p_dspin_int_cmd_in[k][EAST] (signal_dspin_false_int_cmd_in[XMAX-1][y][k][EAST]); + clusters[XMAX-1][y]->p_dspin_int_cmd_out[k][EAST] (signal_dspin_false_int_cmd_out[XMAX-1][y][k][EAST]); + clusters[XMAX-1][y]->p_dspin_int_rsp_in[k][EAST] (signal_dspin_false_int_rsp_in[XMAX-1][y][k][EAST]); + clusters[XMAX-1][y]->p_dspin_int_rsp_out[k][EAST] (signal_dspin_false_int_rsp_out[XMAX-1][y][k][EAST]); + } + + clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); + clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); + clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); + clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); + + clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); + } + + std::cout << "East & West boundaries established" << std::endl; + + // North & South boundary clusters connections + for (size_t x = 0; x < XMAX; x++) + { + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_dspin_int_cmd_in[k][SOUTH] (signal_dspin_false_int_cmd_in[x][0][k][SOUTH]); + clusters[x][0]->p_dspin_int_cmd_out[k][SOUTH] (signal_dspin_false_int_cmd_out[x][0][k][SOUTH]); + clusters[x][0]->p_dspin_int_rsp_in[k][SOUTH] (signal_dspin_false_int_rsp_in[x][0][k][SOUTH]); + clusters[x][0]->p_dspin_int_rsp_out[k][SOUTH] (signal_dspin_false_int_rsp_out[x][0][k][SOUTH]); + + clusters[x][YMAX-1]->p_dspin_int_cmd_in[k][NORTH] (signal_dspin_false_int_cmd_in[x][YMAX-1][k][NORTH]); + clusters[x][YMAX-1]->p_dspin_int_cmd_out[k][NORTH] (signal_dspin_false_int_cmd_out[x][YMAX-1][k][NORTH]); + clusters[x][YMAX-1]->p_dspin_int_rsp_in[k][NORTH] (signal_dspin_false_int_rsp_in[x][YMAX-1][k][NORTH]); + clusters[x][YMAX-1]->p_dspin_int_rsp_out[k][NORTH] (signal_dspin_false_int_rsp_out[x][YMAX-1][k][NORTH]); + } + + clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); + + clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); + } + + std::cout << "North & South boundaries established" << std::endl; + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // network boundaries signals + for (size_t x = 0; x < XMAX ; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + for (size_t a = 0; a < 4; a++) + { + for (size_t k = 0; k < 2; k++) + { + signal_dspin_false_int_cmd_in[x][y][k][a].write = false; + signal_dspin_false_int_cmd_in[x][y][k][a].read = true; + signal_dspin_false_int_cmd_out[x][y][k][a].write = false; + signal_dspin_false_int_cmd_out[x][y][k][a].read = true; + + signal_dspin_false_int_rsp_in[x][y][k][a].write = false; + signal_dspin_false_int_rsp_in[x][y][k][a].read = true; + signal_dspin_false_int_rsp_out[x][y][k][a].write = false; + signal_dspin_false_int_rsp_out[x][y][k][a].read = true; + } + + signal_dspin_false_ram_cmd_in[x][y][a].write = false; + signal_dspin_false_ram_cmd_in[x][y][a].read = true; + signal_dspin_false_ram_cmd_out[x][y][a].write = false; + signal_dspin_false_ram_cmd_out[x][y][a].read = true; + + signal_dspin_false_ram_rsp_in[x][y][a].write = false; + signal_dspin_false_ram_rsp_in[x][y][a].read = true; + signal_dspin_false_ram_rsp_out[x][y][a].write = false; + signal_dspin_false_ram_rsp_out[x][y][a].read = true; + } + } + } + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + for (size_t n = 1; n < ncycles; n++) + { + // Monitor a specific address for L1 & L2 caches + clusters[1][1]->proc[0]->cache_monitor(0xC000039FC0ULL); + clusters[1][1]->memc->cache_monitor( 0xC000039FC0ULL); + + if (debug_ok and (n > debug_from) and (n % debug_period == 0)) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ************************************************" << std::endl; + + // trace proc[debug_proc_id] + if ( debug_proc_id < XMAX*YMAX*NB_PROCS_MAX ) + { + + size_t l = debug_proc_id % NB_PROCS_MAX ; + size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ; + size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ; + + clusters[x][y]->proc[l]->print_trace(); + + std::ostringstream proc_signame; + proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; + clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); + + std::ostringstream p2m_signame; + p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; + clusters[x][y]->signal_int_dspin_p2m_proc[l].print_trace(p2m_signame.str()); + + std::ostringstream m2p_signame; + m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; + clusters[x][y]->signal_int_dspin_m2p_proc[l].print_trace(m2p_signame.str()); + +// std::ostringstream p_cmd_signame; +// p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; +// clusters[x][y]->signal_int_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); + +// std::ostringstream p_rsp_signame; +// p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; +// clusters[x][y]->signal_int_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); + + // trace INT routers and xbar in a given cluster +// clusters[x][y]->int_xbar_m2p_c->print_trace(); +// clusters[x][y]->int_router_cmd->print_trace(1); +// clusters[x][y]->int_xbar_rsp_d->print_trace(); +// clusters[x][y]->int_xbar_cmd_d->print_trace(); +// clusters[x][y]->signal_int_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); +// clusters[x][y]->signal_int_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); +// clusters[x][y]->signal_int_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); +// clusters[x][y]->signal_int_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); + } + + // trace memc[debug_memc_id] + if ( debug_memc_id < XMAX*YMAX ) + { + size_t x = debug_memc_id / YMAX; + size_t y = debug_memc_id % YMAX; + + clusters[x][y]->memc->print_trace(); + + std::ostringstream smemc_tgt; + smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; + clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); + + std::ostringstream smemc_ini; + smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); + +// clusters[x][y]->ram_router_cmd->print_trace(); +// clusters[x][y]->ram_xbar_cmd->print_trace(); + +// std::ostringstream sg2l; +// sg2l << "[SIG]G2L_" << x << "_" << y; +// clusters[x][y]->signal_ram_dspin_cmd_g2l.print_trace(sg2l.str()); + + clusters[x][y]->xram->print_trace(); + + std::ostringstream sxram_tgt; + sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); + + std::ostringstream sm2p; + sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; + clusters[x][y]->signal_int_dspin_m2p_memc.print_trace(sm2p.str()); + + std::ostringstream sp2m; + sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; + clusters[x][y]->signal_int_dspin_p2m_memc.print_trace(sp2m.str()); + +// std::ostringstream m_cmd_signame; +// m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; +// clusters[x][y]->signal_int_dspin_cmd_memc_t.print_trace(m_cmd_signame.str()); + +// std::ostringstream m_rsp_signame; +// m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; +// clusters[x][y]->signal_int_dspin_rsp_memc_t.print_trace(m_rsp_signame.str()); + + std::ostringstream siob_ini; + siob_ini << "[SIG]IOB_INI_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_ini_iobx.print_trace(siob_ini.str()); + } + + // trace components iob + if ( debug_iob ) + { + clusters[0][0]->iob->print_trace(); + clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0 INT" ); + clusters[0][0]->signal_int_dspin_cmd_iobx_t.print_trace("[SIG]IOB0 INT CMD"); + clusters[0][0]->signal_int_dspin_rsp_iobx_t.print_trace("[SIG]IOB0 INT RSP"); + + clusters[XMAX-1][YMAX-1]->iob->print_trace(); + clusters[XMAX-1][YMAX-1]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB1 INT" ); + clusters[XMAX-1][YMAX-1]->signal_int_dspin_cmd_iobx_t.print_trace("[SIG]IOB1 INT CMD"); + clusters[XMAX-1][YMAX-1]->signal_int_dspin_rsp_iobx_t.print_trace("[SIG]IOB1 INT RSP"); + } + + // trace external peripherals + iox_network->print_trace(); + + signal_vci_ini_iob0.print_trace("[SIG]IOB0 INI IOX"); + signal_vci_tgt_iob0.print_trace("[SIG]IOB0 TGT IOX"); + signal_vci_ini_iob1.print_trace("[SIG]IOB1 INI IOX"); + signal_vci_tgt_iob1.print_trace("[SIG]IOB1 TGT IOX"); + + iox_brom->print_trace(); + signal_vci_tgt_brom.print_trace("[SIG]BROM"); + +// iox_mtty->print_trace(); +// signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); + +// iox_bdev->print_trace(); +// signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); +// signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); + +// iox_fbuf->print_trace(); +// signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); + + } + + sc_start(sc_core::sc_time(1, SC_NS)); + } + return EXIT_SUCCESS; +} + +int sc_main (int argc, char *argv[]) +{ + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 + + + Index: trunk/platforms/tsar_generic_iob/top.desc =================================================================== --- trunk/platforms/tsar_generic_iob/top.desc (revision 450) +++ trunk/platforms/tsar_generic_iob/top.desc (revision 450) @@ -0,0 +1,82 @@ + +# -*- python -*- + +# VCI parameters +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 40 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# internal DSPIN network parameters +int_dspin_cmd_flit_size = 39 +int_dspin_rsp_flit_size = 32 + +# external DSPIN network parameters +ram_dspin_cmd_flit_size = 64 +ram_dspin_rsp_flit_size = 64 + +todo = Platform('caba', 'top.cpp', + + uses = [ + # cluster + Uses('caba:tsar_iob_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_int_cmd_width = int_dspin_cmd_flit_size, + dspin_int_rsp_width = int_dspin_rsp_flit_size, + dspin_ram_cmd_width = ram_dspin_cmd_flit_size, + dspin_ram_rsp_width = ram_dspin_rsp_flit_size), + + # IOX Network + Uses('caba:vci_iox_network', + cell_size = vci_cell_size_ext), + + # ROM + Uses('caba:vci_simple_rom', + cell_size = vci_cell_size_ext), + + # Frame Buffer + Uses('caba:vci_framebuffer', + cell_size = vci_cell_size_ext), + + # Block Device + Uses('caba:vci_block_device_tsar', + cell_size = vci_cell_size_ext), + + # NIC + Uses('caba:vci_multi_nic', + cell_size = vci_cell_size_ext), + + # Chained DMA + Uses('caba:vci_chbuf_dma', + cell_size = vci_cell_size_ext), + + # TTY + Uses('caba:vci_multi_tty', + cell_size = vci_cell_size_ext), + + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, + +) Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd =================================================================== --- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 450) +++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 450) @@ -0,0 +1,130 @@ + +# -*- python -*- + +Module('caba:tsar_iob_cluster', + classname = 'soclib::caba::TsarIobCluster', + + tmpl_parameters = [ + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_int')), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_ext')), + parameter.Int('dspin_int_cmd_width'), + parameter.Int('dspin_int_rsp_width'), + parameter.Int('dspin_ram_cmd_width'), + parameter.Int('dspin_ram_rsp_width'), + ], + + header_files = [ + '../source/include/tsar_iob_cluster.h', + ], + + implementation_files = [ + '../source/src/tsar_iob_cluster.cpp', + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + Uses('common:elf_file_loader'), + + # internal network components + Uses('caba:vci_cc_vcache_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_in_width = parameter.Reference('dspin_int_cmd_width'), + dspin_out_width = parameter.Reference('dspin_int_rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_mem_cache', + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + dspin_in_width = parameter.Reference('dspin_int_rsp_width'), + dspin_out_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:vci_xicu', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_multi_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_int_rsp_width')), + + # RAM network components + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_ext'), + dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_ext'), + dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_ram_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:dspin_router', + flit_width = parameter.Reference('dspin_ram_cmd_width')), + + Uses('caba:dspin_router', + flit_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_ext')), + + # IOX network components + Uses('caba:vci_io_bridge', + iob_cell_size_int = parameter.Reference('vci_data_width_int'), + iob_cell_size_ext = parameter.Reference('vci_data_width_ext')), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + + Port('caba:dspin_output', 'p_int_cmd_out', [2, 4], + dspin_data_size = parameter.Reference('dspin_int_cmd_width')), + Port('caba:dspin_input', 'p_int_cmd_in', [2, 4], + dspin_data_size = parameter.Reference('dspin_int_cmd_width')), + Port('caba:dspin_output', 'p_int_rsp_out', [2, 4], + dspin_data_size = parameter.Reference('dspin_int_rsp_width')), + Port('caba:dspin_input', 'p_int_rsp_in', [2, 4], + dspin_data_size = parameter.Reference('dspin_int_rsp_width')), + + Port('caba:dspin_output', 'p_ext_cmd_out', [2, 4], + dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), + Port('caba:dspin_input', 'p_ext_cmd_in', [2, 4], + dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), + Port('caba:dspin_output', 'p_ext_rsp_out', [2, 4], + dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), + Port('caba:dspin_input', 'p_ext_rsp_in', [2, 4], + dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), + ], +) + + Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h =================================================================== --- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 450) +++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 450) @@ -0,0 +1,265 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_iob_cluster.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : april 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H +#define SOCLIB_CABA_TSAR_IOB_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_xicu.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "dspin_router.h" +#include "virtual_dspin_router.h" +#include "vci_multi_dma.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" +#include "vci_io_bridge.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template +class TsarIobCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + + public: + + // Ports + sc_in p_clk; + sc_in p_resetn; + + soclib::caba::VciInitiator* p_vci_iox_ini; + soclib::caba::VciTarget* p_vci_iox_tgt; + + sc_in* p_irq[32]; // not always used + + soclib::caba::DspinOutput** p_dspin_int_cmd_out; + soclib::caba::DspinInput** p_dspin_int_cmd_in; + soclib::caba::DspinOutput** p_dspin_int_rsp_out; + soclib::caba::DspinInput** p_dspin_int_rsp_in; + + soclib::caba::DspinOutput* p_dspin_ram_cmd_out; + soclib::caba::DspinInput* p_dspin_ram_cmd_in; + soclib::caba::DspinOutput* p_dspin_ram_rsp_out; + soclib::caba::DspinInput* p_dspin_ram_rsp_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_it[8]; + sc_signal signal_irq_mdma[8]; + + // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars + DspinSignals signal_int_dspin_cmd_l2g_d; + DspinSignals signal_int_dspin_cmd_g2l_d; + DspinSignals signal_int_dspin_m2p_l2g_c; + DspinSignals signal_int_dspin_m2p_g2l_c; + DspinSignals signal_int_dspin_rsp_l2g_d; + DspinSignals signal_int_dspin_rsp_g2l_d; + DspinSignals signal_int_dspin_p2m_l2g_c; + DspinSignals signal_int_dspin_p2m_g2l_c; + + // INT network VCI signals between VCI components and VCI/DSPIN wrappers + VciSignals signal_int_vci_ini_proc[8]; + VciSignals signal_int_vci_ini_mdma; + VciSignals signal_int_vci_ini_iobx; + + VciSignals signal_int_vci_tgt_memc; + VciSignals signal_int_vci_tgt_xicu; + VciSignals signal_int_vci_tgt_mdma; + VciSignals signal_int_vci_tgt_iobx; + + // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN wrappers + DspinSignals signal_int_dspin_cmd_proc_i[8]; + DspinSignals signal_int_dspin_rsp_proc_i[8]; + DspinSignals signal_int_dspin_cmd_mdma_i; + DspinSignals signal_int_dspin_rsp_mdma_i; + DspinSignals signal_int_dspin_cmd_iobx_i; + DspinSignals signal_int_dspin_rsp_iobx_i; + + DspinSignals signal_int_dspin_cmd_memc_t; + DspinSignals signal_int_dspin_rsp_memc_t; + DspinSignals signal_int_dspin_cmd_xicu_t; + DspinSignals signal_int_dspin_rsp_xicu_t; + DspinSignals signal_int_dspin_cmd_mdma_t; + DspinSignals signal_int_dspin_rsp_mdma_t; + DspinSignals signal_int_dspin_cmd_iobx_t; + DspinSignals signal_int_dspin_rsp_iobx_t; + + // Coherence DSPIN signals between DSPIN local crossbars and CC components + DspinSignals signal_int_dspin_m2p_memc; + DspinSignals signal_int_dspin_p2m_memc; + DspinSignals signal_int_dspin_m2p_proc[8]; + DspinSignals signal_int_dspin_p2m_proc[8]; + + // RAM network VCI signals between VCI components and VCI/DSPIN wrappers + VciSignals signal_ram_vci_ini_memc; + VciSignals signal_ram_vci_ini_iobx; + VciSignals signal_ram_vci_tgt_xram; + + // RAM network DSPIN signals between VCI/DSPIN wrappers and crossbars or routers + DspinSignals signal_ram_dspin_cmd_xram_t; + DspinSignals signal_ram_dspin_rsp_xram_t; + DspinSignals signal_ram_dspin_cmd_memc_i; + DspinSignals signal_ram_dspin_rsp_memc_i; + DspinSignals signal_ram_dspin_cmd_iobx_i; + DspinSignals signal_ram_dspin_rsp_iobx_i; + + // RAM network DSPIN signals between DSPIN routers and DSPIN local crossbars + DspinSignals signal_ram_dspin_cmd_l2g; + DspinSignals signal_ram_dspin_cmd_g2l; + DspinSignals signal_ram_dspin_rsp_l2g; + DspinSignals signal_ram_dspin_rsp_g2l; + + ////////////////////////////////////// + // Hardwate Components (pointers) + ////////////////////////////////////// + VciCcVCacheWrapper >* proc[8]; + + VciDspinInitiatorWrapper* proc_wi[8]; + + VciMemCache* memc; + + VciDspinTargetWrapper* memc_int_wt; + + VciDspinInitiatorWrapper* memc_ram_wi; + + VciXicu* xicu; + + VciDspinTargetWrapper* xicu_int_wt; + + VciMultiDma* mdma; + + VciDspinInitiatorWrapper* mdma_int_wi; + + VciDspinTargetWrapper* mdma_int_wt; + + DspinLocalCrossbar* int_xbar_cmd_d; + DspinLocalCrossbar* int_xbar_rsp_d; + DspinLocalCrossbar* int_xbar_m2p_c; + DspinLocalCrossbar* int_xbar_p2m_c; + + VirtualDspinRouter* int_router_cmd; + VirtualDspinRouter* int_router_rsp; + + VciSimpleRam* xram; + + VciDspinTargetWrapper* xram_ram_wt; + + DspinRouter* ram_router_cmd; + DspinRouter* ram_router_rsp; + + // IO Network Components (not instanciated in all clusters) + + VciIoBridge* iob; + + VciDspinInitiatorWrapper* iob_int_wi; + + VciDspinTargetWrapper* iob_int_wt; + + VciDspinInitiatorWrapper* iob_ram_wi; + + DspinLocalCrossbar* ram_xbar_cmd; + DspinLocalCrossbar* ram_xbar_rsp; + + // cluster constructor + TsarIobCluster( sc_module_name insname, + size_t nb_procs, + size_t nb_dmas, + size_t x, // x coordinate + size_t y, // y coordinate + size_t xmax, + size_t ymax, + + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_ext, + const soclib::common::MappingTable &mt_iox, + + size_t x_width, // x field bits + size_t y_width, // y field bits + size_t l_width, // l field bits + + size_t int_memc_tgtid, + size_t int_xicu_tgtid, + size_t int_mdma_tgtid, + size_t int_iobx_tgtid, + + size_t int_proc_srcid, + size_t int_mdma_srcid, + size_t int_iobx_srcid, + + size_t ext_xram_tgtid, + + size_t ext_memc_srcid, + size_t ext_iobx_srcid, + + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + + const Loader &loader, // loader for XRAM + + uint32_t frozen_cycles, + uint32_t start_debug_cycle, + bool memc_debug_ok, + bool proc_debug_ok, + bool iob0_debug_ok ); + +}; + +}} + +#endif Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp =================================================================== --- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 450) +++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 450) @@ -0,0 +1,756 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_iob_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : april 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. +// These two clusters contain 6 extra components: +// - 1 vci_io_bridge (connected to the 3 networks. +// - 3 vci_dspin_wrapper for the IOB. +// - 2 dspin_local_crossbar for commands and responses. +////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_iob_cluster.h" + +namespace soclib { namespace caba { + +////////////////////////////////////////////////////////////////////////// +// Constructor +////////////////////////////////////////////////////////////////////////// +template +TsarIobCluster::TsarIobCluster( +////////////////////////////////////////////////////////////////////////// + sc_module_name insname, + size_t nb_procs, + size_t nb_dmas, + size_t x_id, + size_t y_id, + size_t xmax, + size_t ymax, + + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_ram, + const soclib::common::MappingTable &mt_iox, + + size_t x_width, + size_t y_width, + size_t l_width, + + size_t memc_int_tgtid, + size_t xicu_int_tgtid, + size_t mdma_int_tgtid, + size_t iobx_int_tgtid, + + size_t proc_int_srcid, + size_t mdma_int_srcid, + size_t iobx_int_srcid, + + size_t xram_ram_tgtid, + + size_t memc_ram_srcid, + size_t iobx_ram_srcid, + + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + + const Loader &loader, + + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok, + bool iob_debug_ok ) + : soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn") +{ + assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); + + size_t cluster_id = x_id * ymax + y_id; + size_t cluster_iob0 = 0; + size_t cluster_iob1 = xmax*ymax-1; + + // Vectors of DSPIN ports for inter-cluster communications + p_dspin_int_cmd_in = alloc_elems >("p_int_cmd_in", 2, 4); + p_dspin_int_cmd_out = alloc_elems >("p_int_cmd_out", 2, 4); + p_dspin_int_rsp_in = alloc_elems >("p_int_rsp_in", 2, 4); + p_dspin_int_rsp_out = alloc_elems >("p_int_rsp_out", 2, 4); + + p_dspin_ram_cmd_in = alloc_elems >("p_ext_cmd_in", 4); + p_dspin_ram_cmd_out = alloc_elems >("p_ext_cmd_out", 4); + p_dspin_ram_rsp_in = alloc_elems >("p_ext_rsp_in", 4); + p_dspin_ram_rsp_out = alloc_elems >("p_ext_rsp_out", 4); + + // VCI ports to IOB0 and IOB1 in cluster_iob0 and cluster_iob1 + if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) + { + p_vci_iox_ini = new soclib::caba::VciInitiator; + p_vci_iox_tgt = new soclib::caba::VciTarget; + } + + // IRQ ports in cluster_iob0 only + if ( cluster_id == cluster_iob0 ) + { + for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_in; + } + + ///////////////////////////////////////////////////////////////////////////// + // Hardware components + ///////////////////////////////////////////////////////////////////////////// + + //////////// PROCS + for (size_t p = 0; p < nb_procs; p++) + { + std::ostringstream s_proc; + s_proc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper >( + s_proc.str().c_str(), + cluster_id*nb_procs + p, // GLOBAL PROC_ID + mt_int, // Mapping Table INT network + IntTab(cluster_id,p), // SRCID + (cluster_id << l_width) + p, // CC_GLOBAL_ID + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways,l1_i_sets,16, // ICACHE size + l1_d_ways,l1_d_sets,16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + frozen_cycles, // max frozen cycles + debug_start_cycle, + proc_debug_ok); + + std::ostringstream s_wi_proc; + s_wi_proc << "proc_wi_" << x_id << "_" << y_id << "_" << p; + proc_wi[p] = new VciDspinInitiatorWrapper( + s_wi_proc.str().c_str(), + x_width + y_width + l_width); + } + + /////////// MEMC + std::ostringstream s_memc; + s_memc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + s_memc.str().c_str(), + mt_int, // Mapping Table INT network + mt_ram, // Mapping Table RAM network + IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network + IntTab(cluster_id, memc_int_tgtid), // TGTID INT network + (cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + debug_start_cycle, + memc_debug_ok ); + + std::ostringstream s_wt_memc; + s_wt_memc << "memc_wt_" << x_id << "_" << y_id; + memc_int_wt = new VciDspinTargetWrapper( + s_wt_memc.str().c_str(), + x_width + y_width + l_width); + + std::ostringstream s_wi_memc; + s_wi_memc << "memc_wi_" << x_id << "_" << y_id; + memc_ram_wi = new VciDspinInitiatorWrapper( + s_wi_memc.str().c_str(), + x_width + y_width + l_width); + + /////////// XICU + std::ostringstream s_xicu; + s_xicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + s_xicu.str().c_str(), + mt_int, // mapping table INT network + IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space + nb_procs, // number of timer IRQs + 32, // number of hard IRQs + 32, // number of soft IRQs + nb_procs); // number of output IRQs + + std::ostringstream s_wt_xicu; + s_wt_xicu << "xicu_wt_" << x_id << "_" << y_id; + xicu_int_wt = new VciDspinTargetWrapper( + s_wt_xicu.str().c_str(), + x_width + y_width + l_width); + + //////////// MDMA + std::ostringstream s_mdma; + s_mdma << "mdma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( + s_mdma.str().c_str(), + mt_int, + IntTab(cluster_id, nb_procs), // SRCID + IntTab(cluster_id, mdma_int_tgtid), // TGTID + 64, // burst size + nb_dmas); // number of IRQs + + std::ostringstream s_wt_mdma; + s_wt_mdma << "mdma_wt_" << x_id << "_" << y_id; + mdma_int_wt = new VciDspinTargetWrapper( + s_wt_mdma.str().c_str(), + x_width + y_width + l_width); + + std::ostringstream s_wi_mdma; + s_wi_mdma << "mdma_wi_" << x_id << "_" << y_id; + mdma_int_wi = new VciDspinInitiatorWrapper( + s_wi_mdma.str().c_str(), + x_width + y_width + l_width); + + /////////// Direct LOCAL_XBAR(S) + size_t nb_direct_initiators = nb_procs + 1; + size_t nb_direct_targets = 3; + if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) + { + nb_direct_initiators = nb_procs + 2; + nb_direct_targets = 4; + } + + std::ostringstream s_int_xbar_cmd_d; + s_int_xbar_cmd_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; + int_xbar_cmd_d = new DspinLocalCrossbar( + s_int_xbar_cmd_d.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + nb_direct_initiators, // number of local of sources + nb_direct_targets, // number of local dests + 2, 2, // fifo depths + true, // CMD crossbar + true, // use routing table + false ); // no broacast + + std::ostringstream s_int_xbar_rsp_d; + s_int_xbar_rsp_d << "int_xbar_rsp_d_" << x_id << "_" << y_id; + int_xbar_rsp_d = new DspinLocalCrossbar( + s_int_xbar_rsp_d.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + nb_direct_targets, // number of local sources + nb_direct_initiators, // number of local dests + 2, 2, // fifo depths + false, // RSP crossbar + false, // don't use routing table + false ); // no broacast + + //////////// Coherence LOCAL_XBAR(S) + std::ostringstream s_int_xbar_m2p_c; + s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; + int_xbar_m2p_c = new DspinLocalCrossbar( + s_int_xbar_m2p_c.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, // several dests + 1, // number of local sources + nb_procs, // number of local dests + 2, 2, // fifo depths + true, // pseudo CMD + false, // no routing table + true ); // broacast + + std::ostringstream s_int_xbar_p2m_c; + s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; + int_xbar_p2m_c = new DspinLocalCrossbar( + s_int_xbar_p2m_c.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // only one dest + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // pseudo RSP + false, // no routing table + false ); // no broacast + + ////////////// INT ROUTER(S) + std::ostringstream s_int_router_cmd; + s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; + int_router_cmd = new VirtualDspinRouter( + s_int_router_cmd.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + std::ostringstream s_int_router_rsp; + s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; + int_router_rsp = new VirtualDspinRouter( + s_int_router_rsp.str().c_str(), + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + ////////////// XRAM + std::ostringstream s_xram; + s_xram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + s_xram.str().c_str(), + IntTab(cluster_id, xram_ram_tgtid ), + mt_ram, + loader, + xram_latency); + + std::ostringstream s_wt_xram; + s_wt_xram << "xram_wt_" << x_id << "_" << y_id; + xram_ram_wt = new VciDspinTargetWrapper( + s_wt_xram.str().c_str(), + x_width + y_width + l_width); + + ///////////// RAM ROUTER(S) + std::ostringstream s_ram_router_cmd; + s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; + ram_router_cmd = new DspinRouter( + s_ram_router_cmd.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + std::ostringstream s_ram_router_rsp; + s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; + ram_router_rsp = new DspinRouter( + s_ram_router_rsp.str().c_str(), + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + ////////////////////// I/O CLUSTER ONLY /////////////////////// + if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) + { + /////////// IO_BRIDGE + size_t iox_local_id; + size_t global_id; + bool has_irqs; + if ( cluster_id == cluster_iob0 ) + { + iox_local_id = 0; + global_id = cluster_iob0; + has_irqs = true; + } + else + { + iox_local_id = 1; + global_id = cluster_iob1; + has_irqs = false; + } + + std::ostringstream s_iob; + s_iob << "iob_" << x_id << "_" << y_id; + iob = new VciIoBridge( + s_iob.str().c_str(), + mt_ram, // EXT network maptab + mt_int, // INT network maptab + mt_iox, // IOX network maptab + IntTab( global_id, iobx_int_tgtid ), // INT TGTID + IntTab( global_id, iobx_int_srcid ), // INT SRCID + IntTab( global_id, iox_local_id ), // IOX TGTID + has_irqs, + 16, // cache line words + 8, // IOTLB ways + 8, // IOTLB sets + debug_start_cycle, + iob_debug_ok ); + + std::ostringstream s_iob_int_wi; + s_iob_int_wi << "iob_int_wi_" << x_id << "_" << y_id; + iob_int_wi = new VciDspinInitiatorWrapper( + s_iob_int_wi.str().c_str(), + x_width + y_width + l_width); + + std::ostringstream s_iob_int_wt; + s_iob_int_wt << "iob_int_wt_" << x_id << "_" << y_id; + iob_int_wt = new VciDspinTargetWrapper( + s_iob_int_wt.str().c_str(), + x_width + y_width + l_width); + + std::ostringstream s_iob_ram_wi; + s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; + iob_ram_wi = new VciDspinInitiatorWrapper( + s_iob_ram_wi.str().c_str(), + x_width + y_width + l_width); + + ///////////// RAM LOCAL_XBAR(S) + std::ostringstream s_ram_xbar_cmd; + s_ram_xbar_cmd << "ram_xbar_cmd_" << x_id << "_" << y_id; + ram_xbar_cmd = new DspinLocalCrossbar( + s_ram_xbar_cmd.str().c_str(), + mt_ram, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // one dest on ram_cmd network + 2, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + true, // CMD crossbar + false, // no routing table (one dest) + false ); // no broadcast + + std::ostringstream s_ram_xbar_rsp; + s_ram_xbar_rsp << "ram_xbar_rsp_" << x_id << "_" << y_id; + ram_xbar_rsp = new DspinLocalCrossbar( + s_ram_xbar_rsp.str().c_str(), + mt_ram, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, // two sources on ram_rsp network + 1, // number of local sources + 2, // number of local dests + 2, 2, // fifo depths + false, // RSP crossbar + true, // use routing table + false ); // no broadcast + } + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + // on coherence network : local srcid[proc] in [0...nb_procs-1] + // : local srcid[memc] = nb_procs + + //////////////////////// internal CMD & RSP routers + int_router_cmd->p_clk (this->p_clk); + int_router_cmd->p_resetn (this->p_resetn); + int_router_rsp->p_clk (this->p_clk); + int_router_rsp->p_resetn (this->p_resetn); + for (int x = 0; x < 2; x++) + { + for(int y = 0; y < 4; y++) + { + int_router_cmd->p_out[x][y] (this->p_dspin_int_cmd_out[x][y]); + int_router_cmd->p_in[x][y] (this->p_dspin_int_cmd_in[x][y]); + int_router_rsp->p_out[x][y] (this->p_dspin_int_rsp_out[x][y]); + int_router_rsp->p_in[x][y] (this->p_dspin_int_rsp_in[x][y]); + } + } + + // local ports + int_router_cmd->p_out[0][4] (signal_int_dspin_cmd_g2l_d); + int_router_cmd->p_out[1][4] (signal_int_dspin_m2p_g2l_c); + int_router_cmd->p_in[0][4] (signal_int_dspin_cmd_l2g_d); + int_router_cmd->p_in[1][4] (signal_int_dspin_m2p_l2g_c); + + int_router_rsp->p_out[0][4] (signal_int_dspin_rsp_g2l_d); + int_router_rsp->p_out[1][4] (signal_int_dspin_p2m_g2l_c); + int_router_rsp->p_in[0][4] (signal_int_dspin_rsp_l2g_d); + int_router_rsp->p_in[1][4] (signal_int_dspin_p2m_l2g_c); + + ///////////////////// CMD DSPIN local crossbar direct + int_xbar_cmd_d->p_clk (this->p_clk); + int_xbar_cmd_d->p_resetn (this->p_resetn); + int_xbar_cmd_d->p_global_out (signal_int_dspin_cmd_l2g_d); + int_xbar_cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d); + + int_xbar_cmd_d->p_local_out[memc_int_tgtid] (signal_int_dspin_cmd_memc_t); + int_xbar_cmd_d->p_local_out[xicu_int_tgtid] (signal_int_dspin_cmd_xicu_t); + int_xbar_cmd_d->p_local_out[mdma_int_tgtid] (signal_int_dspin_cmd_mdma_t); + + int_xbar_cmd_d->p_local_in[mdma_int_srcid] (signal_int_dspin_cmd_mdma_i); + + for (size_t p = 0; p < nb_procs; p++) + int_xbar_cmd_d->p_local_in[proc_int_srcid+p] (signal_int_dspin_cmd_proc_i[p]); + + if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) + { + int_xbar_cmd_d->p_local_out[iobx_int_tgtid] (signal_int_dspin_cmd_iobx_t); + int_xbar_cmd_d->p_local_in[iobx_int_srcid] (signal_int_dspin_cmd_iobx_i); + } + + //////////////////////// RSP DSPIN local crossbar direct + int_xbar_rsp_d->p_clk (this->p_clk); + int_xbar_rsp_d->p_resetn (this->p_resetn); + int_xbar_rsp_d->p_global_out (signal_int_dspin_rsp_l2g_d); + int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); + + int_xbar_rsp_d->p_local_in[memc_int_tgtid] (signal_int_dspin_rsp_memc_t); + int_xbar_rsp_d->p_local_in[xicu_int_tgtid] (signal_int_dspin_rsp_xicu_t); + int_xbar_rsp_d->p_local_in[mdma_int_tgtid] (signal_int_dspin_rsp_mdma_t); + + int_xbar_rsp_d->p_local_out[mdma_int_srcid] (signal_int_dspin_rsp_mdma_i); + + for (size_t p = 0; p < nb_procs; p++) + int_xbar_rsp_d->p_local_out[proc_int_srcid+p] (signal_int_dspin_rsp_proc_i[p]); + + if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) + { + int_xbar_rsp_d->p_local_in[iobx_int_tgtid] (signal_int_dspin_rsp_iobx_t); + int_xbar_rsp_d->p_local_out[iobx_int_srcid] (signal_int_dspin_rsp_iobx_i); + } + + ////////////////////// M2P DSPIN local crossbar coherence + int_xbar_m2p_c->p_clk (this->p_clk); + int_xbar_m2p_c->p_resetn (this->p_resetn); + int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); + int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); + int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); + + ////////////////////////// P2M DSPIN local crossbar coherence + int_xbar_p2m_c->p_clk (this->p_clk); + int_xbar_p2m_c->p_resetn (this->p_resetn); + int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); + int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); + int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_int_vci_ini_proc[p]); + proc[p]->p_dspin_in (signal_int_dspin_m2p_proc[p]); + proc[p]->p_dspin_out (signal_int_dspin_p2m_proc[p]); + proc[p]->p_irq[0] (signal_proc_it[p]); + for ( size_t j = 1 ; j < 6 ; j++) + { + proc[p]->p_irq[j] (signal_false); + } + + proc_wi[p]->p_clk (this->p_clk); + proc_wi[p]->p_resetn (this->p_resetn); + proc_wi[p]->p_dspin_cmd (signal_int_dspin_cmd_proc_i[p]); + proc_wi[p]->p_dspin_rsp (signal_int_dspin_rsp_proc_i[p]); + proc_wi[p]->p_vci (signal_int_vci_ini_proc[p]); + } + + ///////////////////////////////////// XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_int_vci_tgt_xicu); + for ( size_t p=0 ; pp_irq[p] (signal_proc_it[p]); + } + for ( size_t i=0 ; i<4 ; i++) + { + xicu->p_hwi[i] (signal_irq_mdma[i]); + } + for ( size_t i=4 ; i<32 ; i++) + { + if (cluster_id == cluster_iob0) + xicu->p_hwi[i] (*(this->p_irq[i])); + else + xicu->p_hwi[i] (signal_false); + } + + // wrapper XICU + xicu_int_wt->p_clk (this->p_clk); + xicu_int_wt->p_resetn (this->p_resetn); + xicu_int_wt->p_dspin_cmd (signal_int_dspin_cmd_xicu_t); + xicu_int_wt->p_dspin_rsp (signal_int_dspin_rsp_xicu_t); + xicu_int_wt->p_vci (signal_int_vci_tgt_xicu); + + ///////////////////////////////////// MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_vci_ixr (signal_ram_vci_ini_memc); + memc->p_vci_tgt (signal_int_vci_tgt_memc); + memc->p_dspin_in (signal_int_dspin_p2m_memc); + memc->p_dspin_out (signal_int_dspin_m2p_memc); + + // wrapper to INT network + memc_int_wt->p_clk (this->p_clk); + memc_int_wt->p_resetn (this->p_resetn); + memc_int_wt->p_dspin_cmd (signal_int_dspin_cmd_memc_t); + memc_int_wt->p_dspin_rsp (signal_int_dspin_rsp_memc_t); + memc_int_wt->p_vci (signal_int_vci_tgt_memc); + + // wrapper to RAM network + memc_ram_wi->p_clk (this->p_clk); + memc_ram_wi->p_resetn (this->p_resetn); + memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); + memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); + memc_ram_wi->p_vci (signal_ram_vci_ini_memc); + + //////////////////////////////////// XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_ram_vci_tgt_xram); + + // wrapper to RAM network + xram_ram_wt->p_clk (this->p_clk); + xram_ram_wt->p_resetn (this->p_resetn); + xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); + xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); + xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); + + /////////////////////////////////// MDMA + mdma->p_clk (this->p_clk); + mdma->p_resetn (this->p_resetn); + mdma->p_vci_target (signal_int_vci_tgt_mdma); + mdma->p_vci_initiator (signal_int_vci_ini_mdma); + for (size_t i=0 ; ip_irq[i] (signal_irq_mdma[i]); + + // target wrapper + mdma_int_wt->p_clk (this->p_clk); + mdma_int_wt->p_resetn (this->p_resetn); + mdma_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mdma_t); + mdma_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mdma_t); + mdma_int_wt->p_vci (signal_int_vci_tgt_mdma); + + // initiator wrapper + mdma_int_wi->p_clk (this->p_clk); + mdma_int_wi->p_resetn (this->p_resetn); + mdma_int_wi->p_dspin_cmd (signal_int_dspin_cmd_mdma_i); + mdma_int_wi->p_dspin_rsp (signal_int_dspin_rsp_mdma_i); + mdma_int_wi->p_vci (signal_int_vci_ini_mdma); + + // For the IO bridge and the RAM network components, the connexions + // depend on cluster type: The vci_io_bridge and dspin_local_crossbar + // components are only in cluster_iob0 & cluster_iob1 + + if ( (cluster_id != cluster_iob0) and (cluster_id != cluster_iob1) ) + { + // RAM network CMD & RSP routers + ram_router_cmd->p_clk (this->p_clk); + ram_router_cmd->p_resetn (this->p_resetn); + ram_router_rsp->p_clk (this->p_clk); + ram_router_rsp->p_resetn (this->p_resetn); + for( size_t n=0 ; n<4 ; n++) + { + ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); + ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); + ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); + ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); + } + ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); + ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); + ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); + ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); + } + else // IO cluster + { + // IO bridge + iob->p_clk (this->p_clk); + iob->p_resetn (this->p_resetn); + iob->p_vci_ini_iox (*(this->p_vci_iox_ini)); + iob->p_vci_tgt_iox (*(this->p_vci_iox_tgt)); + iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); + iob->p_vci_ini_int (signal_int_vci_ini_iobx); + iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); + if ( cluster_id == cluster_iob0 ) + for ( size_t n=0 ; n<32 ; n++ ) + iob->p_irq[n]->bind (*(this->p_irq[n])); + + // initiator wrapper to RAM network + iob_ram_wi->p_clk (this->p_clk); + iob_ram_wi->p_resetn (this->p_resetn); + iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iobx_i); + iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iobx_i); + iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); + + // initiator wrapper to INT network + iob_int_wi->p_clk (this->p_clk); + iob_int_wi->p_resetn (this->p_resetn); + iob_int_wi->p_dspin_cmd (signal_int_dspin_cmd_iobx_i); + iob_int_wi->p_dspin_rsp (signal_int_dspin_rsp_iobx_i); + iob_int_wi->p_vci (signal_int_vci_ini_iobx); + + // target wrapper to INT network + iob_int_wt->p_clk (this->p_clk); + iob_int_wt->p_resetn (this->p_resetn); + iob_int_wt->p_dspin_cmd (signal_int_dspin_cmd_iobx_t); + iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t); + iob_int_wt->p_vci (signal_int_vci_tgt_iobx); + + // RAM network CMD local crossbar + ram_xbar_cmd->p_clk (this->p_clk); + ram_xbar_cmd->p_resetn (this->p_resetn); + ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_l2g); + ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_g2l); + ram_xbar_cmd->p_local_in[0] (signal_ram_dspin_cmd_memc_i); + ram_xbar_cmd->p_local_in[1] (signal_ram_dspin_cmd_iobx_i); + ram_xbar_cmd->p_local_out[0] (signal_ram_dspin_cmd_xram_t); + + // RAM network RSP local crossbar + ram_xbar_rsp->p_clk (this->p_clk); + ram_xbar_rsp->p_resetn (this->p_resetn); + ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_l2g); + ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_g2l); + ram_xbar_rsp->p_local_in[0] (signal_ram_dspin_rsp_xram_t); + ram_xbar_rsp->p_local_out[0] (signal_ram_dspin_rsp_memc_i); + ram_xbar_rsp->p_local_out[1] (signal_ram_dspin_rsp_iobx_i); + + // RAM network CMD & RSP routers + ram_router_cmd->p_clk (this->p_clk); + ram_router_cmd->p_resetn (this->p_resetn); + ram_router_rsp->p_clk (this->p_clk); + ram_router_rsp->p_resetn (this->p_resetn); + for( size_t n=0 ; n<4 ; n++) + { + ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); + ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); + ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); + ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); + } + ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_g2l); + ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_l2g); + ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_g2l); + ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_l2g); + } + +} // end constructor + +}} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 + + + Index: trunk/platforms/tsar_generic_xbar/Makefile =================================================================== --- trunk/platforms/tsar_generic_xbar/Makefile (revision 449) +++ trunk/platforms/tsar_generic_xbar/Makefile (revision 450) @@ -1,4 +1,4 @@ simul.x: top.cpp top.desc - soclib-cc -j8 -P -p top.desc -I. -o simul.x + soclib-cc -j3 -P -p top.desc -I. -o simul.x clean: