- Timestamp:
- Jul 19, 2013, 10:15:13 AM (11 years ago)
- Location:
- branches/v5/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_vcache_wrapper.h (modified) (3 diffs)
-
src/vci_cc_vcache_wrapper.cpp (modified) (37 diffs)
Legend:
- Unmodified
- Added
- Removed
-
branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r446 r454 91 91 ICACHE_CC_UPDT, 92 92 ICACHE_CC_INVAL, 93 ICACHE_CC_SEND_WAIT,94 93 }; 95 94 … … 139 138 DCACHE_CC_UPDT, 140 139 DCACHE_CC_INVAL, 141 DCACHE_CC_SEND_WAIT,142 140 // handling TLB inval (after a coherence or XTN request) 143 141 DCACHE_INVAL_TLB_SCAN, … … 171 169 { 172 170 CC_RECEIVE_IDLE, 173 CC_RECEIVE_CLACK,174 171 CC_RECEIVE_BRDCAST_HEADER, 175 172 CC_RECEIVE_BRDCAST_NLINE, 176 CC_RECEIVE_INVAL_HEADER, 177 CC_RECEIVE_INVAL_NLINE, 178 CC_RECEIVE_UPDT_HEADER, 179 CC_RECEIVE_UPDT_NLINE, 180 CC_RECEIVE_UPDT_DATA, 173 CC_RECEIVE_INS_INVAL_HEADER, 174 CC_RECEIVE_INS_INVAL_NLINE, 175 CC_RECEIVE_INS_UPDT_HEADER, 176 CC_RECEIVE_INS_UPDT_NLINE, 177 CC_RECEIVE_INS_UPDT_DATA, 178 CC_RECEIVE_DATA_INVAL_HEADER, 179 CC_RECEIVE_DATA_INVAL_NLINE, 180 CC_RECEIVE_DATA_UPDT_HEADER, 181 CC_RECEIVE_DATA_UPDT_NLINE, 182 CC_RECEIVE_DATA_UPDT_DATA, 181 183 }; 182 184 -
branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r446 r454 64 64 "ICACHE_CC_UPDT", 65 65 "ICACHE_CC_INVAL", 66 "ICACHE_CC_SEND_WAIT",67 66 }; 68 67 … … 111 110 "DCACHE_CC_UPDT", 112 111 "DCACHE_CC_INVAL", 113 "DCACHE_CC_SEND_WAIT",114 112 115 113 "DCACHE_INVAL_TLB_SCAN", … … 158 156 const char *cc_receive_fsm_state_str[] = { 159 157 "CC_RECEIVE_IDLE", 160 "CC_RECEIVE_CLACK",161 158 "CC_RECEIVE_BRDCAST_HEADER", 162 159 "CC_RECEIVE_BRDCAST_NLINE", 163 "CC_RECEIVE_INVAL_HEADER", 164 "CC_RECEIVE_INVAL_NLINE", 165 "CC_RECEIVE_UPDT_HEADER", 166 "CC_RECEIVE_UPDT_NLINE", 167 "CC_RECEIVE_UPDT_DATA", 160 "CC_RECEIVE_INS_INVAL_HEADER", 161 "CC_RECEIVE_INS_INVAL_NLINE", 162 "CC_RECEIVE_INS_UPDT_HEADER", 163 "CC_RECEIVE_INS_UPDT_NLINE", 164 "CC_RECEIVE_INS_UPDT_DATA", 165 "CC_RECEIVE_DATA_INVAL_HEADER", 166 "CC_RECEIVE_DATA_INVAL_NLINE", 167 "CC_RECEIVE_DATA_UPDT_HEADER", 168 "CC_RECEIVE_DATA_UPDT_NLINE", 169 "CC_RECEIVE_DATA_UPDT_DATA", 168 170 }; 169 171 … … 1817 1819 paddr_t mask = ~((m_icache_words<<2)-1); 1818 1820 1819 if ( r_icache_clack_req.read())1821 if ( r_icache_clack_req.read() ) 1820 1822 // We switch the directory slot to EMPTY state 1821 1823 // and reset r_icache_miss_clack if the cleanup ack … … 1837 1839 r_icache_miss_clack = false; 1838 1840 1839 r_icache_fsm = r_icache_fsm_save.read() ;1840 1841 r_icache_clack_req = false; 1841 1842 … … 1849 1850 } 1850 1851 #endif 1851 } 1852 else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or 1852 // we should handle the clack request first, 1853 // if the cc request is arrived simultaneously, 1854 // we stay here in next cycle for treating the cc request. 1855 if ( not r_cc_receive_icache_req.read() ) 1856 r_icache_fsm = r_icache_fsm_save.read(); 1857 1858 break; 1859 } 1860 else if( r_cc_receive_icache_req.read() and 1861 ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or 1853 1862 (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or 1854 1863 (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and … … 1901 1910 r_icache_cc_set = set; 1902 1911 1903 if ( state == CACHE_SLOT_STATE_VALID) // hit1912 if ( state == CACHE_SLOT_STATE_VALID) // hit 1904 1913 { 1905 1914 // need to update the cache state 1906 r_icache_cc_need_write = true;1907 1915 if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update 1908 1916 { 1917 r_icache_cc_need_write = true; 1909 1918 r_icache_fsm = ICACHE_CC_UPDT; 1910 1919 r_icache_cc_word = r_cc_receive_word_idx.read(); 1911 1920 } 1912 else if ((r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) || // hit inval 1913 (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST)) // hit broadcast 1921 else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval 1914 1922 { 1915 1923 r_icache_fsm = ICACHE_CC_INVAL; … … 1935 1943 break; 1936 1944 } 1945 ///////////////////// 1946 case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state 1947 { 1948 1949 #if DEBUG_ICACHE 1950 if ( m_debug_activated ) 1951 { 1952 std::cout << " <PROC " << name() 1953 << " ICACHE_CC_INVAL> slot returns to zombi state" 1954 << " set = " << r_icache_cc_set.read() 1955 << " / way = " << r_icache_cc_way.read() << std::endl; 1956 } 1957 #endif 1958 1959 #ifdef INSTRUMENTATION 1960 m_cpt_icache_dir_read++; 1961 #endif 1962 // send a cleanup request to cc_send_fsm 1963 if(not r_icache_cc_send_req.read()) // cc_send is available 1964 { 1965 r_icache.write_dir( 0, 1966 r_icache_cc_way.read(), 1967 r_icache_cc_set.read(), 1968 CACHE_SLOT_STATE_ZOMBI ); 1969 // coherence request completed 1970 r_icache_cc_send_req = true; 1971 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 1972 r_icache_cc_send_way = r_icache_cc_way.read(); 1973 r_icache_cc_send_type = CC_TYPE_CLEANUP; 1974 1975 r_icache_fsm = r_icache_fsm_save.read(); 1976 } 1977 //else go to CC_CHECK 1978 else 1979 r_icache_fsm = ICACHE_CC_CHECK; 1980 break; 1981 1982 } 1937 1983 //////////////////// 1938 1984 case ICACHE_CC_UPDT: // hit update : write one word per cycle … … 1957 2003 size_t set = r_icache_cc_set.read(); 1958 2004 1959 if (r_cc_receive_updt_fifo_be.rok())2005 if( (not r_icache_cc_send_req.read()) and r_cc_receive_updt_fifo_be.rok() ) // cc_send is available 1960 2006 { 1961 2007 if (r_icache_cc_need_write.read()) … … 1973 2019 // no need to write in the cache anymore 1974 2020 r_icache_cc_need_write = false; 1975 // wait to send a request to cc_send_fsm 1976 if(not r_icache_cc_send_req.read()) // cc_send is available 1977 { 1978 //consume last flit 1979 cc_receive_updt_fifo_get = true; 1980 // coherence request completed 1981 r_cc_receive_icache_req = false; 1982 // request multicast acknowledgement 1983 r_icache_cc_send_req = true; 1984 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 1985 r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); 1986 r_icache_cc_send_type = CC_TYPE_MULTI_ACK; 1987 1988 r_icache_fsm = r_icache_fsm_save.read(); 1989 } 1990 } 1991 else 1992 { 1993 //consume fifo if not eop 1994 cc_receive_updt_fifo_get = true; 1995 } 1996 } 2021 // coherence request completed 2022 r_cc_receive_icache_req = false; 2023 // request multicast acknowledgement 2024 r_icache_cc_send_req = true; 2025 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 2026 r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); 2027 r_icache_cc_send_type = CC_TYPE_MULTI_ACK; 2028 2029 r_icache_fsm = r_icache_fsm_save.read(); 2030 } 2031 //consume fifo if not eop 2032 cc_receive_updt_fifo_get = true; 2033 } 2034 else 2035 r_icache_fsm = ICACHE_CC_CHECK; 2036 1997 2037 break; 1998 2038 } 1999 ///////////////////////// 2000 case ICACHE_CC_INVAL: // hit invalidate : switch slot to ZOMBI state 2001 // and request a cleanup 2002 { 2003 2004 #if DEBUG_ICACHE 2005 if ( m_debug_activated ) 2006 { 2007 std::cout << " <PROC " << name() 2008 << " ICACHE_CC_INVAL > Slot goes to zombi state " 2009 << " set = " << r_icache_cc_set.read() 2010 << " / way = " << r_icache_cc_way.read() << std::endl; 2011 } 2012 #endif 2013 2014 #ifdef INSTRUMENTATION 2015 m_cpt_icache_dir_write++; 2016 #endif 2017 if (r_icache_cc_need_write.read()) 2018 { 2019 r_icache.write_dir( r_icache_cc_way.read(), 2020 r_icache_cc_set.read(), 2021 CACHE_SLOT_STATE_ZOMBI ); 2022 // no need to write in the cache anymore 2023 r_icache_cc_need_write = false; 2024 } 2025 2026 // cleanup 2027 // send a request to cc_send_fsm 2028 if(not r_icache_cc_send_req.read()) // cc_send is available 2029 { 2030 // coherence request completed 2031 r_cc_receive_icache_req = false; 2032 // request cleanup 2033 r_icache_cc_send_req = true; 2034 r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); 2035 r_icache_cc_send_way = r_icache_cc_way.read(); 2036 r_icache_cc_send_type = CC_TYPE_CLEANUP; 2037 2038 r_icache_fsm = r_icache_fsm_save.read(); 2039 } 2040 //else wait for previous cc_send request to be sent 2041 break; 2042 } 2039 2043 2040 } // end switch r_icache_fsm 2044 2041 … … 4557 4554 #endif 4558 4555 4559 if ( r_dcache_clack_req.read())4556 if ( r_dcache_clack_req.read() ) 4560 4557 // We switch the directory slot to EMPTY state 4561 4558 // and reset r_icache_miss_clack if the cleanup ack … … 4577 4574 r_dcache_miss_clack = false; 4578 4575 4579 r_dcache_fsm = r_dcache_fsm_cc_save.read() ;4580 4576 r_dcache_clack_req = false; 4581 4577 #if DEBUG_DCACHE … … 4588 4584 } 4589 4585 #endif 4590 } 4591 else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or 4592 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or 4593 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and 4594 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching 4586 if ( not r_cc_receive_dcache_req.read() ) 4587 r_dcache_fsm = r_dcache_fsm_cc_save.read() ; 4588 4589 break; 4590 } 4591 else if( r_cc_receive_dcache_req.read() and 4592 ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or 4593 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or 4594 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and 4595 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching 4595 4596 { 4596 4597 // signaling matching … … 4645 4646 { 4646 4647 // need to update the cache state 4647 r_dcache_cc_need_write = true;4648 4648 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 4649 4649 { 4650 r_dcache_cc_need_write = true; 4650 4651 r_dcache_fsm = DCACHE_CC_UPDT; 4651 4652 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4652 4653 } 4653 else if ((r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) || // hit broadcast 4654 (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL )) // hit inval 4654 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval 4655 4655 { 4656 4656 r_dcache_fsm = DCACHE_CC_INVAL; … … 4687 4687 break; 4688 4688 } 4689 ///////////////////// 4690 case DCACHE_CC_INVAL: // hit inval: switch slot to EMPTY state, 4691 // after possible invalidation of copies in TLBs 4692 { 4693 size_t way = r_dcache_cc_way.read(); 4694 size_t set = r_dcache_cc_set.read(); 4695 4696 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4697 { 4698 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4699 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 4700 r_dcache_tlb_inval_set = 0; 4701 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4702 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4703 break; 4704 } 4705 4706 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4707 { 4708 r_itlb.reset(); 4709 r_dtlb.reset(); 4710 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4711 4712 #if DEBUG_DCACHE 4713 if ( m_debug_activated ) 4714 { 4715 std::cout << " <PROC " << name() 4716 << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl; 4717 } 4718 #endif 4719 } 4720 4721 if ( not r_dcache_cc_send_req.read() ) // cc_send is available 4722 { 4723 r_dcache.write_dir( 0, 4724 way, 4725 set, 4726 CACHE_SLOT_STATE_ZOMBI ); 4727 4728 #if DEBUG_DCACHE 4729 if ( m_debug_activated ) 4730 { 4731 std::cout << " <PROC " << name() 4732 << " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec 4733 << " / WAY = " << way 4734 << " / SET = " << set << std::endl; 4735 } 4736 #endif 4737 // coherence request completed 4738 r_cc_receive_dcache_req = false; 4739 r_dcache_cc_send_req = true; 4740 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4741 r_dcache_cc_send_way = r_dcache_cc_way.read(); 4742 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4743 4744 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4745 } 4746 //else go to DCACHE_CC_CHECK 4747 else 4748 r_dcache_fsm = DCACHE_CC_CHECK; 4749 4750 break; 4751 } 4689 4752 /////////////////// 4690 4753 case DCACHE_CC_UPDT: // hit update: write one word per cycle, … … 4695 4758 size_t set = r_dcache_cc_set.read(); 4696 4759 4697 if (r_cc_receive_updt_fifo_be.rok()) 4698 { 4699 if (r_dcache_cc_need_write.read()) 4700 { 4701 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4702 { 4703 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4704 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 4705 r_dcache_tlb_inval_set = 0; 4706 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4707 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4708 break; 4709 } 4710 4711 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4712 { 4713 r_itlb.reset(); 4714 r_dtlb.reset(); 4715 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4760 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4761 { 4762 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4763 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 4764 r_dcache_tlb_inval_set = 0; 4765 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4766 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4767 break; 4768 } 4769 4770 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4771 { 4772 r_itlb.reset(); 4773 r_dtlb.reset(); 4774 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4716 4775 4717 4776 #if DEBUG_DCACHE … … 4722 4781 } 4723 4782 #endif 4724 } 4725 4783 } 4784 4785 if ( (not r_dcache_cc_send_req.read()) and r_cc_receive_updt_fifo_be.rok()) 4786 { 4787 if (r_dcache_cc_need_write.read()) 4788 { 4789 4726 4790 #ifdef INSTRUMENTATION 4727 4791 m_cpt_dcache_data_write++; … … 4753 4817 r_dcache_cc_need_write = false; 4754 4818 4755 // wait to send a request to cc_send_fsm 4756 if(not r_dcache_cc_send_req.read()) 4757 // cc_send is available 4758 { 4759 //consume last fifo flit if eop and request to cc_send possible 4760 cc_receive_updt_fifo_get = true; 4761 4762 // coherence request completed 4763 r_cc_receive_dcache_req = false; 4764 4765 // request multicast acknowledgement 4766 r_dcache_cc_send_req = true; 4767 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4768 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 4769 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 4770 4771 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4772 } 4773 } 4774 else 4775 { 4776 //consume fifo if not eop 4777 cc_receive_updt_fifo_get = true; 4778 } 4779 } 4780 break; 4781 } 4782 ///////////////////////// 4783 case DCACHE_CC_INVAL: // hit invalidate : switch state to ZOMBI state 4784 // and request a cleanup, after possible 4785 // invalidation of copies in TLBs 4786 { 4787 size_t way = r_dcache_cc_way.read(); 4788 size_t set = r_dcache_cc_set.read(); 4789 paddr_t nline = r_cc_receive_dcache_nline.read(); 4790 4791 if (r_dcache_cc_need_write.read()) 4792 { 4793 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4794 { 4795 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4796 r_dcache_tlb_inval_line = nline; 4797 r_dcache_tlb_inval_set = 0; 4798 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4799 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4800 break; 4801 } 4802 else 4803 { 4804 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4805 { 4806 r_itlb.reset(); 4807 r_dtlb.reset(); 4808 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4809 4810 #if DEBUG_DCACHE 4811 if ( m_debug_activated ) 4812 { 4813 std::cout << " <PROC " << name() 4814 << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl; 4815 } 4816 #endif 4817 } 4818 4819 #ifdef INSTRUMENTATION 4820 m_cpt_dcache_dir_write++; 4821 #endif 4822 r_dcache.write_dir( way, 4823 set, 4824 CACHE_SLOT_STATE_ZOMBI ); 4825 4826 r_dcache_cc_need_write = false; 4827 #if DEBUG_DCACHE 4828 if ( m_debug_activated ) 4829 { 4830 std::cout << " <PROC " << name() 4831 << " DCACHE_CC_INVAL > Slot goes to ZOMBI state " 4832 << " SET = " << set 4833 << " / WAY = " << way << std::endl; 4834 } 4835 #endif 4836 } 4837 } 4838 // cleanup 4839 // send a request to cc_send_fsm 4840 if(not r_dcache_cc_send_req.read()) // cc_send is available 4841 { 4842 // coherence request completed 4843 r_cc_receive_dcache_req = false; 4844 // request cleanup 4845 r_dcache_cc_send_req = true; 4846 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4847 r_dcache_cc_send_way = r_dcache_cc_way.read(); 4848 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4849 4850 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4851 } 4852 //else wait for previous cc_send request to be sent 4819 // coherence request completed 4820 r_cc_receive_dcache_req = false; 4821 4822 // request multicast acknowledgement 4823 r_dcache_cc_send_req = true; 4824 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4825 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 4826 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 4827 4828 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4829 } 4830 4831 //consume fifo if not eop 4832 cc_receive_updt_fifo_get = true; 4833 } 4834 else 4835 r_dcache_fsm = DCACHE_CC_CHECK; 4836 4853 4837 break; 4854 4838 } … … 5480 5464 5481 5465 /////////////////////////////////////////////////////////////////////////////// 5482 // 5466 // CC_RECEIVE FSM 5483 5467 // This FSM receive all coherence packets on a DSPIN40 port. 5484 // There is 7packet types:5468 // There is 5 packet types: 5485 5469 // - CC_DATA_INVAL : DCACHE invalidate request 5486 5470 // - CC_DATA_UPDT : DCACHE update request (multi-words) … … 5488 5472 // - CC_INST_UPDT : ICACHE update request (multi-words) 5489 5473 // - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE) 5490 // - CC_DATA_CLACK : DCACHE cleanup acknowledge5491 // - CC_INST_CLACK : ICACHE cleanup acknowledge5492 5474 ////////////////////////////////////////////////////////////////////////////// 5493 5475 switch( r_cc_receive_fsm.read() ) … … 5504 5486 uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, 5505 5487 DspinDhccpParam::M2P_TYPE); 5506 // initialize data/ins flip_flop (0 data / 1 ins)5507 r_cc_receive_data_ins = (bool)(receive_type & 0x1);5508 5488 // test for a broadcast 5509 5489 if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC)) … … 5512 5492 } 5513 5493 // test for a multi updt 5514 else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or 5515 (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)) 5494 else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) 5516 5495 { 5517 r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER; 5496 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER; 5497 } 5498 else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST) 5499 { 5500 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER; 5518 5501 } 5519 5502 // test for a multi inval 5503 else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA) 5504 { 5505 r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER; 5506 } 5520 5507 else 5521 5508 { 5522 r_cc_receive_fsm = CC_RECEIVE_IN VAL_HEADER;5509 r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER; 5523 5510 } 5524 5511 } … … 5546 5533 { 5547 5534 // request dcache to handle the BROADCAST 5548 r_cc_receive_dcache_req 5535 r_cc_receive_dcache_req = true; 5549 5536 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, 5550 5537 DspinDhccpParam::BROADCAST_NLINE); 5551 r_cc_receive_dcache_type = CC_TYPE_ BRDCAST;5538 r_cc_receive_dcache_type = CC_TYPE_INVAL; 5552 5539 // request icache to handle the BROADCAST 5553 r_cc_receive_icache_req 5540 r_cc_receive_icache_req = true; 5554 5541 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data, 5555 5542 DspinDhccpParam::BROADCAST_NLINE); 5556 r_cc_receive_icache_type = CC_TYPE_ BRDCAST;5543 r_cc_receive_icache_type = CC_TYPE_INVAL; 5557 5544 // get back to idle state 5558 5545 r_cc_receive_fsm = CC_RECEIVE_IDLE; … … 5563 5550 } 5564 5551 ///////////////////////////// 5565 case CC_RECEIVE_ INVAL_HEADER:5552 case CC_RECEIVE_DATA_INVAL_HEADER: 5566 5553 { 5567 5554 // sample updt tab index in the HEADER, then skip to second flit 5568 uint64_t receive_data = p_dspin_m2p.data.read(); 5569 // for data INVAL, wait for dcache to take the request 5570 if ((r_cc_receive_data_ins.read() == 0) and 5571 not (r_cc_receive_dcache_req.read())) 5572 { 5573 r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data, 5574 DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); 5575 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE; 5576 break; 5577 } 5578 // for ins INVAL, wait for icache to take the request 5579 if ((r_cc_receive_data_ins.read() == 1) and 5580 not (r_cc_receive_icache_req.read())) 5581 { 5582 r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data, 5583 DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); 5584 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE; 5585 break; 5586 } 5587 // keep waiting for the correct cache to accept the request 5555 r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE; 5556 break; 5557 } 5558 ///////////////////////////// 5559 case CC_RECEIVE_INS_INVAL_HEADER: 5560 { 5561 // sample updt tab index in the HEADER, then skip to second flit 5562 r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE; 5588 5563 break; 5589 5564 } 5590 5565 //////////////////////////// 5591 case CC_RECEIVE_ INVAL_NLINE:5566 case CC_RECEIVE_DATA_INVAL_NLINE: 5592 5567 { 5593 5568 // sample nline in the second flit 5594 5569 uint64_t receive_data = p_dspin_m2p.data.read(); 5595 5570 // for data INVAL, wait for dcache to take the request 5596 if ( (r_cc_receive_data_ins.read() == 0) and 5597 not (r_cc_receive_dcache_req.read()) and 5598 (p_dspin_m2p.write.read()) ) 5571 if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read()) 5599 5572 { 5600 5573 // request dcache to handle the INVAL 5601 r_cc_receive_dcache_req 5602 r_cc_receive_dcache_nline 5574 r_cc_receive_dcache_req = true; 5575 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); 5603 5576 r_cc_receive_dcache_type = CC_TYPE_INVAL; 5604 5577 // get back to idle state … … 5606 5579 break; 5607 5580 } 5581 break; 5582 } 5583 ////////////////////////////// 5584 case CC_RECEIVE_INS_INVAL_NLINE: 5585 { 5586 // sample nline in the second flit 5587 uint64_t receive_data = p_dspin_m2p.data.read(); 5608 5588 // for ins INVAL, wait for icache to take the request 5609 if ( (r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read()))5589 if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read()) 5610 5590 { 5611 5591 // request icache to handle the INVAL 5612 r_cc_receive_icache_req 5613 r_cc_receive_icache_nline 5592 r_cc_receive_icache_req = true; 5593 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); 5614 5594 r_cc_receive_icache_type = CC_TYPE_INVAL; 5615 5595 // get back to idle state … … 5617 5597 break; 5618 5598 } 5619 // we should never get there 5620 assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_INVAL_NLINE\n"); 5599 break; 5621 5600 } 5622 5601 //////////////////////////// 5623 case CC_RECEIVE_ UPDT_HEADER:5602 case CC_RECEIVE_DATA_UPDT_HEADER: 5624 5603 { 5625 5604 // sample updt tab index in the HEADER, than skip to second flit … … 5627 5606 // for data INVAL, wait for dcache to take the request and fifo to 5628 5607 // be empty 5629 if ( (r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())5608 if (not r_cc_receive_dcache_req.read()) 5630 5609 { 5631 5610 r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); 5632 r_cc_receive_fsm = CC_RECEIVE_ UPDT_NLINE;5611 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE; 5633 5612 break; 5634 5613 } 5614 break; 5615 } 5616 //////////////////////////// 5617 case CC_RECEIVE_INS_UPDT_HEADER: 5618 { 5619 // sample updt tab index in the HEADER, than skip to second flit 5620 uint64_t receive_data = p_dspin_m2p.data.read(); 5635 5621 // for ins INVAL, wait for icache to take the request and fifo to be 5636 5622 // empty 5637 if ( (r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())5623 if (not r_cc_receive_icache_req.read()) 5638 5624 { 5639 5625 r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); 5640 r_cc_receive_fsm = CC_RECEIVE_ UPDT_NLINE;5626 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE; 5641 5627 break; 5642 5628 } … … 5645 5631 } 5646 5632 /////////////////////////// 5647 case CC_RECEIVE_ UPDT_NLINE:5633 case CC_RECEIVE_DATA_UPDT_NLINE: 5648 5634 { 5649 5635 // sample nline and word index in the second flit … … 5651 5637 // for data INVAL, wait for dcache to take the request and fifo to 5652 5638 // be empty 5653 if ( (r_cc_receive_data_ins.read() == 0) and 5654 not (r_cc_receive_dcache_req.read()) and 5655 r_cc_receive_updt_fifo_be.empty() and 5656 (p_dspin_m2p.write.read()) ) 5657 { 5639 if ( r_cc_receive_updt_fifo_be.empty() and 5640 p_dspin_m2p.write.read() ) 5641 { 5642 r_cc_receive_dcache_req = true; 5658 5643 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); 5659 5644 r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); 5660 5645 r_cc_receive_dcache_type = CC_TYPE_UPDT; 5661 5646 // get back to idle state 5662 r_cc_receive_fsm = CC_RECEIVE_ UPDT_DATA;5647 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA; 5663 5648 break; 5664 5649 } 5650 break; 5651 } 5652 //////////////////////////// 5653 case CC_RECEIVE_INS_UPDT_NLINE: 5654 { 5655 // sample nline and word index in the second flit 5656 uint64_t receive_data = p_dspin_m2p.data.read(); 5665 5657 // for ins INVAL, wait for icache to take the request and fifo to be 5666 5658 // empty 5667 if ( (r_cc_receive_data_ins.read() == 1) and 5668 not (r_cc_receive_icache_req.read()) and 5669 r_cc_receive_updt_fifo_be.empty() and 5670 (p_dspin_m2p.write.read())) 5671 { 5659 if ( r_cc_receive_updt_fifo_be.empty() and 5660 p_dspin_m2p.write.read() ) 5661 { 5662 r_cc_receive_icache_req = true; 5672 5663 r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); 5673 5664 r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); 5674 5665 r_cc_receive_icache_type = CC_TYPE_UPDT; 5675 5666 // get back to idle state 5676 r_cc_receive_fsm = CC_RECEIVE_ UPDT_DATA;5667 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA; 5677 5668 break; 5678 5669 } 5679 // we should never get there5680 assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_UPDT_NLINE \n");5681 5670 break; 5682 5671 } 5683 5672 ////////////////////////// 5684 case CC_RECEIVE_UPDT_DATA: 5685 { 5686 if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_m2p.write.read())) 5687 r_cc_receive_dcache_req = true; 5688 if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read())) 5689 r_cc_receive_icache_req = true; 5690 5673 case CC_RECEIVE_DATA_UPDT_DATA: 5674 { 5691 5675 // wait for the fifo 5692 5676 if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) … … 5702 5686 break; 5703 5687 } 5688 ////////////////////////// 5689 case CC_RECEIVE_INS_UPDT_DATA: 5690 { 5691 // wait for the fifo 5692 if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) 5693 { 5694 uint64_t receive_data = p_dspin_m2p.data.read(); 5695 bool receive_eop = p_dspin_m2p.eop.read(); 5696 cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); 5697 cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); 5698 cc_receive_updt_fifo_eop = receive_eop; 5699 cc_receive_updt_fifo_put = true; 5700 if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; 5701 } 5702 break; 5703 } 5704 5704 5705 } // end switch CC_RECEIVE FSM 5705 5706 … … 6091 6092 // Receive coherence packets 6092 6093 // It depends on the CC_RECEIVE FSM 6093 6094 6094 switch( r_cc_receive_fsm.read() ) 6095 6095 { … … 6098 6098 { 6099 6099 p_dspin_m2p.read = false; 6100 break;6101 }6102 //////////////////////6103 case CC_RECEIVE_CLACK:6104 {6105 if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or6106 ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))6107 p_dspin_m2p.read = true;6108 else6109 p_dspin_m2p.read = false;6110 6100 break; 6111 6101 } … … 6129 6119 } 6130 6120 ///////////////////////////// 6131 case CC_RECEIVE_INVAL_HEADER: 6132 { 6133 if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or 6134 ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))) 6121 case CC_RECEIVE_DATA_INVAL_HEADER: 6122 case CC_RECEIVE_INS_INVAL_HEADER: 6123 { 6124 p_dspin_m2p.read = true; 6125 break; 6126 } 6127 //////////////////////////// 6128 case CC_RECEIVE_DATA_INVAL_NLINE: 6129 { 6130 p_dspin_m2p.read = not r_cc_receive_dcache_req.read(); 6131 break; 6132 } 6133 case CC_RECEIVE_INS_INVAL_NLINE: 6134 { 6135 p_dspin_m2p.read = not r_cc_receive_icache_req.read(); 6136 break; 6137 } 6138 /////////////////////////// 6139 case CC_RECEIVE_DATA_UPDT_HEADER: 6140 { 6141 if (not r_cc_receive_dcache_req.read()) 6135 6142 p_dspin_m2p.read = true; 6136 6143 else … … 6139 6146 } 6140 6147 //////////////////////////// 6141 case CC_RECEIVE_INVAL_NLINE: 6142 { 6143 p_dspin_m2p.read = true; 6144 break; 6145 } 6146 //////////////////////////// 6147 case CC_RECEIVE_UPDT_HEADER: 6148 { 6149 if (((r_cc_receive_data_ins.read() == 0) and 6150 not r_cc_receive_dcache_req.read() and 6151 r_cc_receive_updt_fifo_be.empty()) 6152 or 6153 (((r_cc_receive_data_ins.read() == 1) and 6154 not r_cc_receive_icache_req.read()) and 6155 r_cc_receive_updt_fifo_be.empty())) 6148 case CC_RECEIVE_INS_UPDT_HEADER: 6149 { 6150 if ( not r_cc_receive_icache_req.read()) 6156 6151 p_dspin_m2p.read = true; 6157 6152 else … … 6160 6155 } 6161 6156 /////////////////////////// 6162 case CC_RECEIVE_UPDT_NLINE: 6163 { 6164 if (((r_cc_receive_data_ins.read() == 0) and 6165 not (r_cc_receive_dcache_req.read()) and 6166 r_cc_receive_updt_fifo_be.empty()) 6167 or 6168 ((r_cc_receive_data_ins.read() == 1) and 6169 not (r_cc_receive_icache_req.read()) and 6170 r_cc_receive_updt_fifo_be.empty())) 6157 case CC_RECEIVE_DATA_UPDT_NLINE: 6158 case CC_RECEIVE_INS_UPDT_NLINE: 6159 { 6160 if(r_cc_receive_updt_fifo_be.empty()) 6171 6161 p_dspin_m2p.read = true; 6172 6162 else … … 6174 6164 break; 6175 6165 } 6176 ////////////////////////// 6177 case CC_RECEIVE_UPDT_DATA: 6166 /////////////////////////// 6167 case CC_RECEIVE_DATA_UPDT_DATA: 6168 case CC_RECEIVE_INS_UPDT_DATA: 6178 6169 { 6179 6170 if (r_cc_receive_updt_fifo_be.wok()) … … 6184 6175 } 6185 6176 } // end switch CC_RECEIVE FSM 6177 6186 6178 6187 6179 int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
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