Index: branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 446)
+++ branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 454)
@@ -64,5 +64,4 @@
         "ICACHE_CC_UPDT",
         "ICACHE_CC_INVAL",
-        "ICACHE_CC_SEND_WAIT",
     };
 
@@ -111,5 +110,4 @@
         "DCACHE_CC_UPDT",
         "DCACHE_CC_INVAL",
-        "DCACHE_CC_SEND_WAIT",
 
         "DCACHE_INVAL_TLB_SCAN",
@@ -158,12 +156,16 @@
 const char *cc_receive_fsm_state_str[] = {
         "CC_RECEIVE_IDLE",
-        "CC_RECEIVE_CLACK",
         "CC_RECEIVE_BRDCAST_HEADER",
         "CC_RECEIVE_BRDCAST_NLINE",
-        "CC_RECEIVE_INVAL_HEADER",
-        "CC_RECEIVE_INVAL_NLINE",
-        "CC_RECEIVE_UPDT_HEADER",
-        "CC_RECEIVE_UPDT_NLINE",
-        "CC_RECEIVE_UPDT_DATA",
+        "CC_RECEIVE_INS_INVAL_HEADER",
+        "CC_RECEIVE_INS_INVAL_NLINE",
+        "CC_RECEIVE_INS_UPDT_HEADER",
+        "CC_RECEIVE_INS_UPDT_NLINE",
+        "CC_RECEIVE_INS_UPDT_DATA",
+        "CC_RECEIVE_DATA_INVAL_HEADER",
+        "CC_RECEIVE_DATA_INVAL_NLINE",
+        "CC_RECEIVE_DATA_UPDT_HEADER",
+        "CC_RECEIVE_DATA_UPDT_NLINE",
+        "CC_RECEIVE_DATA_UPDT_DATA",
     };
 
@@ -1817,5 +1819,5 @@
         paddr_t  mask  = ~((m_icache_words<<2)-1);
 
-        if (r_icache_clack_req.read())
+        if ( r_icache_clack_req.read() )
                            	// We switch the directory slot to EMPTY state
                             // and reset r_icache_miss_clack if the cleanup ack
@@ -1837,5 +1839,4 @@
                     r_icache_miss_clack = false;
 
-            r_icache_fsm = r_icache_fsm_save.read() ;
             r_icache_clack_req = false;
 
@@ -1849,6 +1850,14 @@
 }
 #endif
-        }
-        else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
+            // we should handle the clack request first, 
+            // if the cc request is arrived simultaneously, 
+            // we stay here in next cycle for treating the cc request. 
+            if ( not r_cc_receive_icache_req.read() )
+                r_icache_fsm          = r_icache_fsm_save.read();
+
+            break;
+       }
+        else if( r_cc_receive_icache_req.read() and
+                 ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
                  (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
                  (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
@@ -1901,15 +1910,14 @@
             r_icache_cc_set = set;
 
-            if (state == CACHE_SLOT_STATE_VALID)            // hit
+            if ( state == CACHE_SLOT_STATE_VALID)            // hit
             {
                 // need to update the cache state
-                r_icache_cc_need_write = true;
                 if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)  // hit update
                 {
+                    r_icache_cc_need_write = true;
                     r_icache_fsm          = ICACHE_CC_UPDT;
                     r_icache_cc_word      = r_cc_receive_word_idx.read();
                 }
-                else if ((r_cc_receive_icache_type.read() == CC_TYPE_INVAL  ) || // hit inval
-                         (r_cc_receive_icache_type.read() == CC_TYPE_BRDCAST))   // hit broadcast
+                else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval
                 {
                     r_icache_fsm          = ICACHE_CC_INVAL;
@@ -1935,4 +1943,42 @@
         break;
     }
+    /////////////////////
+    case ICACHE_CC_INVAL:  	// hit inval : switch slot to ZOMBI state
+    {
+
+#if DEBUG_ICACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " ICACHE_CC_INVAL> slot returns to zombi state"
+              << " set = " << r_icache_cc_set.read()
+              << " / way = " << r_icache_cc_way.read() << std::endl;
+}
+#endif
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_dir_read++;
+#endif
+        // send a cleanup request to cc_send_fsm
+        if(not r_icache_cc_send_req.read()) // cc_send is available
+        {
+            r_icache.write_dir( 0,
+	                            r_icache_cc_way.read(),
+	                            r_icache_cc_set.read(),
+                                CACHE_SLOT_STATE_ZOMBI );
+            // coherence request completed
+            r_icache_cc_send_req = true;
+            r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
+            r_icache_cc_send_way   = r_icache_cc_way.read();
+            r_icache_cc_send_type  = CC_TYPE_CLEANUP;
+
+            r_icache_fsm          = r_icache_fsm_save.read();
+        }
+        //else go to CC_CHECK
+        else
+            r_icache_fsm          = ICACHE_CC_CHECK;
+        break;
+        
+    }
     ////////////////////
     case ICACHE_CC_UPDT:	// hit update : write one word per cycle
@@ -1957,5 +2003,5 @@
         size_t  set   = r_icache_cc_set.read();
 
-        if (r_cc_receive_updt_fifo_be.rok())
+        if( (not r_icache_cc_send_req.read()) and r_cc_receive_updt_fifo_be.rok() ) // cc_send is available
         {
             if (r_icache_cc_need_write.read())
@@ -1973,72 +2019,23 @@
                 // no need to write in the cache anymore
                 r_icache_cc_need_write = false;
-                // wait to send a request to cc_send_fsm
-                if(not r_icache_cc_send_req.read()) // cc_send is available
-                {
-                    //consume last flit
-                    cc_receive_updt_fifo_get  = true;
-                    // coherence request completed
-                    r_cc_receive_icache_req = false;
-                    // request multicast acknowledgement
-                    r_icache_cc_send_req = true;
-                    r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
-                    r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
-                    r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
-
-                    r_icache_fsm          = r_icache_fsm_save.read();
-                }
-            }
-            else
-            {
-                //consume fifo if not eop
-                cc_receive_updt_fifo_get  = true;
-            }
-        }
+                // coherence request completed
+                r_cc_receive_icache_req = false;
+                // request multicast acknowledgement
+                r_icache_cc_send_req = true;
+                r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
+                r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
+                r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
+
+                r_icache_fsm          = r_icache_fsm_save.read();
+            }
+            //consume fifo if not eop
+            cc_receive_updt_fifo_get  = true;
+        }
+        else
+            r_icache_fsm            = ICACHE_CC_CHECK;
+
         break;
     }
-    /////////////////////////
-    case ICACHE_CC_INVAL:  // hit invalidate : switch slot to ZOMBI state
-                           // and request a cleanup
-    {
-
-#if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_CC_INVAL > Slot goes to zombi state "
-              << " set = " << r_icache_cc_set.read()
-              << " / way = " << r_icache_cc_way.read() << std::endl;
-}
-#endif
-
-#ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-        if (r_icache_cc_need_write.read())
-        {
-            r_icache.write_dir( r_icache_cc_way.read(),
-	                            r_icache_cc_set.read(),
-                                CACHE_SLOT_STATE_ZOMBI );
-            // no need to write in the cache anymore
-            r_icache_cc_need_write = false;
-        }
-
-        // cleanup
-        // send a request to cc_send_fsm
-        if(not r_icache_cc_send_req.read()) // cc_send is available
-        {
-            // coherence request completed
-            r_cc_receive_icache_req = false;
-            // request cleanup
-            r_icache_cc_send_req = true;
-            r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
-            r_icache_cc_send_way   = r_icache_cc_way.read();
-            r_icache_cc_send_type  = CC_TYPE_CLEANUP;
-
-            r_icache_fsm          = r_icache_fsm_save.read();
-        }
-        //else wait for previous cc_send request to be sent
-        break;
-    }
+
     } // end switch r_icache_fsm
 
@@ -4557,5 +4554,5 @@
 #endif
 
-        if (r_dcache_clack_req.read())
+        if ( r_dcache_clack_req.read() )
                             // We switch the directory slot to EMPTY state
                             // and reset r_icache_miss_clack if the cleanup ack
@@ -4577,5 +4574,4 @@
                   r_dcache_miss_clack = false;
 
-            r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
             r_dcache_clack_req = false;
 #if DEBUG_DCACHE
@@ -4588,9 +4584,14 @@
 }
 #endif
-        }
-        else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
-                  (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
-                  (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
-                  ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
+            if ( not r_cc_receive_dcache_req.read() )
+                r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
+
+            break;
+        }
+        else if( r_cc_receive_dcache_req.read() and 
+                 ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
+                 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
+                 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
+                 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
         {
             // signaling matching
@@ -4645,12 +4646,11 @@
             {
                 // need to update the cache state
-                r_dcache_cc_need_write = true;
                 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)  // hit update
                 {
+                    r_dcache_cc_need_write = true;
                     r_dcache_fsm          = DCACHE_CC_UPDT;
                     r_dcache_cc_word      = r_cc_receive_word_idx.read();
                 }
-                else if ((r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) || // hit broadcast
-                         (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL  ))      // hit inval
+                else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL )    // hit inval
                 {
                     r_dcache_fsm          = DCACHE_CC_INVAL;
@@ -4687,4 +4687,67 @@
         break;
     }
+    /////////////////////
+    case DCACHE_CC_INVAL:   	// hit inval: switch slot to EMPTY state,
+                                // after possible invalidation of copies in TLBs
+    {
+        size_t	 way    = r_dcache_cc_way.read();
+        size_t	 set    = r_dcache_cc_set.read();
+
+        if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 			// selective TLB inval
+        {
+            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            r_dcache_tlb_inval_line  = r_cc_receive_dcache_nline.read();
+            r_dcache_tlb_inval_set   = 0;
+            r_dcache_fsm_scan_save   = r_dcache_fsm.read();
+            r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+            break;
+        }
+
+        if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 	// TLB flush
+        {
+            r_itlb.reset();
+            r_dtlb.reset();
+            r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
+}
+#endif
+        }
+        
+        if ( not r_dcache_cc_send_req.read() ) // cc_send is available
+        {
+            r_dcache.write_dir( 0,
+                                way,
+                                set,
+                                CACHE_SLOT_STATE_ZOMBI );
+
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+{
+    std::cout << "  <PROC " << name()
+              << " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
+              << " / WAY = " << way
+              << " / SET = " << set << std::endl;
+}
+#endif
+            // coherence request completed
+            r_cc_receive_dcache_req = false;
+            r_dcache_cc_send_req = true;
+            r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
+            r_dcache_cc_send_way   = r_dcache_cc_way.read();
+            r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
+
+            r_dcache_fsm          = r_dcache_fsm_cc_save.read();
+        }
+        //else go to DCACHE_CC_CHECK 
+        else
+            r_dcache_fsm          = DCACHE_CC_CHECK;
+
+        break;
+    }
     ///////////////////
     case DCACHE_CC_UPDT:    	// hit update: write one word per cycle,
@@ -4695,23 +4758,19 @@
         size_t	 set        = r_dcache_cc_set.read();
 
-        if (r_cc_receive_updt_fifo_be.rok())
-        {
-            if (r_dcache_cc_need_write.read())
-            {
-                if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 			// selective TLB inval
-                {
-                    r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-                    r_dcache_tlb_inval_line  = r_cc_receive_dcache_nline.read();
-                    r_dcache_tlb_inval_set   = 0;
-                    r_dcache_fsm_scan_save   = r_dcache_fsm.read();
-                    r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
-                    break;
-                }
-
-                if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 	// TLB flush
-                {
-                    r_itlb.reset();
-                    r_dtlb.reset();
-                    r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+        if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 			// selective TLB inval
+        {
+            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            r_dcache_tlb_inval_line  = r_cc_receive_dcache_nline.read();
+            r_dcache_tlb_inval_set   = 0;
+            r_dcache_fsm_scan_save   = r_dcache_fsm.read();
+            r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+            break;
+        }
+
+        if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 	// TLB flush
+        {
+            r_itlb.reset();
+            r_dtlb.reset();
+            r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
 
 #if DEBUG_DCACHE
@@ -4722,6 +4781,11 @@
 }
 #endif
-                }
-
+        }
+
+        if ( (not r_dcache_cc_send_req.read()) and r_cc_receive_updt_fifo_be.rok())
+        {
+            if (r_dcache_cc_need_write.read())
+            {
+            
 #ifdef INSTRUMENTATION
 m_cpt_dcache_data_write++;
@@ -4753,102 +4817,22 @@
                 r_dcache_cc_need_write = false;
 
-                // wait to send a request to cc_send_fsm
-                if(not r_dcache_cc_send_req.read())
-                // cc_send is available
-                {
-                    //consume last fifo flit if eop and request to cc_send possible
-                    cc_receive_updt_fifo_get  = true;
-
-                    // coherence request completed
-                    r_cc_receive_dcache_req = false;
-
-                    // request multicast acknowledgement
-                    r_dcache_cc_send_req = true;
-                    r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
-                    r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
-                    r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
-
-                    r_dcache_fsm          = r_dcache_fsm_cc_save.read();
-                }
-            }
-            else
-            {
-                //consume fifo if not eop
-                cc_receive_updt_fifo_get  = true;
-            }
-        }
-        break;
-    }
-    /////////////////////////
-    case DCACHE_CC_INVAL:   // hit invalidate : switch state to ZOMBI state
-                            // and request a cleanup, after possible
-                            // invalidation of copies in TLBs
-    {
-        size_t	 way   = r_dcache_cc_way.read();
-        size_t	 set   = r_dcache_cc_set.read();
-        paddr_t  nline = r_cc_receive_dcache_nline.read();
-
-        if (r_dcache_cc_need_write.read())
-        {
-            if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 			// selective TLB inval
-            {
-                r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-                r_dcache_tlb_inval_line  = nline;
-                r_dcache_tlb_inval_set   = 0;
-                r_dcache_fsm_scan_save   = r_dcache_fsm.read();
-                r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
-                break;
-            }
-            else
-            {
-                if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 	// TLB flush
-                {
-                    r_itlb.reset();
-                    r_dtlb.reset();
-                    r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
-
-#if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
-}
-#endif
-                }
-
-#ifdef INSTRUMENTATION
-m_cpt_dcache_dir_write++;
-#endif
-                r_dcache.write_dir( way,
-                                    set,
-                                    CACHE_SLOT_STATE_ZOMBI );
-
-                r_dcache_cc_need_write = false;
-#if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_INVAL > Slot goes to ZOMBI state "
-              << " SET = " << set
-              << " / WAY = " << way << std::endl;
-}
-#endif
-            }
-        }
-        // cleanup
-        // send a request to cc_send_fsm
-        if(not r_dcache_cc_send_req.read()) // cc_send is available
-        {
-            // coherence request completed
-            r_cc_receive_dcache_req = false;
-            // request cleanup
-            r_dcache_cc_send_req = true;
-            r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
-            r_dcache_cc_send_way   = r_dcache_cc_way.read();
-            r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
-
-            r_dcache_fsm          = r_dcache_fsm_cc_save.read();
-        }
-        //else wait for previous cc_send request to be sent
+                // coherence request completed
+                r_cc_receive_dcache_req = false;
+
+                // request multicast acknowledgement
+                r_dcache_cc_send_req = true;
+                r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
+                r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
+                r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
+
+                r_dcache_fsm          = r_dcache_fsm_cc_save.read();
+            }
+
+            //consume fifo if not eop
+            cc_receive_updt_fifo_get  = true;
+        }
+        else
+            r_dcache_fsm        = DCACHE_CC_CHECK;
+
         break;
     }
@@ -5480,7 +5464,7 @@
 
     ///////////////////////////////////////////////////////////////////////////////
-    //   C_RECEIVE  FSM
+    //  CC_RECEIVE  FSM
     // This FSM receive all coherence packets on a DSPIN40 port.
-    // There is 7 packet types:
+    // There is 5 packet types:
     // - CC_DATA_INVAL : DCACHE invalidate request
     // - CC_DATA_UPDT  : DCACHE update request (multi-words)
@@ -5488,6 +5472,4 @@
     // - CC_INST_UPDT  : ICACHE update request (multi-words)
     // - CC_BROADCAST  : Broadcast invalidate request (both DCACHE & ICACHE)
-    // - CC_DATA_CLACK : DCACHE cleanup acknowledge
-    // - CC_INST_CLACK : ICACHE cleanup acknowledge
     //////////////////////////////////////////////////////////////////////////////
     switch( r_cc_receive_fsm.read() )
@@ -5504,6 +5486,4 @@
                 uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
                                             DspinDhccpParam::M2P_TYPE);
-                // initialize data/ins flip_flop (0 data / 1 ins)
-                r_cc_receive_data_ins = (bool)(receive_type & 0x1);
                 // test for a broadcast
                 if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
@@ -5512,13 +5492,20 @@
                 }
                 // test for a multi updt
-                else if ((receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) or
-                         (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST))
+                else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) 
                 {
-                    r_cc_receive_fsm = CC_RECEIVE_UPDT_HEADER;
+                    r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
+                }
+                else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
+                {
+                    r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
                 }
                 // test for a multi inval
+                else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
+                {
+                    r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
+                }
                 else
                 {
-                    r_cc_receive_fsm = CC_RECEIVE_INVAL_HEADER;
+                    r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
                 }
             }
@@ -5546,13 +5533,13 @@
             {
                 // request dcache to handle the BROADCAST
-                r_cc_receive_dcache_req  = true;
+                r_cc_receive_dcache_req = true;
                 r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,
                                              DspinDhccpParam::BROADCAST_NLINE);
-                r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
+                r_cc_receive_dcache_type = CC_TYPE_INVAL;
                 // request icache to handle the BROADCAST
-                r_cc_receive_icache_req  = true;
+                r_cc_receive_icache_req = true;
                 r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,
                                              DspinDhccpParam::BROADCAST_NLINE);
-                r_cc_receive_icache_type = CC_TYPE_BRDCAST;
+                r_cc_receive_icache_type = CC_TYPE_INVAL;
                 // get back to idle state
                 r_cc_receive_fsm = CC_RECEIVE_IDLE;
@@ -5563,42 +5550,28 @@
         }
         /////////////////////////////
-        case CC_RECEIVE_INVAL_HEADER:
+        case CC_RECEIVE_DATA_INVAL_HEADER:
         {
             // sample updt tab index in the HEADER, then skip to second flit
-            uint64_t receive_data = p_dspin_m2p.data.read();
-            // for data INVAL, wait for dcache to take the request
-            if ((r_cc_receive_data_ins.read() == 0) and 
-                 not (r_cc_receive_dcache_req.read()))
-            {
-                r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
-                                                   DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
-                r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
-                break;
-            }
-            // for ins INVAL, wait for icache to take the request
-            if ((r_cc_receive_data_ins.read() == 1) and 
-                 not (r_cc_receive_icache_req.read()))
-            {
-                r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
-                                                   DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
-                r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
-                break;
-            }
-            // keep waiting for the correct cache to accept the request
+            r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
+            break;
+        }
+        /////////////////////////////
+        case CC_RECEIVE_INS_INVAL_HEADER:
+        {
+            // sample updt tab index in the HEADER, then skip to second flit
+            r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
             break;
         }
         ////////////////////////////
-        case CC_RECEIVE_INVAL_NLINE:
+        case CC_RECEIVE_DATA_INVAL_NLINE:
         {
             // sample nline in the second flit
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for data INVAL, wait for dcache to take the request
-            if ( (r_cc_receive_data_ins.read() == 0) and 
-                 not (r_cc_receive_dcache_req.read()) and 
-                 (p_dspin_m2p.write.read()) )
+            if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read())
             {
                 // request dcache to handle the INVAL
-                r_cc_receive_dcache_req  = true;
-                r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
+                r_cc_receive_dcache_req = true;
+                r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
                 r_cc_receive_dcache_type = CC_TYPE_INVAL;
                 // get back to idle state
@@ -5606,10 +5579,17 @@
                 break;
             }
+            break;
+        }
+        //////////////////////////////
+        case CC_RECEIVE_INS_INVAL_NLINE:
+        {
+            // sample nline in the second flit
+            uint64_t receive_data = p_dspin_m2p.data.read();
             // for ins INVAL, wait for icache to take the request
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read()))
+            if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read())
             {
                 // request icache to handle the INVAL
-                r_cc_receive_icache_req  = true;
-                r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
+                r_cc_receive_icache_req = true;
+                r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
                 r_cc_receive_icache_type = CC_TYPE_INVAL;
                 // get back to idle state
@@ -5617,9 +5597,8 @@
                 break;
             }
-            // we should never get there
-            assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_INVAL_NLINE\n");
+            break;
         }
         ////////////////////////////
-        case CC_RECEIVE_UPDT_HEADER:
+        case CC_RECEIVE_DATA_UPDT_HEADER:
         {
             // sample updt tab index in the HEADER, than skip to second flit
@@ -5627,16 +5606,23 @@
             // for data INVAL, wait for dcache to take the request and fifo to
             // be empty
-            if ((r_cc_receive_data_ins.read() == 0) and not r_cc_receive_dcache_req.read() and r_cc_receive_updt_fifo_be.empty())
+            if (not r_cc_receive_dcache_req.read())
             {
                 r_cc_receive_dcache_updt_tab_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
-                r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
+                r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
                 break;
             }
+            break;
+        }
+        ////////////////////////////
+        case CC_RECEIVE_INS_UPDT_HEADER:
+        {
+            // sample updt tab index in the HEADER, than skip to second flit
+            uint64_t receive_data = p_dspin_m2p.data.read();
             // for ins INVAL, wait for icache to take the request and fifo to be
             // empty
-            if ((r_cc_receive_data_ins.read() == 1) and not r_cc_receive_icache_req.read() and r_cc_receive_updt_fifo_be.empty())
+            if (not r_cc_receive_icache_req.read())
             {
                 r_cc_receive_icache_updt_tab_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
-                r_cc_receive_fsm = CC_RECEIVE_UPDT_NLINE;
+                r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
                 break;
             }
@@ -5645,5 +5631,5 @@
         }
         ///////////////////////////
-        case CC_RECEIVE_UPDT_NLINE:
+        case CC_RECEIVE_DATA_UPDT_NLINE:
         {
             // sample nline and word index in the second flit
@@ -5651,42 +5637,40 @@
             // for data INVAL, wait for dcache to take the request and fifo to
             // be empty
-            if ( (r_cc_receive_data_ins.read() == 0) and 
-                 not (r_cc_receive_dcache_req.read()) and 
-                 r_cc_receive_updt_fifo_be.empty() and 
-                 (p_dspin_m2p.write.read()) )
-            {
+            if ( r_cc_receive_updt_fifo_be.empty() and 
+                 p_dspin_m2p.write.read() )
+            {
+                r_cc_receive_dcache_req = true;
                 r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
                 r_cc_receive_word_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
                 r_cc_receive_dcache_type = CC_TYPE_UPDT;
                 // get back to idle state
-                r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
+                r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
                 break;
             }
+            break;
+        }
+        ////////////////////////////
+        case CC_RECEIVE_INS_UPDT_NLINE:
+        {
+            // sample nline and word index in the second flit
+            uint64_t receive_data = p_dspin_m2p.data.read();
             // for ins INVAL, wait for icache to take the request and fifo to be
             // empty
-            if ( (r_cc_receive_data_ins.read() == 1) and 
-                 not (r_cc_receive_icache_req.read()) and 
-                 r_cc_receive_updt_fifo_be.empty() and 
-                 (p_dspin_m2p.write.read()))
-            {
+            if ( r_cc_receive_updt_fifo_be.empty() and 
+                 p_dspin_m2p.write.read() )
+            {
+                r_cc_receive_icache_req = true;
                 r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
                 r_cc_receive_word_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
                 r_cc_receive_icache_type = CC_TYPE_UPDT;
                 // get back to idle state
-                r_cc_receive_fsm = CC_RECEIVE_UPDT_DATA;
+                r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
                 break;
             }
-            // we should never get there
-            assert ( false && "ERROR in CC_VCACHE : CC_RECEIVE_UPDT_NLINE \n");
             break;
         }
         //////////////////////////
-        case CC_RECEIVE_UPDT_DATA:
-        {
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_m2p.write.read()))
-                r_cc_receive_dcache_req = true;
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_m2p.write.read()))
-                r_cc_receive_icache_req = true;
-
+        case CC_RECEIVE_DATA_UPDT_DATA:
+        {
             // wait for the fifo
             if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
@@ -5702,4 +5686,21 @@
             break;
         }
+        //////////////////////////
+        case CC_RECEIVE_INS_UPDT_DATA:
+        {
+            // wait for the fifo
+            if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
+            {
+                uint64_t receive_data = p_dspin_m2p.data.read();
+                bool     receive_eop  = p_dspin_m2p.eop.read();
+                cc_receive_updt_fifo_be   = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
+                cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
+                cc_receive_updt_fifo_eop  = receive_eop;
+                cc_receive_updt_fifo_put  = true;
+                if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
+            }
+            break;
+        }
+
     } // end switch CC_RECEIVE FSM
 
@@ -6091,5 +6092,4 @@
     // Receive coherence packets
     // It depends on the CC_RECEIVE FSM 
-
     switch( r_cc_receive_fsm.read() )
     {
@@ -6098,14 +6098,4 @@
         {
             p_dspin_m2p.read = false;
-            break;
-        }
-        //////////////////////
-        case CC_RECEIVE_CLACK:
-        {
-            if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
-                ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
-                p_dspin_m2p.read = true;
-            else
-                p_dspin_m2p.read = false;
             break;
         }
@@ -6129,8 +6119,25 @@
         }
         /////////////////////////////
-        case CC_RECEIVE_INVAL_HEADER:
-        {
-            if (((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read())) or
-                ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read())))
+        case CC_RECEIVE_DATA_INVAL_HEADER:
+        case CC_RECEIVE_INS_INVAL_HEADER:
+        {
+            p_dspin_m2p.read = true;
+            break;
+        }
+        ////////////////////////////
+        case CC_RECEIVE_DATA_INVAL_NLINE:
+        {
+            p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
+            break;
+        }
+        case CC_RECEIVE_INS_INVAL_NLINE:
+        {
+            p_dspin_m2p.read = not r_cc_receive_icache_req.read();
+            break;
+        }
+        ///////////////////////////
+        case CC_RECEIVE_DATA_UPDT_HEADER:
+        {
+            if (not r_cc_receive_dcache_req.read())
                 p_dspin_m2p.read = true;
             else
@@ -6139,19 +6146,7 @@
         }
         ////////////////////////////
-        case CC_RECEIVE_INVAL_NLINE:
-        {
-            p_dspin_m2p.read = true;
-            break;
-        }
-        ////////////////////////////
-        case CC_RECEIVE_UPDT_HEADER:
-        {
-            if (((r_cc_receive_data_ins.read() == 0) and
-                not r_cc_receive_dcache_req.read() and
-                r_cc_receive_updt_fifo_be.empty())
-                or
-                (((r_cc_receive_data_ins.read() == 1) and
-                not r_cc_receive_icache_req.read()) and
-                r_cc_receive_updt_fifo_be.empty()))
+        case CC_RECEIVE_INS_UPDT_HEADER:
+        {
+            if ( not r_cc_receive_icache_req.read()) 
                 p_dspin_m2p.read = true;
             else
@@ -6160,13 +6155,8 @@
         }
         ///////////////////////////
-        case CC_RECEIVE_UPDT_NLINE:
-        {
-            if (((r_cc_receive_data_ins.read() == 0) and
-                not (r_cc_receive_dcache_req.read()) and
-                r_cc_receive_updt_fifo_be.empty())
-                or
-                ((r_cc_receive_data_ins.read() == 1) and
-                not (r_cc_receive_icache_req.read()) and
-                r_cc_receive_updt_fifo_be.empty()))
+        case CC_RECEIVE_DATA_UPDT_NLINE:
+        case CC_RECEIVE_INS_UPDT_NLINE:
+        {
+            if(r_cc_receive_updt_fifo_be.empty())
                 p_dspin_m2p.read = true;
             else
@@ -6174,6 +6164,7 @@
             break;
         }
-        //////////////////////////
-        case CC_RECEIVE_UPDT_DATA:
+        ///////////////////////////
+        case CC_RECEIVE_DATA_UPDT_DATA:
+        case CC_RECEIVE_INS_UPDT_DATA:
         {
             if (r_cc_receive_updt_fifo_be.wok())
@@ -6184,4 +6175,5 @@
         }
     } // end switch CC_RECEIVE FSM
+
 
     int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
