Changeset 455 for branches/v5

Timestamp:

Jul 19, 2013, 10:16:17 AM (11 years ago)

Author:

cfuguet

Message:

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface

Location:

branches/v5/modules/vci_mem_cache

Files:

• . (modified) (1 prop)
• caba/source/include/mem_cache_directory.h (modified) (6 diffs)
• caba/source/include/vci_mem_cache.h (modified) (4 diffs)
• caba/source/src/vci_mem_cache.cpp (modified) (32 diffs)

branches/v5/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h

@@ -12 +12 @@
 // to behave in an unpredicted way.
 // TODO Either remove the mechanism from the mem cache or update its behaviour.
+
 #define L1_MULTI_CACHE 0
 
@@ -247 +248 @@
     // The function returns a copy of a (valid or invalid) entry  
     /////////////////////////////////////////////////////////////////////
-    DirectoryEntry read(const addr_t &address,size_t &way)
+    DirectoryEntry read(const addr_t &address, size_t &way)
     {
 
@@ -277 +278 @@
     // way arguments. 
     /////////////////////////////////////////////////////////////////////
-    void inval( const size_t &set, const size_t &way )
+    void inval( const size_t &way, const size_t &set )
     {
         m_dir_tab[set][way].init();
@@ -289 +290 @@
     // The function returns a copy of a (valid or invalid) entry  
     /////////////////////////////////////////////////////////////////////
-    DirectoryEntry read_neutral(const addr_t &address)
+    DirectoryEntry read_neutral( const addr_t &address, 
+                                 size_t*      ret_way,
+                                 size_t*      ret_set )
     {
 
 #define L2 soclib::common::uint32_log2
-      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
-      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+        size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+        tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
 #undef L2
 
-      bool hit       = false;
-      for ( size_t i=0 ; i<m_ways ; i++ ) {
-        bool equal = ( m_dir_tab[set][i].tag == tag );
-        bool valid = m_dir_tab[set][i].valid;
-        hit = equal && valid;
-        if ( hit ) {                    
-          return DirectoryEntry(m_dir_tab[set][i]);
+        for ( size_t way = 0 ; way < m_ways ; way++ ) 
+        {
+            bool equal = ( m_dir_tab[set][way].tag == tag );
+            bool valid = m_dir_tab[set][way].valid;
+            if ( equal and valid )
+            {
+                *ret_set = set;
+                *ret_way = way; 
+                return DirectoryEntry(m_dir_tab[set][way]);
+            }
         } 
-      }
-      return DirectoryEntry();
+        return DirectoryEntry();
     } // end read_neutral()
 
@@ -406 +411 @@
     void init()
     {
-      for ( size_t set=0 ; set<m_sets ; set++ ) {
-        for ( size_t way=0 ; way<m_ways ; way++ ) {
+      for ( size_t set=0 ; set<m_sets ; set++ ) 
+      {
+        for ( size_t way=0 ; way<m_ways ; way++ ) 
+        {
           m_dir_tab[set][way].init();
           m_lru_tab[set][way].init();
@@ -688 +695 @@
         assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
         assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
-      
+
         for (uint32_t word=0; word<m_words; word++)
           cache_line[word].write(m_cache_data[way][set][word]);

branches/v5/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -69 +69 @@
     {
       typedef typename vci_param_int::fast_addr_t  addr_t;
-
       typedef typename sc_dt::sc_uint<64>          wide_data_t;
-
-      typedef uint32_t data_t;
-      typedef uint32_t tag_t;
-      typedef uint32_t be_t;
-      typedef uint32_t copy_t;
+      typedef uint32_t                             data_t;
+      typedef uint32_t                             tag_t;
+      typedef uint32_t                             be_t;
+      typedef uint32_t                             copy_t;
 
       /* States of the TGT_CMD fsm */
@@ -396 +394 @@
 
       // debug variables (for each FSM)
-      bool         m_debug;
-      bool         m_debug_previous_hit;
-      size_t       m_debug_previous_count;
+      bool                 m_debug;
+      bool                 m_debug_previous_valid;
+      size_t               m_debug_previous_count;
+      bool                 m_debug_previous_dirty;
+      sc_signal<data_t>*   m_debug_previous_data;
+      sc_signal<data_t>*   m_debug_data;
 
       bool         m_monitor_ok;
@@ -482 +483 @@
       void print_stats();
       void print_trace();
-      void copies_monitor(addr_t addr);
+      void cache_monitor(addr_t addr);
       void start_monitor(addr_t addr, addr_t length);
       void stop_monitor();
@@ -490 +491 @@
       void transition();
       void genMoore();
-      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
+      void check_monitor(addr_t addr, data_t data, bool read);
 
       // Component attributes

branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -527 +527 @@
     r_cas_rdata                = new sc_signal<data_t>[2];
 
+    // Allocation for debug
+    m_debug_previous_data      = new sc_signal<data_t>[nwords];
+    m_debug_data               = new sc_signal<data_t>[nwords];
 
     SC_METHOD(transition);
@@ -554 +557 @@
 
 ////////////////////////////////////////////////
-tmpl(void) ::check_monitor( const char  *buf,
-                            addr_t      addr,
+tmpl(void) ::check_monitor( addr_t      addr,
                             data_t      data,
                             bool        read )
@@ -563 +565 @@
       (addr < m_monitor_base + m_monitor_length))
   {
-    if ( read ) std::cout << " Monitor MEMC Read  ";
-    else        std::cout << " Monitor MEMC Write ";
-    std::cout << buf
-              << " / Address = " << std::hex << addr
+    if ( read ) std::cout << " Monitor MEMC Read ";
+    else        std::cout << " Monitor MEMC Write";
+    std::cout << " / Address = " << std::hex << addr
               << " / Data = " << data
               << " at cycle " << std::dec << m_cpt_cycles << std::endl;
@@ -573 +574 @@
 
 /////////////////////////////////////////////////////
-tmpl(void) ::copies_monitor(addr_t addr)
+tmpl(void) ::cache_monitor(addr_t addr)
 /////////////////////////////////////////////////////
 {
-  DirectoryEntry entry = m_cache_directory.read_neutral(addr);
-
-  if((entry.count != m_debug_previous_count) or
-      (entry.valid != m_debug_previous_hit))
-  {
-    std::cout << "Monitor MEMC " << name()
-              << " at cycle " << std::dec << m_cpt_cycles
-              << " for address " << std::hex << addr
-              << " / HIT = " << entry.valid
-              << " / COUNT = " << std::dec << entry.count << std::endl;
-  }
-  m_debug_previous_count = entry.count;
-  m_debug_previous_hit = entry.valid;
+    size_t way = 0;
+    size_t set = 0;
+    DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set );
+
+    bool data_change = false;
+
+    if ( entry.valid )
+    {
+        m_cache_data.read_line( way, set, m_debug_data );
+
+        for ( size_t i = 0 ; i<m_words ; i++ )
+        {
+            if ( m_debug_previous_valid and
+                 (m_debug_data[i].read() != m_debug_previous_data[i].read()) )
+                 data_change = true;
+            m_debug_previous_data[i] = m_debug_data[i].read();
+        }
+    }
+    
+    if ( (entry.valid != m_debug_previous_valid) or
+         (entry.valid and (entry.count != m_debug_previous_count)) or
+         (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change )
+    {
+        std::cout << "Monitor MEMC " << name()
+                  << " at cycle " << std::dec << m_cpt_cycles
+                  << " for address " << std::hex << addr
+                  << " / HIT = " << std::dec << entry.valid
+                  << " / WAY = " << way
+                  << " / COUNT = " << entry.count 
+                  << " / DIRTY = " << entry.dirty
+                  << " / DATA_CHANGE = " << entry.count 
+                  << std::endl;
+    }
+    m_debug_previous_count = entry.count;
+    m_debug_previous_valid = entry.valid;
+    m_debug_previous_dirty = entry.dirty;
 }
 
@@ -694 +718 @@
 
     m_debug                = false;
-    m_debug_previous_hit   = false;
+    m_debug_previous_valid = false;
+    m_debug_previous_dirty = false;
     m_debug_previous_count = 0;
 
@@ -1440 +1465 @@
   //
   // From the software point of view, a configuration request is a sequence
-  // of 6 atomic accesses:
+  // of 6 atomic accesses in an uncached segment:
   // - Read  MEMC_LOCK       : Get the lock
   // - Write MEMC_ADDR_LO    : Set the buffer address LSB
@@ -1595 +1620 @@
                                   nb_copies,
                                   index);
+
                   if ( wok )  // IVT success => inval DIR slot
                   {
@@ -1837 +1863 @@
       case READ_IDLE:  // waiting a read request
       {
-      if(m_cmd_read_addr_fifo.rok())
-      {
+        if(m_cmd_read_addr_fifo.rok())
+        {
 
 #if DEBUG_MEMC_READ
-if(m_debug)
-std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
-          << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
-          << " / srcid = " << m_cmd_read_srcid_fifo.read()
-          << " / trdid = " << m_cmd_read_trdid_fifo.read()
-          << " / pktid = " << m_cmd_read_pktid_fifo.read()
-          << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
-#endif
-        r_read_fsm = READ_DIR_REQ;
-      }
+          if(m_debug)
+            std::cout << "  <MEMC " << name() << " READ_IDLE> Read request"
+              << " : address = " << std::hex << m_cmd_read_addr_fifo.read()
+              << " / srcid = " << m_cmd_read_srcid_fifo.read()
+              << " / trdid = " << m_cmd_read_trdid_fifo.read()
+              << " / pktid = " << m_cmd_read_pktid_fifo.read()
+              << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
+#endif
+          r_read_fsm = READ_DIR_REQ;
+        }
       break;
     }
@@ -1877 +1903 @@
         DirectoryEntry entry =
           m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
-        if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)   // access the global table ONLY when we have an LL cmd
+        // access the global table ONLY when we have an LL cmd
+        if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)   
         {
           r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
@@ -1939 +1966 @@
 
     //////////////////
-    case READ_DIR_HIT:
-    {
-      //  read data in cache & update the directory
-      //  we enter this state in 3 cases:
-      //  - the read request is uncachable
-      //  - the cache line is in counter mode
-      //  - the cache line is valid but not replcated
-
+    case READ_DIR_HIT:    //  read data in cache & update the directory
+                          //  we enter this state in 3 cases:
+                          //  - the read request is uncachable
+                          //  - the cache line is in counter mode
+                          //  - the cache line is valid but not replicated
+
+    {
       if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
       {
@@ -1965 +1991 @@
         m_cache_data.read_line(way, set, r_read_data);
 
+        if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true);
+
         // update the cache directory
         DirectoryEntry entry;
@@ -1973 +2001 @@
         entry.lock    = r_read_lock.read();
         entry.ptr     = r_read_ptr.read();
+
         if(cached_read)   // Cached read => we must update the copies
         {
@@ -1994 +2023 @@
           }
         }
-        else  // Uncached read
+        else            // Uncached read
         {
           entry.owner.srcid     = r_read_copy.read();
@@ -2005 +2034 @@
 
 #if DEBUG_MEMC_READ
-if(m_debug)
-std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
-          << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
-          << " / set = " << std::dec << set
-          << " / way = " << way
-          << " / owner_id = " << std::hex << entry.owner.srcid
-          << " / owner_ins = " << std::dec << entry.owner.inst
-          << " / count = " << entry.count
-          << " / is_cnt = " << entry.is_cnt << std::endl;
-#endif
-
-          if(m_monitor_ok)
-          {
-            char buf[80];
-            snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d",
-                     (int)m_cmd_read_srcid_fifo.read(),
-                     (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0));
-            check_monitor(buf, m_cmd_read_addr_fifo.read(), r_read_data[0], true);
-          }
-
+        if(m_debug)
+          std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
+            << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
+            << " / set = " << std::dec << set
+            << " / way = " << way
+            << " / owner_id = " << std::hex << entry.owner.srcid
+            << " / owner_ins = " << std::dec << entry.owner.inst
+            << " / count = " << entry.count
+            << " / is_cnt = " << entry.is_cnt << std::endl;
+#endif
 
         m_cache_directory.write(set, way, entry);
@@ -2031 +2050 @@
       break;
     }
-
     ///////////////////
     case READ_HEAP_REQ:    // Get the lock to the HEAP directory
@@ -2062 +2080 @@
 
         m_cache_data.read_line(way, set, r_read_data);
+
+        if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true);
 
         // update the cache directory
@@ -2429 +2449 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug)
-        {
-          std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
-                    << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
-                    << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
-                    << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_IDLE> Write request "
+          << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
+          << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
+          << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
 #endif
       }
@@ -2448 +2466 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug)
-        {
-          std::cout << "  <MEMC " << name()
-                    << " WRITE_NEXT> Write another word in local buffer"
-                    << std::endl;
-        }
+if(m_debug)
+std::cout << "  <MEMC " << name()
+          << " WRITE_NEXT> Write another word in local buffer"
+          << std::endl;
 #endif
         m_cpt_write_cells++;
@@ -2532 +2548 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug)
-      {
-        std::cout
-            << "  <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "
-            << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "
+          << std::endl;
 #endif
 
@@ -2544 +2557 @@
 
     ////////////////////
-    case WRITE_DIR_LOCK:
-      // access directory to check hit/miss
+    case WRITE_DIR_LOCK:     // access directory to check hit/miss
     {
       if(r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE)
@@ -2582 +2594 @@
 
 #if DEBUG_MEMC_WRITE
-        if(m_debug)
-        {
-          std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
-                    << " address = " << std::hex << r_write_address.read()
-                    << " hit = " << std::dec << entry.valid
-                    << " count = " << entry.count
-                    << " is_cnt = " << entry.is_cnt << std::endl;
-          if((r_write_pktid.read() & 0x7) == TYPE_SC)
-            std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_table SC access" << std::endl;
-          else
-            std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> global_llsc_table SW access" << std::endl;
-        }
+if(m_debug)
+{
+std::cout << "  <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: "
+          << " address = " << std::hex << r_write_address.read()
+          << " / hit = " << std::dec << entry.valid
+          << " / count = " << entry.count
+          << " / is_cnt = " << entry.is_cnt ;
+if((r_write_pktid.read() & 0x7) == TYPE_SC)
+std::cout << " / SC access" << std::endl;
+else
+std::cout << " / SW access" << std::endl;
+}
 #endif
       }
@@ -2604 +2616 @@
         exit(0);
       }
-
-      break;
-    }
-
+      break;
+    }
     ////////////////////
     case WRITE_DIR_READ:  // read the cache and complete the buffer when be!=0xF
@@ -2632 +2642 @@
 
 #if DEBUG_MEMC_WRITE
-      if(m_debug)
-      {
-        std::cout << "  <MEMC " << name() << " WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
-      }
+if(m_debug)
+std::cout << "  <MEMC " << name() << " WRITE_DIR_READ>"
+          << " Read the cache to complete local buffer" << std::endl;
 #endif
       break;
@@ -2648 +2657 @@
       entry.valid          = true;
       entry.dirty          = true;
-      entry.tag          = r_write_tag.read();
+      entry.tag            = r_write_tag.read();
       entry.is_cnt         = r_write_is_cnt.read();
       entry.lock           = r_write_lock.read();
@@ -2675 +2684 @@
       // (tests for sc requests)
       bool no_update = ( (r_write_count.read() == 0) or
-                         (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC)));
+                         (owner and (r_write_count.read() ==1) and 
+                         (r_write_pktid.read() != TYPE_SC)));
 
       // write data in the cache if no coherence transaction
@@ -2687 +2697 @@
           {
             addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
-            char buf[80];
-            snprintf(buf, 80, "WRITE_DIR_HIT srcid %d",
-                     (int)r_write_srcid.read());
-            check_monitor(buf, address, r_write_data[word].read(), false);
+            check_monitor( address, r_write_data[word].read(), false);
           }
         }
@@ -2739 +2746 @@
       break;
     }
-
     ////////////////////
     case WRITE_UPT_LOCK:  // Try to register the update request in UPT
@@ -2778 +2784 @@
             {
               addr_t address = (r_write_address.read() & ~(addr_t) 0x3F) | word<<2;
-              char buf[80];
-              snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", (int)srcid);
-              check_monitor(buf, address, r_write_data[word].read(), false);
+              check_monitor( address, r_write_data[word].read(), false);
             }
           }
@@ -3880 +3884 @@
         {
           addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
-          check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word], false);
+          check_monitor( address, r_xram_rsp_trt_buf.wdata[word], false);
         }
       }
@@ -5270 +5274 @@
         {
           addr_t address = m_cmd_cas_addr_fifo.read();
-          char buf[80];
-          snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
-                   (int)m_cmd_cas_srcid_fifo.read());
-          check_monitor(buf, address, r_cas_wdata.read(), false);
+          check_monitor( address, r_cas_wdata.read(), false);
 
           if(r_cas_cpt.read() == 4)
-            check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
+            check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
         }
 
@@ -5335 +5336 @@
           {
             addr_t address = m_cmd_cas_addr_fifo.read();
-            char buf[80];
-            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
-                     (int)m_cmd_cas_srcid_fifo.read());
-            check_monitor(buf, address, r_cas_wdata.read(), false);
+            check_monitor( address, r_cas_wdata.read(), false);
 
             if(r_cas_cpt.read() ==4)
-              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
+              check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
           }
         }
@@ -5572 +5570 @@
           {
             addr_t address = m_cmd_cas_addr_fifo.read();
-            char buf[80];
-            snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d",
-                     (int)m_cmd_cas_srcid_fifo.read());
-            check_monitor(buf, address, r_cas_wdata.read(), false);
+            check_monitor( address, r_cas_wdata.read(), false);
+
             if(r_cas_cpt.read() ==4)
-              check_monitor(buf, address+4, m_cmd_cas_wdata_fifo.read(), false);
+              check_monitor( address+4, m_cmd_cas_wdata_fifo.read(), false);
           }
           r_cas_upt_index = index;